1ddd04b98SVaibhav Hiremath /* 2ddd04b98SVaibhav Hiremath * AM33XX PRM_XXX register bits 3ddd04b98SVaibhav Hiremath * 43aa36fddSAlexander A. Klimov * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/ 5ddd04b98SVaibhav Hiremath * 6ddd04b98SVaibhav Hiremath * This program is free software; you can redistribute it and/or 7ddd04b98SVaibhav Hiremath * modify it under the terms of the GNU General Public License as 8ddd04b98SVaibhav Hiremath * published by the Free Software Foundation version 2. 9ddd04b98SVaibhav Hiremath * 10ddd04b98SVaibhav Hiremath * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11ddd04b98SVaibhav Hiremath * kind, whether express or implied; without even the implied warranty 12ddd04b98SVaibhav Hiremath * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13ddd04b98SVaibhav Hiremath * GNU General Public License for more details. 14ddd04b98SVaibhav Hiremath */ 15ddd04b98SVaibhav Hiremath 16ddd04b98SVaibhav Hiremath #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H 17ddd04b98SVaibhav Hiremath #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H 18ddd04b98SVaibhav Hiremath 19ddd04b98SVaibhav Hiremath #include "prm.h" 20ddd04b98SVaibhav Hiremath 21ddd04b98SVaibhav Hiremath #define AM33XX_GFX_MEM_ONSTATE_MASK (0x3 << 17) 22ddd04b98SVaibhav Hiremath #define AM33XX_GFX_MEM_RETSTATE_MASK (1 << 6) 23ddd04b98SVaibhav Hiremath #define AM33XX_GFX_MEM_STATEST_MASK (0x3 << 4) 24ddd04b98SVaibhav Hiremath #define AM33XX_GLOBAL_WARM_SW_RST_MASK (1 << 1) 257323f219STony Lindgren #define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0) 26ddd04b98SVaibhav Hiremath #define AM33XX_PRUSS_MEM_ONSTATE_MASK (0x3 << 5) 27ddd04b98SVaibhav Hiremath #define AM33XX_PRUSS_MEM_RETSTATE_MASK (1 << 7) 28ddd04b98SVaibhav Hiremath #define AM33XX_PRUSS_MEM_STATEST_MASK (0x3 << 23) 29ddd04b98SVaibhav Hiremath #define AM33XX_LASTPOWERSTATEENTERED_SHIFT 24 30ddd04b98SVaibhav Hiremath #define AM33XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24) 31ddd04b98SVaibhav Hiremath #define AM33XX_LOGICRETSTATE_MASK (1 << 2) 32ddd04b98SVaibhav Hiremath #define AM33XX_LOGICRETSTATE_3_3_MASK (1 << 3) 33ddd04b98SVaibhav Hiremath #define AM33XX_LOGICSTATEST_SHIFT 2 34ddd04b98SVaibhav Hiremath #define AM33XX_LOGICSTATEST_MASK (1 << 2) 35ddd04b98SVaibhav Hiremath #define AM33XX_LOWPOWERSTATECHANGE_SHIFT 4 36ddd04b98SVaibhav Hiremath #define AM33XX_LOWPOWERSTATECHANGE_MASK (1 << 4) 37ddd04b98SVaibhav Hiremath #define AM33XX_MPU_L1_ONSTATE_MASK (0x3 << 18) 38ddd04b98SVaibhav Hiremath #define AM33XX_MPU_L1_RETSTATE_MASK (1 << 22) 39ddd04b98SVaibhav Hiremath #define AM33XX_MPU_L1_STATEST_MASK (0x3 << 6) 40ddd04b98SVaibhav Hiremath #define AM33XX_MPU_L2_ONSTATE_MASK (0x3 << 20) 41ddd04b98SVaibhav Hiremath #define AM33XX_MPU_L2_RETSTATE_MASK (1 << 23) 42ddd04b98SVaibhav Hiremath #define AM33XX_MPU_L2_STATEST_MASK (0x3 << 8) 43ddd04b98SVaibhav Hiremath #define AM33XX_MPU_RAM_ONSTATE_MASK (0x3 << 16) 44ddd04b98SVaibhav Hiremath #define AM33XX_MPU_RAM_RETSTATE_MASK (1 << 24) 45ddd04b98SVaibhav Hiremath #define AM33XX_MPU_RAM_STATEST_MASK (0x3 << 4) 46ddd04b98SVaibhav Hiremath #define AM33XX_PER_MEM_ONSTATE_MASK (0x3 << 25) 47ddd04b98SVaibhav Hiremath #define AM33XX_PER_MEM_RETSTATE_MASK (1 << 29) 48ddd04b98SVaibhav Hiremath #define AM33XX_PER_MEM_STATEST_MASK (0x3 << 17) 49ddd04b98SVaibhav Hiremath #define AM33XX_RAM_MEM_ONSTATE_MASK (0x3 << 30) 50ddd04b98SVaibhav Hiremath #define AM33XX_RAM_MEM_RETSTATE_MASK (1 << 27) 51ddd04b98SVaibhav Hiremath #define AM33XX_RAM_MEM_STATEST_MASK (0x3 << 21) 52ddd04b98SVaibhav Hiremath #endif 53