1f34efee8SBenoit Cousson /* 2f34efee8SBenoit Cousson * OMAP54xx PRCM MPU instance offset macros 3f34efee8SBenoit Cousson * 4f34efee8SBenoit Cousson * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com 5f34efee8SBenoit Cousson * 6f34efee8SBenoit Cousson * Paul Walmsley (paul@pwsan.com) 7f34efee8SBenoit Cousson * Rajendra Nayak (rnayak@ti.com) 8f34efee8SBenoit Cousson * Benoit Cousson (b-cousson@ti.com) 9f34efee8SBenoit Cousson * 10f34efee8SBenoit Cousson * This file is automatically generated from the OMAP hardware databases. 11f34efee8SBenoit Cousson * We respectfully ask that any modifications to this file be coordinated 12f34efee8SBenoit Cousson * with the public linux-omap@vger.kernel.org mailing list and the 13f34efee8SBenoit Cousson * authors above to ensure that the autogeneration scripts are kept 14f34efee8SBenoit Cousson * up-to-date with the file contents. 15f34efee8SBenoit Cousson * 16f34efee8SBenoit Cousson * This program is free software; you can redistribute it and/or modify 17f34efee8SBenoit Cousson * it under the terms of the GNU General Public License version 2 as 18f34efee8SBenoit Cousson * published by the Free Software Foundation. 19f34efee8SBenoit Cousson */ 20f34efee8SBenoit Cousson 21f34efee8SBenoit Cousson #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H 22f34efee8SBenoit Cousson #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H 23f34efee8SBenoit Cousson 24f34efee8SBenoit Cousson #include "prcm_mpu_44xx_54xx.h" 25f34efee8SBenoit Cousson #include "common.h" 26f34efee8SBenoit Cousson 27f34efee8SBenoit Cousson #define OMAP54XX_PRCM_MPU_BASE 0x48243000 28f34efee8SBenoit Cousson 29f34efee8SBenoit Cousson #define OMAP54XX_PRCM_MPU_REGADDR(inst, reg) \ 30f34efee8SBenoit Cousson OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE + (inst) + (reg)) 31f34efee8SBenoit Cousson 32f34efee8SBenoit Cousson /* PRCM_MPU instances */ 33f34efee8SBenoit Cousson #define OMAP54XX_PRCM_MPU_OCP_SOCKET_INST 0x0000 34f34efee8SBenoit Cousson #define OMAP54XX_PRCM_MPU_DEVICE_INST 0x0200 35f34efee8SBenoit Cousson #define OMAP54XX_PRCM_MPU_PRM_C0_INST 0x0400 36f34efee8SBenoit Cousson #define OMAP54XX_PRCM_MPU_CM_C0_INST 0x0600 37f34efee8SBenoit Cousson #define OMAP54XX_PRCM_MPU_PRM_C1_INST 0x0800 38f34efee8SBenoit Cousson #define OMAP54XX_PRCM_MPU_CM_C1_INST 0x0a00 39f34efee8SBenoit Cousson 40f34efee8SBenoit Cousson /* PRCM_MPU clockdomain register offsets (from instance start) */ 41f34efee8SBenoit Cousson #define OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS 0x0000 42f34efee8SBenoit Cousson #define OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS 0x0000 43f34efee8SBenoit Cousson 44f34efee8SBenoit Cousson 45f34efee8SBenoit Cousson /* 46f34efee8SBenoit Cousson * PRCM_MPU 47f34efee8SBenoit Cousson * 48f34efee8SBenoit Cousson * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global) 49f34efee8SBenoit Cousson * point of view the PRCM_MPU is a single entity. It shares the same 50f34efee8SBenoit Cousson * programming model as the global PRCM and thus can be assimilate as two new 51f34efee8SBenoit Cousson * MOD inside the PRCM 52f34efee8SBenoit Cousson */ 53f34efee8SBenoit Cousson 54f34efee8SBenoit Cousson /* PRCM_MPU.PRCM_MPU_OCP_SOCKET register offsets */ 55f34efee8SBenoit Cousson #define OMAP54XX_REVISION_PRCM_MPU_OFFSET 0x0000 56f34efee8SBenoit Cousson 57f34efee8SBenoit Cousson /* PRCM_MPU.PRCM_MPU_DEVICE register offsets */ 58f34efee8SBenoit Cousson #define OMAP54XX_PRCM_MPU_PRM_RSTST_OFFSET 0x0000 59f34efee8SBenoit Cousson #define OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004 60f34efee8SBenoit Cousson #define OMAP54XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET 0x0010 61f34efee8SBenoit Cousson #define OMAP54XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x0014 62f34efee8SBenoit Cousson 63f34efee8SBenoit Cousson /* PRCM_MPU.PRCM_MPU_PRM_C0 register offsets */ 64f34efee8SBenoit Cousson #define OMAP54XX_PM_CPU0_PWRSTCTRL_OFFSET 0x0000 65f34efee8SBenoit Cousson #define OMAP54XX_PM_CPU0_PWRSTST_OFFSET 0x0004 66f34efee8SBenoit Cousson #define OMAP54XX_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x0010 67f34efee8SBenoit Cousson #define OMAP54XX_RM_CPU0_CPU0_RSTST_OFFSET 0x0014 68f34efee8SBenoit Cousson #define OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0024 69f34efee8SBenoit Cousson 70f34efee8SBenoit Cousson /* PRCM_MPU.PRCM_MPU_CM_C0 register offsets */ 71f34efee8SBenoit Cousson #define OMAP54XX_CM_CPU0_CLKSTCTRL_OFFSET 0x0000 72f34efee8SBenoit Cousson #define OMAP54XX_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0020 73f34efee8SBenoit Cousson #define OMAP54XX_CM_CPU0_CPU0_CLKCTRL OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C0_INST, 0x0020) 74f34efee8SBenoit Cousson 75f34efee8SBenoit Cousson /* PRCM_MPU.PRCM_MPU_PRM_C1 register offsets */ 76f34efee8SBenoit Cousson #define OMAP54XX_PM_CPU1_PWRSTCTRL_OFFSET 0x0000 77f34efee8SBenoit Cousson #define OMAP54XX_PM_CPU1_PWRSTST_OFFSET 0x0004 78f34efee8SBenoit Cousson #define OMAP54XX_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x0010 79f34efee8SBenoit Cousson #define OMAP54XX_RM_CPU1_CPU1_RSTST_OFFSET 0x0014 80f34efee8SBenoit Cousson #define OMAP54XX_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0024 81f34efee8SBenoit Cousson 82f34efee8SBenoit Cousson /* PRCM_MPU.PRCM_MPU_CM_C1 register offsets */ 83f34efee8SBenoit Cousson #define OMAP54XX_CM_CPU1_CLKSTCTRL_OFFSET 0x0000 84f34efee8SBenoit Cousson #define OMAP54XX_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0020 85f34efee8SBenoit Cousson #define OMAP54XX_CM_CPU1_CPU1_CLKCTRL OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C1_INST, 0x0020) 86f34efee8SBenoit Cousson 87f34efee8SBenoit Cousson #endif 88