1d198b514SPaul Walmsley /* 2d198b514SPaul Walmsley * OMAP44xx PRCM MPU instance offset macros 3d198b514SPaul Walmsley * 4d9a16f9aSPaul Walmsley * Copyright (C) 2010, 2012 Texas Instruments, Inc. 5d198b514SPaul Walmsley * Copyright (C) 2010 Nokia Corporation 6d198b514SPaul Walmsley * 7d198b514SPaul Walmsley * Paul Walmsley (paul@pwsan.com) 8d198b514SPaul Walmsley * Rajendra Nayak (rnayak@ti.com) 9d198b514SPaul Walmsley * Benoit Cousson (b-cousson@ti.com) 10d198b514SPaul Walmsley * 11d198b514SPaul Walmsley * This file is automatically generated from the OMAP hardware databases. 12d198b514SPaul Walmsley * We respectfully ask that any modifications to this file be coordinated 13d198b514SPaul Walmsley * with the public linux-omap@vger.kernel.org mailing list and the 14d198b514SPaul Walmsley * authors above to ensure that the autogeneration scripts are kept 15d198b514SPaul Walmsley * up-to-date with the file contents. 16d198b514SPaul Walmsley * 17d198b514SPaul Walmsley * This program is free software; you can redistribute it and/or modify 18d198b514SPaul Walmsley * it under the terms of the GNU General Public License version 2 as 19d198b514SPaul Walmsley * published by the Free Software Foundation. 20d198b514SPaul Walmsley * 21d198b514SPaul Walmsley * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX", 22d198b514SPaul Walmsley * or "OMAP4430". 23d198b514SPaul Walmsley */ 24d198b514SPaul Walmsley 25d198b514SPaul Walmsley #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H 26d198b514SPaul Walmsley #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H 27d198b514SPaul Walmsley 28d9a16f9aSPaul Walmsley #include "common.h" 29d9a16f9aSPaul Walmsley 30d9a16f9aSPaul Walmsley # ifndef __ASSEMBLER__ 31d9a16f9aSPaul Walmsley extern void __iomem *prcm_mpu_base; 32d9a16f9aSPaul Walmsley # endif 33d9a16f9aSPaul Walmsley 34d198b514SPaul Walmsley #define OMAP4430_PRCM_MPU_BASE 0x48243000 35d198b514SPaul Walmsley 36cdb54c44SPaul Walmsley #define OMAP44XX_PRCM_MPU_REGADDR(inst, reg) \ 37cdb54c44SPaul Walmsley OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg)) 38d198b514SPaul Walmsley 39d198b514SPaul Walmsley /* PRCM_MPU instances */ 40cdb54c44SPaul Walmsley #define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000 41cdb54c44SPaul Walmsley #define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200 42cdb54c44SPaul Walmsley #define OMAP4430_PRCM_MPU_CPU0_INST 0x0400 43cdb54c44SPaul Walmsley #define OMAP4430_PRCM_MPU_CPU1_INST 0x0800 44d198b514SPaul Walmsley 45e4156ee5SPaul Walmsley /* PRCM_MPU clockdomain register offsets (from instance start) */ 461a9f5e89SBenoit Cousson #define OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS 0x0018 471a9f5e89SBenoit Cousson #define OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS 0x0018 48e4156ee5SPaul Walmsley 49e4156ee5SPaul Walmsley 50d198b514SPaul Walmsley /* 51d198b514SPaul Walmsley * PRCM_MPU 52d198b514SPaul Walmsley * 53d198b514SPaul Walmsley * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global) 54d198b514SPaul Walmsley * point of view the PRCM_MPU is a single entity. It shares the same 55d198b514SPaul Walmsley * programming model as the global PRCM and thus can be assimilate as two new 56d198b514SPaul Walmsley * MOD inside the PRCM 57d198b514SPaul Walmsley */ 58d198b514SPaul Walmsley 59d198b514SPaul Walmsley /* PRCM_MPU.OCP_SOCKET_PRCM register offsets */ 60d198b514SPaul Walmsley #define OMAP4_REVISION_PRCM_OFFSET 0x0000 61cdb54c44SPaul Walmsley #define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000) 62d198b514SPaul Walmsley 63d198b514SPaul Walmsley /* PRCM_MPU.DEVICE_PRM register offsets */ 64d198b514SPaul Walmsley #define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000 65cdb54c44SPaul Walmsley #define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000) 66d198b514SPaul Walmsley #define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004 67cdb54c44SPaul Walmsley #define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004) 68d198b514SPaul Walmsley 69d198b514SPaul Walmsley /* PRCM_MPU.CPU0 register offsets */ 70d198b514SPaul Walmsley #define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000 71cdb54c44SPaul Walmsley #define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000) 72d198b514SPaul Walmsley #define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004 73cdb54c44SPaul Walmsley #define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004) 74d198b514SPaul Walmsley #define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008 75cdb54c44SPaul Walmsley #define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008) 76d198b514SPaul Walmsley #define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c 77cdb54c44SPaul Walmsley #define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c) 78d198b514SPaul Walmsley #define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010 79cdb54c44SPaul Walmsley #define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010) 80d198b514SPaul Walmsley #define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014 81cdb54c44SPaul Walmsley #define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014) 82d198b514SPaul Walmsley #define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018 83cdb54c44SPaul Walmsley #define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018) 84d198b514SPaul Walmsley 85d198b514SPaul Walmsley /* PRCM_MPU.CPU1 register offsets */ 86d198b514SPaul Walmsley #define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000 87cdb54c44SPaul Walmsley #define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000) 88d198b514SPaul Walmsley #define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004 89cdb54c44SPaul Walmsley #define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004) 90d198b514SPaul Walmsley #define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008 91cdb54c44SPaul Walmsley #define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008) 92d198b514SPaul Walmsley #define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c 93cdb54c44SPaul Walmsley #define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c) 94d198b514SPaul Walmsley #define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010 95cdb54c44SPaul Walmsley #define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010) 96d198b514SPaul Walmsley #define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014 97cdb54c44SPaul Walmsley #define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014) 98d198b514SPaul Walmsley #define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018 99cdb54c44SPaul Walmsley #define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018) 100d198b514SPaul Walmsley 1012ace831fSPaul Walmsley /* Function prototypes */ 1022ace831fSPaul Walmsley # ifndef __ASSEMBLER__ 1032ace831fSPaul Walmsley extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx); 1042ace831fSPaul Walmsley extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx); 1052ace831fSPaul Walmsley extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, 1062ace831fSPaul Walmsley s16 idx); 107d9a16f9aSPaul Walmsley extern void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu); 1082ace831fSPaul Walmsley # endif 1092ace831fSPaul Walmsley 110d198b514SPaul Walmsley #endif 111