1 /* 2 * AM43x PRCM defines 3 * 4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 * This file is licensed under the terms of the GNU General Public License 7 * version 2. This program is licensed "as is" without any warranty of any 8 * kind, whether express or implied. 9 */ 10 11 #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H 12 #define __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H 13 14 #define AM43XX_PRM_PARTITION 1 15 #define AM43XX_CM_PARTITION 1 16 17 /* PRM instances */ 18 #define AM43XX_PRM_OCP_SOCKET_INST 0x0000 19 #define AM43XX_PRM_MPU_INST 0x0300 20 #define AM43XX_PRM_GFX_INST 0x0400 21 #define AM43XX_PRM_RTC_INST 0x0500 22 #define AM43XX_PRM_TAMPER_INST 0x0600 23 #define AM43XX_PRM_CEFUSE_INST 0x0700 24 #define AM43XX_PRM_PER_INST 0x0800 25 #define AM43XX_PRM_WKUP_INST 0x2000 26 #define AM43XX_PRM_DEVICE_INST 0x4000 27 28 /* PRM_IRQ offsets */ 29 #define AM43XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004 30 #define AM43XX_PRM_IRQENABLE_MPU_OFFSET 0x0008 31 32 /* Other PRM offsets */ 33 #define AM43XX_PRM_IO_PMCTRL_OFFSET 0x0024 34 35 /* RM RSTCTRL offsets */ 36 #define AM43XX_RM_PER_RSTCTRL_OFFSET 0x0010 37 #define AM43XX_RM_GFX_RSTCTRL_OFFSET 0x0010 38 #define AM43XX_RM_WKUP_RSTCTRL_OFFSET 0x0010 39 40 /* RM RSTST offsets */ 41 #define AM43XX_RM_GFX_RSTST_OFFSET 0x0014 42 #define AM43XX_RM_PER_RSTST_OFFSET 0x0014 43 #define AM43XX_RM_WKUP_RSTST_OFFSET 0x0014 44 45 /* CM instances */ 46 #define AM43XX_CM_WKUP_INST 0x2800 47 #define AM43XX_CM_DEVICE_INST 0x4100 48 #define AM43XX_CM_DPLL_INST 0x4200 49 #define AM43XX_CM_MPU_INST 0x8300 50 #define AM43XX_CM_GFX_INST 0x8400 51 #define AM43XX_CM_RTC_INST 0x8500 52 #define AM43XX_CM_TAMPER_INST 0x8600 53 #define AM43XX_CM_CEFUSE_INST 0x8700 54 #define AM43XX_CM_PER_INST 0x8800 55 56 /* CD offsets */ 57 #define AM43XX_CM_WKUP_L3_AON_CDOFFS 0x0000 58 #define AM43XX_CM_WKUP_L3S_TSC_CDOFFS 0x0100 59 #define AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS 0x0200 60 #define AM43XX_CM_WKUP_WKUP_CDOFFS 0x0300 61 #define AM43XX_CM_MPU_MPU_CDOFFS 0x0000 62 #define AM43XX_CM_GFX_GFX_L3_CDOFFS 0x0000 63 #define AM43XX_CM_RTC_RTC_CDOFFS 0x0000 64 #define AM43XX_CM_TAMPER_TAMPER_CDOFFS 0x0000 65 #define AM43XX_CM_CEFUSE_CEFUSE_CDOFFS 0x0000 66 #define AM43XX_CM_PER_L3_CDOFFS 0x0000 67 #define AM43XX_CM_PER_L3S_CDOFFS 0x0200 68 #define AM43XX_CM_PER_ICSS_CDOFFS 0x0300 69 #define AM43XX_CM_PER_L4LS_CDOFFS 0x0400 70 #define AM43XX_CM_PER_EMIF_CDOFFS 0x0700 71 #define AM43XX_CM_PER_DSS_CDOFFS 0x0a00 72 #define AM43XX_CM_PER_CPSW_CDOFFS 0x0b00 73 #define AM43XX_CM_PER_OCPWP_L3_CDOFFS 0x0c00 74 75 /* CLK CTRL offsets */ 76 #define AM43XX_CM_PER_UART1_CLKCTRL_OFFSET 0x0580 77 #define AM43XX_CM_PER_UART2_CLKCTRL_OFFSET 0x0588 78 #define AM43XX_CM_PER_UART3_CLKCTRL_OFFSET 0x0590 79 #define AM43XX_CM_PER_UART4_CLKCTRL_OFFSET 0x0598 80 #define AM43XX_CM_PER_UART5_CLKCTRL_OFFSET 0x05a0 81 #define AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET 0x0428 82 #define AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET 0x0430 83 #define AM43XX_CM_PER_ELM_CLKCTRL_OFFSET 0x0468 84 #define AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET 0x0438 85 #define AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET 0x0440 86 #define AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET 0x0448 87 #define AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET 0x0478 88 #define AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET 0x0480 89 #define AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET 0x0488 90 #define AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET 0x04a8 91 #define AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET 0x04b0 92 #define AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET 0x04b8 93 #define AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET 0x04c0 94 #define AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET 0x04c8 95 #define AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET 0x0500 96 #define AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET 0x0508 97 #define AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET 0x0528 98 #define AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET 0x0530 99 #define AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET 0x0538 100 #define AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET 0x0540 101 #define AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET 0x0548 102 #define AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET 0x0550 103 #define AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET 0x0558 104 #define AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET 0x0228 105 #define AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET 0x0360 106 #define AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET 0x0350 107 #define AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET 0x0358 108 #define AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET 0x0348 109 #define AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x0328 110 #define AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET 0x0340 111 #define AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET 0x0368 112 #define AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET 0x0120 113 #define AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x0338 114 #define AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x0220 115 #define AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET 0x0020 116 #define AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET 0x0248 117 #define AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET 0x0258 118 #define AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET 0x0220 119 #define AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET 0x0238 120 #define AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET 0x0240 121 #define AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET 0x0420 122 #define AM43XX_CM_PER_L3_CLKCTRL_OFFSET 0x0020 123 #define AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET 0x0078 124 #define AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET 0x0080 125 #define AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET 0x0088 126 #define AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET 0x0090 127 #define AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET 0x0b20 128 #define AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET 0x0320 129 #define AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020 130 #define AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET 0x00a0 131 #define AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 132 #define AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET 0x0040 133 #define AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET 0x0050 134 #define AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET 0x0058 135 #define AM43XX_CM_PER_AES0_CLKCTRL_OFFSET 0x0028 136 #define AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET 0x0560 137 #define AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET 0x0568 138 #define AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET 0x0570 139 #define AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET 0x0578 140 #define AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET 0x0230 141 #define AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET 0x0450 142 #define AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET 0x0458 143 #define AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET 0x0460 144 #define AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET 0x0510 145 #define AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET 0x0518 146 #define AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET 0x0520 147 #define AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET 0x0490 148 #define AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET 0x0498 149 #define AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET 0x0260 150 #define AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET 0x05B8 151 #define AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET 0x0268 152 #define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET 0x05C0 153 #define AM43XX_CM_PER_DSS_CLKCTRL_OFFSET 0x0a20 154 #define AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET 0x04a0 155 #define AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET 0x0068 156 #define AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET 0x0070 157 #define AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET 0x0720 158 159 #endif 160