137fbc27eSAfzal Mohammed /* 237fbc27eSAfzal Mohammed * AM43x PRCM defines 337fbc27eSAfzal Mohammed * 437fbc27eSAfzal Mohammed * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 537fbc27eSAfzal Mohammed * 637fbc27eSAfzal Mohammed * This file is licensed under the terms of the GNU General Public License 737fbc27eSAfzal Mohammed * version 2. This program is licensed "as is" without any warranty of any 837fbc27eSAfzal Mohammed * kind, whether express or implied. 937fbc27eSAfzal Mohammed */ 1037fbc27eSAfzal Mohammed 1137fbc27eSAfzal Mohammed #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H 1237fbc27eSAfzal Mohammed #define __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H 1337fbc27eSAfzal Mohammed 1437fbc27eSAfzal Mohammed #define AM43XX_PRM_PARTITION 1 1537fbc27eSAfzal Mohammed #define AM43XX_CM_PARTITION 1 1637fbc27eSAfzal Mohammed 1737fbc27eSAfzal Mohammed /* PRM instances */ 1837fbc27eSAfzal Mohammed #define AM43XX_PRM_OCP_SOCKET_INST 0x0000 1937fbc27eSAfzal Mohammed #define AM43XX_PRM_MPU_INST 0x0300 2037fbc27eSAfzal Mohammed #define AM43XX_PRM_GFX_INST 0x0400 2137fbc27eSAfzal Mohammed #define AM43XX_PRM_RTC_INST 0x0500 2237fbc27eSAfzal Mohammed #define AM43XX_PRM_TAMPER_INST 0x0600 2337fbc27eSAfzal Mohammed #define AM43XX_PRM_CEFUSE_INST 0x0700 2437fbc27eSAfzal Mohammed #define AM43XX_PRM_PER_INST 0x0800 2537fbc27eSAfzal Mohammed #define AM43XX_PRM_WKUP_INST 0x2000 2637fbc27eSAfzal Mohammed #define AM43XX_PRM_DEVICE_INST 0x4000 2737fbc27eSAfzal Mohammed 2837fbc27eSAfzal Mohammed /* RM RSTCTRL offsets */ 2937fbc27eSAfzal Mohammed #define AM43XX_RM_PER_RSTCTRL_OFFSET 0x0010 3037fbc27eSAfzal Mohammed #define AM43XX_RM_GFX_RSTCTRL_OFFSET 0x0010 3137fbc27eSAfzal Mohammed #define AM43XX_RM_WKUP_RSTCTRL_OFFSET 0x0010 3237fbc27eSAfzal Mohammed 3337fbc27eSAfzal Mohammed /* RM RSTST offsets */ 3437fbc27eSAfzal Mohammed #define AM43XX_RM_GFX_RSTST_OFFSET 0x0014 3537fbc27eSAfzal Mohammed #define AM43XX_RM_WKUP_RSTST_OFFSET 0x0014 3637fbc27eSAfzal Mohammed 3737fbc27eSAfzal Mohammed /* CM instances */ 3837fbc27eSAfzal Mohammed #define AM43XX_CM_WKUP_INST 0x2800 3937fbc27eSAfzal Mohammed #define AM43XX_CM_DEVICE_INST 0x4100 4037fbc27eSAfzal Mohammed #define AM43XX_CM_DPLL_INST 0x4200 4137fbc27eSAfzal Mohammed #define AM43XX_CM_MPU_INST 0x8300 4237fbc27eSAfzal Mohammed #define AM43XX_CM_GFX_INST 0x8400 4337fbc27eSAfzal Mohammed #define AM43XX_CM_RTC_INST 0x8500 4437fbc27eSAfzal Mohammed #define AM43XX_CM_TAMPER_INST 0x8600 4537fbc27eSAfzal Mohammed #define AM43XX_CM_CEFUSE_INST 0x8700 4637fbc27eSAfzal Mohammed #define AM43XX_CM_PER_INST 0x8800 4737fbc27eSAfzal Mohammed 4837fbc27eSAfzal Mohammed /* CD offsets */ 4937fbc27eSAfzal Mohammed #define AM43XX_CM_WKUP_L3_AON_CDOFFS 0x0000 5037fbc27eSAfzal Mohammed #define AM43XX_CM_WKUP_L3S_TSC_CDOFFS 0x0100 5137fbc27eSAfzal Mohammed #define AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS 0x0200 5237fbc27eSAfzal Mohammed #define AM43XX_CM_WKUP_WKUP_CDOFFS 0x0300 5337fbc27eSAfzal Mohammed #define AM43XX_CM_MPU_MPU_CDOFFS 0x0000 5437fbc27eSAfzal Mohammed #define AM43XX_CM_GFX_GFX_L3_CDOFFS 0x0000 5537fbc27eSAfzal Mohammed #define AM43XX_CM_RTC_RTC_CDOFFS 0x0000 5637fbc27eSAfzal Mohammed #define AM43XX_CM_TAMPER_TAMPER_CDOFFS 0x0000 5737fbc27eSAfzal Mohammed #define AM43XX_CM_CEFUSE_CEFUSE_CDOFFS 0x0000 5837fbc27eSAfzal Mohammed #define AM43XX_CM_PER_L3_CDOFFS 0x0000 5937fbc27eSAfzal Mohammed #define AM43XX_CM_PER_L3S_CDOFFS 0x0200 6037fbc27eSAfzal Mohammed #define AM43XX_CM_PER_ICSS_CDOFFS 0x0300 6137fbc27eSAfzal Mohammed #define AM43XX_CM_PER_L4LS_CDOFFS 0x0400 6237fbc27eSAfzal Mohammed #define AM43XX_CM_PER_EMIF_CDOFFS 0x0700 6337fbc27eSAfzal Mohammed #define AM43XX_CM_PER_DSS_CDOFFS 0x0a00 6437fbc27eSAfzal Mohammed #define AM43XX_CM_PER_CPSW_CDOFFS 0x0b00 6537fbc27eSAfzal Mohammed #define AM43XX_CM_PER_OCPWP_L3_CDOFFS 0x0c00 6637fbc27eSAfzal Mohammed 6737fbc27eSAfzal Mohammed /* CLK CTRL offsets */ 6837fbc27eSAfzal Mohammed #define AM43XX_CM_PER_UART1_CLKCTRL_OFFSET 0x0580 6937fbc27eSAfzal Mohammed #define AM43XX_CM_PER_UART2_CLKCTRL_OFFSET 0x0588 7037fbc27eSAfzal Mohammed #define AM43XX_CM_PER_UART3_CLKCTRL_OFFSET 0x0590 7137fbc27eSAfzal Mohammed #define AM43XX_CM_PER_UART4_CLKCTRL_OFFSET 0x0598 7237fbc27eSAfzal Mohammed #define AM43XX_CM_PER_UART5_CLKCTRL_OFFSET 0x05a0 7337fbc27eSAfzal Mohammed #define AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET 0x0428 7437fbc27eSAfzal Mohammed #define AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET 0x0430 7537fbc27eSAfzal Mohammed #define AM43XX_CM_PER_ELM_CLKCTRL_OFFSET 0x0468 7637fbc27eSAfzal Mohammed #define AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET 0x0438 7737fbc27eSAfzal Mohammed #define AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET 0x0440 7837fbc27eSAfzal Mohammed #define AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET 0x0448 7937fbc27eSAfzal Mohammed #define AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET 0x0478 8037fbc27eSAfzal Mohammed #define AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET 0x0480 8137fbc27eSAfzal Mohammed #define AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET 0x0488 8237fbc27eSAfzal Mohammed #define AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET 0x04a8 8337fbc27eSAfzal Mohammed #define AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET 0x04b0 8437fbc27eSAfzal Mohammed #define AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET 0x04b8 8537fbc27eSAfzal Mohammed #define AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET 0x04c0 8637fbc27eSAfzal Mohammed #define AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET 0x04c8 8737fbc27eSAfzal Mohammed #define AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET 0x0500 8837fbc27eSAfzal Mohammed #define AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET 0x0508 8937fbc27eSAfzal Mohammed #define AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET 0x0528 9037fbc27eSAfzal Mohammed #define AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET 0x0530 9137fbc27eSAfzal Mohammed #define AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET 0x0538 9237fbc27eSAfzal Mohammed #define AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET 0x0540 9337fbc27eSAfzal Mohammed #define AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET 0x0548 9437fbc27eSAfzal Mohammed #define AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET 0x0550 9537fbc27eSAfzal Mohammed #define AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET 0x0558 9637fbc27eSAfzal Mohammed #define AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET 0x0228 9737fbc27eSAfzal Mohammed #define AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET 0x0360 9837fbc27eSAfzal Mohammed #define AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET 0x0350 9937fbc27eSAfzal Mohammed #define AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET 0x0358 10037fbc27eSAfzal Mohammed #define AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET 0x0348 10137fbc27eSAfzal Mohammed #define AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x0328 10237fbc27eSAfzal Mohammed #define AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET 0x0340 10337fbc27eSAfzal Mohammed #define AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET 0x0368 10437fbc27eSAfzal Mohammed #define AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET 0x0120 10537fbc27eSAfzal Mohammed #define AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x0338 10637fbc27eSAfzal Mohammed #define AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x0220 10737fbc27eSAfzal Mohammed #define AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET 0x0020 10837fbc27eSAfzal Mohammed #define AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET 0x0248 10970b0d5f5SSourav Poddar #define AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET 0x0258 11037fbc27eSAfzal Mohammed #define AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET 0x0220 11137fbc27eSAfzal Mohammed #define AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET 0x0238 11237fbc27eSAfzal Mohammed #define AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET 0x0240 11337fbc27eSAfzal Mohammed #define AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET 0x0420 11437fbc27eSAfzal Mohammed #define AM43XX_CM_PER_L3_CLKCTRL_OFFSET 0x0020 11537fbc27eSAfzal Mohammed #define AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET 0x0078 11637fbc27eSAfzal Mohammed #define AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET 0x0080 11737fbc27eSAfzal Mohammed #define AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET 0x0088 11837fbc27eSAfzal Mohammed #define AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET 0x0090 11937fbc27eSAfzal Mohammed #define AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET 0x0b20 12037fbc27eSAfzal Mohammed #define AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET 0x0320 12137fbc27eSAfzal Mohammed #define AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020 12237fbc27eSAfzal Mohammed #define AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET 0x00a0 12337fbc27eSAfzal Mohammed #define AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 12437fbc27eSAfzal Mohammed #define AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET 0x0040 12537fbc27eSAfzal Mohammed #define AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET 0x0050 12637fbc27eSAfzal Mohammed #define AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET 0x0058 12737fbc27eSAfzal Mohammed #define AM43XX_CM_PER_AES0_CLKCTRL_OFFSET 0x0028 12837fbc27eSAfzal Mohammed #define AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET 0x0560 12937fbc27eSAfzal Mohammed #define AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET 0x0568 13037fbc27eSAfzal Mohammed #define AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET 0x0570 13137fbc27eSAfzal Mohammed #define AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET 0x0578 13237fbc27eSAfzal Mohammed #define AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET 0x0230 13337fbc27eSAfzal Mohammed #define AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET 0x0450 13437fbc27eSAfzal Mohammed #define AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET 0x0458 13537fbc27eSAfzal Mohammed #define AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET 0x0460 13637fbc27eSAfzal Mohammed #define AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET 0x0510 13737fbc27eSAfzal Mohammed #define AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET 0x0518 13837fbc27eSAfzal Mohammed #define AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET 0x0520 13937fbc27eSAfzal Mohammed #define AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET 0x0490 14037fbc27eSAfzal Mohammed #define AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET 0x0498 141facfbc49SGeorge Cherian #define AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET 0x0260 142facfbc49SGeorge Cherian #define AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET 0x05B8 143facfbc49SGeorge Cherian #define AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET 0x0268 144facfbc49SGeorge Cherian #define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET 0x05C0 145509efaf3SSathya Prakash M R #define AM43XX_CM_PER_DSS_CLKCTRL_OFFSET 0x0a20 14637fbc27eSAfzal Mohammed 14737fbc27eSAfzal Mohammed #endif 148