1 #ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H 2 #define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H 3 4 /* 5 * OMAP2/3 PRCM base and module definitions 6 * 7 * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc. 8 * Copyright (C) 2007-2009 Nokia Corporation 9 * 10 * Written by Paul Walmsley 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 as 14 * published by the Free Software Foundation. 15 */ 16 17 /* Module offsets from both CM_BASE & PRM_BASE */ 18 19 /* 20 * Offsets that are the same on 24xx and 34xx 21 * 22 * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is 23 * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2. 24 */ 25 #define OCP_MOD 0x000 26 #define MPU_MOD 0x100 27 #define CORE_MOD 0x200 28 #define GFX_MOD 0x300 29 #define WKUP_MOD 0x400 30 #define PLL_MOD 0x500 31 32 33 /* Chip-specific module offsets */ 34 #define OMAP24XX_GR_MOD OCP_MOD 35 #define OMAP24XX_DSP_MOD 0x800 36 37 #define OMAP2430_MDM_MOD 0xc00 38 39 /* IVA2 module is < base on 3430 */ 40 #define OMAP3430_IVA2_MOD -0x800 41 #define OMAP3430ES2_SGX_MOD GFX_MOD 42 #define OMAP3430_CCR_MOD PLL_MOD 43 #define OMAP3430_DSS_MOD 0x600 44 #define OMAP3430_CAM_MOD 0x700 45 #define OMAP3430_PER_MOD 0x800 46 #define OMAP3430_EMU_MOD 0x900 47 #define OMAP3430_GR_MOD 0xa00 48 #define OMAP3430_NEON_MOD 0xb00 49 #define OMAP3430ES2_USBHOST_MOD 0xc00 50 51 /* 52 * TI81XX PRM module offsets 53 */ 54 #define TI81XX_PRM_DEVICE_MOD 0x0000 55 #define TI816X_PRM_ACTIVE_MOD 0x0a00 56 #define TI81XX_PRM_DEFAULT_MOD 0x0b00 57 #define TI816X_PRM_IVAHD0_MOD 0x0c00 58 #define TI816X_PRM_IVAHD1_MOD 0x0d00 59 #define TI816X_PRM_IVAHD2_MOD 0x0e00 60 #define TI816X_PRM_SGX_MOD 0x0f00 61 #define TI81XX_PRM_ALWON_MOD 0x1800 62 63 /* 24XX register bits shared between CM & PRM registers */ 64 65 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ 66 #define OMAP2420_EN_MMC_SHIFT 26 67 #define OMAP2420_EN_MMC_MASK (1 << 26) 68 #define OMAP24XX_EN_UART2_SHIFT 22 69 #define OMAP24XX_EN_UART2_MASK (1 << 22) 70 #define OMAP24XX_EN_UART1_SHIFT 21 71 #define OMAP24XX_EN_UART1_MASK (1 << 21) 72 #define OMAP24XX_EN_MCSPI2_SHIFT 18 73 #define OMAP24XX_EN_MCSPI2_MASK (1 << 18) 74 #define OMAP24XX_EN_MCSPI1_SHIFT 17 75 #define OMAP24XX_EN_MCSPI1_MASK (1 << 17) 76 #define OMAP24XX_EN_MCBSP2_SHIFT 16 77 #define OMAP24XX_EN_MCBSP2_MASK (1 << 16) 78 #define OMAP24XX_EN_MCBSP1_SHIFT 15 79 #define OMAP24XX_EN_MCBSP1_MASK (1 << 15) 80 #define OMAP24XX_EN_GPT12_SHIFT 14 81 #define OMAP24XX_EN_GPT12_MASK (1 << 14) 82 #define OMAP24XX_EN_GPT11_SHIFT 13 83 #define OMAP24XX_EN_GPT11_MASK (1 << 13) 84 #define OMAP24XX_EN_GPT10_SHIFT 12 85 #define OMAP24XX_EN_GPT10_MASK (1 << 12) 86 #define OMAP24XX_EN_GPT9_SHIFT 11 87 #define OMAP24XX_EN_GPT9_MASK (1 << 11) 88 #define OMAP24XX_EN_GPT8_SHIFT 10 89 #define OMAP24XX_EN_GPT8_MASK (1 << 10) 90 #define OMAP24XX_EN_GPT7_SHIFT 9 91 #define OMAP24XX_EN_GPT7_MASK (1 << 9) 92 #define OMAP24XX_EN_GPT6_SHIFT 8 93 #define OMAP24XX_EN_GPT6_MASK (1 << 8) 94 #define OMAP24XX_EN_GPT5_SHIFT 7 95 #define OMAP24XX_EN_GPT5_MASK (1 << 7) 96 #define OMAP24XX_EN_GPT4_SHIFT 6 97 #define OMAP24XX_EN_GPT4_MASK (1 << 6) 98 #define OMAP24XX_EN_GPT3_SHIFT 5 99 #define OMAP24XX_EN_GPT3_MASK (1 << 5) 100 #define OMAP24XX_EN_GPT2_SHIFT 4 101 #define OMAP24XX_EN_GPT2_MASK (1 << 4) 102 #define OMAP2420_EN_VLYNQ_SHIFT 3 103 #define OMAP2420_EN_VLYNQ_MASK (1 << 3) 104 105 /* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ 106 #define OMAP2430_EN_GPIO5_SHIFT 10 107 #define OMAP2430_EN_GPIO5_MASK (1 << 10) 108 #define OMAP2430_EN_MCSPI3_SHIFT 9 109 #define OMAP2430_EN_MCSPI3_MASK (1 << 9) 110 #define OMAP2430_EN_MMCHS2_SHIFT 8 111 #define OMAP2430_EN_MMCHS2_MASK (1 << 8) 112 #define OMAP2430_EN_MMCHS1_SHIFT 7 113 #define OMAP2430_EN_MMCHS1_MASK (1 << 7) 114 #define OMAP24XX_EN_UART3_SHIFT 2 115 #define OMAP24XX_EN_UART3_MASK (1 << 2) 116 #define OMAP24XX_EN_USB_SHIFT 0 117 #define OMAP24XX_EN_USB_MASK (1 << 0) 118 119 /* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ 120 #define OMAP2430_EN_MDM_INTC_SHIFT 11 121 #define OMAP2430_EN_MDM_INTC_MASK (1 << 11) 122 #define OMAP2430_EN_USBHS_SHIFT 6 123 #define OMAP2430_EN_USBHS_MASK (1 << 6) 124 #define OMAP24XX_EN_GPMC_SHIFT 1 125 #define OMAP24XX_EN_GPMC_MASK (1 << 1) 126 127 /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */ 128 #define OMAP2420_ST_MMC_SHIFT 26 129 #define OMAP2420_ST_MMC_MASK (1 << 26) 130 #define OMAP24XX_ST_UART2_SHIFT 22 131 #define OMAP24XX_ST_UART2_MASK (1 << 22) 132 #define OMAP24XX_ST_UART1_SHIFT 21 133 #define OMAP24XX_ST_UART1_MASK (1 << 21) 134 #define OMAP24XX_ST_MCSPI2_SHIFT 18 135 #define OMAP24XX_ST_MCSPI2_MASK (1 << 18) 136 #define OMAP24XX_ST_MCSPI1_SHIFT 17 137 #define OMAP24XX_ST_MCSPI1_MASK (1 << 17) 138 #define OMAP24XX_ST_MCBSP2_SHIFT 16 139 #define OMAP24XX_ST_MCBSP2_MASK (1 << 16) 140 #define OMAP24XX_ST_MCBSP1_SHIFT 15 141 #define OMAP24XX_ST_MCBSP1_MASK (1 << 15) 142 #define OMAP24XX_ST_GPT12_SHIFT 14 143 #define OMAP24XX_ST_GPT12_MASK (1 << 14) 144 #define OMAP24XX_ST_GPT11_SHIFT 13 145 #define OMAP24XX_ST_GPT11_MASK (1 << 13) 146 #define OMAP24XX_ST_GPT10_SHIFT 12 147 #define OMAP24XX_ST_GPT10_MASK (1 << 12) 148 #define OMAP24XX_ST_GPT9_SHIFT 11 149 #define OMAP24XX_ST_GPT9_MASK (1 << 11) 150 #define OMAP24XX_ST_GPT8_SHIFT 10 151 #define OMAP24XX_ST_GPT8_MASK (1 << 10) 152 #define OMAP24XX_ST_GPT7_SHIFT 9 153 #define OMAP24XX_ST_GPT7_MASK (1 << 9) 154 #define OMAP24XX_ST_GPT6_SHIFT 8 155 #define OMAP24XX_ST_GPT6_MASK (1 << 8) 156 #define OMAP24XX_ST_GPT5_SHIFT 7 157 #define OMAP24XX_ST_GPT5_MASK (1 << 7) 158 #define OMAP24XX_ST_GPT4_SHIFT 6 159 #define OMAP24XX_ST_GPT4_MASK (1 << 6) 160 #define OMAP24XX_ST_GPT3_SHIFT 5 161 #define OMAP24XX_ST_GPT3_MASK (1 << 5) 162 #define OMAP24XX_ST_GPT2_SHIFT 4 163 #define OMAP24XX_ST_GPT2_MASK (1 << 4) 164 #define OMAP2420_ST_VLYNQ_SHIFT 3 165 #define OMAP2420_ST_VLYNQ_MASK (1 << 3) 166 167 /* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */ 168 #define OMAP2430_ST_MDM_INTC_SHIFT 11 169 #define OMAP2430_ST_MDM_INTC_MASK (1 << 11) 170 #define OMAP2430_ST_GPIO5_SHIFT 10 171 #define OMAP2430_ST_GPIO5_MASK (1 << 10) 172 #define OMAP2430_ST_MCSPI3_SHIFT 9 173 #define OMAP2430_ST_MCSPI3_MASK (1 << 9) 174 #define OMAP2430_ST_MMCHS2_SHIFT 8 175 #define OMAP2430_ST_MMCHS2_MASK (1 << 8) 176 #define OMAP2430_ST_MMCHS1_SHIFT 7 177 #define OMAP2430_ST_MMCHS1_MASK (1 << 7) 178 #define OMAP2430_ST_USBHS_SHIFT 6 179 #define OMAP2430_ST_USBHS_MASK (1 << 6) 180 #define OMAP24XX_ST_UART3_SHIFT 2 181 #define OMAP24XX_ST_UART3_MASK (1 << 2) 182 #define OMAP24XX_ST_USB_SHIFT 0 183 #define OMAP24XX_ST_USB_MASK (1 << 0) 184 185 /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ 186 #define OMAP24XX_EN_GPIOS_SHIFT 2 187 #define OMAP24XX_EN_GPIOS_MASK (1 << 2) 188 #define OMAP24XX_EN_GPT1_SHIFT 0 189 #define OMAP24XX_EN_GPT1_MASK (1 << 0) 190 191 /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */ 192 #define OMAP24XX_ST_GPIOS_SHIFT 2 193 #define OMAP24XX_ST_GPIOS_MASK (1 << 2) 194 #define OMAP24XX_ST_32KSYNC_SHIFT 1 195 #define OMAP24XX_ST_32KSYNC_MASK (1 << 1) 196 #define OMAP24XX_ST_GPT1_SHIFT 0 197 #define OMAP24XX_ST_GPT1_MASK (1 << 0) 198 199 /* CM_IDLEST_MDM and PM_WKST_MDM shared bits */ 200 #define OMAP2430_ST_MDM_SHIFT 0 201 #define OMAP2430_ST_MDM_MASK (1 << 0) 202 203 204 /* 3430 register bits shared between CM & PRM registers */ 205 206 /* CM_REVISION, PRM_REVISION shared bits */ 207 #define OMAP3430_REV_SHIFT 0 208 #define OMAP3430_REV_MASK (0xff << 0) 209 210 /* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */ 211 #define OMAP3430_AUTOIDLE_MASK (1 << 0) 212 213 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ 214 #define OMAP3430_EN_MMC3_MASK (1 << 30) 215 #define OMAP3430_EN_MMC3_SHIFT 30 216 #define OMAP3430_EN_MMC2_MASK (1 << 25) 217 #define OMAP3430_EN_MMC2_SHIFT 25 218 #define OMAP3430_EN_MMC1_MASK (1 << 24) 219 #define OMAP3430_EN_MMC1_SHIFT 24 220 #define AM35XX_EN_UART4_MASK (1 << 23) 221 #define AM35XX_EN_UART4_SHIFT 23 222 #define OMAP3430_EN_MCSPI4_MASK (1 << 21) 223 #define OMAP3430_EN_MCSPI4_SHIFT 21 224 #define OMAP3430_EN_MCSPI3_MASK (1 << 20) 225 #define OMAP3430_EN_MCSPI3_SHIFT 20 226 #define OMAP3430_EN_MCSPI2_MASK (1 << 19) 227 #define OMAP3430_EN_MCSPI2_SHIFT 19 228 #define OMAP3430_EN_MCSPI1_MASK (1 << 18) 229 #define OMAP3430_EN_MCSPI1_SHIFT 18 230 #define OMAP3430_EN_I2C3_MASK (1 << 17) 231 #define OMAP3430_EN_I2C3_SHIFT 17 232 #define OMAP3430_EN_I2C2_MASK (1 << 16) 233 #define OMAP3430_EN_I2C2_SHIFT 16 234 #define OMAP3430_EN_I2C1_MASK (1 << 15) 235 #define OMAP3430_EN_I2C1_SHIFT 15 236 #define OMAP3430_EN_UART2_MASK (1 << 14) 237 #define OMAP3430_EN_UART2_SHIFT 14 238 #define OMAP3430_EN_UART1_MASK (1 << 13) 239 #define OMAP3430_EN_UART1_SHIFT 13 240 #define OMAP3430_EN_GPT11_MASK (1 << 12) 241 #define OMAP3430_EN_GPT11_SHIFT 12 242 #define OMAP3430_EN_GPT10_MASK (1 << 11) 243 #define OMAP3430_EN_GPT10_SHIFT 11 244 #define OMAP3430_EN_MCBSP5_MASK (1 << 10) 245 #define OMAP3430_EN_MCBSP5_SHIFT 10 246 #define OMAP3430_EN_MCBSP1_MASK (1 << 9) 247 #define OMAP3430_EN_MCBSP1_SHIFT 9 248 #define OMAP3430_EN_FSHOSTUSB_MASK (1 << 5) 249 #define OMAP3430_EN_FSHOSTUSB_SHIFT 5 250 #define OMAP3430_EN_D2D_MASK (1 << 3) 251 #define OMAP3430_EN_D2D_SHIFT 3 252 253 /* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ 254 #define OMAP3430_EN_HSOTGUSB_MASK (1 << 4) 255 #define OMAP3430_EN_HSOTGUSB_SHIFT 4 256 257 /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */ 258 #define OMAP3430_ST_MMC3_SHIFT 30 259 #define OMAP3430_ST_MMC3_MASK (1 << 30) 260 #define OMAP3430_ST_MMC2_SHIFT 25 261 #define OMAP3430_ST_MMC2_MASK (1 << 25) 262 #define OMAP3430_ST_MMC1_SHIFT 24 263 #define OMAP3430_ST_MMC1_MASK (1 << 24) 264 #define OMAP3430_ST_MCSPI4_SHIFT 21 265 #define OMAP3430_ST_MCSPI4_MASK (1 << 21) 266 #define OMAP3430_ST_MCSPI3_SHIFT 20 267 #define OMAP3430_ST_MCSPI3_MASK (1 << 20) 268 #define OMAP3430_ST_MCSPI2_SHIFT 19 269 #define OMAP3430_ST_MCSPI2_MASK (1 << 19) 270 #define OMAP3430_ST_MCSPI1_SHIFT 18 271 #define OMAP3430_ST_MCSPI1_MASK (1 << 18) 272 #define OMAP3430_ST_I2C3_SHIFT 17 273 #define OMAP3430_ST_I2C3_MASK (1 << 17) 274 #define OMAP3430_ST_I2C2_SHIFT 16 275 #define OMAP3430_ST_I2C2_MASK (1 << 16) 276 #define OMAP3430_ST_I2C1_SHIFT 15 277 #define OMAP3430_ST_I2C1_MASK (1 << 15) 278 #define OMAP3430_ST_UART2_SHIFT 14 279 #define OMAP3430_ST_UART2_MASK (1 << 14) 280 #define OMAP3430_ST_UART1_SHIFT 13 281 #define OMAP3430_ST_UART1_MASK (1 << 13) 282 #define OMAP3430_ST_GPT11_SHIFT 12 283 #define OMAP3430_ST_GPT11_MASK (1 << 12) 284 #define OMAP3430_ST_GPT10_SHIFT 11 285 #define OMAP3430_ST_GPT10_MASK (1 << 11) 286 #define OMAP3430_ST_MCBSP5_SHIFT 10 287 #define OMAP3430_ST_MCBSP5_MASK (1 << 10) 288 #define OMAP3430_ST_MCBSP1_SHIFT 9 289 #define OMAP3430_ST_MCBSP1_MASK (1 << 9) 290 #define OMAP3430ES1_ST_FSHOSTUSB_SHIFT 5 291 #define OMAP3430ES1_ST_FSHOSTUSB_MASK (1 << 5) 292 #define OMAP3430ES1_ST_HSOTGUSB_SHIFT 4 293 #define OMAP3430ES1_ST_HSOTGUSB_MASK (1 << 4) 294 #define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT 5 295 #define OMAP3430ES2_ST_HSOTGUSB_IDLE_MASK (1 << 5) 296 #define OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT 4 297 #define OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK (1 << 4) 298 #define OMAP3430_ST_D2D_SHIFT 3 299 #define OMAP3430_ST_D2D_MASK (1 << 3) 300 301 /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ 302 #define OMAP3430_EN_GPIO1_MASK (1 << 3) 303 #define OMAP3430_EN_GPIO1_SHIFT 3 304 #define OMAP3430_EN_GPT12_MASK (1 << 1) 305 #define OMAP3430_EN_GPT12_SHIFT 1 306 #define OMAP3430_EN_GPT1_MASK (1 << 0) 307 #define OMAP3430_EN_GPT1_SHIFT 0 308 309 /* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */ 310 #define OMAP3430_EN_SR2_MASK (1 << 7) 311 #define OMAP3430_EN_SR2_SHIFT 7 312 #define OMAP3430_EN_SR1_MASK (1 << 6) 313 #define OMAP3430_EN_SR1_SHIFT 6 314 315 /* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ 316 #define OMAP3430_EN_GPT12_MASK (1 << 1) 317 #define OMAP3430_EN_GPT12_SHIFT 1 318 319 /* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */ 320 #define OMAP3430_ST_SR2_SHIFT 7 321 #define OMAP3430_ST_SR2_MASK (1 << 7) 322 #define OMAP3430_ST_SR1_SHIFT 6 323 #define OMAP3430_ST_SR1_MASK (1 << 6) 324 #define OMAP3430_ST_GPIO1_SHIFT 3 325 #define OMAP3430_ST_GPIO1_MASK (1 << 3) 326 #define OMAP3430_ST_32KSYNC_SHIFT 2 327 #define OMAP3430_ST_32KSYNC_MASK (1 << 2) 328 #define OMAP3430_ST_GPT12_SHIFT 1 329 #define OMAP3430_ST_GPT12_MASK (1 << 1) 330 #define OMAP3430_ST_GPT1_SHIFT 0 331 #define OMAP3430_ST_GPT1_MASK (1 << 0) 332 333 /* 334 * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM, 335 * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX, 336 * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits 337 */ 338 #define OMAP3430_EN_MPU_MASK (1 << 1) 339 #define OMAP3430_EN_MPU_SHIFT 1 340 341 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */ 342 343 #define OMAP3630_EN_UART4_MASK (1 << 18) 344 #define OMAP3630_EN_UART4_SHIFT 18 345 #define OMAP3430_EN_GPIO6_MASK (1 << 17) 346 #define OMAP3430_EN_GPIO6_SHIFT 17 347 #define OMAP3430_EN_GPIO5_MASK (1 << 16) 348 #define OMAP3430_EN_GPIO5_SHIFT 16 349 #define OMAP3430_EN_GPIO4_MASK (1 << 15) 350 #define OMAP3430_EN_GPIO4_SHIFT 15 351 #define OMAP3430_EN_GPIO3_MASK (1 << 14) 352 #define OMAP3430_EN_GPIO3_SHIFT 14 353 #define OMAP3430_EN_GPIO2_MASK (1 << 13) 354 #define OMAP3430_EN_GPIO2_SHIFT 13 355 #define OMAP3430_EN_UART3_MASK (1 << 11) 356 #define OMAP3430_EN_UART3_SHIFT 11 357 #define OMAP3430_EN_GPT9_MASK (1 << 10) 358 #define OMAP3430_EN_GPT9_SHIFT 10 359 #define OMAP3430_EN_GPT8_MASK (1 << 9) 360 #define OMAP3430_EN_GPT8_SHIFT 9 361 #define OMAP3430_EN_GPT7_MASK (1 << 8) 362 #define OMAP3430_EN_GPT7_SHIFT 8 363 #define OMAP3430_EN_GPT6_MASK (1 << 7) 364 #define OMAP3430_EN_GPT6_SHIFT 7 365 #define OMAP3430_EN_GPT5_MASK (1 << 6) 366 #define OMAP3430_EN_GPT5_SHIFT 6 367 #define OMAP3430_EN_GPT4_MASK (1 << 5) 368 #define OMAP3430_EN_GPT4_SHIFT 5 369 #define OMAP3430_EN_GPT3_MASK (1 << 4) 370 #define OMAP3430_EN_GPT3_SHIFT 4 371 #define OMAP3430_EN_GPT2_MASK (1 << 3) 372 #define OMAP3430_EN_GPT2_SHIFT 3 373 374 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */ 375 /* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits 376 * be ST_* bits instead? */ 377 #define OMAP3430_EN_MCBSP4_MASK (1 << 2) 378 #define OMAP3430_EN_MCBSP4_SHIFT 2 379 #define OMAP3430_EN_MCBSP3_MASK (1 << 1) 380 #define OMAP3430_EN_MCBSP3_SHIFT 1 381 #define OMAP3430_EN_MCBSP2_MASK (1 << 0) 382 #define OMAP3430_EN_MCBSP2_SHIFT 0 383 384 /* CM_IDLEST_PER, PM_WKST_PER shared bits */ 385 #define OMAP3630_ST_UART4_SHIFT 18 386 #define OMAP3630_ST_UART4_MASK (1 << 18) 387 #define OMAP3430_ST_GPIO6_SHIFT 17 388 #define OMAP3430_ST_GPIO6_MASK (1 << 17) 389 #define OMAP3430_ST_GPIO5_SHIFT 16 390 #define OMAP3430_ST_GPIO5_MASK (1 << 16) 391 #define OMAP3430_ST_GPIO4_SHIFT 15 392 #define OMAP3430_ST_GPIO4_MASK (1 << 15) 393 #define OMAP3430_ST_GPIO3_SHIFT 14 394 #define OMAP3430_ST_GPIO3_MASK (1 << 14) 395 #define OMAP3430_ST_GPIO2_SHIFT 13 396 #define OMAP3430_ST_GPIO2_MASK (1 << 13) 397 #define OMAP3430_ST_UART3_SHIFT 11 398 #define OMAP3430_ST_UART3_MASK (1 << 11) 399 #define OMAP3430_ST_GPT9_SHIFT 10 400 #define OMAP3430_ST_GPT9_MASK (1 << 10) 401 #define OMAP3430_ST_GPT8_SHIFT 9 402 #define OMAP3430_ST_GPT8_MASK (1 << 9) 403 #define OMAP3430_ST_GPT7_SHIFT 8 404 #define OMAP3430_ST_GPT7_MASK (1 << 8) 405 #define OMAP3430_ST_GPT6_SHIFT 7 406 #define OMAP3430_ST_GPT6_MASK (1 << 7) 407 #define OMAP3430_ST_GPT5_SHIFT 6 408 #define OMAP3430_ST_GPT5_MASK (1 << 6) 409 #define OMAP3430_ST_GPT4_SHIFT 5 410 #define OMAP3430_ST_GPT4_MASK (1 << 5) 411 #define OMAP3430_ST_GPT3_SHIFT 4 412 #define OMAP3430_ST_GPT3_MASK (1 << 4) 413 #define OMAP3430_ST_GPT2_SHIFT 3 414 #define OMAP3430_ST_GPT2_MASK (1 << 3) 415 416 /* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */ 417 #define OMAP3430_EN_CORE_SHIFT 0 418 #define OMAP3430_EN_CORE_MASK (1 << 0) 419 420 421 422 /* 423 * Maximum time(us) it takes to output the signal WUCLKOUT of the last 424 * pad of the I/O ring after asserting WUCLKIN high. Tero measured 425 * the actual time at 7 to 8 microseconds on OMAP3 and 2 to 4 426 * microseconds on OMAP4, so this timeout may be too high. 427 */ 428 #define MAX_IOPAD_LATCH_TIME 100 429 # ifndef __ASSEMBLER__ 430 431 #include <linux/delay.h> 432 433 /** 434 * omap_test_timeout - busy-loop, testing a condition 435 * @cond: condition to test until it evaluates to true 436 * @timeout: maximum number of microseconds in the timeout 437 * @index: loop index (integer) 438 * 439 * Loop waiting for @cond to become true or until at least @timeout 440 * microseconds have passed. To use, define some integer @index in the 441 * calling code. After running, if @index == @timeout, then the loop has 442 * timed out. 443 */ 444 #define omap_test_timeout(cond, timeout, index) \ 445 ({ \ 446 for (index = 0; index < timeout; index++) { \ 447 if (cond) \ 448 break; \ 449 udelay(1); \ 450 } \ 451 }) 452 453 /** 454 * struct omap_prcm_irq - describes a PRCM interrupt bit 455 * @name: a short name describing the interrupt type, e.g. "wkup" or "io" 456 * @offset: the bit shift of the interrupt inside the IRQ{ENABLE,STATUS} regs 457 * @priority: should this interrupt be handled before @priority=false IRQs? 458 * 459 * Describes interrupt bits inside the PRM_IRQ{ENABLE,STATUS}_MPU* registers. 460 * On systems with multiple PRM MPU IRQ registers, the bitfields read from 461 * the registers are concatenated, so @offset could be > 31 on these systems - 462 * see omap_prm_irq_handler() for more details. I/O ring interrupts should 463 * have @priority set to true. 464 */ 465 struct omap_prcm_irq { 466 const char *name; 467 unsigned int offset; 468 bool priority; 469 }; 470 471 /** 472 * struct omap_prcm_irq_setup - PRCM interrupt controller details 473 * @ack: PRM register offset for the first PRM_IRQSTATUS_MPU register 474 * @mask: PRM register offset for the first PRM_IRQENABLE_MPU register 475 * @nr_regs: number of PRM_IRQ{STATUS,ENABLE}_MPU* registers 476 * @nr_irqs: number of entries in the @irqs array 477 * @irqs: ptr to an array of PRCM interrupt bits (see @nr_irqs) 478 * @irq: MPU IRQ asserted when a PRCM interrupt arrives 479 * @read_pending_irqs: fn ptr to determine if any PRCM IRQs are pending 480 * @ocp_barrier: fn ptr to force buffered PRM writes to complete 481 * @save_and_clear_irqen: fn ptr to save and clear IRQENABLE regs 482 * @restore_irqen: fn ptr to save and clear IRQENABLE regs 483 * @reconfigure_io_chain: fn ptr to reconfigure IO chain 484 * @saved_mask: IRQENABLE regs are saved here during suspend 485 * @priority_mask: 1 bit per IRQ, set to 1 if omap_prcm_irq.priority = true 486 * @base_irq: base dynamic IRQ number, returned from irq_alloc_descs() in init 487 * @suspended: set to true after Linux suspend code has called our ->prepare() 488 * @suspend_save_flag: set to true after IRQ masks have been saved and disabled 489 * 490 * @saved_mask, @priority_mask, @base_irq, @suspended, and 491 * @suspend_save_flag are populated dynamically, and are not to be 492 * specified in static initializers. 493 */ 494 struct omap_prcm_irq_setup { 495 u16 ack; 496 u16 mask; 497 u8 nr_regs; 498 u8 nr_irqs; 499 const struct omap_prcm_irq *irqs; 500 int irq; 501 unsigned int (*xlate_irq)(unsigned int); 502 void (*read_pending_irqs)(unsigned long *events); 503 void (*ocp_barrier)(void); 504 void (*save_and_clear_irqen)(u32 *saved_mask); 505 void (*restore_irqen)(u32 *saved_mask); 506 void (*reconfigure_io_chain)(void); 507 u32 *saved_mask; 508 u32 *priority_mask; 509 int base_irq; 510 bool suspended; 511 bool suspend_save_flag; 512 }; 513 514 /* OMAP_PRCM_IRQ: convenience macro for creating struct omap_prcm_irq records */ 515 #define OMAP_PRCM_IRQ(_name, _offset, _priority) { \ 516 .name = _name, \ 517 .offset = _offset, \ 518 .priority = _priority \ 519 } 520 521 /** 522 * struct omap_prcm_init_data - PRCM driver init data 523 * @index: clock memory mapping index to be used 524 * @mem: IO mem pointer for this module 525 * @offset: module base address offset from the IO base 526 * @flags: PRCM module init flags 527 * @device_inst_offset: device instance offset within the module address space 528 * @init: low level PRCM init function for this module 529 * @np: device node for this PRCM module 530 */ 531 struct omap_prcm_init_data { 532 int index; 533 void __iomem *mem; 534 s16 offset; 535 u16 flags; 536 s32 device_inst_offset; 537 int (*init)(const struct omap_prcm_init_data *data); 538 struct device_node *np; 539 }; 540 541 extern void omap_prcm_irq_cleanup(void); 542 extern int omap_prcm_register_chain_handler( 543 struct omap_prcm_irq_setup *irq_setup); 544 extern int omap_prcm_event_to_irq(const char *event); 545 extern void omap_prcm_irq_prepare(void); 546 extern void omap_prcm_irq_complete(void); 547 548 # endif 549 550 #endif 551 552