1 #ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
2 #define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
3 
4 /*
5  * OMAP2/3 PRCM base and module definitions
6  *
7  * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
8  * Copyright (C) 2007-2009 Nokia Corporation
9  *
10  * Written by Paul Walmsley
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License version 2 as
14  * published by the Free Software Foundation.
15  */
16 
17 /* Module offsets from both CM_BASE & PRM_BASE */
18 
19 /*
20  * Offsets that are the same on 24xx and 34xx
21  *
22  * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is
23  * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2.
24  */
25 #define OCP_MOD						0x000
26 #define MPU_MOD						0x100
27 #define CORE_MOD					0x200
28 #define GFX_MOD						0x300
29 #define WKUP_MOD					0x400
30 #define PLL_MOD						0x500
31 
32 
33 /* Chip-specific module offsets */
34 #define OMAP24XX_GR_MOD					OCP_MOD
35 #define OMAP24XX_DSP_MOD				0x800
36 
37 #define OMAP2430_MDM_MOD				0xc00
38 
39 /* IVA2 module is < base on 3430 */
40 #define OMAP3430_IVA2_MOD				-0x800
41 #define OMAP3430ES2_SGX_MOD				GFX_MOD
42 #define OMAP3430_CCR_MOD				PLL_MOD
43 #define OMAP3430_DSS_MOD				0x600
44 #define OMAP3430_CAM_MOD				0x700
45 #define OMAP3430_PER_MOD				0x800
46 #define OMAP3430_EMU_MOD				0x900
47 #define OMAP3430_GR_MOD					0xa00
48 #define OMAP3430_NEON_MOD				0xb00
49 #define OMAP3430ES2_USBHOST_MOD				0xc00
50 
51 /*
52  * TI81XX PRM module offsets
53  */
54 #define TI814X_PRM_DSP_MOD				0x0a00
55 #define TI814X_PRM_HDVICP_MOD				0x0c00
56 #define TI814X_PRM_ISP_MOD				0x0d00
57 #define TI814X_PRM_HDVPSS_MOD				0x0e00
58 #define TI814X_PRM_GFX_MOD				0x0f00
59 
60 #define TI81XX_PRM_DEVICE_MOD			0x0000
61 #define TI816X_PRM_ACTIVE_MOD			0x0a00
62 #define TI81XX_PRM_DEFAULT_MOD			0x0b00
63 #define TI816X_PRM_IVAHD0_MOD			0x0c00
64 #define TI816X_PRM_IVAHD1_MOD			0x0d00
65 #define TI816X_PRM_IVAHD2_MOD			0x0e00
66 #define TI816X_PRM_SGX_MOD				0x0f00
67 #define TI81XX_PRM_ALWON_MOD			0x1800
68 
69 /* 24XX register bits shared between CM & PRM registers */
70 
71 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
72 #define OMAP2420_EN_MMC_SHIFT				26
73 #define OMAP2420_EN_MMC_MASK				(1 << 26)
74 #define OMAP24XX_EN_UART2_SHIFT				22
75 #define OMAP24XX_EN_UART2_MASK				(1 << 22)
76 #define OMAP24XX_EN_UART1_SHIFT				21
77 #define OMAP24XX_EN_UART1_MASK				(1 << 21)
78 #define OMAP24XX_EN_MCSPI2_SHIFT			18
79 #define OMAP24XX_EN_MCSPI2_MASK				(1 << 18)
80 #define OMAP24XX_EN_MCSPI1_SHIFT			17
81 #define OMAP24XX_EN_MCSPI1_MASK				(1 << 17)
82 #define OMAP24XX_EN_MCBSP2_SHIFT			16
83 #define OMAP24XX_EN_MCBSP2_MASK				(1 << 16)
84 #define OMAP24XX_EN_MCBSP1_SHIFT			15
85 #define OMAP24XX_EN_MCBSP1_MASK				(1 << 15)
86 #define OMAP24XX_EN_GPT12_SHIFT				14
87 #define OMAP24XX_EN_GPT12_MASK				(1 << 14)
88 #define OMAP24XX_EN_GPT11_SHIFT				13
89 #define OMAP24XX_EN_GPT11_MASK				(1 << 13)
90 #define OMAP24XX_EN_GPT10_SHIFT				12
91 #define OMAP24XX_EN_GPT10_MASK				(1 << 12)
92 #define OMAP24XX_EN_GPT9_SHIFT				11
93 #define OMAP24XX_EN_GPT9_MASK				(1 << 11)
94 #define OMAP24XX_EN_GPT8_SHIFT				10
95 #define OMAP24XX_EN_GPT8_MASK				(1 << 10)
96 #define OMAP24XX_EN_GPT7_SHIFT				9
97 #define OMAP24XX_EN_GPT7_MASK				(1 << 9)
98 #define OMAP24XX_EN_GPT6_SHIFT				8
99 #define OMAP24XX_EN_GPT6_MASK				(1 << 8)
100 #define OMAP24XX_EN_GPT5_SHIFT				7
101 #define OMAP24XX_EN_GPT5_MASK				(1 << 7)
102 #define OMAP24XX_EN_GPT4_SHIFT				6
103 #define OMAP24XX_EN_GPT4_MASK				(1 << 6)
104 #define OMAP24XX_EN_GPT3_SHIFT				5
105 #define OMAP24XX_EN_GPT3_MASK				(1 << 5)
106 #define OMAP24XX_EN_GPT2_SHIFT				4
107 #define OMAP24XX_EN_GPT2_MASK				(1 << 4)
108 #define OMAP2420_EN_VLYNQ_SHIFT				3
109 #define OMAP2420_EN_VLYNQ_MASK				(1 << 3)
110 
111 /* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
112 #define OMAP2430_EN_GPIO5_SHIFT				10
113 #define OMAP2430_EN_GPIO5_MASK				(1 << 10)
114 #define OMAP2430_EN_MCSPI3_SHIFT			9
115 #define OMAP2430_EN_MCSPI3_MASK				(1 << 9)
116 #define OMAP2430_EN_MMCHS2_SHIFT			8
117 #define OMAP2430_EN_MMCHS2_MASK				(1 << 8)
118 #define OMAP2430_EN_MMCHS1_SHIFT			7
119 #define OMAP2430_EN_MMCHS1_MASK				(1 << 7)
120 #define OMAP24XX_EN_UART3_SHIFT				2
121 #define OMAP24XX_EN_UART3_MASK				(1 << 2)
122 #define OMAP24XX_EN_USB_SHIFT				0
123 #define OMAP24XX_EN_USB_MASK				(1 << 0)
124 
125 /* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
126 #define OMAP2430_EN_MDM_INTC_SHIFT			11
127 #define OMAP2430_EN_MDM_INTC_MASK			(1 << 11)
128 #define OMAP2430_EN_USBHS_SHIFT				6
129 #define OMAP2430_EN_USBHS_MASK				(1 << 6)
130 #define OMAP24XX_EN_GPMC_SHIFT				1
131 #define OMAP24XX_EN_GPMC_MASK				(1 << 1)
132 
133 /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
134 #define OMAP2420_ST_MMC_SHIFT				26
135 #define OMAP2420_ST_MMC_MASK				(1 << 26)
136 #define OMAP24XX_ST_UART2_SHIFT				22
137 #define OMAP24XX_ST_UART2_MASK				(1 << 22)
138 #define OMAP24XX_ST_UART1_SHIFT				21
139 #define OMAP24XX_ST_UART1_MASK				(1 << 21)
140 #define OMAP24XX_ST_MCSPI2_SHIFT			18
141 #define OMAP24XX_ST_MCSPI2_MASK				(1 << 18)
142 #define OMAP24XX_ST_MCSPI1_SHIFT			17
143 #define OMAP24XX_ST_MCSPI1_MASK				(1 << 17)
144 #define OMAP24XX_ST_MCBSP2_SHIFT			16
145 #define OMAP24XX_ST_MCBSP2_MASK				(1 << 16)
146 #define OMAP24XX_ST_MCBSP1_SHIFT			15
147 #define OMAP24XX_ST_MCBSP1_MASK				(1 << 15)
148 #define OMAP24XX_ST_GPT12_SHIFT				14
149 #define OMAP24XX_ST_GPT12_MASK				(1 << 14)
150 #define OMAP24XX_ST_GPT11_SHIFT				13
151 #define OMAP24XX_ST_GPT11_MASK				(1 << 13)
152 #define OMAP24XX_ST_GPT10_SHIFT				12
153 #define OMAP24XX_ST_GPT10_MASK				(1 << 12)
154 #define OMAP24XX_ST_GPT9_SHIFT				11
155 #define OMAP24XX_ST_GPT9_MASK				(1 << 11)
156 #define OMAP24XX_ST_GPT8_SHIFT				10
157 #define OMAP24XX_ST_GPT8_MASK				(1 << 10)
158 #define OMAP24XX_ST_GPT7_SHIFT				9
159 #define OMAP24XX_ST_GPT7_MASK				(1 << 9)
160 #define OMAP24XX_ST_GPT6_SHIFT				8
161 #define OMAP24XX_ST_GPT6_MASK				(1 << 8)
162 #define OMAP24XX_ST_GPT5_SHIFT				7
163 #define OMAP24XX_ST_GPT5_MASK				(1 << 7)
164 #define OMAP24XX_ST_GPT4_SHIFT				6
165 #define OMAP24XX_ST_GPT4_MASK				(1 << 6)
166 #define OMAP24XX_ST_GPT3_SHIFT				5
167 #define OMAP24XX_ST_GPT3_MASK				(1 << 5)
168 #define OMAP24XX_ST_GPT2_SHIFT				4
169 #define OMAP24XX_ST_GPT2_MASK				(1 << 4)
170 #define OMAP2420_ST_VLYNQ_SHIFT				3
171 #define OMAP2420_ST_VLYNQ_MASK				(1 << 3)
172 
173 /* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
174 #define OMAP2430_ST_MDM_INTC_SHIFT			11
175 #define OMAP2430_ST_MDM_INTC_MASK			(1 << 11)
176 #define OMAP2430_ST_GPIO5_SHIFT				10
177 #define OMAP2430_ST_GPIO5_MASK				(1 << 10)
178 #define OMAP2430_ST_MCSPI3_SHIFT			9
179 #define OMAP2430_ST_MCSPI3_MASK				(1 << 9)
180 #define OMAP2430_ST_MMCHS2_SHIFT			8
181 #define OMAP2430_ST_MMCHS2_MASK				(1 << 8)
182 #define OMAP2430_ST_MMCHS1_SHIFT			7
183 #define OMAP2430_ST_MMCHS1_MASK				(1 << 7)
184 #define OMAP2430_ST_USBHS_SHIFT				6
185 #define OMAP2430_ST_USBHS_MASK				(1 << 6)
186 #define OMAP24XX_ST_UART3_SHIFT				2
187 #define OMAP24XX_ST_UART3_MASK				(1 << 2)
188 #define OMAP24XX_ST_USB_SHIFT				0
189 #define OMAP24XX_ST_USB_MASK				(1 << 0)
190 
191 /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
192 #define OMAP24XX_EN_GPIOS_SHIFT				2
193 #define OMAP24XX_EN_GPIOS_MASK				(1 << 2)
194 #define OMAP24XX_EN_GPT1_SHIFT				0
195 #define OMAP24XX_EN_GPT1_MASK				(1 << 0)
196 
197 /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
198 #define OMAP24XX_ST_GPIOS_SHIFT				2
199 #define OMAP24XX_ST_GPIOS_MASK				(1 << 2)
200 #define OMAP24XX_ST_32KSYNC_SHIFT			1
201 #define OMAP24XX_ST_32KSYNC_MASK			(1 << 1)
202 #define OMAP24XX_ST_GPT1_SHIFT				0
203 #define OMAP24XX_ST_GPT1_MASK				(1 << 0)
204 
205 /* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
206 #define OMAP2430_ST_MDM_SHIFT				0
207 #define OMAP2430_ST_MDM_MASK				(1 << 0)
208 
209 
210 /* 3430 register bits shared between CM & PRM registers */
211 
212 /* CM_REVISION, PRM_REVISION shared bits */
213 #define OMAP3430_REV_SHIFT				0
214 #define OMAP3430_REV_MASK				(0xff << 0)
215 
216 /* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */
217 #define OMAP3430_AUTOIDLE_MASK				(1 << 0)
218 
219 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
220 #define OMAP3430_EN_MMC3_MASK				(1 << 30)
221 #define OMAP3430_EN_MMC3_SHIFT				30
222 #define OMAP3430_EN_MMC2_MASK				(1 << 25)
223 #define OMAP3430_EN_MMC2_SHIFT				25
224 #define OMAP3430_EN_MMC1_MASK				(1 << 24)
225 #define OMAP3430_EN_MMC1_SHIFT				24
226 #define AM35XX_EN_UART4_MASK				(1 << 23)
227 #define AM35XX_EN_UART4_SHIFT				23
228 #define OMAP3430_EN_MCSPI4_MASK				(1 << 21)
229 #define OMAP3430_EN_MCSPI4_SHIFT			21
230 #define OMAP3430_EN_MCSPI3_MASK				(1 << 20)
231 #define OMAP3430_EN_MCSPI3_SHIFT			20
232 #define OMAP3430_EN_MCSPI2_MASK				(1 << 19)
233 #define OMAP3430_EN_MCSPI2_SHIFT			19
234 #define OMAP3430_EN_MCSPI1_MASK				(1 << 18)
235 #define OMAP3430_EN_MCSPI1_SHIFT			18
236 #define OMAP3430_EN_I2C3_MASK				(1 << 17)
237 #define OMAP3430_EN_I2C3_SHIFT				17
238 #define OMAP3430_EN_I2C2_MASK				(1 << 16)
239 #define OMAP3430_EN_I2C2_SHIFT				16
240 #define OMAP3430_EN_I2C1_MASK				(1 << 15)
241 #define OMAP3430_EN_I2C1_SHIFT				15
242 #define OMAP3430_EN_UART2_MASK				(1 << 14)
243 #define OMAP3430_EN_UART2_SHIFT				14
244 #define OMAP3430_EN_UART1_MASK				(1 << 13)
245 #define OMAP3430_EN_UART1_SHIFT				13
246 #define OMAP3430_EN_GPT11_MASK				(1 << 12)
247 #define OMAP3430_EN_GPT11_SHIFT				12
248 #define OMAP3430_EN_GPT10_MASK				(1 << 11)
249 #define OMAP3430_EN_GPT10_SHIFT				11
250 #define OMAP3430_EN_MCBSP5_MASK				(1 << 10)
251 #define OMAP3430_EN_MCBSP5_SHIFT			10
252 #define OMAP3430_EN_MCBSP1_MASK				(1 << 9)
253 #define OMAP3430_EN_MCBSP1_SHIFT			9
254 #define OMAP3430_EN_FSHOSTUSB_MASK			(1 << 5)
255 #define OMAP3430_EN_FSHOSTUSB_SHIFT			5
256 #define OMAP3430_EN_D2D_MASK				(1 << 3)
257 #define OMAP3430_EN_D2D_SHIFT				3
258 
259 /* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
260 #define OMAP3430_EN_HSOTGUSB_MASK			(1 << 4)
261 #define OMAP3430_EN_HSOTGUSB_SHIFT			4
262 
263 /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
264 #define OMAP3430_ST_MMC3_SHIFT				30
265 #define OMAP3430_ST_MMC3_MASK				(1 << 30)
266 #define OMAP3430_ST_MMC2_SHIFT				25
267 #define OMAP3430_ST_MMC2_MASK				(1 << 25)
268 #define OMAP3430_ST_MMC1_SHIFT				24
269 #define OMAP3430_ST_MMC1_MASK				(1 << 24)
270 #define OMAP3430_ST_MCSPI4_SHIFT			21
271 #define OMAP3430_ST_MCSPI4_MASK				(1 << 21)
272 #define OMAP3430_ST_MCSPI3_SHIFT			20
273 #define OMAP3430_ST_MCSPI3_MASK				(1 << 20)
274 #define OMAP3430_ST_MCSPI2_SHIFT			19
275 #define OMAP3430_ST_MCSPI2_MASK				(1 << 19)
276 #define OMAP3430_ST_MCSPI1_SHIFT			18
277 #define OMAP3430_ST_MCSPI1_MASK				(1 << 18)
278 #define OMAP3430_ST_I2C3_SHIFT				17
279 #define OMAP3430_ST_I2C3_MASK				(1 << 17)
280 #define OMAP3430_ST_I2C2_SHIFT				16
281 #define OMAP3430_ST_I2C2_MASK				(1 << 16)
282 #define OMAP3430_ST_I2C1_SHIFT				15
283 #define OMAP3430_ST_I2C1_MASK				(1 << 15)
284 #define OMAP3430_ST_UART2_SHIFT				14
285 #define OMAP3430_ST_UART2_MASK				(1 << 14)
286 #define OMAP3430_ST_UART1_SHIFT				13
287 #define OMAP3430_ST_UART1_MASK				(1 << 13)
288 #define OMAP3430_ST_GPT11_SHIFT				12
289 #define OMAP3430_ST_GPT11_MASK				(1 << 12)
290 #define OMAP3430_ST_GPT10_SHIFT				11
291 #define OMAP3430_ST_GPT10_MASK				(1 << 11)
292 #define OMAP3430_ST_MCBSP5_SHIFT			10
293 #define OMAP3430_ST_MCBSP5_MASK				(1 << 10)
294 #define OMAP3430_ST_MCBSP1_SHIFT			9
295 #define OMAP3430_ST_MCBSP1_MASK				(1 << 9)
296 #define OMAP3430ES1_ST_FSHOSTUSB_SHIFT			5
297 #define OMAP3430ES1_ST_FSHOSTUSB_MASK			(1 << 5)
298 #define OMAP3430ES1_ST_HSOTGUSB_SHIFT			4
299 #define OMAP3430ES1_ST_HSOTGUSB_MASK			(1 << 4)
300 #define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT		5
301 #define OMAP3430ES2_ST_HSOTGUSB_IDLE_MASK		(1 << 5)
302 #define OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT		4
303 #define OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK		(1 << 4)
304 #define OMAP3430_ST_D2D_SHIFT				3
305 #define OMAP3430_ST_D2D_MASK				(1 << 3)
306 
307 /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
308 #define OMAP3430_EN_GPIO1_MASK				(1 << 3)
309 #define OMAP3430_EN_GPIO1_SHIFT				3
310 #define OMAP3430_EN_GPT12_MASK				(1 << 1)
311 #define OMAP3430_EN_GPT12_SHIFT				1
312 #define OMAP3430_EN_GPT1_MASK				(1 << 0)
313 #define OMAP3430_EN_GPT1_SHIFT				0
314 
315 /* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */
316 #define OMAP3430_EN_SR2_MASK				(1 << 7)
317 #define OMAP3430_EN_SR2_SHIFT				7
318 #define OMAP3430_EN_SR1_MASK				(1 << 6)
319 #define OMAP3430_EN_SR1_SHIFT				6
320 
321 /* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
322 #define OMAP3430_EN_GPT12_MASK				(1 << 1)
323 #define OMAP3430_EN_GPT12_SHIFT				1
324 
325 /* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
326 #define OMAP3430_ST_SR2_SHIFT				7
327 #define OMAP3430_ST_SR2_MASK				(1 << 7)
328 #define OMAP3430_ST_SR1_SHIFT				6
329 #define OMAP3430_ST_SR1_MASK				(1 << 6)
330 #define OMAP3430_ST_GPIO1_SHIFT				3
331 #define OMAP3430_ST_GPIO1_MASK				(1 << 3)
332 #define OMAP3430_ST_32KSYNC_SHIFT			2
333 #define OMAP3430_ST_32KSYNC_MASK			(1 << 2)
334 #define OMAP3430_ST_GPT12_SHIFT				1
335 #define OMAP3430_ST_GPT12_MASK				(1 << 1)
336 #define OMAP3430_ST_GPT1_SHIFT				0
337 #define OMAP3430_ST_GPT1_MASK				(1 << 0)
338 
339 /*
340  * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM,
341  * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX,
342  * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits
343  */
344 #define OMAP3430_EN_MPU_MASK				(1 << 1)
345 #define OMAP3430_EN_MPU_SHIFT				1
346 
347 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */
348 
349 #define OMAP3630_EN_UART4_MASK				(1 << 18)
350 #define OMAP3630_EN_UART4_SHIFT				18
351 #define OMAP3430_EN_GPIO6_MASK				(1 << 17)
352 #define OMAP3430_EN_GPIO6_SHIFT				17
353 #define OMAP3430_EN_GPIO5_MASK				(1 << 16)
354 #define OMAP3430_EN_GPIO5_SHIFT				16
355 #define OMAP3430_EN_GPIO4_MASK				(1 << 15)
356 #define OMAP3430_EN_GPIO4_SHIFT				15
357 #define OMAP3430_EN_GPIO3_MASK				(1 << 14)
358 #define OMAP3430_EN_GPIO3_SHIFT				14
359 #define OMAP3430_EN_GPIO2_MASK				(1 << 13)
360 #define OMAP3430_EN_GPIO2_SHIFT				13
361 #define OMAP3430_EN_UART3_MASK				(1 << 11)
362 #define OMAP3430_EN_UART3_SHIFT				11
363 #define OMAP3430_EN_GPT9_MASK				(1 << 10)
364 #define OMAP3430_EN_GPT9_SHIFT				10
365 #define OMAP3430_EN_GPT8_MASK				(1 << 9)
366 #define OMAP3430_EN_GPT8_SHIFT				9
367 #define OMAP3430_EN_GPT7_MASK				(1 << 8)
368 #define OMAP3430_EN_GPT7_SHIFT				8
369 #define OMAP3430_EN_GPT6_MASK				(1 << 7)
370 #define OMAP3430_EN_GPT6_SHIFT				7
371 #define OMAP3430_EN_GPT5_MASK				(1 << 6)
372 #define OMAP3430_EN_GPT5_SHIFT				6
373 #define OMAP3430_EN_GPT4_MASK				(1 << 5)
374 #define OMAP3430_EN_GPT4_SHIFT				5
375 #define OMAP3430_EN_GPT3_MASK				(1 << 4)
376 #define OMAP3430_EN_GPT3_SHIFT				4
377 #define OMAP3430_EN_GPT2_MASK				(1 << 3)
378 #define OMAP3430_EN_GPT2_SHIFT				3
379 
380 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */
381 /* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits
382  * be ST_* bits instead? */
383 #define OMAP3430_EN_MCBSP4_MASK				(1 << 2)
384 #define OMAP3430_EN_MCBSP4_SHIFT			2
385 #define OMAP3430_EN_MCBSP3_MASK				(1 << 1)
386 #define OMAP3430_EN_MCBSP3_SHIFT			1
387 #define OMAP3430_EN_MCBSP2_MASK				(1 << 0)
388 #define OMAP3430_EN_MCBSP2_SHIFT			0
389 
390 /* CM_IDLEST_PER, PM_WKST_PER shared bits */
391 #define OMAP3630_ST_UART4_SHIFT				18
392 #define OMAP3630_ST_UART4_MASK				(1 << 18)
393 #define OMAP3430_ST_GPIO6_SHIFT				17
394 #define OMAP3430_ST_GPIO6_MASK				(1 << 17)
395 #define OMAP3430_ST_GPIO5_SHIFT				16
396 #define OMAP3430_ST_GPIO5_MASK				(1 << 16)
397 #define OMAP3430_ST_GPIO4_SHIFT				15
398 #define OMAP3430_ST_GPIO4_MASK				(1 << 15)
399 #define OMAP3430_ST_GPIO3_SHIFT				14
400 #define OMAP3430_ST_GPIO3_MASK				(1 << 14)
401 #define OMAP3430_ST_GPIO2_SHIFT				13
402 #define OMAP3430_ST_GPIO2_MASK				(1 << 13)
403 #define OMAP3430_ST_UART3_SHIFT				11
404 #define OMAP3430_ST_UART3_MASK				(1 << 11)
405 #define OMAP3430_ST_GPT9_SHIFT				10
406 #define OMAP3430_ST_GPT9_MASK				(1 << 10)
407 #define OMAP3430_ST_GPT8_SHIFT				9
408 #define OMAP3430_ST_GPT8_MASK				(1 << 9)
409 #define OMAP3430_ST_GPT7_SHIFT				8
410 #define OMAP3430_ST_GPT7_MASK				(1 << 8)
411 #define OMAP3430_ST_GPT6_SHIFT				7
412 #define OMAP3430_ST_GPT6_MASK				(1 << 7)
413 #define OMAP3430_ST_GPT5_SHIFT				6
414 #define OMAP3430_ST_GPT5_MASK				(1 << 6)
415 #define OMAP3430_ST_GPT4_SHIFT				5
416 #define OMAP3430_ST_GPT4_MASK				(1 << 5)
417 #define OMAP3430_ST_GPT3_SHIFT				4
418 #define OMAP3430_ST_GPT3_MASK				(1 << 4)
419 #define OMAP3430_ST_GPT2_SHIFT				3
420 #define OMAP3430_ST_GPT2_MASK				(1 << 3)
421 
422 /* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
423 #define OMAP3430_EN_CORE_SHIFT				0
424 #define OMAP3430_EN_CORE_MASK				(1 << 0)
425 
426 
427 
428 /*
429  * Maximum time(us) it takes to output the signal WUCLKOUT of the last
430  * pad of the I/O ring after asserting WUCLKIN high.  Tero measured
431  * the actual time at 7 to 8 microseconds on OMAP3 and 2 to 4
432  * microseconds on OMAP4, so this timeout may be too high.
433  */
434 #define MAX_IOPAD_LATCH_TIME			100
435 # ifndef __ASSEMBLER__
436 
437 #include <linux/delay.h>
438 
439 /**
440  * omap_test_timeout - busy-loop, testing a condition
441  * @cond: condition to test until it evaluates to true
442  * @timeout: maximum number of microseconds in the timeout
443  * @index: loop index (integer)
444  *
445  * Loop waiting for @cond to become true or until at least @timeout
446  * microseconds have passed.  To use, define some integer @index in the
447  * calling code.  After running, if @index == @timeout, then the loop has
448  * timed out.
449  */
450 #define omap_test_timeout(cond, timeout, index)			\
451 ({								\
452 	for (index = 0; index < timeout; index++) {		\
453 		if (cond)					\
454 			break;					\
455 		udelay(1);					\
456 	}							\
457 })
458 
459 /**
460  * struct omap_prcm_irq - describes a PRCM interrupt bit
461  * @name: a short name describing the interrupt type, e.g. "wkup" or "io"
462  * @offset: the bit shift of the interrupt inside the IRQ{ENABLE,STATUS} regs
463  * @priority: should this interrupt be handled before @priority=false IRQs?
464  *
465  * Describes interrupt bits inside the PRM_IRQ{ENABLE,STATUS}_MPU* registers.
466  * On systems with multiple PRM MPU IRQ registers, the bitfields read from
467  * the registers are concatenated, so @offset could be > 31 on these systems -
468  * see omap_prm_irq_handler() for more details.  I/O ring interrupts should
469  * have @priority set to true.
470  */
471 struct omap_prcm_irq {
472 	const char *name;
473 	unsigned int offset;
474 	bool priority;
475 };
476 
477 /**
478  * struct omap_prcm_irq_setup - PRCM interrupt controller details
479  * @ack: PRM register offset for the first PRM_IRQSTATUS_MPU register
480  * @mask: PRM register offset for the first PRM_IRQENABLE_MPU register
481  * @pm_ctrl: PRM register offset for the PRM_IO_PMCTRL register
482  * @nr_regs: number of PRM_IRQ{STATUS,ENABLE}_MPU* registers
483  * @nr_irqs: number of entries in the @irqs array
484  * @irqs: ptr to an array of PRCM interrupt bits (see @nr_irqs)
485  * @irq: MPU IRQ asserted when a PRCM interrupt arrives
486  * @read_pending_irqs: fn ptr to determine if any PRCM IRQs are pending
487  * @ocp_barrier: fn ptr to force buffered PRM writes to complete
488  * @save_and_clear_irqen: fn ptr to save and clear IRQENABLE regs
489  * @restore_irqen: fn ptr to save and clear IRQENABLE regs
490  * @reconfigure_io_chain: fn ptr to reconfigure IO chain
491  * @saved_mask: IRQENABLE regs are saved here during suspend
492  * @priority_mask: 1 bit per IRQ, set to 1 if omap_prcm_irq.priority = true
493  * @base_irq: base dynamic IRQ number, returned from irq_alloc_descs() in init
494  * @suspended: set to true after Linux suspend code has called our ->prepare()
495  * @suspend_save_flag: set to true after IRQ masks have been saved and disabled
496  *
497  * @saved_mask, @priority_mask, @base_irq, @suspended, and
498  * @suspend_save_flag are populated dynamically, and are not to be
499  * specified in static initializers.
500  */
501 struct omap_prcm_irq_setup {
502 	u16 ack;
503 	u16 mask;
504 	u16 pm_ctrl;
505 	u8 nr_regs;
506 	u8 nr_irqs;
507 	const struct omap_prcm_irq *irqs;
508 	int irq;
509 	unsigned int (*xlate_irq)(unsigned int);
510 	void (*read_pending_irqs)(unsigned long *events);
511 	void (*ocp_barrier)(void);
512 	void (*save_and_clear_irqen)(u32 *saved_mask);
513 	void (*restore_irqen)(u32 *saved_mask);
514 	void (*reconfigure_io_chain)(void);
515 	u32 *saved_mask;
516 	u32 *priority_mask;
517 	int base_irq;
518 	bool suspended;
519 	bool suspend_save_flag;
520 };
521 
522 /* OMAP_PRCM_IRQ: convenience macro for creating struct omap_prcm_irq records */
523 #define OMAP_PRCM_IRQ(_name, _offset, _priority) {	\
524 	.name = _name,					\
525 	.offset = _offset,				\
526 	.priority = _priority				\
527 	}
528 
529 /**
530  * struct omap_prcm_init_data - PRCM driver init data
531  * @index: clock memory mapping index to be used
532  * @mem: IO mem pointer for this module
533  * @offset: module base address offset from the IO base
534  * @flags: PRCM module init flags
535  * @device_inst_offset: device instance offset within the module address space
536  * @init: low level PRCM init function for this module
537  * @np: device node for this PRCM module
538  */
539 struct omap_prcm_init_data {
540 	int index;
541 	void __iomem *mem;
542 	s16 offset;
543 	u16 flags;
544 	s32 device_inst_offset;
545 	int (*init)(const struct omap_prcm_init_data *data);
546 	struct device_node *np;
547 };
548 
549 extern void omap_prcm_irq_cleanup(void);
550 extern int omap_prcm_register_chain_handler(
551 	struct omap_prcm_irq_setup *irq_setup);
552 extern int omap_prcm_event_to_irq(const char *event);
553 extern void omap_prcm_irq_prepare(void);
554 extern void omap_prcm_irq_complete(void);
555 
556 # endif
557 
558 #endif
559 
560