1 /*
2  * DRA7xx Power domains framework
3  *
4  * Copyright (C) 2009-2013 Texas Instruments, Inc.
5  * Copyright (C) 2009-2011 Nokia Corporation
6  *
7  * Generated by code originally written by:
8  * Abhijit Pagare (abhijitpagare@ti.com)
9  * Benoit Cousson (b-cousson@ti.com)
10  * Paul Walmsley (paul@pwsan.com)
11  *
12  * This file is automatically generated from the OMAP hardware databases.
13  * We respectfully ask that any modifications to this file be coordinated
14  * with the public linux-omap@vger.kernel.org mailing list and the
15  * authors above to ensure that the autogeneration scripts are kept
16  * up-to-date with the file contents.
17  *
18  * This program is free software; you can redistribute it and/or modify
19  * it under the terms of the GNU General Public License version 2 as
20  * published by the Free Software Foundation.
21  */
22 
23 #include <linux/kernel.h>
24 #include <linux/init.h>
25 
26 #include "powerdomain.h"
27 
28 #include "prcm-common.h"
29 #include "prcm44xx.h"
30 #include "prm7xx.h"
31 #include "prcm_mpu7xx.h"
32 
33 /* iva_7xx_pwrdm: IVA-HD power domain */
34 static struct powerdomain iva_7xx_pwrdm = {
35 	.name		  = "iva_pwrdm",
36 	.prcm_offs	  = DRA7XX_PRM_IVA_INST,
37 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
38 	.pwrsts		  = PWRSTS_OFF_RET_ON,
39 	.pwrsts_logic_ret = PWRSTS_OFF,
40 	.banks		  = 4,
41 	.pwrsts_mem_ret	= {
42 		[0] = PWRSTS_OFF_RET,	/* hwa_mem */
43 		[1] = PWRSTS_OFF_RET,	/* sl2_mem */
44 		[2] = PWRSTS_OFF_RET,	/* tcm1_mem */
45 		[3] = PWRSTS_OFF_RET,	/* tcm2_mem */
46 	},
47 	.pwrsts_mem_on	= {
48 		[0] = PWRSTS_OFF_RET,	/* hwa_mem */
49 		[1] = PWRSTS_OFF_RET,	/* sl2_mem */
50 		[2] = PWRSTS_OFF_RET,	/* tcm1_mem */
51 		[3] = PWRSTS_OFF_RET,	/* tcm2_mem */
52 	},
53 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
54 };
55 
56 /* rtc_7xx_pwrdm:  */
57 static struct powerdomain rtc_7xx_pwrdm = {
58 	.name		  = "rtc_pwrdm",
59 	.prcm_offs	  = DRA7XX_PRM_RTC_INST,
60 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
61 	.pwrsts		  = PWRSTS_ON,
62 };
63 
64 /* custefuse_7xx_pwrdm: Customer efuse controller power domain */
65 static struct powerdomain custefuse_7xx_pwrdm = {
66 	.name		  = "custefuse_pwrdm",
67 	.prcm_offs	  = DRA7XX_PRM_CUSTEFUSE_INST,
68 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
69 	.pwrsts		  = PWRSTS_OFF_ON,
70 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
71 };
72 
73 /* ipu_7xx_pwrdm: Audio back end power domain */
74 static struct powerdomain ipu_7xx_pwrdm = {
75 	.name		  = "ipu_pwrdm",
76 	.prcm_offs	  = DRA7XX_PRM_IPU_INST,
77 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
78 	.pwrsts		  = PWRSTS_OFF_RET_ON,
79 	.pwrsts_logic_ret = PWRSTS_OFF,
80 	.banks		  = 2,
81 	.pwrsts_mem_ret	= {
82 		[0] = PWRSTS_OFF_RET,	/* aessmem */
83 		[1] = PWRSTS_OFF_RET,	/* periphmem */
84 	},
85 	.pwrsts_mem_on	= {
86 		[0] = PWRSTS_OFF_RET,	/* aessmem */
87 		[1] = PWRSTS_OFF_RET,	/* periphmem */
88 	},
89 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
90 };
91 
92 /* dss_7xx_pwrdm: Display subsystem power domain */
93 static struct powerdomain dss_7xx_pwrdm = {
94 	.name		  = "dss_pwrdm",
95 	.prcm_offs	  = DRA7XX_PRM_DSS_INST,
96 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
97 	.pwrsts		  = PWRSTS_OFF_RET_ON,
98 	.pwrsts_logic_ret = PWRSTS_OFF,
99 	.banks		  = 1,
100 	.pwrsts_mem_ret	= {
101 		[0] = PWRSTS_OFF_RET,	/* dss_mem */
102 	},
103 	.pwrsts_mem_on	= {
104 		[0] = PWRSTS_OFF_RET,	/* dss_mem */
105 	},
106 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
107 };
108 
109 /* l4per_7xx_pwrdm: Target peripherals power domain */
110 static struct powerdomain l4per_7xx_pwrdm = {
111 	.name		  = "l4per_pwrdm",
112 	.prcm_offs	  = DRA7XX_PRM_L4PER_INST,
113 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
114 	.pwrsts		  = PWRSTS_RET_ON,
115 	.pwrsts_logic_ret = PWRSTS_OFF_RET,
116 	.banks		  = 2,
117 	.pwrsts_mem_ret	= {
118 		[0] = PWRSTS_OFF_RET,	/* nonretained_bank */
119 		[1] = PWRSTS_OFF_RET,	/* retained_bank */
120 	},
121 	.pwrsts_mem_on	= {
122 		[0] = PWRSTS_OFF_RET,	/* nonretained_bank */
123 		[1] = PWRSTS_OFF_RET,	/* retained_bank */
124 	},
125 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
126 };
127 
128 /* gpu_7xx_pwrdm: 3D accelerator power domain */
129 static struct powerdomain gpu_7xx_pwrdm = {
130 	.name		  = "gpu_pwrdm",
131 	.prcm_offs	  = DRA7XX_PRM_GPU_INST,
132 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
133 	.pwrsts		  = PWRSTS_OFF_ON,
134 	.banks		  = 1,
135 	.pwrsts_mem_ret	= {
136 		[0] = PWRSTS_OFF_RET,	/* gpu_mem */
137 	},
138 	.pwrsts_mem_on	= {
139 		[0] = PWRSTS_OFF_RET,	/* gpu_mem */
140 	},
141 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
142 };
143 
144 /* wkupaon_7xx_pwrdm: Wake-up power domain */
145 static struct powerdomain wkupaon_7xx_pwrdm = {
146 	.name		  = "wkupaon_pwrdm",
147 	.prcm_offs	  = DRA7XX_PRM_WKUPAON_INST,
148 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
149 	.pwrsts		  = PWRSTS_ON,
150 	.banks		  = 1,
151 	.pwrsts_mem_ret	= {
152 	},
153 	.pwrsts_mem_on	= {
154 		[0] = PWRSTS_ON,	/* wkup_bank */
155 	},
156 };
157 
158 /* core_7xx_pwrdm: CORE power domain */
159 static struct powerdomain core_7xx_pwrdm = {
160 	.name		  = "core_pwrdm",
161 	.prcm_offs	  = DRA7XX_PRM_CORE_INST,
162 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
163 	.pwrsts		  = PWRSTS_INA_ON,
164 	.pwrsts_logic_ret = PWRSTS_RET,
165 	.banks		  = 5,
166 	.pwrsts_mem_ret	= {
167 		[0] = PWRSTS_OFF_RET,	/* core_nret_bank */
168 		[1] = PWRSTS_OFF_RET,	/* core_ocmram */
169 		[2] = PWRSTS_OFF_RET,	/* core_other_bank */
170 		[3] = PWRSTS_OFF_RET,	/* ipu_l2ram */
171 		[4] = PWRSTS_OFF_RET,	/* ipu_unicache */
172 	},
173 	.pwrsts_mem_on	= {
174 		[0] = PWRSTS_OFF_RET,	/* core_nret_bank */
175 		[1] = PWRSTS_OFF_RET,	/* core_ocmram */
176 		[2] = PWRSTS_OFF_RET,	/* core_other_bank */
177 		[3] = PWRSTS_OFF_RET,	/* ipu_l2ram */
178 		[4] = PWRSTS_OFF_RET,	/* ipu_unicache */
179 	},
180 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
181 };
182 
183 /* coreaon_7xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
184 static struct powerdomain coreaon_7xx_pwrdm = {
185 	.name		  = "coreaon_pwrdm",
186 	.prcm_offs	  = DRA7XX_PRM_COREAON_INST,
187 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
188 	.pwrsts		  = PWRSTS_ON,
189 };
190 
191 /* cpu0_7xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
192 static struct powerdomain cpu0_7xx_pwrdm = {
193 	.name		  = "cpu0_pwrdm",
194 	.prcm_offs	  = DRA7XX_MPU_PRCM_PRM_C0_INST,
195 	.prcm_partition	  = DRA7XX_MPU_PRCM_PARTITION,
196 	.pwrsts		  = PWRSTS_RET_ON,
197 	.pwrsts_logic_ret = PWRSTS_RET,
198 	.banks		  = 1,
199 	.pwrsts_mem_ret	= {
200 		[0] = PWRSTS_OFF_RET,	/* cpu0_l1 */
201 	},
202 	.pwrsts_mem_on	= {
203 		[0] = PWRSTS_ON,	/* cpu0_l1 */
204 	},
205 };
206 
207 /* cpu1_7xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
208 static struct powerdomain cpu1_7xx_pwrdm = {
209 	.name		  = "cpu1_pwrdm",
210 	.prcm_offs	  = DRA7XX_MPU_PRCM_PRM_C1_INST,
211 	.prcm_partition	  = DRA7XX_MPU_PRCM_PARTITION,
212 	.pwrsts		  = PWRSTS_RET_ON,
213 	.pwrsts_logic_ret = PWRSTS_RET,
214 	.banks		  = 1,
215 	.pwrsts_mem_ret	= {
216 		[0] = PWRSTS_OFF_RET,	/* cpu1_l1 */
217 	},
218 	.pwrsts_mem_on	= {
219 		[0] = PWRSTS_ON,	/* cpu1_l1 */
220 	},
221 };
222 
223 /* vpe_7xx_pwrdm:  */
224 static struct powerdomain vpe_7xx_pwrdm = {
225 	.name		  = "vpe_pwrdm",
226 	.prcm_offs	  = DRA7XX_PRM_VPE_INST,
227 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
228 	.pwrsts		  = PWRSTS_OFF_RET_ON,
229 	.pwrsts_logic_ret = PWRSTS_OFF_RET,
230 	.banks		  = 1,
231 	.pwrsts_mem_ret	= {
232 		[0] = PWRSTS_OFF_RET,	/* vpe_bank */
233 	},
234 	.pwrsts_mem_on	= {
235 		[0] = PWRSTS_OFF_RET,	/* vpe_bank */
236 	},
237 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
238 };
239 
240 /* mpu_7xx_pwrdm: Modena processor and the Neon coprocessor power domain */
241 static struct powerdomain mpu_7xx_pwrdm = {
242 	.name		  = "mpu_pwrdm",
243 	.prcm_offs	  = DRA7XX_PRM_MPU_INST,
244 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
245 	.pwrsts		  = PWRSTS_RET_ON,
246 	.pwrsts_logic_ret = PWRSTS_RET,
247 	.banks		  = 2,
248 	.pwrsts_mem_ret	= {
249 		[0] = PWRSTS_OFF_RET,	/* mpu_l2 */
250 		[1] = PWRSTS_RET,	/* mpu_ram */
251 	},
252 	.pwrsts_mem_on	= {
253 		[0] = PWRSTS_OFF_RET,	/* mpu_l2 */
254 		[1] = PWRSTS_OFF_RET,	/* mpu_ram */
255 	},
256 };
257 
258 /* l3init_7xx_pwrdm: L3 initators pheripherals power domain  */
259 static struct powerdomain l3init_7xx_pwrdm = {
260 	.name		  = "l3init_pwrdm",
261 	.prcm_offs	  = DRA7XX_PRM_L3INIT_INST,
262 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
263 	.pwrsts		  = PWRSTS_RET_ON,
264 	.pwrsts_logic_ret = PWRSTS_OFF_RET,
265 	.banks		  = 3,
266 	.pwrsts_mem_ret	= {
267 		[0] = PWRSTS_OFF_RET,	/* gmac_bank */
268 		[1] = PWRSTS_OFF_RET,	/* l3init_bank1 */
269 		[2] = PWRSTS_OFF_RET,	/* l3init_bank2 */
270 	},
271 	.pwrsts_mem_on	= {
272 		[0] = PWRSTS_OFF_RET,	/* gmac_bank */
273 		[1] = PWRSTS_OFF_RET,	/* l3init_bank1 */
274 		[2] = PWRSTS_OFF_RET,	/* l3init_bank2 */
275 	},
276 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
277 };
278 
279 /* eve3_7xx_pwrdm:  */
280 static struct powerdomain eve3_7xx_pwrdm = {
281 	.name		  = "eve3_pwrdm",
282 	.prcm_offs	  = DRA7XX_PRM_EVE3_INST,
283 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
284 	.pwrsts		  = PWRSTS_OFF_ON,
285 	.banks		  = 1,
286 	.pwrsts_mem_ret	= {
287 		[0] = PWRSTS_OFF_RET,	/* eve3_bank */
288 	},
289 	.pwrsts_mem_on	= {
290 		[0] = PWRSTS_OFF_RET,	/* eve3_bank */
291 	},
292 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
293 };
294 
295 /* emu_7xx_pwrdm: Emulation power domain */
296 static struct powerdomain emu_7xx_pwrdm = {
297 	.name		  = "emu_pwrdm",
298 	.prcm_offs	  = DRA7XX_PRM_EMU_INST,
299 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
300 	.pwrsts		  = PWRSTS_OFF_ON,
301 	.banks		  = 1,
302 	.pwrsts_mem_ret	= {
303 		[0] = PWRSTS_OFF_RET,	/* emu_bank */
304 	},
305 	.pwrsts_mem_on	= {
306 		[0] = PWRSTS_OFF_RET,	/* emu_bank */
307 	},
308 };
309 
310 /* dsp2_7xx_pwrdm:  */
311 static struct powerdomain dsp2_7xx_pwrdm = {
312 	.name		  = "dsp2_pwrdm",
313 	.prcm_offs	  = DRA7XX_PRM_DSP2_INST,
314 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
315 	.pwrsts		  = PWRSTS_OFF_ON,
316 	.banks		  = 3,
317 	.pwrsts_mem_ret	= {
318 		[0] = PWRSTS_OFF_RET,	/* dsp2_edma */
319 		[1] = PWRSTS_OFF_RET,	/* dsp2_l1 */
320 		[2] = PWRSTS_OFF_RET,	/* dsp2_l2 */
321 	},
322 	.pwrsts_mem_on	= {
323 		[0] = PWRSTS_OFF_RET,	/* dsp2_edma */
324 		[1] = PWRSTS_OFF_RET,	/* dsp2_l1 */
325 		[2] = PWRSTS_OFF_RET,	/* dsp2_l2 */
326 	},
327 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
328 };
329 
330 /* dsp1_7xx_pwrdm: Tesla processor power domain */
331 static struct powerdomain dsp1_7xx_pwrdm = {
332 	.name		  = "dsp1_pwrdm",
333 	.prcm_offs	  = DRA7XX_PRM_DSP1_INST,
334 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
335 	.pwrsts		  = PWRSTS_OFF_ON,
336 	.banks		  = 3,
337 	.pwrsts_mem_ret	= {
338 		[0] = PWRSTS_OFF_RET,	/* dsp1_edma */
339 		[1] = PWRSTS_OFF_RET,	/* dsp1_l1 */
340 		[2] = PWRSTS_OFF_RET,	/* dsp1_l2 */
341 	},
342 	.pwrsts_mem_on	= {
343 		[0] = PWRSTS_OFF_RET,	/* dsp1_edma */
344 		[1] = PWRSTS_OFF_RET,	/* dsp1_l1 */
345 		[2] = PWRSTS_OFF_RET,	/* dsp1_l2 */
346 	},
347 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
348 };
349 
350 /* cam_7xx_pwrdm: Camera subsystem power domain */
351 static struct powerdomain cam_7xx_pwrdm = {
352 	.name		  = "cam_pwrdm",
353 	.prcm_offs	  = DRA7XX_PRM_CAM_INST,
354 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
355 	.pwrsts		  = PWRSTS_OFF_ON,
356 	.banks		  = 1,
357 	.pwrsts_mem_ret	= {
358 		[0] = PWRSTS_OFF_RET,	/* vip_bank */
359 	},
360 	.pwrsts_mem_on	= {
361 		[0] = PWRSTS_OFF_RET,	/* vip_bank */
362 	},
363 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
364 };
365 
366 /* eve4_7xx_pwrdm:  */
367 static struct powerdomain eve4_7xx_pwrdm = {
368 	.name		  = "eve4_pwrdm",
369 	.prcm_offs	  = DRA7XX_PRM_EVE4_INST,
370 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
371 	.pwrsts		  = PWRSTS_OFF_ON,
372 	.banks		  = 1,
373 	.pwrsts_mem_ret	= {
374 		[0] = PWRSTS_OFF_RET,	/* eve4_bank */
375 	},
376 	.pwrsts_mem_on	= {
377 		[0] = PWRSTS_OFF_RET,	/* eve4_bank */
378 	},
379 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
380 };
381 
382 /* eve2_7xx_pwrdm:  */
383 static struct powerdomain eve2_7xx_pwrdm = {
384 	.name		  = "eve2_pwrdm",
385 	.prcm_offs	  = DRA7XX_PRM_EVE2_INST,
386 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
387 	.pwrsts		  = PWRSTS_OFF_ON,
388 	.banks		  = 1,
389 	.pwrsts_mem_ret	= {
390 		[0] = PWRSTS_OFF_RET,	/* eve2_bank */
391 	},
392 	.pwrsts_mem_on	= {
393 		[0] = PWRSTS_OFF_RET,	/* eve2_bank */
394 	},
395 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
396 };
397 
398 /* eve1_7xx_pwrdm:  */
399 static struct powerdomain eve1_7xx_pwrdm = {
400 	.name		  = "eve1_pwrdm",
401 	.prcm_offs	  = DRA7XX_PRM_EVE1_INST,
402 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
403 	.pwrsts		  = PWRSTS_OFF_ON,
404 	.banks		  = 1,
405 	.pwrsts_mem_ret	= {
406 		[0] = PWRSTS_OFF_RET,	/* eve1_bank */
407 	},
408 	.pwrsts_mem_on	= {
409 		[0] = PWRSTS_OFF_RET,	/* eve1_bank */
410 	},
411 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
412 };
413 
414 /*
415  * The following power domains are not under SW control
416  *
417  * mpuaon
418  * mmaon
419  */
420 
421 /* As powerdomains are added or removed above, this list must also be changed */
422 static struct powerdomain *powerdomains_dra7xx[] __initdata = {
423 	&iva_7xx_pwrdm,
424 	&rtc_7xx_pwrdm,
425 	&custefuse_7xx_pwrdm,
426 	&ipu_7xx_pwrdm,
427 	&dss_7xx_pwrdm,
428 	&l4per_7xx_pwrdm,
429 	&gpu_7xx_pwrdm,
430 	&wkupaon_7xx_pwrdm,
431 	&core_7xx_pwrdm,
432 	&coreaon_7xx_pwrdm,
433 	&cpu0_7xx_pwrdm,
434 	&cpu1_7xx_pwrdm,
435 	&vpe_7xx_pwrdm,
436 	&mpu_7xx_pwrdm,
437 	&l3init_7xx_pwrdm,
438 	&eve3_7xx_pwrdm,
439 	&emu_7xx_pwrdm,
440 	&dsp2_7xx_pwrdm,
441 	&dsp1_7xx_pwrdm,
442 	&cam_7xx_pwrdm,
443 	&eve4_7xx_pwrdm,
444 	&eve2_7xx_pwrdm,
445 	&eve1_7xx_pwrdm,
446 	NULL
447 };
448 
449 void __init dra7xx_powerdomains_init(void)
450 {
451 	pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
452 	pwrdm_register_pwrdms(powerdomains_dra7xx);
453 	pwrdm_complete_init();
454 }
455