1 /* 2 * DRA7xx Power domains framework 3 * 4 * Copyright (C) 2009-2013 Texas Instruments, Inc. 5 * Copyright (C) 2009-2011 Nokia Corporation 6 * 7 * Generated by code originally written by: 8 * Abhijit Pagare (abhijitpagare@ti.com) 9 * Benoit Cousson (b-cousson@ti.com) 10 * Paul Walmsley (paul@pwsan.com) 11 * 12 * This file is automatically generated from the OMAP hardware databases. 13 * We respectfully ask that any modifications to this file be coordinated 14 * with the public linux-omap@vger.kernel.org mailing list and the 15 * authors above to ensure that the autogeneration scripts are kept 16 * up-to-date with the file contents. 17 * 18 * This program is free software; you can redistribute it and/or modify 19 * it under the terms of the GNU General Public License version 2 as 20 * published by the Free Software Foundation. 21 */ 22 23 #include <linux/kernel.h> 24 #include <linux/init.h> 25 26 #include "powerdomain.h" 27 28 #include "prcm-common.h" 29 #include "prcm44xx.h" 30 #include "prm7xx.h" 31 #include "prcm_mpu7xx.h" 32 33 /* iva_7xx_pwrdm: IVA-HD power domain */ 34 static struct powerdomain iva_7xx_pwrdm = { 35 .name = "iva_pwrdm", 36 .prcm_offs = DRA7XX_PRM_IVA_INST, 37 .prcm_partition = DRA7XX_PRM_PARTITION, 38 .pwrsts = PWRSTS_OFF_ON, 39 .banks = 4, 40 .pwrsts_mem_ret = { 41 [0] = PWRSTS_OFF_RET, /* hwa_mem */ 42 [1] = PWRSTS_OFF_RET, /* sl2_mem */ 43 [2] = PWRSTS_OFF_RET, /* tcm1_mem */ 44 [3] = PWRSTS_OFF_RET, /* tcm2_mem */ 45 }, 46 .pwrsts_mem_on = { 47 [0] = PWRSTS_ON, /* hwa_mem */ 48 [1] = PWRSTS_ON, /* sl2_mem */ 49 [2] = PWRSTS_ON, /* tcm1_mem */ 50 [3] = PWRSTS_ON, /* tcm2_mem */ 51 }, 52 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 53 }; 54 55 /* rtc_7xx_pwrdm: */ 56 static struct powerdomain rtc_7xx_pwrdm = { 57 .name = "rtc_pwrdm", 58 .prcm_offs = DRA7XX_PRM_RTC_INST, 59 .prcm_partition = DRA7XX_PRM_PARTITION, 60 .pwrsts = PWRSTS_ON, 61 }; 62 63 /* custefuse_7xx_pwrdm: Customer efuse controller power domain */ 64 static struct powerdomain custefuse_7xx_pwrdm = { 65 .name = "custefuse_pwrdm", 66 .prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST, 67 .prcm_partition = DRA7XX_PRM_PARTITION, 68 .pwrsts = PWRSTS_OFF_ON, 69 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 70 }; 71 72 /* ipu_7xx_pwrdm: Audio back end power domain */ 73 static struct powerdomain ipu_7xx_pwrdm = { 74 .name = "ipu_pwrdm", 75 .prcm_offs = DRA7XX_PRM_IPU_INST, 76 .prcm_partition = DRA7XX_PRM_PARTITION, 77 .pwrsts = PWRSTS_OFF_ON, 78 .banks = 2, 79 .pwrsts_mem_ret = { 80 [0] = PWRSTS_OFF_RET, /* aessmem */ 81 [1] = PWRSTS_OFF_RET, /* periphmem */ 82 }, 83 .pwrsts_mem_on = { 84 [0] = PWRSTS_ON, /* aessmem */ 85 [1] = PWRSTS_ON, /* periphmem */ 86 }, 87 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 88 }; 89 90 /* dss_7xx_pwrdm: Display subsystem power domain */ 91 static struct powerdomain dss_7xx_pwrdm = { 92 .name = "dss_pwrdm", 93 .prcm_offs = DRA7XX_PRM_DSS_INST, 94 .prcm_partition = DRA7XX_PRM_PARTITION, 95 .pwrsts = PWRSTS_OFF_ON, 96 .banks = 1, 97 .pwrsts_mem_ret = { 98 [0] = PWRSTS_OFF_RET, /* dss_mem */ 99 }, 100 .pwrsts_mem_on = { 101 [0] = PWRSTS_ON, /* dss_mem */ 102 }, 103 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 104 }; 105 106 /* l4per_7xx_pwrdm: Target peripherals power domain */ 107 static struct powerdomain l4per_7xx_pwrdm = { 108 .name = "l4per_pwrdm", 109 .prcm_offs = DRA7XX_PRM_L4PER_INST, 110 .prcm_partition = DRA7XX_PRM_PARTITION, 111 .pwrsts = PWRSTS_ON, 112 .banks = 2, 113 .pwrsts_mem_ret = { 114 [0] = PWRSTS_OFF_RET, /* nonretained_bank */ 115 [1] = PWRSTS_OFF_RET, /* retained_bank */ 116 }, 117 .pwrsts_mem_on = { 118 [0] = PWRSTS_ON, /* nonretained_bank */ 119 [1] = PWRSTS_ON, /* retained_bank */ 120 }, 121 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 122 }; 123 124 /* gpu_7xx_pwrdm: 3D accelerator power domain */ 125 static struct powerdomain gpu_7xx_pwrdm = { 126 .name = "gpu_pwrdm", 127 .prcm_offs = DRA7XX_PRM_GPU_INST, 128 .prcm_partition = DRA7XX_PRM_PARTITION, 129 .pwrsts = PWRSTS_OFF_ON, 130 .banks = 1, 131 .pwrsts_mem_ret = { 132 [0] = PWRSTS_OFF_RET, /* gpu_mem */ 133 }, 134 .pwrsts_mem_on = { 135 [0] = PWRSTS_ON, /* gpu_mem */ 136 }, 137 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 138 }; 139 140 /* wkupaon_7xx_pwrdm: Wake-up power domain */ 141 static struct powerdomain wkupaon_7xx_pwrdm = { 142 .name = "wkupaon_pwrdm", 143 .prcm_offs = DRA7XX_PRM_WKUPAON_INST, 144 .prcm_partition = DRA7XX_PRM_PARTITION, 145 .pwrsts = PWRSTS_ON, 146 .banks = 1, 147 .pwrsts_mem_ret = { 148 }, 149 .pwrsts_mem_on = { 150 [0] = PWRSTS_ON, /* wkup_bank */ 151 }, 152 }; 153 154 /* core_7xx_pwrdm: CORE power domain */ 155 static struct powerdomain core_7xx_pwrdm = { 156 .name = "core_pwrdm", 157 .prcm_offs = DRA7XX_PRM_CORE_INST, 158 .prcm_partition = DRA7XX_PRM_PARTITION, 159 .pwrsts = PWRSTS_ON, 160 .banks = 5, 161 .pwrsts_mem_ret = { 162 [0] = PWRSTS_OFF_RET, /* core_nret_bank */ 163 [1] = PWRSTS_OFF_RET, /* core_ocmram */ 164 [2] = PWRSTS_OFF_RET, /* core_other_bank */ 165 [3] = PWRSTS_OFF_RET, /* ipu_l2ram */ 166 [4] = PWRSTS_OFF_RET, /* ipu_unicache */ 167 }, 168 .pwrsts_mem_on = { 169 [0] = PWRSTS_ON, /* core_nret_bank */ 170 [1] = PWRSTS_ON, /* core_ocmram */ 171 [2] = PWRSTS_ON, /* core_other_bank */ 172 [3] = PWRSTS_ON, /* ipu_l2ram */ 173 [4] = PWRSTS_ON, /* ipu_unicache */ 174 }, 175 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 176 }; 177 178 /* coreaon_7xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */ 179 static struct powerdomain coreaon_7xx_pwrdm = { 180 .name = "coreaon_pwrdm", 181 .prcm_offs = DRA7XX_PRM_COREAON_INST, 182 .prcm_partition = DRA7XX_PRM_PARTITION, 183 .pwrsts = PWRSTS_ON, 184 }; 185 186 /* cpu0_7xx_pwrdm: MPU0 processor and Neon coprocessor power domain */ 187 static struct powerdomain cpu0_7xx_pwrdm = { 188 .name = "cpu0_pwrdm", 189 .prcm_offs = DRA7XX_MPU_PRCM_PRM_C0_INST, 190 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION, 191 .pwrsts = PWRSTS_RET_ON, 192 .pwrsts_logic_ret = PWRSTS_RET, 193 .banks = 1, 194 .pwrsts_mem_ret = { 195 [0] = PWRSTS_OFF_RET, /* cpu0_l1 */ 196 }, 197 .pwrsts_mem_on = { 198 [0] = PWRSTS_ON, /* cpu0_l1 */ 199 }, 200 }; 201 202 /* cpu1_7xx_pwrdm: MPU1 processor and Neon coprocessor power domain */ 203 static struct powerdomain cpu1_7xx_pwrdm = { 204 .name = "cpu1_pwrdm", 205 .prcm_offs = DRA7XX_MPU_PRCM_PRM_C1_INST, 206 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION, 207 .pwrsts = PWRSTS_RET_ON, 208 .pwrsts_logic_ret = PWRSTS_RET, 209 .banks = 1, 210 .pwrsts_mem_ret = { 211 [0] = PWRSTS_OFF_RET, /* cpu1_l1 */ 212 }, 213 .pwrsts_mem_on = { 214 [0] = PWRSTS_ON, /* cpu1_l1 */ 215 }, 216 }; 217 218 /* vpe_7xx_pwrdm: */ 219 static struct powerdomain vpe_7xx_pwrdm = { 220 .name = "vpe_pwrdm", 221 .prcm_offs = DRA7XX_PRM_VPE_INST, 222 .prcm_partition = DRA7XX_PRM_PARTITION, 223 .pwrsts = PWRSTS_OFF_ON, 224 .banks = 1, 225 .pwrsts_mem_ret = { 226 [0] = PWRSTS_OFF_RET, /* vpe_bank */ 227 }, 228 .pwrsts_mem_on = { 229 [0] = PWRSTS_ON, /* vpe_bank */ 230 }, 231 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 232 }; 233 234 /* mpu_7xx_pwrdm: Modena processor and the Neon coprocessor power domain */ 235 static struct powerdomain mpu_7xx_pwrdm = { 236 .name = "mpu_pwrdm", 237 .prcm_offs = DRA7XX_PRM_MPU_INST, 238 .prcm_partition = DRA7XX_PRM_PARTITION, 239 .pwrsts = PWRSTS_RET_ON, 240 .pwrsts_logic_ret = PWRSTS_RET, 241 .banks = 2, 242 .pwrsts_mem_ret = { 243 [0] = PWRSTS_OFF_RET, /* mpu_l2 */ 244 [1] = PWRSTS_RET, /* mpu_ram */ 245 }, 246 .pwrsts_mem_on = { 247 [0] = PWRSTS_ON, /* mpu_l2 */ 248 [1] = PWRSTS_ON, /* mpu_ram */ 249 }, 250 }; 251 252 /* l3init_7xx_pwrdm: L3 initators pheripherals power domain */ 253 static struct powerdomain l3init_7xx_pwrdm = { 254 .name = "l3init_pwrdm", 255 .prcm_offs = DRA7XX_PRM_L3INIT_INST, 256 .prcm_partition = DRA7XX_PRM_PARTITION, 257 .pwrsts = PWRSTS_ON, 258 .banks = 3, 259 .pwrsts_mem_ret = { 260 [0] = PWRSTS_OFF_RET, /* gmac_bank */ 261 [1] = PWRSTS_OFF_RET, /* l3init_bank1 */ 262 [2] = PWRSTS_OFF_RET, /* l3init_bank2 */ 263 }, 264 .pwrsts_mem_on = { 265 [0] = PWRSTS_ON, /* gmac_bank */ 266 [1] = PWRSTS_ON, /* l3init_bank1 */ 267 [2] = PWRSTS_ON, /* l3init_bank2 */ 268 }, 269 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 270 }; 271 272 /* eve3_7xx_pwrdm: */ 273 static struct powerdomain eve3_7xx_pwrdm = { 274 .name = "eve3_pwrdm", 275 .prcm_offs = DRA7XX_PRM_EVE3_INST, 276 .prcm_partition = DRA7XX_PRM_PARTITION, 277 .pwrsts = PWRSTS_OFF_ON, 278 .banks = 1, 279 .pwrsts_mem_ret = { 280 [0] = PWRSTS_OFF_RET, /* eve3_bank */ 281 }, 282 .pwrsts_mem_on = { 283 [0] = PWRSTS_ON, /* eve3_bank */ 284 }, 285 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 286 }; 287 288 /* emu_7xx_pwrdm: Emulation power domain */ 289 static struct powerdomain emu_7xx_pwrdm = { 290 .name = "emu_pwrdm", 291 .prcm_offs = DRA7XX_PRM_EMU_INST, 292 .prcm_partition = DRA7XX_PRM_PARTITION, 293 .pwrsts = PWRSTS_OFF_ON, 294 .banks = 1, 295 .pwrsts_mem_ret = { 296 [0] = PWRSTS_OFF_RET, /* emu_bank */ 297 }, 298 .pwrsts_mem_on = { 299 [0] = PWRSTS_ON, /* emu_bank */ 300 }, 301 }; 302 303 /* dsp2_7xx_pwrdm: */ 304 static struct powerdomain dsp2_7xx_pwrdm = { 305 .name = "dsp2_pwrdm", 306 .prcm_offs = DRA7XX_PRM_DSP2_INST, 307 .prcm_partition = DRA7XX_PRM_PARTITION, 308 .pwrsts = PWRSTS_OFF_ON, 309 .banks = 3, 310 .pwrsts_mem_ret = { 311 [0] = PWRSTS_OFF_RET, /* dsp2_edma */ 312 [1] = PWRSTS_OFF_RET, /* dsp2_l1 */ 313 [2] = PWRSTS_OFF_RET, /* dsp2_l2 */ 314 }, 315 .pwrsts_mem_on = { 316 [0] = PWRSTS_ON, /* dsp2_edma */ 317 [1] = PWRSTS_ON, /* dsp2_l1 */ 318 [2] = PWRSTS_ON, /* dsp2_l2 */ 319 }, 320 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 321 }; 322 323 /* dsp1_7xx_pwrdm: Tesla processor power domain */ 324 static struct powerdomain dsp1_7xx_pwrdm = { 325 .name = "dsp1_pwrdm", 326 .prcm_offs = DRA7XX_PRM_DSP1_INST, 327 .prcm_partition = DRA7XX_PRM_PARTITION, 328 .pwrsts = PWRSTS_OFF_ON, 329 .banks = 3, 330 .pwrsts_mem_ret = { 331 [0] = PWRSTS_OFF_RET, /* dsp1_edma */ 332 [1] = PWRSTS_OFF_RET, /* dsp1_l1 */ 333 [2] = PWRSTS_OFF_RET, /* dsp1_l2 */ 334 }, 335 .pwrsts_mem_on = { 336 [0] = PWRSTS_ON, /* dsp1_edma */ 337 [1] = PWRSTS_ON, /* dsp1_l1 */ 338 [2] = PWRSTS_ON, /* dsp1_l2 */ 339 }, 340 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 341 }; 342 343 /* cam_7xx_pwrdm: Camera subsystem power domain */ 344 static struct powerdomain cam_7xx_pwrdm = { 345 .name = "cam_pwrdm", 346 .prcm_offs = DRA7XX_PRM_CAM_INST, 347 .prcm_partition = DRA7XX_PRM_PARTITION, 348 .pwrsts = PWRSTS_OFF_ON, 349 .banks = 1, 350 .pwrsts_mem_ret = { 351 [0] = PWRSTS_OFF_RET, /* vip_bank */ 352 }, 353 .pwrsts_mem_on = { 354 [0] = PWRSTS_ON, /* vip_bank */ 355 }, 356 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 357 }; 358 359 /* eve4_7xx_pwrdm: */ 360 static struct powerdomain eve4_7xx_pwrdm = { 361 .name = "eve4_pwrdm", 362 .prcm_offs = DRA7XX_PRM_EVE4_INST, 363 .prcm_partition = DRA7XX_PRM_PARTITION, 364 .pwrsts = PWRSTS_OFF_ON, 365 .banks = 1, 366 .pwrsts_mem_ret = { 367 [0] = PWRSTS_OFF_RET, /* eve4_bank */ 368 }, 369 .pwrsts_mem_on = { 370 [0] = PWRSTS_ON, /* eve4_bank */ 371 }, 372 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 373 }; 374 375 /* eve2_7xx_pwrdm: */ 376 static struct powerdomain eve2_7xx_pwrdm = { 377 .name = "eve2_pwrdm", 378 .prcm_offs = DRA7XX_PRM_EVE2_INST, 379 .prcm_partition = DRA7XX_PRM_PARTITION, 380 .pwrsts = PWRSTS_OFF_ON, 381 .banks = 1, 382 .pwrsts_mem_ret = { 383 [0] = PWRSTS_OFF_RET, /* eve2_bank */ 384 }, 385 .pwrsts_mem_on = { 386 [0] = PWRSTS_ON, /* eve2_bank */ 387 }, 388 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 389 }; 390 391 /* eve1_7xx_pwrdm: */ 392 static struct powerdomain eve1_7xx_pwrdm = { 393 .name = "eve1_pwrdm", 394 .prcm_offs = DRA7XX_PRM_EVE1_INST, 395 .prcm_partition = DRA7XX_PRM_PARTITION, 396 .pwrsts = PWRSTS_OFF_ON, 397 .banks = 1, 398 .pwrsts_mem_ret = { 399 [0] = PWRSTS_OFF_RET, /* eve1_bank */ 400 }, 401 .pwrsts_mem_on = { 402 [0] = PWRSTS_ON, /* eve1_bank */ 403 }, 404 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 405 }; 406 407 /* 408 * The following power domains are not under SW control 409 * 410 * mpuaon 411 * mmaon 412 */ 413 414 /* As powerdomains are added or removed above, this list must also be changed */ 415 static struct powerdomain *powerdomains_dra7xx[] __initdata = { 416 &iva_7xx_pwrdm, 417 &rtc_7xx_pwrdm, 418 &custefuse_7xx_pwrdm, 419 &ipu_7xx_pwrdm, 420 &dss_7xx_pwrdm, 421 &l4per_7xx_pwrdm, 422 &gpu_7xx_pwrdm, 423 &wkupaon_7xx_pwrdm, 424 &core_7xx_pwrdm, 425 &coreaon_7xx_pwrdm, 426 &cpu0_7xx_pwrdm, 427 &cpu1_7xx_pwrdm, 428 &vpe_7xx_pwrdm, 429 &mpu_7xx_pwrdm, 430 &l3init_7xx_pwrdm, 431 &eve3_7xx_pwrdm, 432 &emu_7xx_pwrdm, 433 &dsp2_7xx_pwrdm, 434 &dsp1_7xx_pwrdm, 435 &cam_7xx_pwrdm, 436 &eve4_7xx_pwrdm, 437 &eve2_7xx_pwrdm, 438 &eve1_7xx_pwrdm, 439 NULL 440 }; 441 442 void __init dra7xx_powerdomains_init(void) 443 { 444 pwrdm_register_platform_funcs(&omap4_pwrdm_operations); 445 pwrdm_register_pwrdms(powerdomains_dra7xx); 446 pwrdm_complete_init(); 447 } 448