1 /* 2 * DRA7xx Power domains framework 3 * 4 * Copyright (C) 2009-2013 Texas Instruments, Inc. 5 * Copyright (C) 2009-2011 Nokia Corporation 6 * 7 * Generated by code originally written by: 8 * Abhijit Pagare (abhijitpagare@ti.com) 9 * Benoit Cousson (b-cousson@ti.com) 10 * Paul Walmsley (paul@pwsan.com) 11 * 12 * This file is automatically generated from the OMAP hardware databases. 13 * We respectfully ask that any modifications to this file be coordinated 14 * with the public linux-omap@vger.kernel.org mailing list and the 15 * authors above to ensure that the autogeneration scripts are kept 16 * up-to-date with the file contents. 17 * 18 * This program is free software; you can redistribute it and/or modify 19 * it under the terms of the GNU General Public License version 2 as 20 * published by the Free Software Foundation. 21 */ 22 23 #include <linux/kernel.h> 24 #include <linux/init.h> 25 26 #include "powerdomain.h" 27 28 #include "prcm-common.h" 29 #include "prcm44xx.h" 30 #include "prm7xx.h" 31 #include "prcm_mpu7xx.h" 32 #include "soc.h" 33 34 /* iva_7xx_pwrdm: IVA-HD power domain */ 35 static struct powerdomain iva_7xx_pwrdm = { 36 .name = "iva_pwrdm", 37 .prcm_offs = DRA7XX_PRM_IVA_INST, 38 .prcm_partition = DRA7XX_PRM_PARTITION, 39 .pwrsts = PWRSTS_OFF_ON, 40 .banks = 4, 41 .pwrsts_mem_on = { 42 [0] = PWRSTS_ON, /* hwa_mem */ 43 [1] = PWRSTS_ON, /* sl2_mem */ 44 [2] = PWRSTS_ON, /* tcm1_mem */ 45 [3] = PWRSTS_ON, /* tcm2_mem */ 46 }, 47 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 48 }; 49 50 /* rtc_7xx_pwrdm: */ 51 static struct powerdomain rtc_7xx_pwrdm = { 52 .name = "rtc_pwrdm", 53 .prcm_offs = DRA7XX_PRM_RTC_INST, 54 .prcm_partition = DRA7XX_PRM_PARTITION, 55 .pwrsts = PWRSTS_ON, 56 }; 57 58 /* custefuse_7xx_pwrdm: Customer efuse controller power domain */ 59 static struct powerdomain custefuse_7xx_pwrdm = { 60 .name = "custefuse_pwrdm", 61 .prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST, 62 .prcm_partition = DRA7XX_PRM_PARTITION, 63 .pwrsts = PWRSTS_OFF_ON, 64 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 65 }; 66 67 /* custefuse_aon_7xx_pwrdm: Customer efuse controller power domain */ 68 static struct powerdomain custefuse_aon_7xx_pwrdm = { 69 .name = "custefuse_pwrdm", 70 .prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST, 71 .prcm_partition = DRA7XX_PRM_PARTITION, 72 .pwrsts = PWRSTS_ON, 73 }; 74 75 /* ipu_7xx_pwrdm: Audio back end power domain */ 76 static struct powerdomain ipu_7xx_pwrdm = { 77 .name = "ipu_pwrdm", 78 .prcm_offs = DRA7XX_PRM_IPU_INST, 79 .prcm_partition = DRA7XX_PRM_PARTITION, 80 .pwrsts = PWRSTS_OFF_ON, 81 .banks = 2, 82 .pwrsts_mem_on = { 83 [0] = PWRSTS_ON, /* aessmem */ 84 [1] = PWRSTS_ON, /* periphmem */ 85 }, 86 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 87 }; 88 89 /* dss_7xx_pwrdm: Display subsystem power domain */ 90 static struct powerdomain dss_7xx_pwrdm = { 91 .name = "dss_pwrdm", 92 .prcm_offs = DRA7XX_PRM_DSS_INST, 93 .prcm_partition = DRA7XX_PRM_PARTITION, 94 .pwrsts = PWRSTS_OFF_ON, 95 .banks = 1, 96 .pwrsts_mem_on = { 97 [0] = PWRSTS_ON, /* dss_mem */ 98 }, 99 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 100 }; 101 102 /* l4per_7xx_pwrdm: Target peripherals power domain */ 103 static struct powerdomain l4per_7xx_pwrdm = { 104 .name = "l4per_pwrdm", 105 .prcm_offs = DRA7XX_PRM_L4PER_INST, 106 .prcm_partition = DRA7XX_PRM_PARTITION, 107 .pwrsts = PWRSTS_ON, 108 .banks = 2, 109 .pwrsts_mem_on = { 110 [0] = PWRSTS_ON, /* nonretained_bank */ 111 [1] = PWRSTS_ON, /* retained_bank */ 112 }, 113 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 114 }; 115 116 /* gpu_7xx_pwrdm: 3D accelerator power domain */ 117 static struct powerdomain gpu_7xx_pwrdm = { 118 .name = "gpu_pwrdm", 119 .prcm_offs = DRA7XX_PRM_GPU_INST, 120 .prcm_partition = DRA7XX_PRM_PARTITION, 121 .pwrsts = PWRSTS_OFF_ON, 122 .banks = 1, 123 .pwrsts_mem_on = { 124 [0] = PWRSTS_ON, /* gpu_mem */ 125 }, 126 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 127 }; 128 129 /* wkupaon_7xx_pwrdm: Wake-up power domain */ 130 static struct powerdomain wkupaon_7xx_pwrdm = { 131 .name = "wkupaon_pwrdm", 132 .prcm_offs = DRA7XX_PRM_WKUPAON_INST, 133 .prcm_partition = DRA7XX_PRM_PARTITION, 134 .pwrsts = PWRSTS_ON, 135 .banks = 1, 136 .pwrsts_mem_on = { 137 [0] = PWRSTS_ON, /* wkup_bank */ 138 }, 139 }; 140 141 /* core_7xx_pwrdm: CORE power domain */ 142 static struct powerdomain core_7xx_pwrdm = { 143 .name = "core_pwrdm", 144 .prcm_offs = DRA7XX_PRM_CORE_INST, 145 .prcm_partition = DRA7XX_PRM_PARTITION, 146 .pwrsts = PWRSTS_ON, 147 .banks = 5, 148 .pwrsts_mem_on = { 149 [0] = PWRSTS_ON, /* core_nret_bank */ 150 [1] = PWRSTS_ON, /* core_ocmram */ 151 [2] = PWRSTS_ON, /* core_other_bank */ 152 [3] = PWRSTS_ON, /* ipu_l2ram */ 153 [4] = PWRSTS_ON, /* ipu_unicache */ 154 }, 155 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 156 }; 157 158 /* coreaon_7xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */ 159 static struct powerdomain coreaon_7xx_pwrdm = { 160 .name = "coreaon_pwrdm", 161 .prcm_offs = DRA7XX_PRM_COREAON_INST, 162 .prcm_partition = DRA7XX_PRM_PARTITION, 163 .pwrsts = PWRSTS_ON, 164 }; 165 166 /* cpu0_7xx_pwrdm: MPU0 processor and Neon coprocessor power domain */ 167 static struct powerdomain cpu0_7xx_pwrdm = { 168 .name = "cpu0_pwrdm", 169 .prcm_offs = DRA7XX_MPU_PRCM_PRM_C0_INST, 170 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION, 171 .pwrsts = PWRSTS_RET_ON, 172 .pwrsts_logic_ret = PWRSTS_RET, 173 .banks = 1, 174 .pwrsts_mem_ret = { 175 [0] = PWRSTS_OFF_RET, /* cpu0_l1 */ 176 }, 177 .pwrsts_mem_on = { 178 [0] = PWRSTS_ON, /* cpu0_l1 */ 179 }, 180 }; 181 182 /* cpu1_7xx_pwrdm: MPU1 processor and Neon coprocessor power domain */ 183 static struct powerdomain cpu1_7xx_pwrdm = { 184 .name = "cpu1_pwrdm", 185 .prcm_offs = DRA7XX_MPU_PRCM_PRM_C1_INST, 186 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION, 187 .pwrsts = PWRSTS_RET_ON, 188 .pwrsts_logic_ret = PWRSTS_RET, 189 .banks = 1, 190 .pwrsts_mem_ret = { 191 [0] = PWRSTS_OFF_RET, /* cpu1_l1 */ 192 }, 193 .pwrsts_mem_on = { 194 [0] = PWRSTS_ON, /* cpu1_l1 */ 195 }, 196 }; 197 198 /* vpe_7xx_pwrdm: */ 199 static struct powerdomain vpe_7xx_pwrdm = { 200 .name = "vpe_pwrdm", 201 .prcm_offs = DRA7XX_PRM_VPE_INST, 202 .prcm_partition = DRA7XX_PRM_PARTITION, 203 .pwrsts = PWRSTS_OFF_ON, 204 .banks = 1, 205 .pwrsts_mem_on = { 206 [0] = PWRSTS_ON, /* vpe_bank */ 207 }, 208 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 209 }; 210 211 /* mpu_7xx_pwrdm: Modena processor and the Neon coprocessor power domain */ 212 static struct powerdomain mpu_7xx_pwrdm = { 213 .name = "mpu_pwrdm", 214 .prcm_offs = DRA7XX_PRM_MPU_INST, 215 .prcm_partition = DRA7XX_PRM_PARTITION, 216 .pwrsts = PWRSTS_RET_ON, 217 .pwrsts_logic_ret = PWRSTS_RET, 218 .banks = 2, 219 .pwrsts_mem_ret = { 220 [0] = PWRSTS_OFF_RET, /* mpu_l2 */ 221 [1] = PWRSTS_RET, /* mpu_ram */ 222 }, 223 .pwrsts_mem_on = { 224 [0] = PWRSTS_ON, /* mpu_l2 */ 225 [1] = PWRSTS_ON, /* mpu_ram */ 226 }, 227 }; 228 229 /* l3init_7xx_pwrdm: L3 initators pheripherals power domain */ 230 static struct powerdomain l3init_7xx_pwrdm = { 231 .name = "l3init_pwrdm", 232 .prcm_offs = DRA7XX_PRM_L3INIT_INST, 233 .prcm_partition = DRA7XX_PRM_PARTITION, 234 .pwrsts = PWRSTS_ON, 235 .banks = 3, 236 .pwrsts_mem_on = { 237 [0] = PWRSTS_ON, /* gmac_bank */ 238 [1] = PWRSTS_ON, /* l3init_bank1 */ 239 [2] = PWRSTS_ON, /* l3init_bank2 */ 240 }, 241 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 242 }; 243 244 /* eve3_7xx_pwrdm: */ 245 static struct powerdomain eve3_7xx_pwrdm = { 246 .name = "eve3_pwrdm", 247 .prcm_offs = DRA7XX_PRM_EVE3_INST, 248 .prcm_partition = DRA7XX_PRM_PARTITION, 249 .pwrsts = PWRSTS_OFF_ON, 250 .banks = 1, 251 .pwrsts_mem_on = { 252 [0] = PWRSTS_ON, /* eve3_bank */ 253 }, 254 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 255 }; 256 257 /* emu_7xx_pwrdm: Emulation power domain */ 258 static struct powerdomain emu_7xx_pwrdm = { 259 .name = "emu_pwrdm", 260 .prcm_offs = DRA7XX_PRM_EMU_INST, 261 .prcm_partition = DRA7XX_PRM_PARTITION, 262 .pwrsts = PWRSTS_OFF_ON, 263 .banks = 1, 264 .pwrsts_mem_on = { 265 [0] = PWRSTS_ON, /* emu_bank */ 266 }, 267 }; 268 269 /* dsp2_7xx_pwrdm: */ 270 static struct powerdomain dsp2_7xx_pwrdm = { 271 .name = "dsp2_pwrdm", 272 .prcm_offs = DRA7XX_PRM_DSP2_INST, 273 .prcm_partition = DRA7XX_PRM_PARTITION, 274 .pwrsts = PWRSTS_OFF_ON, 275 .banks = 3, 276 .pwrsts_mem_on = { 277 [0] = PWRSTS_ON, /* dsp2_edma */ 278 [1] = PWRSTS_ON, /* dsp2_l1 */ 279 [2] = PWRSTS_ON, /* dsp2_l2 */ 280 }, 281 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 282 }; 283 284 /* dsp1_7xx_pwrdm: Tesla processor power domain */ 285 static struct powerdomain dsp1_7xx_pwrdm = { 286 .name = "dsp1_pwrdm", 287 .prcm_offs = DRA7XX_PRM_DSP1_INST, 288 .prcm_partition = DRA7XX_PRM_PARTITION, 289 .pwrsts = PWRSTS_OFF_ON, 290 .banks = 3, 291 .pwrsts_mem_on = { 292 [0] = PWRSTS_ON, /* dsp1_edma */ 293 [1] = PWRSTS_ON, /* dsp1_l1 */ 294 [2] = PWRSTS_ON, /* dsp1_l2 */ 295 }, 296 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 297 }; 298 299 /* cam_7xx_pwrdm: Camera subsystem power domain */ 300 static struct powerdomain cam_7xx_pwrdm = { 301 .name = "cam_pwrdm", 302 .prcm_offs = DRA7XX_PRM_CAM_INST, 303 .prcm_partition = DRA7XX_PRM_PARTITION, 304 .pwrsts = PWRSTS_OFF_ON, 305 .banks = 1, 306 .pwrsts_mem_on = { 307 [0] = PWRSTS_ON, /* vip_bank */ 308 }, 309 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 310 }; 311 312 /* eve4_7xx_pwrdm: */ 313 static struct powerdomain eve4_7xx_pwrdm = { 314 .name = "eve4_pwrdm", 315 .prcm_offs = DRA7XX_PRM_EVE4_INST, 316 .prcm_partition = DRA7XX_PRM_PARTITION, 317 .pwrsts = PWRSTS_OFF_ON, 318 .banks = 1, 319 .pwrsts_mem_on = { 320 [0] = PWRSTS_ON, /* eve4_bank */ 321 }, 322 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 323 }; 324 325 /* eve2_7xx_pwrdm: */ 326 static struct powerdomain eve2_7xx_pwrdm = { 327 .name = "eve2_pwrdm", 328 .prcm_offs = DRA7XX_PRM_EVE2_INST, 329 .prcm_partition = DRA7XX_PRM_PARTITION, 330 .pwrsts = PWRSTS_OFF_ON, 331 .banks = 1, 332 .pwrsts_mem_on = { 333 [0] = PWRSTS_ON, /* eve2_bank */ 334 }, 335 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 336 }; 337 338 /* eve1_7xx_pwrdm: */ 339 static struct powerdomain eve1_7xx_pwrdm = { 340 .name = "eve1_pwrdm", 341 .prcm_offs = DRA7XX_PRM_EVE1_INST, 342 .prcm_partition = DRA7XX_PRM_PARTITION, 343 .pwrsts = PWRSTS_OFF_ON, 344 .banks = 1, 345 .pwrsts_mem_on = { 346 [0] = PWRSTS_ON, /* eve1_bank */ 347 }, 348 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 349 }; 350 351 /* 352 * The following power domains are not under SW control 353 * 354 * mpuaon 355 * mmaon 356 */ 357 358 /* As powerdomains are added or removed above, this list must also be changed */ 359 static struct powerdomain *powerdomains_dra7xx[] __initdata = { 360 &iva_7xx_pwrdm, 361 &rtc_7xx_pwrdm, 362 &ipu_7xx_pwrdm, 363 &dss_7xx_pwrdm, 364 &l4per_7xx_pwrdm, 365 &gpu_7xx_pwrdm, 366 &wkupaon_7xx_pwrdm, 367 &core_7xx_pwrdm, 368 &coreaon_7xx_pwrdm, 369 &cpu0_7xx_pwrdm, 370 &cpu1_7xx_pwrdm, 371 &vpe_7xx_pwrdm, 372 &mpu_7xx_pwrdm, 373 &l3init_7xx_pwrdm, 374 &eve3_7xx_pwrdm, 375 &emu_7xx_pwrdm, 376 &dsp2_7xx_pwrdm, 377 &dsp1_7xx_pwrdm, 378 &cam_7xx_pwrdm, 379 &eve4_7xx_pwrdm, 380 &eve2_7xx_pwrdm, 381 &eve1_7xx_pwrdm, 382 NULL 383 }; 384 385 static struct powerdomain *powerdomains_dra76x[] __initdata = { 386 &custefuse_aon_7xx_pwrdm, 387 NULL 388 }; 389 390 static struct powerdomain *powerdomains_dra74x[] __initdata = { 391 &custefuse_7xx_pwrdm, 392 NULL 393 }; 394 395 static struct powerdomain *powerdomains_dra72x[] __initdata = { 396 &custefuse_aon_7xx_pwrdm, 397 NULL 398 }; 399 400 void __init dra7xx_powerdomains_init(void) 401 { 402 pwrdm_register_platform_funcs(&omap4_pwrdm_operations); 403 pwrdm_register_pwrdms(powerdomains_dra7xx); 404 405 if (soc_is_dra76x()) 406 pwrdm_register_pwrdms(powerdomains_dra76x); 407 else if (soc_is_dra74x()) 408 pwrdm_register_pwrdms(powerdomains_dra74x); 409 else if (soc_is_dra72x()) 410 pwrdm_register_pwrdms(powerdomains_dra72x); 411 412 pwrdm_complete_init(); 413 } 414