197dd16b1SAmbresh K /* 297dd16b1SAmbresh K * DRA7xx Power domains framework 397dd16b1SAmbresh K * 497dd16b1SAmbresh K * Copyright (C) 2009-2013 Texas Instruments, Inc. 597dd16b1SAmbresh K * Copyright (C) 2009-2011 Nokia Corporation 697dd16b1SAmbresh K * 797dd16b1SAmbresh K * Generated by code originally written by: 897dd16b1SAmbresh K * Abhijit Pagare (abhijitpagare@ti.com) 997dd16b1SAmbresh K * Benoit Cousson (b-cousson@ti.com) 1097dd16b1SAmbresh K * Paul Walmsley (paul@pwsan.com) 1197dd16b1SAmbresh K * 1297dd16b1SAmbresh K * This file is automatically generated from the OMAP hardware databases. 1397dd16b1SAmbresh K * We respectfully ask that any modifications to this file be coordinated 1497dd16b1SAmbresh K * with the public linux-omap@vger.kernel.org mailing list and the 1597dd16b1SAmbresh K * authors above to ensure that the autogeneration scripts are kept 1697dd16b1SAmbresh K * up-to-date with the file contents. 1797dd16b1SAmbresh K * 1897dd16b1SAmbresh K * This program is free software; you can redistribute it and/or modify 1997dd16b1SAmbresh K * it under the terms of the GNU General Public License version 2 as 2097dd16b1SAmbresh K * published by the Free Software Foundation. 2197dd16b1SAmbresh K */ 2297dd16b1SAmbresh K 2397dd16b1SAmbresh K #include <linux/kernel.h> 2497dd16b1SAmbresh K #include <linux/init.h> 2597dd16b1SAmbresh K 2697dd16b1SAmbresh K #include "powerdomain.h" 2797dd16b1SAmbresh K 2897dd16b1SAmbresh K #include "prcm-common.h" 2997dd16b1SAmbresh K #include "prcm44xx.h" 3097dd16b1SAmbresh K #include "prm7xx.h" 3197dd16b1SAmbresh K #include "prcm_mpu7xx.h" 3297dd16b1SAmbresh K 3397dd16b1SAmbresh K /* iva_7xx_pwrdm: IVA-HD power domain */ 3497dd16b1SAmbresh K static struct powerdomain iva_7xx_pwrdm = { 3597dd16b1SAmbresh K .name = "iva_pwrdm", 3697dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_IVA_INST, 3797dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 38dac4fba2SNishanth Menon .pwrsts = PWRSTS_OFF_ON, 3997dd16b1SAmbresh K .pwrsts_logic_ret = PWRSTS_OFF, 4097dd16b1SAmbresh K .banks = 4, 4197dd16b1SAmbresh K .pwrsts_mem_ret = { 4297dd16b1SAmbresh K [0] = PWRSTS_OFF_RET, /* hwa_mem */ 4397dd16b1SAmbresh K [1] = PWRSTS_OFF_RET, /* sl2_mem */ 4497dd16b1SAmbresh K [2] = PWRSTS_OFF_RET, /* tcm1_mem */ 4597dd16b1SAmbresh K [3] = PWRSTS_OFF_RET, /* tcm2_mem */ 4697dd16b1SAmbresh K }, 4797dd16b1SAmbresh K .pwrsts_mem_on = { 4841feb8efSNishanth Menon [0] = PWRSTS_ON, /* hwa_mem */ 4941feb8efSNishanth Menon [1] = PWRSTS_ON, /* sl2_mem */ 5041feb8efSNishanth Menon [2] = PWRSTS_ON, /* tcm1_mem */ 5141feb8efSNishanth Menon [3] = PWRSTS_ON, /* tcm2_mem */ 5297dd16b1SAmbresh K }, 5397dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 5497dd16b1SAmbresh K }; 5597dd16b1SAmbresh K 5697dd16b1SAmbresh K /* rtc_7xx_pwrdm: */ 5797dd16b1SAmbresh K static struct powerdomain rtc_7xx_pwrdm = { 5897dd16b1SAmbresh K .name = "rtc_pwrdm", 5997dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_RTC_INST, 6097dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 6197dd16b1SAmbresh K .pwrsts = PWRSTS_ON, 6297dd16b1SAmbresh K }; 6397dd16b1SAmbresh K 6497dd16b1SAmbresh K /* custefuse_7xx_pwrdm: Customer efuse controller power domain */ 6597dd16b1SAmbresh K static struct powerdomain custefuse_7xx_pwrdm = { 6697dd16b1SAmbresh K .name = "custefuse_pwrdm", 6797dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST, 6897dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 6997dd16b1SAmbresh K .pwrsts = PWRSTS_OFF_ON, 7097dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 7197dd16b1SAmbresh K }; 7297dd16b1SAmbresh K 7397dd16b1SAmbresh K /* ipu_7xx_pwrdm: Audio back end power domain */ 7497dd16b1SAmbresh K static struct powerdomain ipu_7xx_pwrdm = { 7597dd16b1SAmbresh K .name = "ipu_pwrdm", 7697dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_IPU_INST, 7797dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 78dac4fba2SNishanth Menon .pwrsts = PWRSTS_OFF_ON, 7997dd16b1SAmbresh K .pwrsts_logic_ret = PWRSTS_OFF, 8097dd16b1SAmbresh K .banks = 2, 8197dd16b1SAmbresh K .pwrsts_mem_ret = { 8297dd16b1SAmbresh K [0] = PWRSTS_OFF_RET, /* aessmem */ 8397dd16b1SAmbresh K [1] = PWRSTS_OFF_RET, /* periphmem */ 8497dd16b1SAmbresh K }, 8597dd16b1SAmbresh K .pwrsts_mem_on = { 8641feb8efSNishanth Menon [0] = PWRSTS_ON, /* aessmem */ 8741feb8efSNishanth Menon [1] = PWRSTS_ON, /* periphmem */ 8897dd16b1SAmbresh K }, 8997dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 9097dd16b1SAmbresh K }; 9197dd16b1SAmbresh K 9297dd16b1SAmbresh K /* dss_7xx_pwrdm: Display subsystem power domain */ 9397dd16b1SAmbresh K static struct powerdomain dss_7xx_pwrdm = { 9497dd16b1SAmbresh K .name = "dss_pwrdm", 9597dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_DSS_INST, 9697dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 97dac4fba2SNishanth Menon .pwrsts = PWRSTS_OFF_ON, 9897dd16b1SAmbresh K .pwrsts_logic_ret = PWRSTS_OFF, 9997dd16b1SAmbresh K .banks = 1, 10097dd16b1SAmbresh K .pwrsts_mem_ret = { 10197dd16b1SAmbresh K [0] = PWRSTS_OFF_RET, /* dss_mem */ 10297dd16b1SAmbresh K }, 10397dd16b1SAmbresh K .pwrsts_mem_on = { 10441feb8efSNishanth Menon [0] = PWRSTS_ON, /* dss_mem */ 10597dd16b1SAmbresh K }, 10697dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 10797dd16b1SAmbresh K }; 10897dd16b1SAmbresh K 10997dd16b1SAmbresh K /* l4per_7xx_pwrdm: Target peripherals power domain */ 11097dd16b1SAmbresh K static struct powerdomain l4per_7xx_pwrdm = { 11197dd16b1SAmbresh K .name = "l4per_pwrdm", 11297dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_L4PER_INST, 11397dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 114d16c0d72SNishanth Menon .pwrsts = PWRSTS_ON, 115dac4fba2SNishanth Menon .pwrsts_logic_ret = PWRSTS_RET, 11697dd16b1SAmbresh K .banks = 2, 11797dd16b1SAmbresh K .pwrsts_mem_ret = { 11897dd16b1SAmbresh K [0] = PWRSTS_OFF_RET, /* nonretained_bank */ 11997dd16b1SAmbresh K [1] = PWRSTS_OFF_RET, /* retained_bank */ 12097dd16b1SAmbresh K }, 12197dd16b1SAmbresh K .pwrsts_mem_on = { 12241feb8efSNishanth Menon [0] = PWRSTS_ON, /* nonretained_bank */ 12341feb8efSNishanth Menon [1] = PWRSTS_ON, /* retained_bank */ 12497dd16b1SAmbresh K }, 12597dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 12697dd16b1SAmbresh K }; 12797dd16b1SAmbresh K 12897dd16b1SAmbresh K /* gpu_7xx_pwrdm: 3D accelerator power domain */ 12997dd16b1SAmbresh K static struct powerdomain gpu_7xx_pwrdm = { 13097dd16b1SAmbresh K .name = "gpu_pwrdm", 13197dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_GPU_INST, 13297dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 13397dd16b1SAmbresh K .pwrsts = PWRSTS_OFF_ON, 13497dd16b1SAmbresh K .banks = 1, 13597dd16b1SAmbresh K .pwrsts_mem_ret = { 13697dd16b1SAmbresh K [0] = PWRSTS_OFF_RET, /* gpu_mem */ 13797dd16b1SAmbresh K }, 13897dd16b1SAmbresh K .pwrsts_mem_on = { 13941feb8efSNishanth Menon [0] = PWRSTS_ON, /* gpu_mem */ 14097dd16b1SAmbresh K }, 14197dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 14297dd16b1SAmbresh K }; 14397dd16b1SAmbresh K 14497dd16b1SAmbresh K /* wkupaon_7xx_pwrdm: Wake-up power domain */ 14597dd16b1SAmbresh K static struct powerdomain wkupaon_7xx_pwrdm = { 14697dd16b1SAmbresh K .name = "wkupaon_pwrdm", 14797dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_WKUPAON_INST, 14897dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 14997dd16b1SAmbresh K .pwrsts = PWRSTS_ON, 15097dd16b1SAmbresh K .banks = 1, 15197dd16b1SAmbresh K .pwrsts_mem_ret = { 15297dd16b1SAmbresh K }, 15397dd16b1SAmbresh K .pwrsts_mem_on = { 15497dd16b1SAmbresh K [0] = PWRSTS_ON, /* wkup_bank */ 15597dd16b1SAmbresh K }, 15697dd16b1SAmbresh K }; 15797dd16b1SAmbresh K 15897dd16b1SAmbresh K /* core_7xx_pwrdm: CORE power domain */ 15997dd16b1SAmbresh K static struct powerdomain core_7xx_pwrdm = { 16097dd16b1SAmbresh K .name = "core_pwrdm", 16197dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_CORE_INST, 16297dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 163f971512cSNishanth Menon .pwrsts = PWRSTS_ON, 164cafc8cb5SNishanth Menon .pwrsts_logic_ret = PWRSTS_RET, 16597dd16b1SAmbresh K .banks = 5, 16697dd16b1SAmbresh K .pwrsts_mem_ret = { 16797dd16b1SAmbresh K [0] = PWRSTS_OFF_RET, /* core_nret_bank */ 16897dd16b1SAmbresh K [1] = PWRSTS_OFF_RET, /* core_ocmram */ 16997dd16b1SAmbresh K [2] = PWRSTS_OFF_RET, /* core_other_bank */ 17097dd16b1SAmbresh K [3] = PWRSTS_OFF_RET, /* ipu_l2ram */ 17197dd16b1SAmbresh K [4] = PWRSTS_OFF_RET, /* ipu_unicache */ 17297dd16b1SAmbresh K }, 17397dd16b1SAmbresh K .pwrsts_mem_on = { 17441feb8efSNishanth Menon [0] = PWRSTS_ON, /* core_nret_bank */ 17541feb8efSNishanth Menon [1] = PWRSTS_ON, /* core_ocmram */ 17641feb8efSNishanth Menon [2] = PWRSTS_ON, /* core_other_bank */ 17741feb8efSNishanth Menon [3] = PWRSTS_ON, /* ipu_l2ram */ 17841feb8efSNishanth Menon [4] = PWRSTS_ON, /* ipu_unicache */ 17997dd16b1SAmbresh K }, 18097dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 18197dd16b1SAmbresh K }; 18297dd16b1SAmbresh K 18397dd16b1SAmbresh K /* coreaon_7xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */ 18497dd16b1SAmbresh K static struct powerdomain coreaon_7xx_pwrdm = { 18597dd16b1SAmbresh K .name = "coreaon_pwrdm", 18697dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_COREAON_INST, 18797dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 18897dd16b1SAmbresh K .pwrsts = PWRSTS_ON, 18997dd16b1SAmbresh K }; 19097dd16b1SAmbresh K 19197dd16b1SAmbresh K /* cpu0_7xx_pwrdm: MPU0 processor and Neon coprocessor power domain */ 19297dd16b1SAmbresh K static struct powerdomain cpu0_7xx_pwrdm = { 19397dd16b1SAmbresh K .name = "cpu0_pwrdm", 19497dd16b1SAmbresh K .prcm_offs = DRA7XX_MPU_PRCM_PRM_C0_INST, 19597dd16b1SAmbresh K .prcm_partition = DRA7XX_MPU_PRCM_PARTITION, 196cafc8cb5SNishanth Menon .pwrsts = PWRSTS_RET_ON, 197cafc8cb5SNishanth Menon .pwrsts_logic_ret = PWRSTS_RET, 19897dd16b1SAmbresh K .banks = 1, 19997dd16b1SAmbresh K .pwrsts_mem_ret = { 20097dd16b1SAmbresh K [0] = PWRSTS_OFF_RET, /* cpu0_l1 */ 20197dd16b1SAmbresh K }, 20297dd16b1SAmbresh K .pwrsts_mem_on = { 20397dd16b1SAmbresh K [0] = PWRSTS_ON, /* cpu0_l1 */ 20497dd16b1SAmbresh K }, 20597dd16b1SAmbresh K }; 20697dd16b1SAmbresh K 20797dd16b1SAmbresh K /* cpu1_7xx_pwrdm: MPU1 processor and Neon coprocessor power domain */ 20897dd16b1SAmbresh K static struct powerdomain cpu1_7xx_pwrdm = { 20997dd16b1SAmbresh K .name = "cpu1_pwrdm", 21097dd16b1SAmbresh K .prcm_offs = DRA7XX_MPU_PRCM_PRM_C1_INST, 21197dd16b1SAmbresh K .prcm_partition = DRA7XX_MPU_PRCM_PARTITION, 212cafc8cb5SNishanth Menon .pwrsts = PWRSTS_RET_ON, 213cafc8cb5SNishanth Menon .pwrsts_logic_ret = PWRSTS_RET, 21497dd16b1SAmbresh K .banks = 1, 21597dd16b1SAmbresh K .pwrsts_mem_ret = { 21697dd16b1SAmbresh K [0] = PWRSTS_OFF_RET, /* cpu1_l1 */ 21797dd16b1SAmbresh K }, 21897dd16b1SAmbresh K .pwrsts_mem_on = { 21997dd16b1SAmbresh K [0] = PWRSTS_ON, /* cpu1_l1 */ 22097dd16b1SAmbresh K }, 22197dd16b1SAmbresh K }; 22297dd16b1SAmbresh K 22397dd16b1SAmbresh K /* vpe_7xx_pwrdm: */ 22497dd16b1SAmbresh K static struct powerdomain vpe_7xx_pwrdm = { 22597dd16b1SAmbresh K .name = "vpe_pwrdm", 22697dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_VPE_INST, 22797dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 228dac4fba2SNishanth Menon .pwrsts = PWRSTS_OFF_ON, 229dac4fba2SNishanth Menon .pwrsts_logic_ret = PWRSTS_OFF, 23097dd16b1SAmbresh K .banks = 1, 23197dd16b1SAmbresh K .pwrsts_mem_ret = { 23297dd16b1SAmbresh K [0] = PWRSTS_OFF_RET, /* vpe_bank */ 23397dd16b1SAmbresh K }, 23497dd16b1SAmbresh K .pwrsts_mem_on = { 23541feb8efSNishanth Menon [0] = PWRSTS_ON, /* vpe_bank */ 23697dd16b1SAmbresh K }, 23797dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 23897dd16b1SAmbresh K }; 23997dd16b1SAmbresh K 24097dd16b1SAmbresh K /* mpu_7xx_pwrdm: Modena processor and the Neon coprocessor power domain */ 24197dd16b1SAmbresh K static struct powerdomain mpu_7xx_pwrdm = { 24297dd16b1SAmbresh K .name = "mpu_pwrdm", 24397dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_MPU_INST, 24497dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 24597dd16b1SAmbresh K .pwrsts = PWRSTS_RET_ON, 246cafc8cb5SNishanth Menon .pwrsts_logic_ret = PWRSTS_RET, 24797dd16b1SAmbresh K .banks = 2, 24897dd16b1SAmbresh K .pwrsts_mem_ret = { 24997dd16b1SAmbresh K [0] = PWRSTS_OFF_RET, /* mpu_l2 */ 25097dd16b1SAmbresh K [1] = PWRSTS_RET, /* mpu_ram */ 25197dd16b1SAmbresh K }, 25297dd16b1SAmbresh K .pwrsts_mem_on = { 25341feb8efSNishanth Menon [0] = PWRSTS_ON, /* mpu_l2 */ 25441feb8efSNishanth Menon [1] = PWRSTS_ON, /* mpu_ram */ 25597dd16b1SAmbresh K }, 25697dd16b1SAmbresh K }; 25797dd16b1SAmbresh K 25897dd16b1SAmbresh K /* l3init_7xx_pwrdm: L3 initators pheripherals power domain */ 25997dd16b1SAmbresh K static struct powerdomain l3init_7xx_pwrdm = { 26097dd16b1SAmbresh K .name = "l3init_pwrdm", 26197dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_L3INIT_INST, 26297dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 263d16c0d72SNishanth Menon .pwrsts = PWRSTS_ON, 264dac4fba2SNishanth Menon .pwrsts_logic_ret = PWRSTS_RET, 26597dd16b1SAmbresh K .banks = 3, 26697dd16b1SAmbresh K .pwrsts_mem_ret = { 26797dd16b1SAmbresh K [0] = PWRSTS_OFF_RET, /* gmac_bank */ 26897dd16b1SAmbresh K [1] = PWRSTS_OFF_RET, /* l3init_bank1 */ 26997dd16b1SAmbresh K [2] = PWRSTS_OFF_RET, /* l3init_bank2 */ 27097dd16b1SAmbresh K }, 27197dd16b1SAmbresh K .pwrsts_mem_on = { 27241feb8efSNishanth Menon [0] = PWRSTS_ON, /* gmac_bank */ 27341feb8efSNishanth Menon [1] = PWRSTS_ON, /* l3init_bank1 */ 27441feb8efSNishanth Menon [2] = PWRSTS_ON, /* l3init_bank2 */ 27597dd16b1SAmbresh K }, 27697dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 27797dd16b1SAmbresh K }; 27897dd16b1SAmbresh K 27997dd16b1SAmbresh K /* eve3_7xx_pwrdm: */ 28097dd16b1SAmbresh K static struct powerdomain eve3_7xx_pwrdm = { 28197dd16b1SAmbresh K .name = "eve3_pwrdm", 28297dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_EVE3_INST, 28397dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 28497dd16b1SAmbresh K .pwrsts = PWRSTS_OFF_ON, 28597dd16b1SAmbresh K .banks = 1, 28697dd16b1SAmbresh K .pwrsts_mem_ret = { 28797dd16b1SAmbresh K [0] = PWRSTS_OFF_RET, /* eve3_bank */ 28897dd16b1SAmbresh K }, 28997dd16b1SAmbresh K .pwrsts_mem_on = { 29041feb8efSNishanth Menon [0] = PWRSTS_ON, /* eve3_bank */ 29197dd16b1SAmbresh K }, 29297dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 29397dd16b1SAmbresh K }; 29497dd16b1SAmbresh K 29597dd16b1SAmbresh K /* emu_7xx_pwrdm: Emulation power domain */ 29697dd16b1SAmbresh K static struct powerdomain emu_7xx_pwrdm = { 29797dd16b1SAmbresh K .name = "emu_pwrdm", 29897dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_EMU_INST, 29997dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 30097dd16b1SAmbresh K .pwrsts = PWRSTS_OFF_ON, 30197dd16b1SAmbresh K .banks = 1, 30297dd16b1SAmbresh K .pwrsts_mem_ret = { 30397dd16b1SAmbresh K [0] = PWRSTS_OFF_RET, /* emu_bank */ 30497dd16b1SAmbresh K }, 30597dd16b1SAmbresh K .pwrsts_mem_on = { 30641feb8efSNishanth Menon [0] = PWRSTS_ON, /* emu_bank */ 30797dd16b1SAmbresh K }, 30897dd16b1SAmbresh K }; 30997dd16b1SAmbresh K 31097dd16b1SAmbresh K /* dsp2_7xx_pwrdm: */ 31197dd16b1SAmbresh K static struct powerdomain dsp2_7xx_pwrdm = { 31297dd16b1SAmbresh K .name = "dsp2_pwrdm", 31397dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_DSP2_INST, 31497dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 31597dd16b1SAmbresh K .pwrsts = PWRSTS_OFF_ON, 31697dd16b1SAmbresh K .banks = 3, 31797dd16b1SAmbresh K .pwrsts_mem_ret = { 31897dd16b1SAmbresh K [0] = PWRSTS_OFF_RET, /* dsp2_edma */ 31997dd16b1SAmbresh K [1] = PWRSTS_OFF_RET, /* dsp2_l1 */ 32097dd16b1SAmbresh K [2] = PWRSTS_OFF_RET, /* dsp2_l2 */ 32197dd16b1SAmbresh K }, 32297dd16b1SAmbresh K .pwrsts_mem_on = { 32341feb8efSNishanth Menon [0] = PWRSTS_ON, /* dsp2_edma */ 32441feb8efSNishanth Menon [1] = PWRSTS_ON, /* dsp2_l1 */ 32541feb8efSNishanth Menon [2] = PWRSTS_ON, /* dsp2_l2 */ 32697dd16b1SAmbresh K }, 32797dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 32897dd16b1SAmbresh K }; 32997dd16b1SAmbresh K 33097dd16b1SAmbresh K /* dsp1_7xx_pwrdm: Tesla processor power domain */ 33197dd16b1SAmbresh K static struct powerdomain dsp1_7xx_pwrdm = { 33297dd16b1SAmbresh K .name = "dsp1_pwrdm", 33397dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_DSP1_INST, 33497dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 33597dd16b1SAmbresh K .pwrsts = PWRSTS_OFF_ON, 33697dd16b1SAmbresh K .banks = 3, 33797dd16b1SAmbresh K .pwrsts_mem_ret = { 33897dd16b1SAmbresh K [0] = PWRSTS_OFF_RET, /* dsp1_edma */ 33997dd16b1SAmbresh K [1] = PWRSTS_OFF_RET, /* dsp1_l1 */ 34097dd16b1SAmbresh K [2] = PWRSTS_OFF_RET, /* dsp1_l2 */ 34197dd16b1SAmbresh K }, 34297dd16b1SAmbresh K .pwrsts_mem_on = { 34341feb8efSNishanth Menon [0] = PWRSTS_ON, /* dsp1_edma */ 34441feb8efSNishanth Menon [1] = PWRSTS_ON, /* dsp1_l1 */ 34541feb8efSNishanth Menon [2] = PWRSTS_ON, /* dsp1_l2 */ 34697dd16b1SAmbresh K }, 34797dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 34897dd16b1SAmbresh K }; 34997dd16b1SAmbresh K 35097dd16b1SAmbresh K /* cam_7xx_pwrdm: Camera subsystem power domain */ 35197dd16b1SAmbresh K static struct powerdomain cam_7xx_pwrdm = { 35297dd16b1SAmbresh K .name = "cam_pwrdm", 35397dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_CAM_INST, 35497dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 35597dd16b1SAmbresh K .pwrsts = PWRSTS_OFF_ON, 35697dd16b1SAmbresh K .banks = 1, 35797dd16b1SAmbresh K .pwrsts_mem_ret = { 35897dd16b1SAmbresh K [0] = PWRSTS_OFF_RET, /* vip_bank */ 35997dd16b1SAmbresh K }, 36097dd16b1SAmbresh K .pwrsts_mem_on = { 36141feb8efSNishanth Menon [0] = PWRSTS_ON, /* vip_bank */ 36297dd16b1SAmbresh K }, 36397dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 36497dd16b1SAmbresh K }; 36597dd16b1SAmbresh K 36697dd16b1SAmbresh K /* eve4_7xx_pwrdm: */ 36797dd16b1SAmbresh K static struct powerdomain eve4_7xx_pwrdm = { 36897dd16b1SAmbresh K .name = "eve4_pwrdm", 36997dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_EVE4_INST, 37097dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 37197dd16b1SAmbresh K .pwrsts = PWRSTS_OFF_ON, 37297dd16b1SAmbresh K .banks = 1, 37397dd16b1SAmbresh K .pwrsts_mem_ret = { 37497dd16b1SAmbresh K [0] = PWRSTS_OFF_RET, /* eve4_bank */ 37597dd16b1SAmbresh K }, 37697dd16b1SAmbresh K .pwrsts_mem_on = { 37741feb8efSNishanth Menon [0] = PWRSTS_ON, /* eve4_bank */ 37897dd16b1SAmbresh K }, 37997dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 38097dd16b1SAmbresh K }; 38197dd16b1SAmbresh K 38297dd16b1SAmbresh K /* eve2_7xx_pwrdm: */ 38397dd16b1SAmbresh K static struct powerdomain eve2_7xx_pwrdm = { 38497dd16b1SAmbresh K .name = "eve2_pwrdm", 38597dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_EVE2_INST, 38697dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 38797dd16b1SAmbresh K .pwrsts = PWRSTS_OFF_ON, 38897dd16b1SAmbresh K .banks = 1, 38997dd16b1SAmbresh K .pwrsts_mem_ret = { 39097dd16b1SAmbresh K [0] = PWRSTS_OFF_RET, /* eve2_bank */ 39197dd16b1SAmbresh K }, 39297dd16b1SAmbresh K .pwrsts_mem_on = { 39341feb8efSNishanth Menon [0] = PWRSTS_ON, /* eve2_bank */ 39497dd16b1SAmbresh K }, 39597dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 39697dd16b1SAmbresh K }; 39797dd16b1SAmbresh K 39897dd16b1SAmbresh K /* eve1_7xx_pwrdm: */ 39997dd16b1SAmbresh K static struct powerdomain eve1_7xx_pwrdm = { 40097dd16b1SAmbresh K .name = "eve1_pwrdm", 40197dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_EVE1_INST, 40297dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 40397dd16b1SAmbresh K .pwrsts = PWRSTS_OFF_ON, 40497dd16b1SAmbresh K .banks = 1, 40597dd16b1SAmbresh K .pwrsts_mem_ret = { 40697dd16b1SAmbresh K [0] = PWRSTS_OFF_RET, /* eve1_bank */ 40797dd16b1SAmbresh K }, 40897dd16b1SAmbresh K .pwrsts_mem_on = { 40941feb8efSNishanth Menon [0] = PWRSTS_ON, /* eve1_bank */ 41097dd16b1SAmbresh K }, 41197dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 41297dd16b1SAmbresh K }; 41397dd16b1SAmbresh K 41497dd16b1SAmbresh K /* 41597dd16b1SAmbresh K * The following power domains are not under SW control 41697dd16b1SAmbresh K * 41797dd16b1SAmbresh K * mpuaon 41897dd16b1SAmbresh K * mmaon 41997dd16b1SAmbresh K */ 42097dd16b1SAmbresh K 42197dd16b1SAmbresh K /* As powerdomains are added or removed above, this list must also be changed */ 42297dd16b1SAmbresh K static struct powerdomain *powerdomains_dra7xx[] __initdata = { 42397dd16b1SAmbresh K &iva_7xx_pwrdm, 42497dd16b1SAmbresh K &rtc_7xx_pwrdm, 42597dd16b1SAmbresh K &custefuse_7xx_pwrdm, 42697dd16b1SAmbresh K &ipu_7xx_pwrdm, 42797dd16b1SAmbresh K &dss_7xx_pwrdm, 42897dd16b1SAmbresh K &l4per_7xx_pwrdm, 42997dd16b1SAmbresh K &gpu_7xx_pwrdm, 43097dd16b1SAmbresh K &wkupaon_7xx_pwrdm, 43197dd16b1SAmbresh K &core_7xx_pwrdm, 43297dd16b1SAmbresh K &coreaon_7xx_pwrdm, 43397dd16b1SAmbresh K &cpu0_7xx_pwrdm, 43497dd16b1SAmbresh K &cpu1_7xx_pwrdm, 43597dd16b1SAmbresh K &vpe_7xx_pwrdm, 43697dd16b1SAmbresh K &mpu_7xx_pwrdm, 43797dd16b1SAmbresh K &l3init_7xx_pwrdm, 43897dd16b1SAmbresh K &eve3_7xx_pwrdm, 43997dd16b1SAmbresh K &emu_7xx_pwrdm, 44097dd16b1SAmbresh K &dsp2_7xx_pwrdm, 44197dd16b1SAmbresh K &dsp1_7xx_pwrdm, 44297dd16b1SAmbresh K &cam_7xx_pwrdm, 44397dd16b1SAmbresh K &eve4_7xx_pwrdm, 44497dd16b1SAmbresh K &eve2_7xx_pwrdm, 44597dd16b1SAmbresh K &eve1_7xx_pwrdm, 44697dd16b1SAmbresh K NULL 44797dd16b1SAmbresh K }; 44897dd16b1SAmbresh K 44997dd16b1SAmbresh K void __init dra7xx_powerdomains_init(void) 45097dd16b1SAmbresh K { 45197dd16b1SAmbresh K pwrdm_register_platform_funcs(&omap4_pwrdm_operations); 45297dd16b1SAmbresh K pwrdm_register_pwrdms(powerdomains_dra7xx); 45397dd16b1SAmbresh K pwrdm_complete_init(); 45497dd16b1SAmbresh K } 455