197dd16b1SAmbresh K /* 297dd16b1SAmbresh K * DRA7xx Power domains framework 397dd16b1SAmbresh K * 497dd16b1SAmbresh K * Copyright (C) 2009-2013 Texas Instruments, Inc. 597dd16b1SAmbresh K * Copyright (C) 2009-2011 Nokia Corporation 697dd16b1SAmbresh K * 797dd16b1SAmbresh K * Generated by code originally written by: 897dd16b1SAmbresh K * Abhijit Pagare (abhijitpagare@ti.com) 997dd16b1SAmbresh K * Benoit Cousson (b-cousson@ti.com) 1097dd16b1SAmbresh K * Paul Walmsley (paul@pwsan.com) 1197dd16b1SAmbresh K * 1297dd16b1SAmbresh K * This file is automatically generated from the OMAP hardware databases. 1397dd16b1SAmbresh K * We respectfully ask that any modifications to this file be coordinated 1497dd16b1SAmbresh K * with the public linux-omap@vger.kernel.org mailing list and the 1597dd16b1SAmbresh K * authors above to ensure that the autogeneration scripts are kept 1697dd16b1SAmbresh K * up-to-date with the file contents. 1797dd16b1SAmbresh K * 1897dd16b1SAmbresh K * This program is free software; you can redistribute it and/or modify 1997dd16b1SAmbresh K * it under the terms of the GNU General Public License version 2 as 2097dd16b1SAmbresh K * published by the Free Software Foundation. 2197dd16b1SAmbresh K */ 2297dd16b1SAmbresh K 2397dd16b1SAmbresh K #include <linux/kernel.h> 2497dd16b1SAmbresh K #include <linux/init.h> 2597dd16b1SAmbresh K 2697dd16b1SAmbresh K #include "powerdomain.h" 2797dd16b1SAmbresh K 2897dd16b1SAmbresh K #include "prcm-common.h" 2997dd16b1SAmbresh K #include "prcm44xx.h" 3097dd16b1SAmbresh K #include "prm7xx.h" 3197dd16b1SAmbresh K #include "prcm_mpu7xx.h" 323af6ccc3SLokesh Vutla #include "soc.h" 3397dd16b1SAmbresh K 3497dd16b1SAmbresh K /* iva_7xx_pwrdm: IVA-HD power domain */ 3597dd16b1SAmbresh K static struct powerdomain iva_7xx_pwrdm = { 3697dd16b1SAmbresh K .name = "iva_pwrdm", 3797dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_IVA_INST, 3897dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 39dac4fba2SNishanth Menon .pwrsts = PWRSTS_OFF_ON, 4097dd16b1SAmbresh K .banks = 4, 4197dd16b1SAmbresh K .pwrsts_mem_on = { 4241feb8efSNishanth Menon [0] = PWRSTS_ON, /* hwa_mem */ 4341feb8efSNishanth Menon [1] = PWRSTS_ON, /* sl2_mem */ 4441feb8efSNishanth Menon [2] = PWRSTS_ON, /* tcm1_mem */ 4541feb8efSNishanth Menon [3] = PWRSTS_ON, /* tcm2_mem */ 4697dd16b1SAmbresh K }, 4797dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 4897dd16b1SAmbresh K }; 4997dd16b1SAmbresh K 5097dd16b1SAmbresh K /* rtc_7xx_pwrdm: */ 5197dd16b1SAmbresh K static struct powerdomain rtc_7xx_pwrdm = { 5297dd16b1SAmbresh K .name = "rtc_pwrdm", 5397dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_RTC_INST, 5497dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 5597dd16b1SAmbresh K .pwrsts = PWRSTS_ON, 5697dd16b1SAmbresh K }; 5797dd16b1SAmbresh K 5897dd16b1SAmbresh K /* custefuse_7xx_pwrdm: Customer efuse controller power domain */ 5997dd16b1SAmbresh K static struct powerdomain custefuse_7xx_pwrdm = { 6097dd16b1SAmbresh K .name = "custefuse_pwrdm", 6197dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST, 6297dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 6397dd16b1SAmbresh K .pwrsts = PWRSTS_OFF_ON, 6497dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 6597dd16b1SAmbresh K }; 6697dd16b1SAmbresh K 673af6ccc3SLokesh Vutla /* custefuse_aon_7xx_pwrdm: Customer efuse controller power domain */ 683af6ccc3SLokesh Vutla static struct powerdomain custefuse_aon_7xx_pwrdm = { 693af6ccc3SLokesh Vutla .name = "custefuse_pwrdm", 703af6ccc3SLokesh Vutla .prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST, 713af6ccc3SLokesh Vutla .prcm_partition = DRA7XX_PRM_PARTITION, 723af6ccc3SLokesh Vutla .pwrsts = PWRSTS_ON, 733af6ccc3SLokesh Vutla }; 743af6ccc3SLokesh Vutla 7597dd16b1SAmbresh K /* ipu_7xx_pwrdm: Audio back end power domain */ 7697dd16b1SAmbresh K static struct powerdomain ipu_7xx_pwrdm = { 7797dd16b1SAmbresh K .name = "ipu_pwrdm", 7897dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_IPU_INST, 7997dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 80dac4fba2SNishanth Menon .pwrsts = PWRSTS_OFF_ON, 8197dd16b1SAmbresh K .banks = 2, 8297dd16b1SAmbresh K .pwrsts_mem_on = { 8341feb8efSNishanth Menon [0] = PWRSTS_ON, /* aessmem */ 8441feb8efSNishanth Menon [1] = PWRSTS_ON, /* periphmem */ 8597dd16b1SAmbresh K }, 8697dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 8797dd16b1SAmbresh K }; 8897dd16b1SAmbresh K 8997dd16b1SAmbresh K /* dss_7xx_pwrdm: Display subsystem power domain */ 9097dd16b1SAmbresh K static struct powerdomain dss_7xx_pwrdm = { 9197dd16b1SAmbresh K .name = "dss_pwrdm", 9297dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_DSS_INST, 9397dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 94dac4fba2SNishanth Menon .pwrsts = PWRSTS_OFF_ON, 9597dd16b1SAmbresh K .banks = 1, 9697dd16b1SAmbresh K .pwrsts_mem_on = { 9741feb8efSNishanth Menon [0] = PWRSTS_ON, /* dss_mem */ 9897dd16b1SAmbresh K }, 9997dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 10097dd16b1SAmbresh K }; 10197dd16b1SAmbresh K 10297dd16b1SAmbresh K /* l4per_7xx_pwrdm: Target peripherals power domain */ 10397dd16b1SAmbresh K static struct powerdomain l4per_7xx_pwrdm = { 10497dd16b1SAmbresh K .name = "l4per_pwrdm", 10597dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_L4PER_INST, 10697dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 107d16c0d72SNishanth Menon .pwrsts = PWRSTS_ON, 10897dd16b1SAmbresh K .banks = 2, 10997dd16b1SAmbresh K .pwrsts_mem_on = { 11041feb8efSNishanth Menon [0] = PWRSTS_ON, /* nonretained_bank */ 11141feb8efSNishanth Menon [1] = PWRSTS_ON, /* retained_bank */ 11297dd16b1SAmbresh K }, 11397dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 11497dd16b1SAmbresh K }; 11597dd16b1SAmbresh K 11697dd16b1SAmbresh K /* gpu_7xx_pwrdm: 3D accelerator power domain */ 11797dd16b1SAmbresh K static struct powerdomain gpu_7xx_pwrdm = { 11897dd16b1SAmbresh K .name = "gpu_pwrdm", 11997dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_GPU_INST, 12097dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 12197dd16b1SAmbresh K .pwrsts = PWRSTS_OFF_ON, 12297dd16b1SAmbresh K .banks = 1, 12397dd16b1SAmbresh K .pwrsts_mem_on = { 12441feb8efSNishanth Menon [0] = PWRSTS_ON, /* gpu_mem */ 12597dd16b1SAmbresh K }, 12697dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 12797dd16b1SAmbresh K }; 12897dd16b1SAmbresh K 12997dd16b1SAmbresh K /* wkupaon_7xx_pwrdm: Wake-up power domain */ 13097dd16b1SAmbresh K static struct powerdomain wkupaon_7xx_pwrdm = { 13197dd16b1SAmbresh K .name = "wkupaon_pwrdm", 13297dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_WKUPAON_INST, 13397dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 13497dd16b1SAmbresh K .pwrsts = PWRSTS_ON, 13597dd16b1SAmbresh K .banks = 1, 13697dd16b1SAmbresh K .pwrsts_mem_on = { 13797dd16b1SAmbresh K [0] = PWRSTS_ON, /* wkup_bank */ 13897dd16b1SAmbresh K }, 13997dd16b1SAmbresh K }; 14097dd16b1SAmbresh K 14197dd16b1SAmbresh K /* core_7xx_pwrdm: CORE power domain */ 14297dd16b1SAmbresh K static struct powerdomain core_7xx_pwrdm = { 14397dd16b1SAmbresh K .name = "core_pwrdm", 14497dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_CORE_INST, 14597dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 146f971512cSNishanth Menon .pwrsts = PWRSTS_ON, 14797dd16b1SAmbresh K .banks = 5, 14897dd16b1SAmbresh K .pwrsts_mem_on = { 14941feb8efSNishanth Menon [0] = PWRSTS_ON, /* core_nret_bank */ 15041feb8efSNishanth Menon [1] = PWRSTS_ON, /* core_ocmram */ 15141feb8efSNishanth Menon [2] = PWRSTS_ON, /* core_other_bank */ 15241feb8efSNishanth Menon [3] = PWRSTS_ON, /* ipu_l2ram */ 15341feb8efSNishanth Menon [4] = PWRSTS_ON, /* ipu_unicache */ 15497dd16b1SAmbresh K }, 15597dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 15697dd16b1SAmbresh K }; 15797dd16b1SAmbresh K 15897dd16b1SAmbresh K /* coreaon_7xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */ 15997dd16b1SAmbresh K static struct powerdomain coreaon_7xx_pwrdm = { 16097dd16b1SAmbresh K .name = "coreaon_pwrdm", 16197dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_COREAON_INST, 16297dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 16397dd16b1SAmbresh K .pwrsts = PWRSTS_ON, 16497dd16b1SAmbresh K }; 16597dd16b1SAmbresh K 16697dd16b1SAmbresh K /* cpu0_7xx_pwrdm: MPU0 processor and Neon coprocessor power domain */ 16797dd16b1SAmbresh K static struct powerdomain cpu0_7xx_pwrdm = { 16897dd16b1SAmbresh K .name = "cpu0_pwrdm", 16997dd16b1SAmbresh K .prcm_offs = DRA7XX_MPU_PRCM_PRM_C0_INST, 17097dd16b1SAmbresh K .prcm_partition = DRA7XX_MPU_PRCM_PARTITION, 171cafc8cb5SNishanth Menon .pwrsts = PWRSTS_RET_ON, 172cafc8cb5SNishanth Menon .pwrsts_logic_ret = PWRSTS_RET, 17397dd16b1SAmbresh K .banks = 1, 17497dd16b1SAmbresh K .pwrsts_mem_ret = { 17597dd16b1SAmbresh K [0] = PWRSTS_OFF_RET, /* cpu0_l1 */ 17697dd16b1SAmbresh K }, 17797dd16b1SAmbresh K .pwrsts_mem_on = { 17897dd16b1SAmbresh K [0] = PWRSTS_ON, /* cpu0_l1 */ 17997dd16b1SAmbresh K }, 18097dd16b1SAmbresh K }; 18197dd16b1SAmbresh K 18297dd16b1SAmbresh K /* cpu1_7xx_pwrdm: MPU1 processor and Neon coprocessor power domain */ 18397dd16b1SAmbresh K static struct powerdomain cpu1_7xx_pwrdm = { 18497dd16b1SAmbresh K .name = "cpu1_pwrdm", 18597dd16b1SAmbresh K .prcm_offs = DRA7XX_MPU_PRCM_PRM_C1_INST, 18697dd16b1SAmbresh K .prcm_partition = DRA7XX_MPU_PRCM_PARTITION, 187cafc8cb5SNishanth Menon .pwrsts = PWRSTS_RET_ON, 188cafc8cb5SNishanth Menon .pwrsts_logic_ret = PWRSTS_RET, 18997dd16b1SAmbresh K .banks = 1, 19097dd16b1SAmbresh K .pwrsts_mem_ret = { 19197dd16b1SAmbresh K [0] = PWRSTS_OFF_RET, /* cpu1_l1 */ 19297dd16b1SAmbresh K }, 19397dd16b1SAmbresh K .pwrsts_mem_on = { 19497dd16b1SAmbresh K [0] = PWRSTS_ON, /* cpu1_l1 */ 19597dd16b1SAmbresh K }, 19697dd16b1SAmbresh K }; 19797dd16b1SAmbresh K 19897dd16b1SAmbresh K /* vpe_7xx_pwrdm: */ 19997dd16b1SAmbresh K static struct powerdomain vpe_7xx_pwrdm = { 20097dd16b1SAmbresh K .name = "vpe_pwrdm", 20197dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_VPE_INST, 20297dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 203dac4fba2SNishanth Menon .pwrsts = PWRSTS_OFF_ON, 20497dd16b1SAmbresh K .banks = 1, 20597dd16b1SAmbresh K .pwrsts_mem_on = { 20641feb8efSNishanth Menon [0] = PWRSTS_ON, /* vpe_bank */ 20797dd16b1SAmbresh K }, 20897dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 20997dd16b1SAmbresh K }; 21097dd16b1SAmbresh K 21197dd16b1SAmbresh K /* mpu_7xx_pwrdm: Modena processor and the Neon coprocessor power domain */ 21297dd16b1SAmbresh K static struct powerdomain mpu_7xx_pwrdm = { 21397dd16b1SAmbresh K .name = "mpu_pwrdm", 21497dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_MPU_INST, 21597dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 21697dd16b1SAmbresh K .pwrsts = PWRSTS_RET_ON, 217cafc8cb5SNishanth Menon .pwrsts_logic_ret = PWRSTS_RET, 21897dd16b1SAmbresh K .banks = 2, 21997dd16b1SAmbresh K .pwrsts_mem_ret = { 22097dd16b1SAmbresh K [0] = PWRSTS_OFF_RET, /* mpu_l2 */ 22197dd16b1SAmbresh K [1] = PWRSTS_RET, /* mpu_ram */ 22297dd16b1SAmbresh K }, 22397dd16b1SAmbresh K .pwrsts_mem_on = { 22441feb8efSNishanth Menon [0] = PWRSTS_ON, /* mpu_l2 */ 22541feb8efSNishanth Menon [1] = PWRSTS_ON, /* mpu_ram */ 22697dd16b1SAmbresh K }, 22797dd16b1SAmbresh K }; 22897dd16b1SAmbresh K 22997dd16b1SAmbresh K /* l3init_7xx_pwrdm: L3 initators pheripherals power domain */ 23097dd16b1SAmbresh K static struct powerdomain l3init_7xx_pwrdm = { 23197dd16b1SAmbresh K .name = "l3init_pwrdm", 23297dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_L3INIT_INST, 23397dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 234d16c0d72SNishanth Menon .pwrsts = PWRSTS_ON, 23597dd16b1SAmbresh K .banks = 3, 23697dd16b1SAmbresh K .pwrsts_mem_on = { 23741feb8efSNishanth Menon [0] = PWRSTS_ON, /* gmac_bank */ 23841feb8efSNishanth Menon [1] = PWRSTS_ON, /* l3init_bank1 */ 23941feb8efSNishanth Menon [2] = PWRSTS_ON, /* l3init_bank2 */ 24097dd16b1SAmbresh K }, 24197dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 24297dd16b1SAmbresh K }; 24397dd16b1SAmbresh K 24497dd16b1SAmbresh K /* eve3_7xx_pwrdm: */ 24597dd16b1SAmbresh K static struct powerdomain eve3_7xx_pwrdm = { 24697dd16b1SAmbresh K .name = "eve3_pwrdm", 24797dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_EVE3_INST, 24897dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 24997dd16b1SAmbresh K .pwrsts = PWRSTS_OFF_ON, 25097dd16b1SAmbresh K .banks = 1, 25197dd16b1SAmbresh K .pwrsts_mem_on = { 25241feb8efSNishanth Menon [0] = PWRSTS_ON, /* eve3_bank */ 25397dd16b1SAmbresh K }, 25497dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 25597dd16b1SAmbresh K }; 25697dd16b1SAmbresh K 25797dd16b1SAmbresh K /* emu_7xx_pwrdm: Emulation power domain */ 25897dd16b1SAmbresh K static struct powerdomain emu_7xx_pwrdm = { 25997dd16b1SAmbresh K .name = "emu_pwrdm", 26097dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_EMU_INST, 26197dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 26297dd16b1SAmbresh K .pwrsts = PWRSTS_OFF_ON, 26397dd16b1SAmbresh K .banks = 1, 26497dd16b1SAmbresh K .pwrsts_mem_on = { 26541feb8efSNishanth Menon [0] = PWRSTS_ON, /* emu_bank */ 26697dd16b1SAmbresh K }, 26797dd16b1SAmbresh K }; 26897dd16b1SAmbresh K 26997dd16b1SAmbresh K /* dsp2_7xx_pwrdm: */ 27097dd16b1SAmbresh K static struct powerdomain dsp2_7xx_pwrdm = { 27197dd16b1SAmbresh K .name = "dsp2_pwrdm", 27297dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_DSP2_INST, 27397dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 27497dd16b1SAmbresh K .pwrsts = PWRSTS_OFF_ON, 27597dd16b1SAmbresh K .banks = 3, 27697dd16b1SAmbresh K .pwrsts_mem_on = { 27741feb8efSNishanth Menon [0] = PWRSTS_ON, /* dsp2_edma */ 27841feb8efSNishanth Menon [1] = PWRSTS_ON, /* dsp2_l1 */ 27941feb8efSNishanth Menon [2] = PWRSTS_ON, /* dsp2_l2 */ 28097dd16b1SAmbresh K }, 28197dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 28297dd16b1SAmbresh K }; 28397dd16b1SAmbresh K 28497dd16b1SAmbresh K /* dsp1_7xx_pwrdm: Tesla processor power domain */ 28597dd16b1SAmbresh K static struct powerdomain dsp1_7xx_pwrdm = { 28697dd16b1SAmbresh K .name = "dsp1_pwrdm", 28797dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_DSP1_INST, 28897dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 28997dd16b1SAmbresh K .pwrsts = PWRSTS_OFF_ON, 29097dd16b1SAmbresh K .banks = 3, 29197dd16b1SAmbresh K .pwrsts_mem_on = { 29241feb8efSNishanth Menon [0] = PWRSTS_ON, /* dsp1_edma */ 29341feb8efSNishanth Menon [1] = PWRSTS_ON, /* dsp1_l1 */ 29441feb8efSNishanth Menon [2] = PWRSTS_ON, /* dsp1_l2 */ 29597dd16b1SAmbresh K }, 29697dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 29797dd16b1SAmbresh K }; 29897dd16b1SAmbresh K 29997dd16b1SAmbresh K /* cam_7xx_pwrdm: Camera subsystem power domain */ 30097dd16b1SAmbresh K static struct powerdomain cam_7xx_pwrdm = { 30197dd16b1SAmbresh K .name = "cam_pwrdm", 30297dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_CAM_INST, 30397dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 30497dd16b1SAmbresh K .pwrsts = PWRSTS_OFF_ON, 30597dd16b1SAmbresh K .banks = 1, 30697dd16b1SAmbresh K .pwrsts_mem_on = { 30741feb8efSNishanth Menon [0] = PWRSTS_ON, /* vip_bank */ 30897dd16b1SAmbresh K }, 30997dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 31097dd16b1SAmbresh K }; 31197dd16b1SAmbresh K 31297dd16b1SAmbresh K /* eve4_7xx_pwrdm: */ 31397dd16b1SAmbresh K static struct powerdomain eve4_7xx_pwrdm = { 31497dd16b1SAmbresh K .name = "eve4_pwrdm", 31597dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_EVE4_INST, 31697dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 31797dd16b1SAmbresh K .pwrsts = PWRSTS_OFF_ON, 31897dd16b1SAmbresh K .banks = 1, 31997dd16b1SAmbresh K .pwrsts_mem_on = { 32041feb8efSNishanth Menon [0] = PWRSTS_ON, /* eve4_bank */ 32197dd16b1SAmbresh K }, 32297dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 32397dd16b1SAmbresh K }; 32497dd16b1SAmbresh K 32597dd16b1SAmbresh K /* eve2_7xx_pwrdm: */ 32697dd16b1SAmbresh K static struct powerdomain eve2_7xx_pwrdm = { 32797dd16b1SAmbresh K .name = "eve2_pwrdm", 32897dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_EVE2_INST, 32997dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 33097dd16b1SAmbresh K .pwrsts = PWRSTS_OFF_ON, 33197dd16b1SAmbresh K .banks = 1, 33297dd16b1SAmbresh K .pwrsts_mem_on = { 33341feb8efSNishanth Menon [0] = PWRSTS_ON, /* eve2_bank */ 33497dd16b1SAmbresh K }, 33597dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 33697dd16b1SAmbresh K }; 33797dd16b1SAmbresh K 33897dd16b1SAmbresh K /* eve1_7xx_pwrdm: */ 33997dd16b1SAmbresh K static struct powerdomain eve1_7xx_pwrdm = { 34097dd16b1SAmbresh K .name = "eve1_pwrdm", 34197dd16b1SAmbresh K .prcm_offs = DRA7XX_PRM_EVE1_INST, 34297dd16b1SAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION, 34397dd16b1SAmbresh K .pwrsts = PWRSTS_OFF_ON, 34497dd16b1SAmbresh K .banks = 1, 34597dd16b1SAmbresh K .pwrsts_mem_on = { 34641feb8efSNishanth Menon [0] = PWRSTS_ON, /* eve1_bank */ 34797dd16b1SAmbresh K }, 34897dd16b1SAmbresh K .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 34997dd16b1SAmbresh K }; 35097dd16b1SAmbresh K 35197dd16b1SAmbresh K /* 35297dd16b1SAmbresh K * The following power domains are not under SW control 35397dd16b1SAmbresh K * 35497dd16b1SAmbresh K * mpuaon 35597dd16b1SAmbresh K * mmaon 35697dd16b1SAmbresh K */ 35797dd16b1SAmbresh K 35897dd16b1SAmbresh K /* As powerdomains are added or removed above, this list must also be changed */ 35997dd16b1SAmbresh K static struct powerdomain *powerdomains_dra7xx[] __initdata = { 36097dd16b1SAmbresh K &iva_7xx_pwrdm, 36197dd16b1SAmbresh K &rtc_7xx_pwrdm, 36297dd16b1SAmbresh K &ipu_7xx_pwrdm, 36397dd16b1SAmbresh K &dss_7xx_pwrdm, 36497dd16b1SAmbresh K &l4per_7xx_pwrdm, 36597dd16b1SAmbresh K &gpu_7xx_pwrdm, 36697dd16b1SAmbresh K &wkupaon_7xx_pwrdm, 36797dd16b1SAmbresh K &core_7xx_pwrdm, 36897dd16b1SAmbresh K &coreaon_7xx_pwrdm, 36997dd16b1SAmbresh K &cpu0_7xx_pwrdm, 37097dd16b1SAmbresh K &cpu1_7xx_pwrdm, 37197dd16b1SAmbresh K &vpe_7xx_pwrdm, 37297dd16b1SAmbresh K &mpu_7xx_pwrdm, 37397dd16b1SAmbresh K &l3init_7xx_pwrdm, 37497dd16b1SAmbresh K &eve3_7xx_pwrdm, 37597dd16b1SAmbresh K &emu_7xx_pwrdm, 37697dd16b1SAmbresh K &dsp2_7xx_pwrdm, 37797dd16b1SAmbresh K &dsp1_7xx_pwrdm, 37897dd16b1SAmbresh K &cam_7xx_pwrdm, 37997dd16b1SAmbresh K &eve4_7xx_pwrdm, 38097dd16b1SAmbresh K &eve2_7xx_pwrdm, 38197dd16b1SAmbresh K &eve1_7xx_pwrdm, 38297dd16b1SAmbresh K NULL 38397dd16b1SAmbresh K }; 38497dd16b1SAmbresh K 3853af6ccc3SLokesh Vutla static struct powerdomain *powerdomains_dra76x[] __initdata = { 3863af6ccc3SLokesh Vutla &custefuse_aon_7xx_pwrdm, 3873af6ccc3SLokesh Vutla NULL 3883af6ccc3SLokesh Vutla }; 3893af6ccc3SLokesh Vutla 3903af6ccc3SLokesh Vutla static struct powerdomain *powerdomains_dra74x[] __initdata = { 3913af6ccc3SLokesh Vutla &custefuse_7xx_pwrdm, 3923af6ccc3SLokesh Vutla NULL 3933af6ccc3SLokesh Vutla }; 3943af6ccc3SLokesh Vutla 3953af6ccc3SLokesh Vutla static struct powerdomain *powerdomains_dra72x[] __initdata = { 3963af6ccc3SLokesh Vutla &custefuse_aon_7xx_pwrdm, 3973af6ccc3SLokesh Vutla NULL 3983af6ccc3SLokesh Vutla }; 3993af6ccc3SLokesh Vutla 40097dd16b1SAmbresh K void __init dra7xx_powerdomains_init(void) 40197dd16b1SAmbresh K { 40297dd16b1SAmbresh K pwrdm_register_platform_funcs(&omap4_pwrdm_operations); 40397dd16b1SAmbresh K pwrdm_register_pwrdms(powerdomains_dra7xx); 4043af6ccc3SLokesh Vutla 4053af6ccc3SLokesh Vutla if (soc_is_dra76x()) 4063af6ccc3SLokesh Vutla pwrdm_register_pwrdms(powerdomains_dra76x); 4073af6ccc3SLokesh Vutla else if (soc_is_dra74x()) 4083af6ccc3SLokesh Vutla pwrdm_register_pwrdms(powerdomains_dra74x); 4093af6ccc3SLokesh Vutla else if (soc_is_dra72x()) 4103af6ccc3SLokesh Vutla pwrdm_register_pwrdms(powerdomains_dra72x); 4113af6ccc3SLokesh Vutla 41297dd16b1SAmbresh K pwrdm_complete_init(); 41397dd16b1SAmbresh K } 414