1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2411f968fSBenoit Cousson /*
3411f968fSBenoit Cousson * OMAP54XX Power domains framework
4411f968fSBenoit Cousson *
5411f968fSBenoit Cousson * Copyright (C) 2013 Texas Instruments, Inc.
6411f968fSBenoit Cousson *
7411f968fSBenoit Cousson * Abhijit Pagare (abhijitpagare@ti.com)
8411f968fSBenoit Cousson * Benoit Cousson (b-cousson@ti.com)
9411f968fSBenoit Cousson * Paul Walmsley (paul@pwsan.com)
10411f968fSBenoit Cousson *
11411f968fSBenoit Cousson * This file is automatically generated from the OMAP hardware databases.
12411f968fSBenoit Cousson * We respectfully ask that any modifications to this file be coordinated
13411f968fSBenoit Cousson * with the public linux-omap@vger.kernel.org mailing list and the
14411f968fSBenoit Cousson * authors above to ensure that the autogeneration scripts are kept
15411f968fSBenoit Cousson * up-to-date with the file contents.
16411f968fSBenoit Cousson */
17411f968fSBenoit Cousson
18411f968fSBenoit Cousson #include <linux/kernel.h>
19411f968fSBenoit Cousson #include <linux/init.h>
20411f968fSBenoit Cousson
21411f968fSBenoit Cousson #include "powerdomain.h"
22411f968fSBenoit Cousson
23411f968fSBenoit Cousson #include "prcm-common.h"
24411f968fSBenoit Cousson #include "prcm44xx.h"
25411f968fSBenoit Cousson #include "prm54xx.h"
26411f968fSBenoit Cousson #include "prcm_mpu54xx.h"
27411f968fSBenoit Cousson
28411f968fSBenoit Cousson /* core_54xx_pwrdm: CORE power domain */
29411f968fSBenoit Cousson static struct powerdomain core_54xx_pwrdm = {
30411f968fSBenoit Cousson .name = "core_pwrdm",
31411f968fSBenoit Cousson .voltdm = { .name = "core" },
32411f968fSBenoit Cousson .prcm_offs = OMAP54XX_PRM_CORE_INST,
33411f968fSBenoit Cousson .prcm_partition = OMAP54XX_PRM_PARTITION,
34411f968fSBenoit Cousson .pwrsts = PWRSTS_RET_ON,
359f5dc91bSNishanth Menon .pwrsts_logic_ret = PWRSTS_RET,
36411f968fSBenoit Cousson .banks = 5,
37411f968fSBenoit Cousson .pwrsts_mem_ret = {
38411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* core_nret_bank */
39411f968fSBenoit Cousson [1] = PWRSTS_OFF_RET, /* core_ocmram */
40411f968fSBenoit Cousson [2] = PWRSTS_OFF_RET, /* core_other_bank */
41411f968fSBenoit Cousson [3] = PWRSTS_OFF_RET, /* ipu_l2ram */
42411f968fSBenoit Cousson [4] = PWRSTS_OFF_RET, /* ipu_unicache */
43411f968fSBenoit Cousson },
44411f968fSBenoit Cousson .pwrsts_mem_on = {
45411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* core_nret_bank */
46411f968fSBenoit Cousson [1] = PWRSTS_OFF_RET, /* core_ocmram */
47411f968fSBenoit Cousson [2] = PWRSTS_OFF_RET, /* core_other_bank */
48411f968fSBenoit Cousson [3] = PWRSTS_OFF_RET, /* ipu_l2ram */
49411f968fSBenoit Cousson [4] = PWRSTS_OFF_RET, /* ipu_unicache */
50411f968fSBenoit Cousson },
51411f968fSBenoit Cousson .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
52411f968fSBenoit Cousson };
53411f968fSBenoit Cousson
54411f968fSBenoit Cousson /* abe_54xx_pwrdm: Audio back end power domain */
55411f968fSBenoit Cousson static struct powerdomain abe_54xx_pwrdm = {
56411f968fSBenoit Cousson .name = "abe_pwrdm",
57411f968fSBenoit Cousson .voltdm = { .name = "core" },
58411f968fSBenoit Cousson .prcm_offs = OMAP54XX_PRM_ABE_INST,
59411f968fSBenoit Cousson .prcm_partition = OMAP54XX_PRM_PARTITION,
60411f968fSBenoit Cousson .pwrsts = PWRSTS_OFF_RET_ON,
61411f968fSBenoit Cousson .pwrsts_logic_ret = PWRSTS_OFF,
62411f968fSBenoit Cousson .banks = 2,
63411f968fSBenoit Cousson .pwrsts_mem_ret = {
64411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* aessmem */
65411f968fSBenoit Cousson [1] = PWRSTS_OFF_RET, /* periphmem */
66411f968fSBenoit Cousson },
67411f968fSBenoit Cousson .pwrsts_mem_on = {
68411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* aessmem */
69411f968fSBenoit Cousson [1] = PWRSTS_OFF_RET, /* periphmem */
70411f968fSBenoit Cousson },
71411f968fSBenoit Cousson .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
72411f968fSBenoit Cousson };
73411f968fSBenoit Cousson
74411f968fSBenoit Cousson /* coreaon_54xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
75411f968fSBenoit Cousson static struct powerdomain coreaon_54xx_pwrdm = {
76411f968fSBenoit Cousson .name = "coreaon_pwrdm",
77411f968fSBenoit Cousson .voltdm = { .name = "core" },
78411f968fSBenoit Cousson .prcm_offs = OMAP54XX_PRM_COREAON_INST,
79411f968fSBenoit Cousson .prcm_partition = OMAP54XX_PRM_PARTITION,
80411f968fSBenoit Cousson .pwrsts = PWRSTS_ON,
81411f968fSBenoit Cousson };
82411f968fSBenoit Cousson
83411f968fSBenoit Cousson /* dss_54xx_pwrdm: Display subsystem power domain */
84411f968fSBenoit Cousson static struct powerdomain dss_54xx_pwrdm = {
85411f968fSBenoit Cousson .name = "dss_pwrdm",
86411f968fSBenoit Cousson .voltdm = { .name = "core" },
87411f968fSBenoit Cousson .prcm_offs = OMAP54XX_PRM_DSS_INST,
88411f968fSBenoit Cousson .prcm_partition = OMAP54XX_PRM_PARTITION,
89411f968fSBenoit Cousson .pwrsts = PWRSTS_OFF_RET_ON,
90411f968fSBenoit Cousson .pwrsts_logic_ret = PWRSTS_OFF,
91411f968fSBenoit Cousson .banks = 1,
92411f968fSBenoit Cousson .pwrsts_mem_ret = {
93411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* dss_mem */
94411f968fSBenoit Cousson },
95411f968fSBenoit Cousson .pwrsts_mem_on = {
96411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* dss_mem */
97411f968fSBenoit Cousson },
98411f968fSBenoit Cousson .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
99411f968fSBenoit Cousson };
100411f968fSBenoit Cousson
101411f968fSBenoit Cousson /* cpu0_54xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
102411f968fSBenoit Cousson static struct powerdomain cpu0_54xx_pwrdm = {
103411f968fSBenoit Cousson .name = "cpu0_pwrdm",
104411f968fSBenoit Cousson .voltdm = { .name = "mpu" },
105411f968fSBenoit Cousson .prcm_offs = OMAP54XX_PRCM_MPU_PRM_C0_INST,
106411f968fSBenoit Cousson .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
1079f5dc91bSNishanth Menon .pwrsts = PWRSTS_RET_ON,
1089f5dc91bSNishanth Menon .pwrsts_logic_ret = PWRSTS_RET,
109411f968fSBenoit Cousson .banks = 1,
110411f968fSBenoit Cousson .pwrsts_mem_ret = {
111411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* cpu0_l1 */
112411f968fSBenoit Cousson },
113411f968fSBenoit Cousson .pwrsts_mem_on = {
114411f968fSBenoit Cousson [0] = PWRSTS_ON, /* cpu0_l1 */
115411f968fSBenoit Cousson },
116411f968fSBenoit Cousson };
117411f968fSBenoit Cousson
118411f968fSBenoit Cousson /* cpu1_54xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
119411f968fSBenoit Cousson static struct powerdomain cpu1_54xx_pwrdm = {
120411f968fSBenoit Cousson .name = "cpu1_pwrdm",
121411f968fSBenoit Cousson .voltdm = { .name = "mpu" },
122411f968fSBenoit Cousson .prcm_offs = OMAP54XX_PRCM_MPU_PRM_C1_INST,
123411f968fSBenoit Cousson .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
1249f5dc91bSNishanth Menon .pwrsts = PWRSTS_RET_ON,
1259f5dc91bSNishanth Menon .pwrsts_logic_ret = PWRSTS_RET,
126411f968fSBenoit Cousson .banks = 1,
127411f968fSBenoit Cousson .pwrsts_mem_ret = {
128411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* cpu1_l1 */
129411f968fSBenoit Cousson },
130411f968fSBenoit Cousson .pwrsts_mem_on = {
131411f968fSBenoit Cousson [0] = PWRSTS_ON, /* cpu1_l1 */
132411f968fSBenoit Cousson },
133411f968fSBenoit Cousson };
134411f968fSBenoit Cousson
135411f968fSBenoit Cousson /* emu_54xx_pwrdm: Emulation power domain */
136411f968fSBenoit Cousson static struct powerdomain emu_54xx_pwrdm = {
137411f968fSBenoit Cousson .name = "emu_pwrdm",
138411f968fSBenoit Cousson .voltdm = { .name = "wkup" },
139411f968fSBenoit Cousson .prcm_offs = OMAP54XX_PRM_EMU_INST,
140411f968fSBenoit Cousson .prcm_partition = OMAP54XX_PRM_PARTITION,
141411f968fSBenoit Cousson .pwrsts = PWRSTS_OFF_ON,
142411f968fSBenoit Cousson .banks = 1,
143411f968fSBenoit Cousson .pwrsts_mem_ret = {
144411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* emu_bank */
145411f968fSBenoit Cousson },
146411f968fSBenoit Cousson .pwrsts_mem_on = {
147411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* emu_bank */
148411f968fSBenoit Cousson },
149411f968fSBenoit Cousson };
150411f968fSBenoit Cousson
151411f968fSBenoit Cousson /* mpu_54xx_pwrdm: Modena processor and the Neon coprocessor power domain */
152411f968fSBenoit Cousson static struct powerdomain mpu_54xx_pwrdm = {
153411f968fSBenoit Cousson .name = "mpu_pwrdm",
154411f968fSBenoit Cousson .voltdm = { .name = "mpu" },
155411f968fSBenoit Cousson .prcm_offs = OMAP54XX_PRM_MPU_INST,
156411f968fSBenoit Cousson .prcm_partition = OMAP54XX_PRM_PARTITION,
157411f968fSBenoit Cousson .pwrsts = PWRSTS_RET_ON,
1589f5dc91bSNishanth Menon .pwrsts_logic_ret = PWRSTS_RET,
159411f968fSBenoit Cousson .banks = 2,
160411f968fSBenoit Cousson .pwrsts_mem_ret = {
161411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* mpu_l2 */
162411f968fSBenoit Cousson [1] = PWRSTS_RET, /* mpu_ram */
163411f968fSBenoit Cousson },
164411f968fSBenoit Cousson .pwrsts_mem_on = {
165411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* mpu_l2 */
166411f968fSBenoit Cousson [1] = PWRSTS_OFF_RET, /* mpu_ram */
167411f968fSBenoit Cousson },
168411f968fSBenoit Cousson };
169411f968fSBenoit Cousson
170411f968fSBenoit Cousson /* custefuse_54xx_pwrdm: Customer efuse controller power domain */
171411f968fSBenoit Cousson static struct powerdomain custefuse_54xx_pwrdm = {
172411f968fSBenoit Cousson .name = "custefuse_pwrdm",
173411f968fSBenoit Cousson .voltdm = { .name = "core" },
174411f968fSBenoit Cousson .prcm_offs = OMAP54XX_PRM_CUSTEFUSE_INST,
175411f968fSBenoit Cousson .prcm_partition = OMAP54XX_PRM_PARTITION,
176411f968fSBenoit Cousson .pwrsts = PWRSTS_OFF_ON,
177411f968fSBenoit Cousson .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
178411f968fSBenoit Cousson };
179411f968fSBenoit Cousson
180411f968fSBenoit Cousson /* dsp_54xx_pwrdm: Tesla processor power domain */
181411f968fSBenoit Cousson static struct powerdomain dsp_54xx_pwrdm = {
182411f968fSBenoit Cousson .name = "dsp_pwrdm",
183411f968fSBenoit Cousson .voltdm = { .name = "mm" },
184411f968fSBenoit Cousson .prcm_offs = OMAP54XX_PRM_DSP_INST,
185411f968fSBenoit Cousson .prcm_partition = OMAP54XX_PRM_PARTITION,
186411f968fSBenoit Cousson .pwrsts = PWRSTS_OFF_RET_ON,
187411f968fSBenoit Cousson .pwrsts_logic_ret = PWRSTS_OFF_RET,
188411f968fSBenoit Cousson .banks = 3,
189411f968fSBenoit Cousson .pwrsts_mem_ret = {
190411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* dsp_edma */
191411f968fSBenoit Cousson [1] = PWRSTS_OFF_RET, /* dsp_l1 */
192411f968fSBenoit Cousson [2] = PWRSTS_OFF_RET, /* dsp_l2 */
193411f968fSBenoit Cousson },
194411f968fSBenoit Cousson .pwrsts_mem_on = {
195411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* dsp_edma */
196411f968fSBenoit Cousson [1] = PWRSTS_OFF_RET, /* dsp_l1 */
197411f968fSBenoit Cousson [2] = PWRSTS_OFF_RET, /* dsp_l2 */
198411f968fSBenoit Cousson },
199411f968fSBenoit Cousson .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
200411f968fSBenoit Cousson };
201411f968fSBenoit Cousson
202411f968fSBenoit Cousson /* cam_54xx_pwrdm: Camera subsystem power domain */
203411f968fSBenoit Cousson static struct powerdomain cam_54xx_pwrdm = {
204411f968fSBenoit Cousson .name = "cam_pwrdm",
205411f968fSBenoit Cousson .voltdm = { .name = "core" },
206411f968fSBenoit Cousson .prcm_offs = OMAP54XX_PRM_CAM_INST,
207411f968fSBenoit Cousson .prcm_partition = OMAP54XX_PRM_PARTITION,
208411f968fSBenoit Cousson .pwrsts = PWRSTS_OFF_ON,
209411f968fSBenoit Cousson .banks = 1,
210411f968fSBenoit Cousson .pwrsts_mem_ret = {
211411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* cam_mem */
212411f968fSBenoit Cousson },
213411f968fSBenoit Cousson .pwrsts_mem_on = {
214411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* cam_mem */
215411f968fSBenoit Cousson },
216411f968fSBenoit Cousson .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
217411f968fSBenoit Cousson };
218411f968fSBenoit Cousson
219411f968fSBenoit Cousson /* l3init_54xx_pwrdm: L3 initators pheripherals power domain */
220411f968fSBenoit Cousson static struct powerdomain l3init_54xx_pwrdm = {
221411f968fSBenoit Cousson .name = "l3init_pwrdm",
222411f968fSBenoit Cousson .voltdm = { .name = "core" },
223411f968fSBenoit Cousson .prcm_offs = OMAP54XX_PRM_L3INIT_INST,
224411f968fSBenoit Cousson .prcm_partition = OMAP54XX_PRM_PARTITION,
225411f968fSBenoit Cousson .pwrsts = PWRSTS_RET_ON,
226411f968fSBenoit Cousson .pwrsts_logic_ret = PWRSTS_OFF_RET,
227411f968fSBenoit Cousson .banks = 2,
228411f968fSBenoit Cousson .pwrsts_mem_ret = {
229411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* l3init_bank1 */
230411f968fSBenoit Cousson [1] = PWRSTS_OFF_RET, /* l3init_bank2 */
231411f968fSBenoit Cousson },
232411f968fSBenoit Cousson .pwrsts_mem_on = {
233411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* l3init_bank1 */
234411f968fSBenoit Cousson [1] = PWRSTS_OFF_RET, /* l3init_bank2 */
235411f968fSBenoit Cousson },
236411f968fSBenoit Cousson .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
237411f968fSBenoit Cousson };
238411f968fSBenoit Cousson
239411f968fSBenoit Cousson /* gpu_54xx_pwrdm: 3D accelerator power domain */
240411f968fSBenoit Cousson static struct powerdomain gpu_54xx_pwrdm = {
241411f968fSBenoit Cousson .name = "gpu_pwrdm",
242411f968fSBenoit Cousson .voltdm = { .name = "mm" },
243411f968fSBenoit Cousson .prcm_offs = OMAP54XX_PRM_GPU_INST,
244411f968fSBenoit Cousson .prcm_partition = OMAP54XX_PRM_PARTITION,
245411f968fSBenoit Cousson .pwrsts = PWRSTS_OFF_ON,
246411f968fSBenoit Cousson .banks = 1,
247411f968fSBenoit Cousson .pwrsts_mem_ret = {
248411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* gpu_mem */
249411f968fSBenoit Cousson },
250411f968fSBenoit Cousson .pwrsts_mem_on = {
251411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* gpu_mem */
252411f968fSBenoit Cousson },
253411f968fSBenoit Cousson .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
254411f968fSBenoit Cousson };
255411f968fSBenoit Cousson
256411f968fSBenoit Cousson /* wkupaon_54xx_pwrdm: Wake-up power domain */
257411f968fSBenoit Cousson static struct powerdomain wkupaon_54xx_pwrdm = {
258411f968fSBenoit Cousson .name = "wkupaon_pwrdm",
259411f968fSBenoit Cousson .voltdm = { .name = "wkup" },
260411f968fSBenoit Cousson .prcm_offs = OMAP54XX_PRM_WKUPAON_INST,
261411f968fSBenoit Cousson .prcm_partition = OMAP54XX_PRM_PARTITION,
262411f968fSBenoit Cousson .pwrsts = PWRSTS_ON,
263411f968fSBenoit Cousson .banks = 1,
264411f968fSBenoit Cousson .pwrsts_mem_ret = {
265411f968fSBenoit Cousson },
266411f968fSBenoit Cousson .pwrsts_mem_on = {
267411f968fSBenoit Cousson [0] = PWRSTS_ON, /* wkup_bank */
268411f968fSBenoit Cousson },
269411f968fSBenoit Cousson };
270411f968fSBenoit Cousson
271411f968fSBenoit Cousson /* iva_54xx_pwrdm: IVA-HD power domain */
272411f968fSBenoit Cousson static struct powerdomain iva_54xx_pwrdm = {
273411f968fSBenoit Cousson .name = "iva_pwrdm",
274411f968fSBenoit Cousson .voltdm = { .name = "mm" },
275411f968fSBenoit Cousson .prcm_offs = OMAP54XX_PRM_IVA_INST,
276411f968fSBenoit Cousson .prcm_partition = OMAP54XX_PRM_PARTITION,
277411f968fSBenoit Cousson .pwrsts = PWRSTS_OFF_RET_ON,
278411f968fSBenoit Cousson .pwrsts_logic_ret = PWRSTS_OFF,
279411f968fSBenoit Cousson .banks = 4,
280411f968fSBenoit Cousson .pwrsts_mem_ret = {
281411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* hwa_mem */
282411f968fSBenoit Cousson [1] = PWRSTS_OFF_RET, /* sl2_mem */
283411f968fSBenoit Cousson [2] = PWRSTS_OFF_RET, /* tcm1_mem */
284411f968fSBenoit Cousson [3] = PWRSTS_OFF_RET, /* tcm2_mem */
285411f968fSBenoit Cousson },
286411f968fSBenoit Cousson .pwrsts_mem_on = {
287411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* hwa_mem */
288411f968fSBenoit Cousson [1] = PWRSTS_OFF_RET, /* sl2_mem */
289411f968fSBenoit Cousson [2] = PWRSTS_OFF_RET, /* tcm1_mem */
290411f968fSBenoit Cousson [3] = PWRSTS_OFF_RET, /* tcm2_mem */
291411f968fSBenoit Cousson },
292411f968fSBenoit Cousson .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
293411f968fSBenoit Cousson };
294411f968fSBenoit Cousson
295411f968fSBenoit Cousson /*
296411f968fSBenoit Cousson * The following power domains are not under SW control
297411f968fSBenoit Cousson *
298411f968fSBenoit Cousson * mpuaon
299411f968fSBenoit Cousson * mmaon
300411f968fSBenoit Cousson */
301411f968fSBenoit Cousson
302411f968fSBenoit Cousson /* As powerdomains are added or removed above, this list must also be changed */
303411f968fSBenoit Cousson static struct powerdomain *powerdomains_omap54xx[] __initdata = {
304411f968fSBenoit Cousson &core_54xx_pwrdm,
305411f968fSBenoit Cousson &abe_54xx_pwrdm,
306411f968fSBenoit Cousson &coreaon_54xx_pwrdm,
307411f968fSBenoit Cousson &dss_54xx_pwrdm,
308411f968fSBenoit Cousson &cpu0_54xx_pwrdm,
309411f968fSBenoit Cousson &cpu1_54xx_pwrdm,
310411f968fSBenoit Cousson &emu_54xx_pwrdm,
311411f968fSBenoit Cousson &mpu_54xx_pwrdm,
312411f968fSBenoit Cousson &custefuse_54xx_pwrdm,
313411f968fSBenoit Cousson &dsp_54xx_pwrdm,
314411f968fSBenoit Cousson &cam_54xx_pwrdm,
315411f968fSBenoit Cousson &l3init_54xx_pwrdm,
316411f968fSBenoit Cousson &gpu_54xx_pwrdm,
317411f968fSBenoit Cousson &wkupaon_54xx_pwrdm,
318411f968fSBenoit Cousson &iva_54xx_pwrdm,
319411f968fSBenoit Cousson NULL
320411f968fSBenoit Cousson };
321411f968fSBenoit Cousson
omap54xx_powerdomains_init(void)322411f968fSBenoit Cousson void __init omap54xx_powerdomains_init(void)
323411f968fSBenoit Cousson {
324411f968fSBenoit Cousson pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
325411f968fSBenoit Cousson pwrdm_register_pwrdms(powerdomains_omap54xx);
326411f968fSBenoit Cousson pwrdm_complete_init();
327411f968fSBenoit Cousson }
328