1411f968fSBenoit Cousson /* 2411f968fSBenoit Cousson * OMAP54XX Power domains framework 3411f968fSBenoit Cousson * 4411f968fSBenoit Cousson * Copyright (C) 2013 Texas Instruments, Inc. 5411f968fSBenoit Cousson * 6411f968fSBenoit Cousson * Abhijit Pagare (abhijitpagare@ti.com) 7411f968fSBenoit Cousson * Benoit Cousson (b-cousson@ti.com) 8411f968fSBenoit Cousson * Paul Walmsley (paul@pwsan.com) 9411f968fSBenoit Cousson * 10411f968fSBenoit Cousson * This file is automatically generated from the OMAP hardware databases. 11411f968fSBenoit Cousson * We respectfully ask that any modifications to this file be coordinated 12411f968fSBenoit Cousson * with the public linux-omap@vger.kernel.org mailing list and the 13411f968fSBenoit Cousson * authors above to ensure that the autogeneration scripts are kept 14411f968fSBenoit Cousson * up-to-date with the file contents. 15411f968fSBenoit Cousson * 16411f968fSBenoit Cousson * This program is free software; you can redistribute it and/or modify 17411f968fSBenoit Cousson * it under the terms of the GNU General Public License version 2 as 18411f968fSBenoit Cousson * published by the Free Software Foundation. 19411f968fSBenoit Cousson */ 20411f968fSBenoit Cousson 21411f968fSBenoit Cousson #include <linux/kernel.h> 22411f968fSBenoit Cousson #include <linux/init.h> 23411f968fSBenoit Cousson 24411f968fSBenoit Cousson #include "powerdomain.h" 25411f968fSBenoit Cousson 26411f968fSBenoit Cousson #include "prcm-common.h" 27411f968fSBenoit Cousson #include "prcm44xx.h" 28411f968fSBenoit Cousson #include "prm54xx.h" 29411f968fSBenoit Cousson #include "prcm_mpu54xx.h" 30411f968fSBenoit Cousson 31411f968fSBenoit Cousson /* core_54xx_pwrdm: CORE power domain */ 32411f968fSBenoit Cousson static struct powerdomain core_54xx_pwrdm = { 33411f968fSBenoit Cousson .name = "core_pwrdm", 34411f968fSBenoit Cousson .voltdm = { .name = "core" }, 35411f968fSBenoit Cousson .prcm_offs = OMAP54XX_PRM_CORE_INST, 36411f968fSBenoit Cousson .prcm_partition = OMAP54XX_PRM_PARTITION, 37411f968fSBenoit Cousson .pwrsts = PWRSTS_RET_ON, 389f5dc91bSNishanth Menon .pwrsts_logic_ret = PWRSTS_RET, 39411f968fSBenoit Cousson .banks = 5, 40411f968fSBenoit Cousson .pwrsts_mem_ret = { 41411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* core_nret_bank */ 42411f968fSBenoit Cousson [1] = PWRSTS_OFF_RET, /* core_ocmram */ 43411f968fSBenoit Cousson [2] = PWRSTS_OFF_RET, /* core_other_bank */ 44411f968fSBenoit Cousson [3] = PWRSTS_OFF_RET, /* ipu_l2ram */ 45411f968fSBenoit Cousson [4] = PWRSTS_OFF_RET, /* ipu_unicache */ 46411f968fSBenoit Cousson }, 47411f968fSBenoit Cousson .pwrsts_mem_on = { 48411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* core_nret_bank */ 49411f968fSBenoit Cousson [1] = PWRSTS_OFF_RET, /* core_ocmram */ 50411f968fSBenoit Cousson [2] = PWRSTS_OFF_RET, /* core_other_bank */ 51411f968fSBenoit Cousson [3] = PWRSTS_OFF_RET, /* ipu_l2ram */ 52411f968fSBenoit Cousson [4] = PWRSTS_OFF_RET, /* ipu_unicache */ 53411f968fSBenoit Cousson }, 54411f968fSBenoit Cousson .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 55411f968fSBenoit Cousson }; 56411f968fSBenoit Cousson 57411f968fSBenoit Cousson /* abe_54xx_pwrdm: Audio back end power domain */ 58411f968fSBenoit Cousson static struct powerdomain abe_54xx_pwrdm = { 59411f968fSBenoit Cousson .name = "abe_pwrdm", 60411f968fSBenoit Cousson .voltdm = { .name = "core" }, 61411f968fSBenoit Cousson .prcm_offs = OMAP54XX_PRM_ABE_INST, 62411f968fSBenoit Cousson .prcm_partition = OMAP54XX_PRM_PARTITION, 63411f968fSBenoit Cousson .pwrsts = PWRSTS_OFF_RET_ON, 64411f968fSBenoit Cousson .pwrsts_logic_ret = PWRSTS_OFF, 65411f968fSBenoit Cousson .banks = 2, 66411f968fSBenoit Cousson .pwrsts_mem_ret = { 67411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* aessmem */ 68411f968fSBenoit Cousson [1] = PWRSTS_OFF_RET, /* periphmem */ 69411f968fSBenoit Cousson }, 70411f968fSBenoit Cousson .pwrsts_mem_on = { 71411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* aessmem */ 72411f968fSBenoit Cousson [1] = PWRSTS_OFF_RET, /* periphmem */ 73411f968fSBenoit Cousson }, 74411f968fSBenoit Cousson .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 75411f968fSBenoit Cousson }; 76411f968fSBenoit Cousson 77411f968fSBenoit Cousson /* coreaon_54xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */ 78411f968fSBenoit Cousson static struct powerdomain coreaon_54xx_pwrdm = { 79411f968fSBenoit Cousson .name = "coreaon_pwrdm", 80411f968fSBenoit Cousson .voltdm = { .name = "core" }, 81411f968fSBenoit Cousson .prcm_offs = OMAP54XX_PRM_COREAON_INST, 82411f968fSBenoit Cousson .prcm_partition = OMAP54XX_PRM_PARTITION, 83411f968fSBenoit Cousson .pwrsts = PWRSTS_ON, 84411f968fSBenoit Cousson }; 85411f968fSBenoit Cousson 86411f968fSBenoit Cousson /* dss_54xx_pwrdm: Display subsystem power domain */ 87411f968fSBenoit Cousson static struct powerdomain dss_54xx_pwrdm = { 88411f968fSBenoit Cousson .name = "dss_pwrdm", 89411f968fSBenoit Cousson .voltdm = { .name = "core" }, 90411f968fSBenoit Cousson .prcm_offs = OMAP54XX_PRM_DSS_INST, 91411f968fSBenoit Cousson .prcm_partition = OMAP54XX_PRM_PARTITION, 92411f968fSBenoit Cousson .pwrsts = PWRSTS_OFF_RET_ON, 93411f968fSBenoit Cousson .pwrsts_logic_ret = PWRSTS_OFF, 94411f968fSBenoit Cousson .banks = 1, 95411f968fSBenoit Cousson .pwrsts_mem_ret = { 96411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* dss_mem */ 97411f968fSBenoit Cousson }, 98411f968fSBenoit Cousson .pwrsts_mem_on = { 99411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* dss_mem */ 100411f968fSBenoit Cousson }, 101411f968fSBenoit Cousson .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 102411f968fSBenoit Cousson }; 103411f968fSBenoit Cousson 104411f968fSBenoit Cousson /* cpu0_54xx_pwrdm: MPU0 processor and Neon coprocessor power domain */ 105411f968fSBenoit Cousson static struct powerdomain cpu0_54xx_pwrdm = { 106411f968fSBenoit Cousson .name = "cpu0_pwrdm", 107411f968fSBenoit Cousson .voltdm = { .name = "mpu" }, 108411f968fSBenoit Cousson .prcm_offs = OMAP54XX_PRCM_MPU_PRM_C0_INST, 109411f968fSBenoit Cousson .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION, 1109f5dc91bSNishanth Menon .pwrsts = PWRSTS_RET_ON, 1119f5dc91bSNishanth Menon .pwrsts_logic_ret = PWRSTS_RET, 112411f968fSBenoit Cousson .banks = 1, 113411f968fSBenoit Cousson .pwrsts_mem_ret = { 114411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* cpu0_l1 */ 115411f968fSBenoit Cousson }, 116411f968fSBenoit Cousson .pwrsts_mem_on = { 117411f968fSBenoit Cousson [0] = PWRSTS_ON, /* cpu0_l1 */ 118411f968fSBenoit Cousson }, 119411f968fSBenoit Cousson }; 120411f968fSBenoit Cousson 121411f968fSBenoit Cousson /* cpu1_54xx_pwrdm: MPU1 processor and Neon coprocessor power domain */ 122411f968fSBenoit Cousson static struct powerdomain cpu1_54xx_pwrdm = { 123411f968fSBenoit Cousson .name = "cpu1_pwrdm", 124411f968fSBenoit Cousson .voltdm = { .name = "mpu" }, 125411f968fSBenoit Cousson .prcm_offs = OMAP54XX_PRCM_MPU_PRM_C1_INST, 126411f968fSBenoit Cousson .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION, 1279f5dc91bSNishanth Menon .pwrsts = PWRSTS_RET_ON, 1289f5dc91bSNishanth Menon .pwrsts_logic_ret = PWRSTS_RET, 129411f968fSBenoit Cousson .banks = 1, 130411f968fSBenoit Cousson .pwrsts_mem_ret = { 131411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* cpu1_l1 */ 132411f968fSBenoit Cousson }, 133411f968fSBenoit Cousson .pwrsts_mem_on = { 134411f968fSBenoit Cousson [0] = PWRSTS_ON, /* cpu1_l1 */ 135411f968fSBenoit Cousson }, 136411f968fSBenoit Cousson }; 137411f968fSBenoit Cousson 138411f968fSBenoit Cousson /* emu_54xx_pwrdm: Emulation power domain */ 139411f968fSBenoit Cousson static struct powerdomain emu_54xx_pwrdm = { 140411f968fSBenoit Cousson .name = "emu_pwrdm", 141411f968fSBenoit Cousson .voltdm = { .name = "wkup" }, 142411f968fSBenoit Cousson .prcm_offs = OMAP54XX_PRM_EMU_INST, 143411f968fSBenoit Cousson .prcm_partition = OMAP54XX_PRM_PARTITION, 144411f968fSBenoit Cousson .pwrsts = PWRSTS_OFF_ON, 145411f968fSBenoit Cousson .banks = 1, 146411f968fSBenoit Cousson .pwrsts_mem_ret = { 147411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* emu_bank */ 148411f968fSBenoit Cousson }, 149411f968fSBenoit Cousson .pwrsts_mem_on = { 150411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* emu_bank */ 151411f968fSBenoit Cousson }, 152411f968fSBenoit Cousson }; 153411f968fSBenoit Cousson 154411f968fSBenoit Cousson /* mpu_54xx_pwrdm: Modena processor and the Neon coprocessor power domain */ 155411f968fSBenoit Cousson static struct powerdomain mpu_54xx_pwrdm = { 156411f968fSBenoit Cousson .name = "mpu_pwrdm", 157411f968fSBenoit Cousson .voltdm = { .name = "mpu" }, 158411f968fSBenoit Cousson .prcm_offs = OMAP54XX_PRM_MPU_INST, 159411f968fSBenoit Cousson .prcm_partition = OMAP54XX_PRM_PARTITION, 160411f968fSBenoit Cousson .pwrsts = PWRSTS_RET_ON, 1619f5dc91bSNishanth Menon .pwrsts_logic_ret = PWRSTS_RET, 162411f968fSBenoit Cousson .banks = 2, 163411f968fSBenoit Cousson .pwrsts_mem_ret = { 164411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* mpu_l2 */ 165411f968fSBenoit Cousson [1] = PWRSTS_RET, /* mpu_ram */ 166411f968fSBenoit Cousson }, 167411f968fSBenoit Cousson .pwrsts_mem_on = { 168411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* mpu_l2 */ 169411f968fSBenoit Cousson [1] = PWRSTS_OFF_RET, /* mpu_ram */ 170411f968fSBenoit Cousson }, 171411f968fSBenoit Cousson }; 172411f968fSBenoit Cousson 173411f968fSBenoit Cousson /* custefuse_54xx_pwrdm: Customer efuse controller power domain */ 174411f968fSBenoit Cousson static struct powerdomain custefuse_54xx_pwrdm = { 175411f968fSBenoit Cousson .name = "custefuse_pwrdm", 176411f968fSBenoit Cousson .voltdm = { .name = "core" }, 177411f968fSBenoit Cousson .prcm_offs = OMAP54XX_PRM_CUSTEFUSE_INST, 178411f968fSBenoit Cousson .prcm_partition = OMAP54XX_PRM_PARTITION, 179411f968fSBenoit Cousson .pwrsts = PWRSTS_OFF_ON, 180411f968fSBenoit Cousson .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 181411f968fSBenoit Cousson }; 182411f968fSBenoit Cousson 183411f968fSBenoit Cousson /* dsp_54xx_pwrdm: Tesla processor power domain */ 184411f968fSBenoit Cousson static struct powerdomain dsp_54xx_pwrdm = { 185411f968fSBenoit Cousson .name = "dsp_pwrdm", 186411f968fSBenoit Cousson .voltdm = { .name = "mm" }, 187411f968fSBenoit Cousson .prcm_offs = OMAP54XX_PRM_DSP_INST, 188411f968fSBenoit Cousson .prcm_partition = OMAP54XX_PRM_PARTITION, 189411f968fSBenoit Cousson .pwrsts = PWRSTS_OFF_RET_ON, 190411f968fSBenoit Cousson .pwrsts_logic_ret = PWRSTS_OFF_RET, 191411f968fSBenoit Cousson .banks = 3, 192411f968fSBenoit Cousson .pwrsts_mem_ret = { 193411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* dsp_edma */ 194411f968fSBenoit Cousson [1] = PWRSTS_OFF_RET, /* dsp_l1 */ 195411f968fSBenoit Cousson [2] = PWRSTS_OFF_RET, /* dsp_l2 */ 196411f968fSBenoit Cousson }, 197411f968fSBenoit Cousson .pwrsts_mem_on = { 198411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* dsp_edma */ 199411f968fSBenoit Cousson [1] = PWRSTS_OFF_RET, /* dsp_l1 */ 200411f968fSBenoit Cousson [2] = PWRSTS_OFF_RET, /* dsp_l2 */ 201411f968fSBenoit Cousson }, 202411f968fSBenoit Cousson .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 203411f968fSBenoit Cousson }; 204411f968fSBenoit Cousson 205411f968fSBenoit Cousson /* cam_54xx_pwrdm: Camera subsystem power domain */ 206411f968fSBenoit Cousson static struct powerdomain cam_54xx_pwrdm = { 207411f968fSBenoit Cousson .name = "cam_pwrdm", 208411f968fSBenoit Cousson .voltdm = { .name = "core" }, 209411f968fSBenoit Cousson .prcm_offs = OMAP54XX_PRM_CAM_INST, 210411f968fSBenoit Cousson .prcm_partition = OMAP54XX_PRM_PARTITION, 211411f968fSBenoit Cousson .pwrsts = PWRSTS_OFF_ON, 212411f968fSBenoit Cousson .banks = 1, 213411f968fSBenoit Cousson .pwrsts_mem_ret = { 214411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* cam_mem */ 215411f968fSBenoit Cousson }, 216411f968fSBenoit Cousson .pwrsts_mem_on = { 217411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* cam_mem */ 218411f968fSBenoit Cousson }, 219411f968fSBenoit Cousson .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 220411f968fSBenoit Cousson }; 221411f968fSBenoit Cousson 222411f968fSBenoit Cousson /* l3init_54xx_pwrdm: L3 initators pheripherals power domain */ 223411f968fSBenoit Cousson static struct powerdomain l3init_54xx_pwrdm = { 224411f968fSBenoit Cousson .name = "l3init_pwrdm", 225411f968fSBenoit Cousson .voltdm = { .name = "core" }, 226411f968fSBenoit Cousson .prcm_offs = OMAP54XX_PRM_L3INIT_INST, 227411f968fSBenoit Cousson .prcm_partition = OMAP54XX_PRM_PARTITION, 228411f968fSBenoit Cousson .pwrsts = PWRSTS_RET_ON, 229411f968fSBenoit Cousson .pwrsts_logic_ret = PWRSTS_OFF_RET, 230411f968fSBenoit Cousson .banks = 2, 231411f968fSBenoit Cousson .pwrsts_mem_ret = { 232411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* l3init_bank1 */ 233411f968fSBenoit Cousson [1] = PWRSTS_OFF_RET, /* l3init_bank2 */ 234411f968fSBenoit Cousson }, 235411f968fSBenoit Cousson .pwrsts_mem_on = { 236411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* l3init_bank1 */ 237411f968fSBenoit Cousson [1] = PWRSTS_OFF_RET, /* l3init_bank2 */ 238411f968fSBenoit Cousson }, 239411f968fSBenoit Cousson .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 240411f968fSBenoit Cousson }; 241411f968fSBenoit Cousson 242411f968fSBenoit Cousson /* gpu_54xx_pwrdm: 3D accelerator power domain */ 243411f968fSBenoit Cousson static struct powerdomain gpu_54xx_pwrdm = { 244411f968fSBenoit Cousson .name = "gpu_pwrdm", 245411f968fSBenoit Cousson .voltdm = { .name = "mm" }, 246411f968fSBenoit Cousson .prcm_offs = OMAP54XX_PRM_GPU_INST, 247411f968fSBenoit Cousson .prcm_partition = OMAP54XX_PRM_PARTITION, 248411f968fSBenoit Cousson .pwrsts = PWRSTS_OFF_ON, 249411f968fSBenoit Cousson .banks = 1, 250411f968fSBenoit Cousson .pwrsts_mem_ret = { 251411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* gpu_mem */ 252411f968fSBenoit Cousson }, 253411f968fSBenoit Cousson .pwrsts_mem_on = { 254411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* gpu_mem */ 255411f968fSBenoit Cousson }, 256411f968fSBenoit Cousson .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 257411f968fSBenoit Cousson }; 258411f968fSBenoit Cousson 259411f968fSBenoit Cousson /* wkupaon_54xx_pwrdm: Wake-up power domain */ 260411f968fSBenoit Cousson static struct powerdomain wkupaon_54xx_pwrdm = { 261411f968fSBenoit Cousson .name = "wkupaon_pwrdm", 262411f968fSBenoit Cousson .voltdm = { .name = "wkup" }, 263411f968fSBenoit Cousson .prcm_offs = OMAP54XX_PRM_WKUPAON_INST, 264411f968fSBenoit Cousson .prcm_partition = OMAP54XX_PRM_PARTITION, 265411f968fSBenoit Cousson .pwrsts = PWRSTS_ON, 266411f968fSBenoit Cousson .banks = 1, 267411f968fSBenoit Cousson .pwrsts_mem_ret = { 268411f968fSBenoit Cousson }, 269411f968fSBenoit Cousson .pwrsts_mem_on = { 270411f968fSBenoit Cousson [0] = PWRSTS_ON, /* wkup_bank */ 271411f968fSBenoit Cousson }, 272411f968fSBenoit Cousson }; 273411f968fSBenoit Cousson 274411f968fSBenoit Cousson /* iva_54xx_pwrdm: IVA-HD power domain */ 275411f968fSBenoit Cousson static struct powerdomain iva_54xx_pwrdm = { 276411f968fSBenoit Cousson .name = "iva_pwrdm", 277411f968fSBenoit Cousson .voltdm = { .name = "mm" }, 278411f968fSBenoit Cousson .prcm_offs = OMAP54XX_PRM_IVA_INST, 279411f968fSBenoit Cousson .prcm_partition = OMAP54XX_PRM_PARTITION, 280411f968fSBenoit Cousson .pwrsts = PWRSTS_OFF_RET_ON, 281411f968fSBenoit Cousson .pwrsts_logic_ret = PWRSTS_OFF, 282411f968fSBenoit Cousson .banks = 4, 283411f968fSBenoit Cousson .pwrsts_mem_ret = { 284411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* hwa_mem */ 285411f968fSBenoit Cousson [1] = PWRSTS_OFF_RET, /* sl2_mem */ 286411f968fSBenoit Cousson [2] = PWRSTS_OFF_RET, /* tcm1_mem */ 287411f968fSBenoit Cousson [3] = PWRSTS_OFF_RET, /* tcm2_mem */ 288411f968fSBenoit Cousson }, 289411f968fSBenoit Cousson .pwrsts_mem_on = { 290411f968fSBenoit Cousson [0] = PWRSTS_OFF_RET, /* hwa_mem */ 291411f968fSBenoit Cousson [1] = PWRSTS_OFF_RET, /* sl2_mem */ 292411f968fSBenoit Cousson [2] = PWRSTS_OFF_RET, /* tcm1_mem */ 293411f968fSBenoit Cousson [3] = PWRSTS_OFF_RET, /* tcm2_mem */ 294411f968fSBenoit Cousson }, 295411f968fSBenoit Cousson .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 296411f968fSBenoit Cousson }; 297411f968fSBenoit Cousson 298411f968fSBenoit Cousson /* 299411f968fSBenoit Cousson * The following power domains are not under SW control 300411f968fSBenoit Cousson * 301411f968fSBenoit Cousson * mpuaon 302411f968fSBenoit Cousson * mmaon 303411f968fSBenoit Cousson */ 304411f968fSBenoit Cousson 305411f968fSBenoit Cousson /* As powerdomains are added or removed above, this list must also be changed */ 306411f968fSBenoit Cousson static struct powerdomain *powerdomains_omap54xx[] __initdata = { 307411f968fSBenoit Cousson &core_54xx_pwrdm, 308411f968fSBenoit Cousson &abe_54xx_pwrdm, 309411f968fSBenoit Cousson &coreaon_54xx_pwrdm, 310411f968fSBenoit Cousson &dss_54xx_pwrdm, 311411f968fSBenoit Cousson &cpu0_54xx_pwrdm, 312411f968fSBenoit Cousson &cpu1_54xx_pwrdm, 313411f968fSBenoit Cousson &emu_54xx_pwrdm, 314411f968fSBenoit Cousson &mpu_54xx_pwrdm, 315411f968fSBenoit Cousson &custefuse_54xx_pwrdm, 316411f968fSBenoit Cousson &dsp_54xx_pwrdm, 317411f968fSBenoit Cousson &cam_54xx_pwrdm, 318411f968fSBenoit Cousson &l3init_54xx_pwrdm, 319411f968fSBenoit Cousson &gpu_54xx_pwrdm, 320411f968fSBenoit Cousson &wkupaon_54xx_pwrdm, 321411f968fSBenoit Cousson &iva_54xx_pwrdm, 322411f968fSBenoit Cousson NULL 323411f968fSBenoit Cousson }; 324411f968fSBenoit Cousson 325411f968fSBenoit Cousson void __init omap54xx_powerdomains_init(void) 326411f968fSBenoit Cousson { 327411f968fSBenoit Cousson pwrdm_register_platform_funcs(&omap4_pwrdm_operations); 328411f968fSBenoit Cousson pwrdm_register_pwrdms(powerdomains_omap54xx); 329411f968fSBenoit Cousson pwrdm_complete_init(); 330411f968fSBenoit Cousson } 331