1 /* 2 * OMAP2/3/4 powerdomain control 3 * 4 * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc. 5 * Copyright (C) 2007-2011 Nokia Corporation 6 * 7 * Paul Walmsley 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * XXX This should be moved to the mach-omap2/ directory at the earliest 14 * opportunity. 15 */ 16 17 #ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H 18 #define __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H 19 20 #include <linux/types.h> 21 #include <linux/list.h> 22 23 #include <linux/atomic.h> 24 25 #include <plat/cpu.h> 26 27 #include "voltage.h" 28 29 /* Powerdomain basic power states */ 30 #define PWRDM_POWER_OFF 0x0 31 #define PWRDM_POWER_RET 0x1 32 #define PWRDM_POWER_INACTIVE 0x2 33 #define PWRDM_POWER_ON 0x3 34 35 #define PWRDM_MAX_PWRSTS 4 36 37 /* Powerdomain allowable state bitfields */ 38 #define PWRSTS_ON (1 << PWRDM_POWER_ON) 39 #define PWRSTS_INACTIVE (1 << PWRDM_POWER_INACTIVE) 40 #define PWRSTS_RET (1 << PWRDM_POWER_RET) 41 #define PWRSTS_OFF (1 << PWRDM_POWER_OFF) 42 43 #define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON) 44 #define PWRSTS_OFF_RET (PWRSTS_OFF | PWRSTS_RET) 45 #define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON) 46 #define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON) 47 48 49 /* Powerdomain flags */ 50 #define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */ 51 #define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits 52 * in MEM bank 1 position. This is 53 * true for OMAP3430 54 */ 55 #define PWRDM_HAS_LOWPOWERSTATECHANGE (1 << 2) /* 56 * support to transition from a 57 * sleep state to a lower sleep 58 * state without waking up the 59 * powerdomain 60 */ 61 62 /* 63 * Number of memory banks that are power-controllable. On OMAP4430, the 64 * maximum is 5. 65 */ 66 #define PWRDM_MAX_MEM_BANKS 5 67 68 /* 69 * Maximum number of clockdomains that can be associated with a powerdomain. 70 * PER powerdomain on AM33XX is the worst case 71 */ 72 #define PWRDM_MAX_CLKDMS 11 73 74 /* XXX A completely arbitrary number. What is reasonable here? */ 75 #define PWRDM_TRANSITION_BAILOUT 100000 76 77 struct clockdomain; 78 struct powerdomain; 79 80 /** 81 * struct powerdomain - OMAP powerdomain 82 * @name: Powerdomain name 83 * @voltdm: voltagedomain containing this powerdomain 84 * @prcm_offs: the address offset from CM_BASE/PRM_BASE 85 * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs 86 * @pwrsts: Possible powerdomain power states 87 * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION 88 * @flags: Powerdomain flags 89 * @banks: Number of software-controllable memory banks in this powerdomain 90 * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION 91 * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON 92 * @pwrdm_clkdms: Clockdomains in this powerdomain 93 * @node: list_head linking all powerdomains 94 * @voltdm_node: list_head linking all powerdomains in a voltagedomain 95 * @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs 96 * @pwrstst_offs: (AM33XX only) XXX_PWRSTST reg offset from prcm_offs 97 * @logicretstate_mask: (AM33XX only) mask for logic retention bitfield 98 * in @pwrstctrl_offs 99 * @mem_on_mask: (AM33XX only) mask for mem on bitfield in @pwrstctrl_offs 100 * @mem_ret_mask: (AM33XX only) mask for mem ret bitfield in @pwrstctrl_offs 101 * @mem_pwrst_mask: (AM33XX only) mask for mem state bitfield in @pwrstst_offs 102 * @mem_retst_mask: (AM33XX only) mask for mem retention state bitfield 103 * in @pwrstctrl_offs 104 * @state: 105 * @state_counter: 106 * @timer: 107 * @state_timer: 108 * 109 * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h. 110 */ 111 struct powerdomain { 112 const char *name; 113 union { 114 const char *name; 115 struct voltagedomain *ptr; 116 } voltdm; 117 const s16 prcm_offs; 118 const u8 pwrsts; 119 const u8 pwrsts_logic_ret; 120 const u8 flags; 121 const u8 banks; 122 const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS]; 123 const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS]; 124 const u8 prcm_partition; 125 struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS]; 126 struct list_head node; 127 struct list_head voltdm_node; 128 int state; 129 unsigned state_counter[PWRDM_MAX_PWRSTS]; 130 unsigned ret_logic_off_counter; 131 unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS]; 132 133 const u8 pwrstctrl_offs; 134 const u8 pwrstst_offs; 135 const u32 logicretstate_mask; 136 const u32 mem_on_mask[PWRDM_MAX_MEM_BANKS]; 137 const u32 mem_ret_mask[PWRDM_MAX_MEM_BANKS]; 138 const u32 mem_pwrst_mask[PWRDM_MAX_MEM_BANKS]; 139 const u32 mem_retst_mask[PWRDM_MAX_MEM_BANKS]; 140 141 #ifdef CONFIG_PM_DEBUG 142 s64 timer; 143 s64 state_timer[PWRDM_MAX_PWRSTS]; 144 #endif 145 }; 146 147 /** 148 * struct pwrdm_ops - Arch specific function implementations 149 * @pwrdm_set_next_pwrst: Set the target power state for a pd 150 * @pwrdm_read_next_pwrst: Read the target power state set for a pd 151 * @pwrdm_read_pwrst: Read the current power state of a pd 152 * @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd 153 * @pwrdm_set_logic_retst: Set the logic state in RET for a pd 154 * @pwrdm_set_mem_onst: Set the Memory state in ON for a pd 155 * @pwrdm_set_mem_retst: Set the Memory state in RET for a pd 156 * @pwrdm_read_logic_pwrst: Read the current logic state of a pd 157 * @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd 158 * @pwrdm_read_logic_retst: Read the logic state in RET for a pd 159 * @pwrdm_read_mem_pwrst: Read the current memory state of a pd 160 * @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd 161 * @pwrdm_read_mem_retst: Read the memory state in RET for a pd 162 * @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd 163 * @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd 164 * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd 165 * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep 166 * @pwrdm_wait_transition: Wait for a pd state transition to complete 167 */ 168 struct pwrdm_ops { 169 int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst); 170 int (*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm); 171 int (*pwrdm_read_pwrst)(struct powerdomain *pwrdm); 172 int (*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm); 173 int (*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst); 174 int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst); 175 int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst); 176 int (*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm); 177 int (*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm); 178 int (*pwrdm_read_logic_retst)(struct powerdomain *pwrdm); 179 int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank); 180 int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank); 181 int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank); 182 int (*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm); 183 int (*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm); 184 int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm); 185 int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm); 186 int (*pwrdm_wait_transition)(struct powerdomain *pwrdm); 187 }; 188 189 int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs); 190 int pwrdm_register_pwrdms(struct powerdomain **pwrdm_list); 191 int pwrdm_complete_init(void); 192 193 struct powerdomain *pwrdm_lookup(const char *name); 194 195 int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user), 196 void *user); 197 int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user), 198 void *user); 199 200 int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); 201 int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); 202 int pwrdm_for_each_clkdm(struct powerdomain *pwrdm, 203 int (*fn)(struct powerdomain *pwrdm, 204 struct clockdomain *clkdm)); 205 struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm); 206 207 int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm); 208 209 int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst); 210 int pwrdm_read_next_pwrst(struct powerdomain *pwrdm); 211 int pwrdm_read_pwrst(struct powerdomain *pwrdm); 212 int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm); 213 int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm); 214 215 int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst); 216 int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); 217 int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); 218 219 int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm); 220 int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm); 221 int pwrdm_read_logic_retst(struct powerdomain *pwrdm); 222 int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank); 223 int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank); 224 int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank); 225 226 int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm); 227 int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm); 228 bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm); 229 230 int pwrdm_wait_transition(struct powerdomain *pwrdm); 231 232 int pwrdm_state_switch(struct powerdomain *pwrdm); 233 int pwrdm_pre_transition(struct powerdomain *pwrdm); 234 int pwrdm_post_transition(struct powerdomain *pwrdm); 235 int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm); 236 int pwrdm_get_context_loss_count(struct powerdomain *pwrdm); 237 bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm); 238 239 extern void omap242x_powerdomains_init(void); 240 extern void omap243x_powerdomains_init(void); 241 extern void omap3xxx_powerdomains_init(void); 242 extern void am33xx_powerdomains_init(void); 243 extern void omap44xx_powerdomains_init(void); 244 245 extern struct pwrdm_ops omap2_pwrdm_operations; 246 extern struct pwrdm_ops omap3_pwrdm_operations; 247 extern struct pwrdm_ops am33xx_pwrdm_operations; 248 extern struct pwrdm_ops omap4_pwrdm_operations; 249 250 /* Common Internal functions used across OMAP rev's */ 251 extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank); 252 extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank); 253 extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank); 254 255 extern struct powerdomain wkup_omap2_pwrdm; 256 extern struct powerdomain gfx_omap2_pwrdm; 257 258 259 #endif 260