1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Common powerdomain framework functions 4 * 5 * Copyright (C) 2010-2011 Texas Instruments, Inc. 6 * Copyright (C) 2010 Nokia Corporation 7 * 8 * Derived from mach-omap2/powerdomain.c written by Paul Walmsley 9 */ 10 11 #include <linux/errno.h> 12 #include <linux/kernel.h> 13 #include <linux/bug.h> 14 #include "pm.h" 15 #include "cm.h" 16 #include "cm-regbits-34xx.h" 17 #include "prm-regbits-34xx.h" 18 #include "prm-regbits-44xx.h" 19 20 /* 21 * OMAP3 and OMAP4 specific register bit initialisations 22 * Notice that the names here are not according to each power 23 * domain but the bit mapping used applies to all of them 24 */ 25 /* OMAP3 and OMAP4 Memory Onstate Masks (common across all power domains) */ 26 #define OMAP_MEM0_ONSTATE_MASK OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK 27 #define OMAP_MEM1_ONSTATE_MASK OMAP3430_L1FLATMEMONSTATE_MASK 28 #define OMAP_MEM2_ONSTATE_MASK OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK 29 #define OMAP_MEM3_ONSTATE_MASK OMAP3430_L2FLATMEMONSTATE_MASK 30 #define OMAP_MEM4_ONSTATE_MASK OMAP4430_OCP_NRET_BANK_ONSTATE_MASK 31 32 /* OMAP3 and OMAP4 Memory Retstate Masks (common across all power domains) */ 33 #define OMAP_MEM0_RETSTATE_MASK OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK 34 #define OMAP_MEM1_RETSTATE_MASK OMAP3430_L1FLATMEMRETSTATE_MASK 35 #define OMAP_MEM2_RETSTATE_MASK OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK 36 #define OMAP_MEM3_RETSTATE_MASK OMAP3430_L2FLATMEMRETSTATE_MASK 37 #define OMAP_MEM4_RETSTATE_MASK OMAP4430_OCP_NRET_BANK_RETSTATE_MASK 38 39 /* OMAP3 and OMAP4 Memory Status bits */ 40 #define OMAP_MEM0_STATEST_MASK OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK 41 #define OMAP_MEM1_STATEST_MASK OMAP3430_L1FLATMEMSTATEST_MASK 42 #define OMAP_MEM2_STATEST_MASK OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK 43 #define OMAP_MEM3_STATEST_MASK OMAP3430_L2FLATMEMSTATEST_MASK 44 #define OMAP_MEM4_STATEST_MASK OMAP4430_OCP_NRET_BANK_STATEST_MASK 45 46 /* Common Internal functions used across OMAP rev's*/ omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank)47u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank) 48 { 49 switch (bank) { 50 case 0: 51 return OMAP_MEM0_ONSTATE_MASK; 52 case 1: 53 return OMAP_MEM1_ONSTATE_MASK; 54 case 2: 55 return OMAP_MEM2_ONSTATE_MASK; 56 case 3: 57 return OMAP_MEM3_ONSTATE_MASK; 58 case 4: 59 return OMAP_MEM4_ONSTATE_MASK; 60 default: 61 WARN_ON(1); /* should never happen */ 62 return -EEXIST; 63 } 64 return 0; 65 } 66 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank)67u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank) 68 { 69 switch (bank) { 70 case 0: 71 return OMAP_MEM0_RETSTATE_MASK; 72 case 1: 73 return OMAP_MEM1_RETSTATE_MASK; 74 case 2: 75 return OMAP_MEM2_RETSTATE_MASK; 76 case 3: 77 return OMAP_MEM3_RETSTATE_MASK; 78 case 4: 79 return OMAP_MEM4_RETSTATE_MASK; 80 default: 81 WARN_ON(1); /* should never happen */ 82 return -EEXIST; 83 } 84 return 0; 85 } 86 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank)87u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank) 88 { 89 switch (bank) { 90 case 0: 91 return OMAP_MEM0_STATEST_MASK; 92 case 1: 93 return OMAP_MEM1_STATEST_MASK; 94 case 2: 95 return OMAP_MEM2_STATEST_MASK; 96 case 3: 97 return OMAP_MEM3_STATEST_MASK; 98 case 4: 99 return OMAP_MEM4_STATEST_MASK; 100 default: 101 WARN_ON(1); /* should never happen */ 102 return -EEXIST; 103 } 104 return 0; 105 } 106 107