1 /* 2 * OMAP3 Power Management Routines 3 * 4 * Copyright (C) 2006-2008 Nokia Corporation 5 * Tony Lindgren <tony@atomide.com> 6 * Jouni Hogander 7 * 8 * Copyright (C) 2005 Texas Instruments, Inc. 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * 11 * Based on pm.c for omap1 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License version 2 as 15 * published by the Free Software Foundation. 16 */ 17 18 #include <linux/pm.h> 19 #include <linux/suspend.h> 20 #include <linux/interrupt.h> 21 #include <linux/module.h> 22 #include <linux/list.h> 23 #include <linux/err.h> 24 #include <linux/gpio.h> 25 26 #include <mach/sram.h> 27 #include <mach/clockdomain.h> 28 #include <mach/powerdomain.h> 29 #include <mach/control.h> 30 #include <mach/serial.h> 31 32 #include "cm.h" 33 #include "cm-regbits-34xx.h" 34 #include "prm-regbits-34xx.h" 35 36 #include "prm.h" 37 #include "pm.h" 38 39 struct power_state { 40 struct powerdomain *pwrdm; 41 u32 next_state; 42 #ifdef CONFIG_SUSPEND 43 u32 saved_state; 44 #endif 45 struct list_head node; 46 }; 47 48 static LIST_HEAD(pwrst_list); 49 50 static void (*_omap_sram_idle)(u32 *addr, int save_state); 51 52 static struct powerdomain *mpu_pwrdm; 53 54 /* PRCM Interrupt Handler for wakeups */ 55 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) 56 { 57 u32 wkst, irqstatus_mpu; 58 u32 fclk, iclk; 59 60 /* WKUP */ 61 wkst = prm_read_mod_reg(WKUP_MOD, PM_WKST); 62 if (wkst) { 63 iclk = cm_read_mod_reg(WKUP_MOD, CM_ICLKEN); 64 fclk = cm_read_mod_reg(WKUP_MOD, CM_FCLKEN); 65 cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_ICLKEN); 66 cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_FCLKEN); 67 prm_write_mod_reg(wkst, WKUP_MOD, PM_WKST); 68 while (prm_read_mod_reg(WKUP_MOD, PM_WKST)) 69 cpu_relax(); 70 cm_write_mod_reg(iclk, WKUP_MOD, CM_ICLKEN); 71 cm_write_mod_reg(fclk, WKUP_MOD, CM_FCLKEN); 72 } 73 74 /* CORE */ 75 wkst = prm_read_mod_reg(CORE_MOD, PM_WKST1); 76 if (wkst) { 77 iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN1); 78 fclk = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); 79 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN1); 80 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_FCLKEN1); 81 prm_write_mod_reg(wkst, CORE_MOD, PM_WKST1); 82 while (prm_read_mod_reg(CORE_MOD, PM_WKST1)) 83 cpu_relax(); 84 cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN1); 85 cm_write_mod_reg(fclk, CORE_MOD, CM_FCLKEN1); 86 } 87 wkst = prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3); 88 if (wkst) { 89 iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN3); 90 fclk = cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3); 91 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN3); 92 cm_set_mod_reg_bits(wkst, CORE_MOD, OMAP3430ES2_CM_FCLKEN3); 93 prm_write_mod_reg(wkst, CORE_MOD, OMAP3430ES2_PM_WKST3); 94 while (prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3)) 95 cpu_relax(); 96 cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN3); 97 cm_write_mod_reg(fclk, CORE_MOD, OMAP3430ES2_CM_FCLKEN3); 98 } 99 100 /* PER */ 101 wkst = prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST); 102 if (wkst) { 103 iclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN); 104 fclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN); 105 cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_ICLKEN); 106 cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_FCLKEN); 107 prm_write_mod_reg(wkst, OMAP3430_PER_MOD, PM_WKST); 108 while (prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST)) 109 cpu_relax(); 110 cm_write_mod_reg(iclk, OMAP3430_PER_MOD, CM_ICLKEN); 111 cm_write_mod_reg(fclk, OMAP3430_PER_MOD, CM_FCLKEN); 112 } 113 114 if (omap_rev() > OMAP3430_REV_ES1_0) { 115 /* USBHOST */ 116 wkst = prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKST); 117 if (wkst) { 118 iclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, 119 CM_ICLKEN); 120 fclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, 121 CM_FCLKEN); 122 cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD, 123 CM_ICLKEN); 124 cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD, 125 CM_FCLKEN); 126 prm_write_mod_reg(wkst, OMAP3430ES2_USBHOST_MOD, 127 PM_WKST); 128 while (prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, 129 PM_WKST)) 130 cpu_relax(); 131 cm_write_mod_reg(iclk, OMAP3430ES2_USBHOST_MOD, 132 CM_ICLKEN); 133 cm_write_mod_reg(fclk, OMAP3430ES2_USBHOST_MOD, 134 CM_FCLKEN); 135 } 136 } 137 138 irqstatus_mpu = prm_read_mod_reg(OCP_MOD, 139 OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 140 prm_write_mod_reg(irqstatus_mpu, OCP_MOD, 141 OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 142 143 while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET)) 144 cpu_relax(); 145 146 return IRQ_HANDLED; 147 } 148 149 static void omap_sram_idle(void) 150 { 151 /* Variable to tell what needs to be saved and restored 152 * in omap_sram_idle*/ 153 /* save_state = 0 => Nothing to save and restored */ 154 /* save_state = 1 => Only L1 and logic lost */ 155 /* save_state = 2 => Only L2 lost */ 156 /* save_state = 3 => L1, L2 and logic lost */ 157 int save_state = 0, mpu_next_state; 158 159 if (!_omap_sram_idle) 160 return; 161 162 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 163 switch (mpu_next_state) { 164 case PWRDM_POWER_RET: 165 /* No need to save context */ 166 save_state = 0; 167 break; 168 default: 169 /* Invalid state */ 170 printk(KERN_ERR "Invalid mpu state in sram_idle\n"); 171 return; 172 } 173 pwrdm_pre_transition(); 174 175 omap2_gpio_prepare_for_retention(); 176 omap_uart_prepare_idle(0); 177 omap_uart_prepare_idle(1); 178 omap_uart_prepare_idle(2); 179 180 _omap_sram_idle(NULL, save_state); 181 cpu_init(); 182 183 omap_uart_resume_idle(2); 184 omap_uart_resume_idle(1); 185 omap_uart_resume_idle(0); 186 omap2_gpio_resume_after_retention(); 187 188 pwrdm_post_transition(); 189 190 } 191 192 /* 193 * Check if functional clocks are enabled before entering 194 * sleep. This function could be behind CONFIG_PM_DEBUG 195 * when all drivers are configuring their sysconfig registers 196 * properly and using their clocks properly. 197 */ 198 static int omap3_fclks_active(void) 199 { 200 u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0, 201 fck_cam = 0, fck_per = 0, fck_usbhost = 0; 202 203 fck_core1 = cm_read_mod_reg(CORE_MOD, 204 CM_FCLKEN1); 205 if (omap_rev() > OMAP3430_REV_ES1_0) { 206 fck_core3 = cm_read_mod_reg(CORE_MOD, 207 OMAP3430ES2_CM_FCLKEN3); 208 fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD, 209 CM_FCLKEN); 210 fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, 211 CM_FCLKEN); 212 } else 213 fck_sgx = cm_read_mod_reg(GFX_MOD, 214 OMAP3430ES2_CM_FCLKEN3); 215 fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD, 216 CM_FCLKEN); 217 fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD, 218 CM_FCLKEN); 219 fck_per = cm_read_mod_reg(OMAP3430_PER_MOD, 220 CM_FCLKEN); 221 222 /* Ignore UART clocks. These are handled by UART core (serial.c) */ 223 fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2); 224 fck_per &= ~OMAP3430_EN_UART3; 225 226 if (fck_core1 | fck_core3 | fck_sgx | fck_dss | 227 fck_cam | fck_per | fck_usbhost) 228 return 1; 229 return 0; 230 } 231 232 static int omap3_can_sleep(void) 233 { 234 if (!omap_uart_can_sleep()) 235 return 0; 236 if (omap3_fclks_active()) 237 return 0; 238 return 1; 239 } 240 241 /* This sets pwrdm state (other than mpu & core. Currently only ON & 242 * RET are supported. Function is assuming that clkdm doesn't have 243 * hw_sup mode enabled. */ 244 static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state) 245 { 246 u32 cur_state; 247 int sleep_switch = 0; 248 int ret = 0; 249 250 if (pwrdm == NULL || IS_ERR(pwrdm)) 251 return -EINVAL; 252 253 while (!(pwrdm->pwrsts & (1 << state))) { 254 if (state == PWRDM_POWER_OFF) 255 return ret; 256 state--; 257 } 258 259 cur_state = pwrdm_read_next_pwrst(pwrdm); 260 if (cur_state == state) 261 return ret; 262 263 if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) { 264 omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); 265 sleep_switch = 1; 266 pwrdm_wait_transition(pwrdm); 267 } 268 269 ret = pwrdm_set_next_pwrst(pwrdm, state); 270 if (ret) { 271 printk(KERN_ERR "Unable to set state of powerdomain: %s\n", 272 pwrdm->name); 273 goto err; 274 } 275 276 if (sleep_switch) { 277 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); 278 pwrdm_wait_transition(pwrdm); 279 pwrdm_state_switch(pwrdm); 280 } 281 282 err: 283 return ret; 284 } 285 286 static void omap3_pm_idle(void) 287 { 288 local_irq_disable(); 289 local_fiq_disable(); 290 291 if (!omap3_can_sleep()) 292 goto out; 293 294 if (omap_irq_pending()) 295 goto out; 296 297 omap_sram_idle(); 298 299 out: 300 local_fiq_enable(); 301 local_irq_enable(); 302 } 303 304 #ifdef CONFIG_SUSPEND 305 static suspend_state_t suspend_state; 306 307 static int omap3_pm_prepare(void) 308 { 309 disable_hlt(); 310 return 0; 311 } 312 313 static int omap3_pm_suspend(void) 314 { 315 struct power_state *pwrst; 316 int state, ret = 0; 317 318 /* Read current next_pwrsts */ 319 list_for_each_entry(pwrst, &pwrst_list, node) 320 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 321 /* Set ones wanted by suspend */ 322 list_for_each_entry(pwrst, &pwrst_list, node) { 323 if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) 324 goto restore; 325 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) 326 goto restore; 327 } 328 329 omap_uart_prepare_suspend(); 330 omap_sram_idle(); 331 332 restore: 333 /* Restore next_pwrsts */ 334 list_for_each_entry(pwrst, &pwrst_list, node) { 335 state = pwrdm_read_prev_pwrst(pwrst->pwrdm); 336 if (state > pwrst->next_state) { 337 printk(KERN_INFO "Powerdomain (%s) didn't enter " 338 "target state %d\n", 339 pwrst->pwrdm->name, pwrst->next_state); 340 ret = -1; 341 } 342 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); 343 } 344 if (ret) 345 printk(KERN_ERR "Could not enter target state in pm_suspend\n"); 346 else 347 printk(KERN_INFO "Successfully put all powerdomains " 348 "to target state\n"); 349 350 return ret; 351 } 352 353 static int omap3_pm_enter(suspend_state_t unused) 354 { 355 int ret = 0; 356 357 switch (suspend_state) { 358 case PM_SUSPEND_STANDBY: 359 case PM_SUSPEND_MEM: 360 ret = omap3_pm_suspend(); 361 break; 362 default: 363 ret = -EINVAL; 364 } 365 366 return ret; 367 } 368 369 static void omap3_pm_finish(void) 370 { 371 enable_hlt(); 372 } 373 374 /* Hooks to enable / disable UART interrupts during suspend */ 375 static int omap3_pm_begin(suspend_state_t state) 376 { 377 suspend_state = state; 378 omap_uart_enable_irqs(0); 379 return 0; 380 } 381 382 static void omap3_pm_end(void) 383 { 384 suspend_state = PM_SUSPEND_ON; 385 omap_uart_enable_irqs(1); 386 return; 387 } 388 389 static struct platform_suspend_ops omap_pm_ops = { 390 .begin = omap3_pm_begin, 391 .end = omap3_pm_end, 392 .prepare = omap3_pm_prepare, 393 .enter = omap3_pm_enter, 394 .finish = omap3_pm_finish, 395 .valid = suspend_valid_only_mem, 396 }; 397 #endif /* CONFIG_SUSPEND */ 398 399 400 /** 401 * omap3_iva_idle(): ensure IVA is in idle so it can be put into 402 * retention 403 * 404 * In cases where IVA2 is activated by bootcode, it may prevent 405 * full-chip retention or off-mode because it is not idle. This 406 * function forces the IVA2 into idle state so it can go 407 * into retention/off and thus allow full-chip retention/off. 408 * 409 **/ 410 static void __init omap3_iva_idle(void) 411 { 412 /* ensure IVA2 clock is disabled */ 413 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 414 415 /* if no clock activity, nothing else to do */ 416 if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & 417 OMAP3430_CLKACTIVITY_IVA2_MASK)) 418 return; 419 420 /* Reset IVA2 */ 421 prm_write_mod_reg(OMAP3430_RST1_IVA2 | 422 OMAP3430_RST2_IVA2 | 423 OMAP3430_RST3_IVA2, 424 OMAP3430_IVA2_MOD, RM_RSTCTRL); 425 426 /* Enable IVA2 clock */ 427 cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2, 428 OMAP3430_IVA2_MOD, CM_FCLKEN); 429 430 /* Set IVA2 boot mode to 'idle' */ 431 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, 432 OMAP343X_CONTROL_IVA2_BOOTMOD); 433 434 /* Un-reset IVA2 */ 435 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL); 436 437 /* Disable IVA2 clock */ 438 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 439 440 /* Reset IVA2 */ 441 prm_write_mod_reg(OMAP3430_RST1_IVA2 | 442 OMAP3430_RST2_IVA2 | 443 OMAP3430_RST3_IVA2, 444 OMAP3430_IVA2_MOD, RM_RSTCTRL); 445 } 446 447 static void __init omap3_d2d_idle(void) 448 { 449 u16 mask, padconf; 450 451 /* In a stand alone OMAP3430 where there is not a stacked 452 * modem for the D2D Idle Ack and D2D MStandby must be pulled 453 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and 454 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ 455 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ 456 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); 457 padconf |= mask; 458 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); 459 460 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); 461 padconf |= mask; 462 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 463 464 /* reset modem */ 465 prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON | 466 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST, 467 CORE_MOD, RM_RSTCTRL); 468 prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL); 469 } 470 471 static void __init prcm_setup_regs(void) 472 { 473 /* XXX Reset all wkdeps. This should be done when initializing 474 * powerdomains */ 475 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); 476 prm_write_mod_reg(0, MPU_MOD, PM_WKDEP); 477 prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP); 478 prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP); 479 prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP); 480 prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP); 481 if (omap_rev() > OMAP3430_REV_ES1_0) { 482 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP); 483 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP); 484 } else 485 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); 486 487 /* 488 * Enable interface clock autoidle for all modules. 489 * Note that in the long run this should be done by clockfw 490 */ 491 cm_write_mod_reg( 492 OMAP3430_AUTO_MODEM | 493 OMAP3430ES2_AUTO_MMC3 | 494 OMAP3430ES2_AUTO_ICR | 495 OMAP3430_AUTO_AES2 | 496 OMAP3430_AUTO_SHA12 | 497 OMAP3430_AUTO_DES2 | 498 OMAP3430_AUTO_MMC2 | 499 OMAP3430_AUTO_MMC1 | 500 OMAP3430_AUTO_MSPRO | 501 OMAP3430_AUTO_HDQ | 502 OMAP3430_AUTO_MCSPI4 | 503 OMAP3430_AUTO_MCSPI3 | 504 OMAP3430_AUTO_MCSPI2 | 505 OMAP3430_AUTO_MCSPI1 | 506 OMAP3430_AUTO_I2C3 | 507 OMAP3430_AUTO_I2C2 | 508 OMAP3430_AUTO_I2C1 | 509 OMAP3430_AUTO_UART2 | 510 OMAP3430_AUTO_UART1 | 511 OMAP3430_AUTO_GPT11 | 512 OMAP3430_AUTO_GPT10 | 513 OMAP3430_AUTO_MCBSP5 | 514 OMAP3430_AUTO_MCBSP1 | 515 OMAP3430ES1_AUTO_FAC | /* This is es1 only */ 516 OMAP3430_AUTO_MAILBOXES | 517 OMAP3430_AUTO_OMAPCTRL | 518 OMAP3430ES1_AUTO_FSHOSTUSB | 519 OMAP3430_AUTO_HSOTGUSB | 520 OMAP3430_AUTO_SAD2D | 521 OMAP3430_AUTO_SSI, 522 CORE_MOD, CM_AUTOIDLE1); 523 524 cm_write_mod_reg( 525 OMAP3430_AUTO_PKA | 526 OMAP3430_AUTO_AES1 | 527 OMAP3430_AUTO_RNG | 528 OMAP3430_AUTO_SHA11 | 529 OMAP3430_AUTO_DES1, 530 CORE_MOD, CM_AUTOIDLE2); 531 532 if (omap_rev() > OMAP3430_REV_ES1_0) { 533 cm_write_mod_reg( 534 OMAP3430_AUTO_MAD2D | 535 OMAP3430ES2_AUTO_USBTLL, 536 CORE_MOD, CM_AUTOIDLE3); 537 } 538 539 cm_write_mod_reg( 540 OMAP3430_AUTO_WDT2 | 541 OMAP3430_AUTO_WDT1 | 542 OMAP3430_AUTO_GPIO1 | 543 OMAP3430_AUTO_32KSYNC | 544 OMAP3430_AUTO_GPT12 | 545 OMAP3430_AUTO_GPT1 , 546 WKUP_MOD, CM_AUTOIDLE); 547 548 cm_write_mod_reg( 549 OMAP3430_AUTO_DSS, 550 OMAP3430_DSS_MOD, 551 CM_AUTOIDLE); 552 553 cm_write_mod_reg( 554 OMAP3430_AUTO_CAM, 555 OMAP3430_CAM_MOD, 556 CM_AUTOIDLE); 557 558 cm_write_mod_reg( 559 OMAP3430_AUTO_GPIO6 | 560 OMAP3430_AUTO_GPIO5 | 561 OMAP3430_AUTO_GPIO4 | 562 OMAP3430_AUTO_GPIO3 | 563 OMAP3430_AUTO_GPIO2 | 564 OMAP3430_AUTO_WDT3 | 565 OMAP3430_AUTO_UART3 | 566 OMAP3430_AUTO_GPT9 | 567 OMAP3430_AUTO_GPT8 | 568 OMAP3430_AUTO_GPT7 | 569 OMAP3430_AUTO_GPT6 | 570 OMAP3430_AUTO_GPT5 | 571 OMAP3430_AUTO_GPT4 | 572 OMAP3430_AUTO_GPT3 | 573 OMAP3430_AUTO_GPT2 | 574 OMAP3430_AUTO_MCBSP4 | 575 OMAP3430_AUTO_MCBSP3 | 576 OMAP3430_AUTO_MCBSP2, 577 OMAP3430_PER_MOD, 578 CM_AUTOIDLE); 579 580 if (omap_rev() > OMAP3430_REV_ES1_0) { 581 cm_write_mod_reg( 582 OMAP3430ES2_AUTO_USBHOST, 583 OMAP3430ES2_USBHOST_MOD, 584 CM_AUTOIDLE); 585 } 586 587 /* 588 * Set all plls to autoidle. This is needed until autoidle is 589 * enabled by clockfw 590 */ 591 cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, 592 OMAP3430_IVA2_MOD, CM_AUTOIDLE2); 593 cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT, 594 MPU_MOD, 595 CM_AUTOIDLE2); 596 cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | 597 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT), 598 PLL_MOD, 599 CM_AUTOIDLE); 600 cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, 601 PLL_MOD, 602 CM_AUTOIDLE2); 603 604 /* 605 * Enable control of expternal oscillator through 606 * sys_clkreq. In the long run clock framework should 607 * take care of this. 608 */ 609 prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 610 1 << OMAP_AUTOEXTCLKMODE_SHIFT, 611 OMAP3430_GR_MOD, 612 OMAP3_PRM_CLKSRC_CTRL_OFFSET); 613 614 /* setup wakup source */ 615 prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 | 616 OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12, 617 WKUP_MOD, PM_WKEN); 618 /* No need to write EN_IO, that is always enabled */ 619 prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 | 620 OMAP3430_EN_GPT12, 621 WKUP_MOD, OMAP3430_PM_MPUGRPSEL); 622 /* For some reason IO doesn't generate wakeup event even if 623 * it is selected to mpu wakeup goup */ 624 prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN, 625 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); 626 627 /* Don't attach IVA interrupts */ 628 prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 629 prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 630 prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 631 prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); 632 633 /* Clear any pending 'reset' flags */ 634 prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST); 635 prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST); 636 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST); 637 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST); 638 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST); 639 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST); 640 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST); 641 642 /* Clear any pending PRCM interrupts */ 643 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 644 645 /* Don't attach IVA interrupts */ 646 prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 647 prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 648 prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 649 prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); 650 651 /* Clear any pending 'reset' flags */ 652 prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST); 653 prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST); 654 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST); 655 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST); 656 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST); 657 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST); 658 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST); 659 660 /* Clear any pending PRCM interrupts */ 661 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 662 663 omap3_iva_idle(); 664 omap3_d2d_idle(); 665 } 666 667 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) 668 { 669 struct power_state *pwrst; 670 671 list_for_each_entry(pwrst, &pwrst_list, node) { 672 if (pwrst->pwrdm == pwrdm) 673 return pwrst->next_state; 674 } 675 return -EINVAL; 676 } 677 678 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) 679 { 680 struct power_state *pwrst; 681 682 list_for_each_entry(pwrst, &pwrst_list, node) { 683 if (pwrst->pwrdm == pwrdm) { 684 pwrst->next_state = state; 685 return 0; 686 } 687 } 688 return -EINVAL; 689 } 690 691 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) 692 { 693 struct power_state *pwrst; 694 695 if (!pwrdm->pwrsts) 696 return 0; 697 698 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); 699 if (!pwrst) 700 return -ENOMEM; 701 pwrst->pwrdm = pwrdm; 702 pwrst->next_state = PWRDM_POWER_RET; 703 list_add(&pwrst->node, &pwrst_list); 704 705 if (pwrdm_has_hdwr_sar(pwrdm)) 706 pwrdm_enable_hdwr_sar(pwrdm); 707 708 return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 709 } 710 711 /* 712 * Enable hw supervised mode for all clockdomains if it's 713 * supported. Initiate sleep transition for other clockdomains, if 714 * they are not used 715 */ 716 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) 717 { 718 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) 719 omap2_clkdm_allow_idle(clkdm); 720 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && 721 atomic_read(&clkdm->usecount) == 0) 722 omap2_clkdm_sleep(clkdm); 723 return 0; 724 } 725 726 static int __init omap3_pm_init(void) 727 { 728 struct power_state *pwrst, *tmp; 729 int ret; 730 731 if (!cpu_is_omap34xx()) 732 return -ENODEV; 733 734 printk(KERN_ERR "Power Management for TI OMAP3.\n"); 735 736 /* XXX prcm_setup_regs needs to be before enabling hw 737 * supervised mode for powerdomains */ 738 prcm_setup_regs(); 739 740 ret = request_irq(INT_34XX_PRCM_MPU_IRQ, 741 (irq_handler_t)prcm_interrupt_handler, 742 IRQF_DISABLED, "prcm", NULL); 743 if (ret) { 744 printk(KERN_ERR "request_irq failed to register for 0x%x\n", 745 INT_34XX_PRCM_MPU_IRQ); 746 goto err1; 747 } 748 749 ret = pwrdm_for_each(pwrdms_setup, NULL); 750 if (ret) { 751 printk(KERN_ERR "Failed to setup powerdomains\n"); 752 goto err2; 753 } 754 755 (void) clkdm_for_each(clkdms_setup, NULL); 756 757 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); 758 if (mpu_pwrdm == NULL) { 759 printk(KERN_ERR "Failed to get mpu_pwrdm\n"); 760 goto err2; 761 } 762 763 _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend, 764 omap34xx_cpu_suspend_sz); 765 766 #ifdef CONFIG_SUSPEND 767 suspend_set_ops(&omap_pm_ops); 768 #endif /* CONFIG_SUSPEND */ 769 770 pm_idle = omap3_pm_idle; 771 772 err1: 773 return ret; 774 err2: 775 free_irq(INT_34XX_PRCM_MPU_IRQ, NULL); 776 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { 777 list_del(&pwrst->node); 778 kfree(pwrst); 779 } 780 return ret; 781 } 782 783 late_initcall(omap3_pm_init); 784