1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * OMAP3 Power Management Routines 4 * 5 * Copyright (C) 2006-2008 Nokia Corporation 6 * Tony Lindgren <tony@atomide.com> 7 * Jouni Hogander 8 * 9 * Copyright (C) 2007 Texas Instruments, Inc. 10 * Rajendra Nayak <rnayak@ti.com> 11 * 12 * Copyright (C) 2005 Texas Instruments, Inc. 13 * Richard Woodruff <r-woodruff2@ti.com> 14 * 15 * Based on pm.c for omap1 16 */ 17 18 #include <linux/cpu_pm.h> 19 #include <linux/pm.h> 20 #include <linux/suspend.h> 21 #include <linux/interrupt.h> 22 #include <linux/module.h> 23 #include <linux/list.h> 24 #include <linux/err.h> 25 #include <linux/clk.h> 26 #include <linux/delay.h> 27 #include <linux/slab.h> 28 #include <linux/of.h> 29 #include <linux/omap-gpmc.h> 30 31 #include <trace/events/power.h> 32 33 #include <asm/fncpy.h> 34 #include <asm/suspend.h> 35 #include <asm/system_misc.h> 36 37 #include "clockdomain.h" 38 #include "powerdomain.h" 39 #include "soc.h" 40 #include "common.h" 41 #include "cm3xxx.h" 42 #include "cm-regbits-34xx.h" 43 #include "prm-regbits-34xx.h" 44 #include "prm3xxx.h" 45 #include "pm.h" 46 #include "sdrc.h" 47 #include "omap-secure.h" 48 #include "sram.h" 49 #include "control.h" 50 #include "vc.h" 51 52 /* pm34xx errata defined in pm.h */ 53 u16 pm34xx_errata; 54 55 struct power_state { 56 struct powerdomain *pwrdm; 57 u32 next_state; 58 #ifdef CONFIG_SUSPEND 59 u32 saved_state; 60 #endif 61 struct list_head node; 62 }; 63 64 static LIST_HEAD(pwrst_list); 65 66 void (*omap3_do_wfi_sram)(void); 67 68 static struct powerdomain *mpu_pwrdm, *neon_pwrdm; 69 static struct powerdomain *core_pwrdm, *per_pwrdm; 70 71 static void omap3_core_save_context(void) 72 { 73 omap3_ctrl_save_padconf(); 74 75 /* 76 * Force write last pad into memory, as this can fail in some 77 * cases according to errata 1.157, 1.185 78 */ 79 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), 80 OMAP343X_CONTROL_MEM_WKUP + 0x2a0); 81 82 /* Save the Interrupt controller context */ 83 omap_intc_save_context(); 84 /* Save the GPMC context */ 85 omap3_gpmc_save_context(); 86 /* Save the system control module context, padconf already save above*/ 87 omap3_control_save_context(); 88 } 89 90 static void omap3_core_restore_context(void) 91 { 92 /* Restore the control module context, padconf restored by h/w */ 93 omap3_control_restore_context(); 94 /* Restore the GPMC context */ 95 omap3_gpmc_restore_context(); 96 /* Restore the interrupt controller context */ 97 omap_intc_restore_context(); 98 } 99 100 /* 101 * FIXME: This function should be called before entering off-mode after 102 * OMAP3 secure services have been accessed. Currently it is only called 103 * once during boot sequence, but this works as we are not using secure 104 * services. 105 */ 106 static void omap3_save_secure_ram_context(void) 107 { 108 u32 ret; 109 int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 110 111 if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 112 /* 113 * MPU next state must be set to POWER_ON temporarily, 114 * otherwise the WFI executed inside the ROM code 115 * will hang the system. 116 */ 117 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); 118 ret = omap3_save_secure_ram(omap3_secure_ram_storage, 119 OMAP3_SAVE_SECURE_RAM_SZ); 120 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state); 121 /* Following is for error tracking, it should not happen */ 122 if (ret) { 123 pr_err("save_secure_sram() returns %08x\n", ret); 124 while (1) 125 ; 126 } 127 } 128 } 129 130 static irqreturn_t _prcm_int_handle_io(int irq, void *unused) 131 { 132 int c; 133 134 c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, OMAP3430_ST_IO_MASK | 135 OMAP3430_ST_IO_CHAIN_MASK); 136 137 return c ? IRQ_HANDLED : IRQ_NONE; 138 } 139 140 static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused) 141 { 142 int c; 143 144 /* 145 * Clear all except ST_IO and ST_IO_CHAIN for wkup module, 146 * these are handled in a separate handler to avoid acking 147 * IO events before parsing in mux code 148 */ 149 c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, ~(OMAP3430_ST_IO_MASK | 150 OMAP3430_ST_IO_CHAIN_MASK)); 151 c += omap_prm_clear_mod_irqs(CORE_MOD, 1, ~0); 152 c += omap_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, ~0); 153 if (omap_rev() > OMAP3430_REV_ES1_0) { 154 c += omap_prm_clear_mod_irqs(CORE_MOD, 3, ~0); 155 c += omap_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, ~0); 156 } 157 158 return c ? IRQ_HANDLED : IRQ_NONE; 159 } 160 161 static void omap34xx_save_context(u32 *save) 162 { 163 u32 val; 164 165 /* Read Auxiliary Control Register */ 166 asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val)); 167 *save++ = 1; 168 *save++ = val; 169 170 /* Read L2 AUX ctrl register */ 171 asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); 172 *save++ = 1; 173 *save++ = val; 174 } 175 176 static int omap34xx_do_sram_idle(unsigned long save_state) 177 { 178 omap34xx_cpu_suspend(save_state); 179 return 0; 180 } 181 182 void omap_sram_idle(void) 183 { 184 /* Variable to tell what needs to be saved and restored 185 * in omap_sram_idle*/ 186 /* save_state = 0 => Nothing to save and restored */ 187 /* save_state = 1 => Only L1 and logic lost */ 188 /* save_state = 2 => Only L2 lost */ 189 /* save_state = 3 => L1, L2 and logic lost */ 190 int save_state = 0; 191 int mpu_next_state = PWRDM_POWER_ON; 192 int per_next_state = PWRDM_POWER_ON; 193 int core_next_state = PWRDM_POWER_ON; 194 u32 sdrc_pwr = 0; 195 int error; 196 197 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 198 switch (mpu_next_state) { 199 case PWRDM_POWER_ON: 200 case PWRDM_POWER_RET: 201 /* No need to save context */ 202 save_state = 0; 203 break; 204 case PWRDM_POWER_OFF: 205 save_state = 3; 206 break; 207 default: 208 /* Invalid state */ 209 pr_err("Invalid mpu state in sram_idle\n"); 210 return; 211 } 212 213 /* NEON control */ 214 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) 215 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); 216 217 /* Enable IO-PAD and IO-CHAIN wakeups */ 218 per_next_state = pwrdm_read_next_pwrst(per_pwrdm); 219 core_next_state = pwrdm_read_next_pwrst(core_pwrdm); 220 221 pwrdm_pre_transition(NULL); 222 223 /* PER */ 224 if (per_next_state == PWRDM_POWER_OFF) { 225 error = cpu_cluster_pm_enter(); 226 if (error) 227 return; 228 } 229 230 /* CORE */ 231 if (core_next_state < PWRDM_POWER_ON) { 232 if (core_next_state == PWRDM_POWER_OFF) { 233 omap3_core_save_context(); 234 omap3_cm_save_context(); 235 } 236 } 237 238 /* Configure PMIC signaling for I2C4 or sys_off_mode */ 239 omap3_vc_set_pmic_signaling(core_next_state); 240 241 omap3_intc_prepare_idle(); 242 243 /* 244 * On EMU/HS devices ROM code restores a SRDC value 245 * from scratchpad which has automatic self refresh on timeout 246 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443. 247 * Hence store/restore the SDRC_POWER register here. 248 */ 249 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && 250 (omap_type() == OMAP2_DEVICE_TYPE_EMU || 251 omap_type() == OMAP2_DEVICE_TYPE_SEC) && 252 core_next_state == PWRDM_POWER_OFF) 253 sdrc_pwr = sdrc_read_reg(SDRC_POWER); 254 255 /* 256 * omap3_arm_context is the location where some ARM context 257 * get saved. The rest is placed on the stack, and restored 258 * from there before resuming. 259 */ 260 if (save_state) 261 omap34xx_save_context(omap3_arm_context); 262 if (save_state == 1 || save_state == 3) 263 cpu_suspend(save_state, omap34xx_do_sram_idle); 264 else 265 omap34xx_do_sram_idle(save_state); 266 267 /* Restore normal SDRC POWER settings */ 268 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && 269 (omap_type() == OMAP2_DEVICE_TYPE_EMU || 270 omap_type() == OMAP2_DEVICE_TYPE_SEC) && 271 core_next_state == PWRDM_POWER_OFF) 272 sdrc_write_reg(sdrc_pwr, SDRC_POWER); 273 274 /* CORE */ 275 if (core_next_state < PWRDM_POWER_ON && 276 pwrdm_read_prev_pwrst(core_pwrdm) == PWRDM_POWER_OFF) { 277 omap3_core_restore_context(); 278 omap3_cm_restore_context(); 279 omap3_sram_restore_context(); 280 omap2_sms_restore_context(); 281 } else { 282 /* 283 * In off-mode resume path above, omap3_core_restore_context 284 * also handles the INTC autoidle restore done here so limit 285 * this to non-off mode resume paths so we don't do it twice. 286 */ 287 omap3_intc_resume_idle(); 288 } 289 290 pwrdm_post_transition(NULL); 291 292 /* PER */ 293 if (per_next_state == PWRDM_POWER_OFF) 294 cpu_cluster_pm_exit(); 295 } 296 297 static void omap3_pm_idle(void) 298 { 299 if (omap_irq_pending()) 300 return; 301 302 omap_sram_idle(); 303 } 304 305 #ifdef CONFIG_SUSPEND 306 static int omap3_pm_suspend(void) 307 { 308 struct power_state *pwrst; 309 int state, ret = 0; 310 311 /* Read current next_pwrsts */ 312 list_for_each_entry(pwrst, &pwrst_list, node) 313 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 314 /* Set ones wanted by suspend */ 315 list_for_each_entry(pwrst, &pwrst_list, node) { 316 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) 317 goto restore; 318 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) 319 goto restore; 320 } 321 322 omap3_intc_suspend(); 323 324 omap_sram_idle(); 325 326 restore: 327 /* Restore next_pwrsts */ 328 list_for_each_entry(pwrst, &pwrst_list, node) { 329 state = pwrdm_read_prev_pwrst(pwrst->pwrdm); 330 if (state > pwrst->next_state) { 331 pr_info("Powerdomain (%s) didn't enter target state %d\n", 332 pwrst->pwrdm->name, pwrst->next_state); 333 ret = -1; 334 } 335 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); 336 } 337 if (ret) 338 pr_err("Could not enter target state in pm_suspend\n"); 339 else 340 pr_info("Successfully put all powerdomains to target state\n"); 341 342 return ret; 343 } 344 #else 345 #define omap3_pm_suspend NULL 346 #endif /* CONFIG_SUSPEND */ 347 348 static void __init prcm_setup_regs(void) 349 { 350 omap3_ctrl_init(); 351 352 omap3_prm_init_pm(cpu_is_omap3630(), omap3_has_iva()); 353 } 354 355 void omap3_pm_off_mode_enable(int enable) 356 { 357 struct power_state *pwrst; 358 u32 state; 359 360 if (enable) 361 state = PWRDM_POWER_OFF; 362 else 363 state = PWRDM_POWER_RET; 364 365 list_for_each_entry(pwrst, &pwrst_list, node) { 366 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) && 367 pwrst->pwrdm == core_pwrdm && 368 state == PWRDM_POWER_OFF) { 369 pwrst->next_state = PWRDM_POWER_RET; 370 pr_warn("%s: Core OFF disabled due to errata i583\n", 371 __func__); 372 } else { 373 pwrst->next_state = state; 374 } 375 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 376 } 377 } 378 379 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) 380 { 381 struct power_state *pwrst; 382 383 list_for_each_entry(pwrst, &pwrst_list, node) { 384 if (pwrst->pwrdm == pwrdm) 385 return pwrst->next_state; 386 } 387 return -EINVAL; 388 } 389 390 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) 391 { 392 struct power_state *pwrst; 393 394 list_for_each_entry(pwrst, &pwrst_list, node) { 395 if (pwrst->pwrdm == pwrdm) { 396 pwrst->next_state = state; 397 return 0; 398 } 399 } 400 return -EINVAL; 401 } 402 403 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) 404 { 405 struct power_state *pwrst; 406 407 if (!pwrdm->pwrsts) 408 return 0; 409 410 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); 411 if (!pwrst) 412 return -ENOMEM; 413 pwrst->pwrdm = pwrdm; 414 415 if (enable_off_mode) 416 pwrst->next_state = PWRDM_POWER_OFF; 417 else 418 pwrst->next_state = PWRDM_POWER_RET; 419 420 list_add(&pwrst->node, &pwrst_list); 421 422 if (pwrdm_has_hdwr_sar(pwrdm)) 423 pwrdm_enable_hdwr_sar(pwrdm); 424 425 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 426 } 427 428 /* 429 * Push functions to SRAM 430 * 431 * The minimum set of functions is pushed to SRAM for execution: 432 * - omap3_do_wfi for erratum i581 WA, 433 */ 434 void omap_push_sram_idle(void) 435 { 436 omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz); 437 } 438 439 static void __init pm_errata_configure(void) 440 { 441 if (cpu_is_omap3630()) { 442 pm34xx_errata |= PM_RTA_ERRATUM_i608; 443 /* Enable the l2 cache toggling in sleep logic */ 444 enable_omap3630_toggle_l2_on_restore(); 445 if (omap_rev() < OMAP3630_REV_ES1_2) 446 pm34xx_errata |= (PM_SDRC_WAKEUP_ERRATUM_i583 | 447 PM_PER_MEMORIES_ERRATUM_i582); 448 } else if (cpu_is_omap34xx()) { 449 pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582; 450 } 451 } 452 453 static void __init omap3_pm_check_pmic(void) 454 { 455 struct device_node *np; 456 457 np = of_find_compatible_node(NULL, NULL, "ti,twl4030-power-idle"); 458 if (!np) 459 np = of_find_compatible_node(NULL, NULL, "ti,twl4030-power-idle-osc-off"); 460 461 if (np) { 462 of_node_put(np); 463 enable_off_mode = 1; 464 } else { 465 enable_off_mode = 0; 466 } 467 } 468 469 int __init omap3_pm_init(void) 470 { 471 struct power_state *pwrst, *tmp; 472 struct clockdomain *neon_clkdm, *mpu_clkdm, *per_clkdm, *wkup_clkdm; 473 int ret; 474 475 if (!omap3_has_io_chain_ctrl()) 476 pr_warn("PM: no software I/O chain control; some wakeups may be lost\n"); 477 478 pm_errata_configure(); 479 480 /* XXX prcm_setup_regs needs to be before enabling hw 481 * supervised mode for powerdomains */ 482 prcm_setup_regs(); 483 484 ret = request_irq(omap_prcm_event_to_irq("wkup"), 485 _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL); 486 487 if (ret) { 488 pr_err("pm: Failed to request pm_wkup irq\n"); 489 goto err1; 490 } 491 492 /* IO interrupt is shared with mux code */ 493 ret = request_irq(omap_prcm_event_to_irq("io"), 494 _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io", 495 omap3_pm_init); 496 497 if (ret) { 498 pr_err("pm: Failed to request pm_io irq\n"); 499 goto err2; 500 } 501 502 omap3_pm_check_pmic(); 503 504 ret = pwrdm_for_each(pwrdms_setup, NULL); 505 if (ret) { 506 pr_err("Failed to setup powerdomains\n"); 507 goto err3; 508 } 509 510 (void) clkdm_for_each(omap_pm_clkdms_setup, NULL); 511 512 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); 513 if (mpu_pwrdm == NULL) { 514 pr_err("Failed to get mpu_pwrdm\n"); 515 ret = -EINVAL; 516 goto err3; 517 } 518 519 neon_pwrdm = pwrdm_lookup("neon_pwrdm"); 520 per_pwrdm = pwrdm_lookup("per_pwrdm"); 521 core_pwrdm = pwrdm_lookup("core_pwrdm"); 522 523 neon_clkdm = clkdm_lookup("neon_clkdm"); 524 mpu_clkdm = clkdm_lookup("mpu_clkdm"); 525 per_clkdm = clkdm_lookup("per_clkdm"); 526 wkup_clkdm = clkdm_lookup("wkup_clkdm"); 527 528 omap_common_suspend_init(omap3_pm_suspend); 529 530 arm_pm_idle = omap3_pm_idle; 531 omap3_idle_init(); 532 533 /* 534 * RTA is disabled during initialization as per erratum i608 535 * it is safer to disable RTA by the bootloader, but we would like 536 * to be doubly sure here and prevent any mishaps. 537 */ 538 if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608)) 539 omap3630_ctrl_disable_rta(); 540 541 /* 542 * The UART3/4 FIFO and the sidetone memory in McBSP2/3 are 543 * not correctly reset when the PER powerdomain comes back 544 * from OFF or OSWR when the CORE powerdomain is kept active. 545 * See OMAP36xx Erratum i582 "PER Domain reset issue after 546 * Domain-OFF/OSWR Wakeup". This wakeup dependency is not a 547 * complete workaround. The kernel must also prevent the PER 548 * powerdomain from going to OSWR/OFF while the CORE 549 * powerdomain is not going to OSWR/OFF. And if PER last 550 * power state was off while CORE last power state was ON, the 551 * UART3/4 and McBSP2/3 SIDETONE devices need to run a 552 * self-test using their loopback tests; if that fails, those 553 * devices are unusable until the PER/CORE can complete a transition 554 * from ON to OSWR/OFF and then back to ON. 555 * 556 * XXX Technically this workaround is only needed if off-mode 557 * or OSWR is enabled. 558 */ 559 if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582)) 560 clkdm_add_wkdep(per_clkdm, wkup_clkdm); 561 562 clkdm_add_wkdep(neon_clkdm, mpu_clkdm); 563 if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 564 omap3_secure_ram_storage = 565 kmalloc(OMAP3_SAVE_SECURE_RAM_SZ, GFP_KERNEL); 566 if (!omap3_secure_ram_storage) 567 pr_err("Memory allocation failed when allocating for secure sram context\n"); 568 569 local_irq_disable(); 570 571 omap3_save_secure_ram_context(); 572 573 local_irq_enable(); 574 } 575 576 omap3_save_scratchpad_contents(); 577 return ret; 578 579 err3: 580 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { 581 list_del(&pwrst->node); 582 kfree(pwrst); 583 } 584 free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init); 585 err2: 586 free_irq(omap_prcm_event_to_irq("wkup"), NULL); 587 err1: 588 return ret; 589 } 590