18bd22949SKevin Hilman /* 28bd22949SKevin Hilman * OMAP3 Power Management Routines 38bd22949SKevin Hilman * 48bd22949SKevin Hilman * Copyright (C) 2006-2008 Nokia Corporation 58bd22949SKevin Hilman * Tony Lindgren <tony@atomide.com> 68bd22949SKevin Hilman * Jouni Hogander 78bd22949SKevin Hilman * 82f5939c3SRajendra Nayak * Copyright (C) 2007 Texas Instruments, Inc. 92f5939c3SRajendra Nayak * Rajendra Nayak <rnayak@ti.com> 102f5939c3SRajendra Nayak * 118bd22949SKevin Hilman * Copyright (C) 2005 Texas Instruments, Inc. 128bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 138bd22949SKevin Hilman * 148bd22949SKevin Hilman * Based on pm.c for omap1 158bd22949SKevin Hilman * 168bd22949SKevin Hilman * This program is free software; you can redistribute it and/or modify 178bd22949SKevin Hilman * it under the terms of the GNU General Public License version 2 as 188bd22949SKevin Hilman * published by the Free Software Foundation. 198bd22949SKevin Hilman */ 208bd22949SKevin Hilman 218bd22949SKevin Hilman #include <linux/pm.h> 228bd22949SKevin Hilman #include <linux/suspend.h> 238bd22949SKevin Hilman #include <linux/interrupt.h> 248bd22949SKevin Hilman #include <linux/module.h> 258bd22949SKevin Hilman #include <linux/list.h> 268bd22949SKevin Hilman #include <linux/err.h> 278bd22949SKevin Hilman #include <linux/gpio.h> 28c40552bcSKevin Hilman #include <linux/clk.h> 29dccaad89STero Kristo #include <linux/delay.h> 305a0e3ad6STejun Heo #include <linux/slab.h> 310d8e2d0dSPaul Walmsley #include <linux/console.h> 325e7c58dcSJean Pihet #include <trace/events/power.h> 338bd22949SKevin Hilman 342c74a0ceSRussell King #include <asm/suspend.h> 352c74a0ceSRussell King 36ce491cf8STony Lindgren #include <plat/sram.h> 371540f214SPaul Walmsley #include "clockdomain.h" 3872e06d08SPaul Walmsley #include "powerdomain.h" 39ce491cf8STony Lindgren #include <plat/serial.h> 4061255ab9SRajendra Nayak #include <plat/sdrc.h> 412f5939c3SRajendra Nayak #include <plat/prcm.h> 422f5939c3SRajendra Nayak #include <plat/gpmc.h> 43f2d11858STero Kristo #include <plat/dma.h> 448bd22949SKevin Hilman 4559fb659bSPaul Walmsley #include "cm2xxx_3xxx.h" 468bd22949SKevin Hilman #include "cm-regbits-34xx.h" 478bd22949SKevin Hilman #include "prm-regbits-34xx.h" 488bd22949SKevin Hilman 4959fb659bSPaul Walmsley #include "prm2xxx_3xxx.h" 508bd22949SKevin Hilman #include "pm.h" 5113a6fe0fSTero Kristo #include "sdrc.h" 524814ced5SPaul Walmsley #include "control.h" 5313a6fe0fSTero Kristo 54e83df17fSKevin Hilman #ifdef CONFIG_SUSPEND 55e83df17fSKevin Hilman static suspend_state_t suspend_state = PM_SUSPEND_ON; 56e83df17fSKevin Hilman static inline bool is_suspending(void) 57e83df17fSKevin Hilman { 58e83df17fSKevin Hilman return (suspend_state != PM_SUSPEND_ON); 59e83df17fSKevin Hilman } 60e83df17fSKevin Hilman #else 61e83df17fSKevin Hilman static inline bool is_suspending(void) 62e83df17fSKevin Hilman { 63e83df17fSKevin Hilman return false; 64e83df17fSKevin Hilman } 65e83df17fSKevin Hilman #endif 66e83df17fSKevin Hilman 678cdfd834SNishanth Menon /* pm34xx errata defined in pm.h */ 688cdfd834SNishanth Menon u16 pm34xx_errata; 698cdfd834SNishanth Menon 708bd22949SKevin Hilman struct power_state { 718bd22949SKevin Hilman struct powerdomain *pwrdm; 728bd22949SKevin Hilman u32 next_state; 7310f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 748bd22949SKevin Hilman u32 saved_state; 7510f90ed2SKevin Hilman #endif 768bd22949SKevin Hilman struct list_head node; 778bd22949SKevin Hilman }; 788bd22949SKevin Hilman 798bd22949SKevin Hilman static LIST_HEAD(pwrst_list); 808bd22949SKevin Hilman 8127d59a4aSTero Kristo static int (*_omap_save_secure_sram)(u32 *addr); 8246e130d2SJean Pihet void (*omap3_do_wfi_sram)(void); 8327d59a4aSTero Kristo 84fa3c2a4fSRajendra Nayak static struct powerdomain *mpu_pwrdm, *neon_pwrdm; 85fa3c2a4fSRajendra Nayak static struct powerdomain *core_pwrdm, *per_pwrdm; 86c16c3f67STero Kristo static struct powerdomain *cam_pwrdm; 87fa3c2a4fSRajendra Nayak 882f5939c3SRajendra Nayak static inline void omap3_per_save_context(void) 892f5939c3SRajendra Nayak { 902f5939c3SRajendra Nayak omap_gpio_save_context(); 912f5939c3SRajendra Nayak } 922f5939c3SRajendra Nayak 932f5939c3SRajendra Nayak static inline void omap3_per_restore_context(void) 942f5939c3SRajendra Nayak { 952f5939c3SRajendra Nayak omap_gpio_restore_context(); 962f5939c3SRajendra Nayak } 972f5939c3SRajendra Nayak 983a7ec26bSKalle Jokiniemi static void omap3_enable_io_chain(void) 993a7ec26bSKalle Jokiniemi { 1003a7ec26bSKalle Jokiniemi int timeout = 0; 1013a7ec26bSKalle Jokiniemi 1023a7ec26bSKalle Jokiniemi if (omap_rev() >= OMAP3430_REV_ES3_1) { 103c4d7e58fSPaul Walmsley omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, 1042bc4ef71SPaul Walmsley PM_WKEN); 1053a7ec26bSKalle Jokiniemi /* Do a readback to assure write has been done */ 106c4d7e58fSPaul Walmsley omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN); 1073a7ec26bSKalle Jokiniemi 108c4d7e58fSPaul Walmsley while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) & 1092bc4ef71SPaul Walmsley OMAP3430_ST_IO_CHAIN_MASK)) { 1103a7ec26bSKalle Jokiniemi timeout++; 1113a7ec26bSKalle Jokiniemi if (timeout > 1000) { 1123a7ec26bSKalle Jokiniemi printk(KERN_ERR "Wake up daisy chain " 1133a7ec26bSKalle Jokiniemi "activation failed.\n"); 1143a7ec26bSKalle Jokiniemi return; 1153a7ec26bSKalle Jokiniemi } 116c4d7e58fSPaul Walmsley omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, 1170b96a3a3SKevin Hilman WKUP_MOD, PM_WKEN); 1183a7ec26bSKalle Jokiniemi } 1193a7ec26bSKalle Jokiniemi } 1203a7ec26bSKalle Jokiniemi } 1213a7ec26bSKalle Jokiniemi 1223a7ec26bSKalle Jokiniemi static void omap3_disable_io_chain(void) 1233a7ec26bSKalle Jokiniemi { 1243a7ec26bSKalle Jokiniemi if (omap_rev() >= OMAP3430_REV_ES3_1) 125c4d7e58fSPaul Walmsley omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, 1262bc4ef71SPaul Walmsley PM_WKEN); 1273a7ec26bSKalle Jokiniemi } 1283a7ec26bSKalle Jokiniemi 1292f5939c3SRajendra Nayak static void omap3_core_save_context(void) 1302f5939c3SRajendra Nayak { 131596efe47SPaul Walmsley omap3_ctrl_save_padconf(); 132dccaad89STero Kristo 133dccaad89STero Kristo /* 134dccaad89STero Kristo * Force write last pad into memory, as this can fail in some 13583521291SJean Pihet * cases according to errata 1.157, 1.185 136dccaad89STero Kristo */ 137dccaad89STero Kristo omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), 138dccaad89STero Kristo OMAP343X_CONTROL_MEM_WKUP + 0x2a0); 139dccaad89STero Kristo 1402f5939c3SRajendra Nayak /* Save the Interrupt controller context */ 1412f5939c3SRajendra Nayak omap_intc_save_context(); 1422f5939c3SRajendra Nayak /* Save the GPMC context */ 1432f5939c3SRajendra Nayak omap3_gpmc_save_context(); 1442f5939c3SRajendra Nayak /* Save the system control module context, padconf already save above*/ 1452f5939c3SRajendra Nayak omap3_control_save_context(); 146f2d11858STero Kristo omap_dma_global_context_save(); 1472f5939c3SRajendra Nayak } 1482f5939c3SRajendra Nayak 1492f5939c3SRajendra Nayak static void omap3_core_restore_context(void) 1502f5939c3SRajendra Nayak { 1512f5939c3SRajendra Nayak /* Restore the control module context, padconf restored by h/w */ 1522f5939c3SRajendra Nayak omap3_control_restore_context(); 1532f5939c3SRajendra Nayak /* Restore the GPMC context */ 1542f5939c3SRajendra Nayak omap3_gpmc_restore_context(); 1552f5939c3SRajendra Nayak /* Restore the interrupt controller context */ 1562f5939c3SRajendra Nayak omap_intc_restore_context(); 157f2d11858STero Kristo omap_dma_global_context_restore(); 1582f5939c3SRajendra Nayak } 1592f5939c3SRajendra Nayak 1609d97140bSTero Kristo /* 1619d97140bSTero Kristo * FIXME: This function should be called before entering off-mode after 1629d97140bSTero Kristo * OMAP3 secure services have been accessed. Currently it is only called 1639d97140bSTero Kristo * once during boot sequence, but this works as we are not using secure 1649d97140bSTero Kristo * services. 1659d97140bSTero Kristo */ 166617fcc98SKevin Hilman static void omap3_save_secure_ram_context(void) 16727d59a4aSTero Kristo { 16827d59a4aSTero Kristo u32 ret; 169617fcc98SKevin Hilman int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 17027d59a4aSTero Kristo 17127d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 17227d59a4aSTero Kristo /* 17327d59a4aSTero Kristo * MPU next state must be set to POWER_ON temporarily, 17427d59a4aSTero Kristo * otherwise the WFI executed inside the ROM code 17527d59a4aSTero Kristo * will hang the system. 17627d59a4aSTero Kristo */ 17727d59a4aSTero Kristo pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); 17827d59a4aSTero Kristo ret = _omap_save_secure_sram((u32 *) 17927d59a4aSTero Kristo __pa(omap3_secure_ram_storage)); 180617fcc98SKevin Hilman pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state); 18127d59a4aSTero Kristo /* Following is for error tracking, it should not happen */ 18227d59a4aSTero Kristo if (ret) { 18327d59a4aSTero Kristo printk(KERN_ERR "save_secure_sram() returns %08x\n", 18427d59a4aSTero Kristo ret); 18527d59a4aSTero Kristo while (1) 18627d59a4aSTero Kristo ; 18727d59a4aSTero Kristo } 18827d59a4aSTero Kristo } 18927d59a4aSTero Kristo } 19027d59a4aSTero Kristo 19177da2d91SJon Hunter /* 19277da2d91SJon Hunter * PRCM Interrupt Handler Helper Function 19377da2d91SJon Hunter * 19477da2d91SJon Hunter * The purpose of this function is to clear any wake-up events latched 19577da2d91SJon Hunter * in the PRCM PM_WKST_x registers. It is possible that a wake-up event 19677da2d91SJon Hunter * may occur whilst attempting to clear a PM_WKST_x register and thus 19777da2d91SJon Hunter * set another bit in this register. A while loop is used to ensure 19877da2d91SJon Hunter * that any peripheral wake-up events occurring while attempting to 19977da2d91SJon Hunter * clear the PM_WKST_x are detected and cleared. 20077da2d91SJon Hunter */ 2018cb0ac99SPaul Walmsley static int prcm_clear_mod_irqs(s16 module, u8 regs) 20277da2d91SJon Hunter { 20371a80775SVikram Pandita u32 wkst, fclk, iclk, clken; 20477da2d91SJon Hunter u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; 20577da2d91SJon Hunter u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; 20677da2d91SJon Hunter u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; 2075d805978SPaul Walmsley u16 grpsel_off = (regs == 3) ? 2085d805978SPaul Walmsley OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; 2098cb0ac99SPaul Walmsley int c = 0; 21077da2d91SJon Hunter 211c4d7e58fSPaul Walmsley wkst = omap2_prm_read_mod_reg(module, wkst_off); 212c4d7e58fSPaul Walmsley wkst &= omap2_prm_read_mod_reg(module, grpsel_off); 21377da2d91SJon Hunter if (wkst) { 214c4d7e58fSPaul Walmsley iclk = omap2_cm_read_mod_reg(module, iclk_off); 215c4d7e58fSPaul Walmsley fclk = omap2_cm_read_mod_reg(module, fclk_off); 21677da2d91SJon Hunter while (wkst) { 21771a80775SVikram Pandita clken = wkst; 218c4d7e58fSPaul Walmsley omap2_cm_set_mod_reg_bits(clken, module, iclk_off); 21971a80775SVikram Pandita /* 22071a80775SVikram Pandita * For USBHOST, we don't know whether HOST1 or 22171a80775SVikram Pandita * HOST2 woke us up, so enable both f-clocks 22271a80775SVikram Pandita */ 22371a80775SVikram Pandita if (module == OMAP3430ES2_USBHOST_MOD) 22471a80775SVikram Pandita clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; 225c4d7e58fSPaul Walmsley omap2_cm_set_mod_reg_bits(clken, module, fclk_off); 226c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(wkst, module, wkst_off); 227c4d7e58fSPaul Walmsley wkst = omap2_prm_read_mod_reg(module, wkst_off); 2288cb0ac99SPaul Walmsley c++; 22977da2d91SJon Hunter } 230c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(iclk, module, iclk_off); 231c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(fclk, module, fclk_off); 23277da2d91SJon Hunter } 2338cb0ac99SPaul Walmsley 2348cb0ac99SPaul Walmsley return c; 2358cb0ac99SPaul Walmsley } 2368cb0ac99SPaul Walmsley 2378cb0ac99SPaul Walmsley static int _prcm_int_handle_wakeup(void) 2388cb0ac99SPaul Walmsley { 2398cb0ac99SPaul Walmsley int c; 2408cb0ac99SPaul Walmsley 2418cb0ac99SPaul Walmsley c = prcm_clear_mod_irqs(WKUP_MOD, 1); 2428cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(CORE_MOD, 1); 2438cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1); 2448cb0ac99SPaul Walmsley if (omap_rev() > OMAP3430_REV_ES1_0) { 2458cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(CORE_MOD, 3); 2468cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1); 2478cb0ac99SPaul Walmsley } 2488cb0ac99SPaul Walmsley 2498cb0ac99SPaul Walmsley return c; 25077da2d91SJon Hunter } 25177da2d91SJon Hunter 25277da2d91SJon Hunter /* 25377da2d91SJon Hunter * PRCM Interrupt Handler 25477da2d91SJon Hunter * 25577da2d91SJon Hunter * The PRM_IRQSTATUS_MPU register indicates if there are any pending 25677da2d91SJon Hunter * interrupts from the PRCM for the MPU. These bits must be cleared in 25777da2d91SJon Hunter * order to clear the PRCM interrupt. The PRCM interrupt handler is 25877da2d91SJon Hunter * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear 25977da2d91SJon Hunter * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU 26077da2d91SJon Hunter * register indicates that a wake-up event is pending for the MPU and 26177da2d91SJon Hunter * this bit can only be cleared if the all the wake-up events latched 26277da2d91SJon Hunter * in the various PM_WKST_x registers have been cleared. The interrupt 26377da2d91SJon Hunter * handler is implemented using a do-while loop so that if a wake-up 26477da2d91SJon Hunter * event occurred during the processing of the prcm interrupt handler 26577da2d91SJon Hunter * (setting a bit in the corresponding PM_WKST_x register and thus 26677da2d91SJon Hunter * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register) 26777da2d91SJon Hunter * this would be handled. 26877da2d91SJon Hunter */ 2698bd22949SKevin Hilman static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) 2708bd22949SKevin Hilman { 271d6290a3eSKevin Hilman u32 irqenable_mpu, irqstatus_mpu; 2728cb0ac99SPaul Walmsley int c = 0; 2738bd22949SKevin Hilman 274c4d7e58fSPaul Walmsley irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD, 275d6290a3eSKevin Hilman OMAP3_PRM_IRQENABLE_MPU_OFFSET); 276c4d7e58fSPaul Walmsley irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD, 2778bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 278d6290a3eSKevin Hilman irqstatus_mpu &= irqenable_mpu; 2798cb0ac99SPaul Walmsley 280d6290a3eSKevin Hilman do { 2812bc4ef71SPaul Walmsley if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK | 2822bc4ef71SPaul Walmsley OMAP3430_IO_ST_MASK)) { 2838cb0ac99SPaul Walmsley c = _prcm_int_handle_wakeup(); 2848cb0ac99SPaul Walmsley 2858cb0ac99SPaul Walmsley /* 2868cb0ac99SPaul Walmsley * Is the MPU PRCM interrupt handler racing with the 2878cb0ac99SPaul Walmsley * IVA2 PRCM interrupt handler ? 2888cb0ac99SPaul Walmsley */ 2898cb0ac99SPaul Walmsley WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup " 2908cb0ac99SPaul Walmsley "but no wakeup sources are marked\n"); 2918cb0ac99SPaul Walmsley } else { 2928cb0ac99SPaul Walmsley /* XXX we need to expand our PRCM interrupt handler */ 2938cb0ac99SPaul Walmsley WARN(1, "prcm: WARNING: PRCM interrupt received, but " 2948cb0ac99SPaul Walmsley "no code to handle it (%08x)\n", irqstatus_mpu); 2958cb0ac99SPaul Walmsley } 2968cb0ac99SPaul Walmsley 297c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD, 2988bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 2998bd22949SKevin Hilman 300c4d7e58fSPaul Walmsley irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD, 301d6290a3eSKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 302d6290a3eSKevin Hilman irqstatus_mpu &= irqenable_mpu; 303d6290a3eSKevin Hilman 304d6290a3eSKevin Hilman } while (irqstatus_mpu); 3058bd22949SKevin Hilman 3068bd22949SKevin Hilman return IRQ_HANDLED; 3078bd22949SKevin Hilman } 3088bd22949SKevin Hilman 309cbe26349SRussell King static void omap34xx_save_context(u32 *save) 310cbe26349SRussell King { 311cbe26349SRussell King u32 val; 312cbe26349SRussell King 313cbe26349SRussell King /* Read Auxiliary Control Register */ 314cbe26349SRussell King asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val)); 315cbe26349SRussell King *save++ = 1; 316cbe26349SRussell King *save++ = val; 317cbe26349SRussell King 318cbe26349SRussell King /* Read L2 AUX ctrl register */ 319cbe26349SRussell King asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); 320cbe26349SRussell King *save++ = 1; 321cbe26349SRussell King *save++ = val; 322cbe26349SRussell King } 323cbe26349SRussell King 32429cb3cd2SRussell King static int omap34xx_do_sram_idle(unsigned long save_state) 32557f277b0SRajendra Nayak { 326cbe26349SRussell King omap34xx_cpu_suspend(save_state); 32729cb3cd2SRussell King return 0; 32857f277b0SRajendra Nayak } 32957f277b0SRajendra Nayak 33099e6a4d2SRajendra Nayak void omap_sram_idle(void) 3318bd22949SKevin Hilman { 3328bd22949SKevin Hilman /* Variable to tell what needs to be saved and restored 3338bd22949SKevin Hilman * in omap_sram_idle*/ 3348bd22949SKevin Hilman /* save_state = 0 => Nothing to save and restored */ 3358bd22949SKevin Hilman /* save_state = 1 => Only L1 and logic lost */ 3368bd22949SKevin Hilman /* save_state = 2 => Only L2 lost */ 3378bd22949SKevin Hilman /* save_state = 3 => L1, L2 and logic lost */ 338fa3c2a4fSRajendra Nayak int save_state = 0; 339fa3c2a4fSRajendra Nayak int mpu_next_state = PWRDM_POWER_ON; 340fa3c2a4fSRajendra Nayak int per_next_state = PWRDM_POWER_ON; 341fa3c2a4fSRajendra Nayak int core_next_state = PWRDM_POWER_ON; 34272e06d08SPaul Walmsley int per_going_off; 3432f5939c3SRajendra Nayak int core_prev_state, per_prev_state; 34413a6fe0fSTero Kristo u32 sdrc_pwr = 0; 3458bd22949SKevin Hilman 346fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(mpu_pwrdm); 347fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(neon_pwrdm); 348fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(core_pwrdm); 349fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(per_pwrdm); 350fa3c2a4fSRajendra Nayak 3518bd22949SKevin Hilman mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 3528bd22949SKevin Hilman switch (mpu_next_state) { 353fa3c2a4fSRajendra Nayak case PWRDM_POWER_ON: 3548bd22949SKevin Hilman case PWRDM_POWER_RET: 3558bd22949SKevin Hilman /* No need to save context */ 3568bd22949SKevin Hilman save_state = 0; 3578bd22949SKevin Hilman break; 35861255ab9SRajendra Nayak case PWRDM_POWER_OFF: 35961255ab9SRajendra Nayak save_state = 3; 36061255ab9SRajendra Nayak break; 3618bd22949SKevin Hilman default: 3628bd22949SKevin Hilman /* Invalid state */ 3638bd22949SKevin Hilman printk(KERN_ERR "Invalid mpu state in sram_idle\n"); 3648bd22949SKevin Hilman return; 3658bd22949SKevin Hilman } 366fe617af7SPeter 'p2' De Schrijver 367fa3c2a4fSRajendra Nayak /* NEON control */ 368fa3c2a4fSRajendra Nayak if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) 3697139178eSJouni Hogander pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); 370fa3c2a4fSRajendra Nayak 37140742fa8SMike Chan /* Enable IO-PAD and IO-CHAIN wakeups */ 372fa3c2a4fSRajendra Nayak per_next_state = pwrdm_read_next_pwrst(per_pwrdm); 373ecf157d0STero Kristo core_next_state = pwrdm_read_next_pwrst(core_pwrdm); 374d5c47d7eSKevin Hilman if (omap3_has_io_wakeup() && 375ad0c63f1Sstanley.miao (per_next_state < PWRDM_POWER_ON || 376ad0c63f1Sstanley.miao core_next_state < PWRDM_POWER_ON)) { 377c4d7e58fSPaul Walmsley omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); 37840742fa8SMike Chan omap3_enable_io_chain(); 37940742fa8SMike Chan } 38040742fa8SMike Chan 3810d8e2d0dSPaul Walmsley /* Block console output in case it is on one of the OMAP UARTs */ 382e83df17fSKevin Hilman if (!is_suspending()) 3830d8e2d0dSPaul Walmsley if (per_next_state < PWRDM_POWER_ON || 3840d8e2d0dSPaul Walmsley core_next_state < PWRDM_POWER_ON) 385ac751efaSTorben Hohn if (!console_trylock()) 3860d8e2d0dSPaul Walmsley goto console_still_active; 3870d8e2d0dSPaul Walmsley 388ff2f8e5fSCharulatha V pwrdm_pre_transition(); 389ff2f8e5fSCharulatha V 39040742fa8SMike Chan /* PER */ 3912f5939c3SRajendra Nayak if (per_next_state < PWRDM_POWER_ON) { 39272e06d08SPaul Walmsley per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0; 3934af4016cSKevin Hilman omap_uart_prepare_idle(2); 394cd4f1faeSGovindraj.R omap_uart_prepare_idle(3); 39572e06d08SPaul Walmsley omap2_gpio_prepare_for_idle(per_going_off); 396e7410cf7SKevin Hilman if (per_next_state == PWRDM_POWER_OFF) 3972f5939c3SRajendra Nayak omap3_per_save_context(); 3982f5939c3SRajendra Nayak } 399c16c3f67STero Kristo 400658ce97eSKevin Hilman /* CORE */ 401658ce97eSKevin Hilman if (core_next_state < PWRDM_POWER_ON) { 402658ce97eSKevin Hilman omap_uart_prepare_idle(0); 403658ce97eSKevin Hilman omap_uart_prepare_idle(1); 4042f5939c3SRajendra Nayak if (core_next_state == PWRDM_POWER_OFF) { 4052f5939c3SRajendra Nayak omap3_core_save_context(); 406f0611a5cSPaul Walmsley omap3_cm_save_context(); 4072f5939c3SRajendra Nayak } 408fa3c2a4fSRajendra Nayak } 40940742fa8SMike Chan 410f18cc2ffSTero Kristo omap3_intc_prepare_idle(); 4118bd22949SKevin Hilman 41261255ab9SRajendra Nayak /* 413f265dc4cSRajendra Nayak * On EMU/HS devices ROM code restores a SRDC value 414f265dc4cSRajendra Nayak * from scratchpad which has automatic self refresh on timeout 41583521291SJean Pihet * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443. 416f265dc4cSRajendra Nayak * Hence store/restore the SDRC_POWER register here. 41713a6fe0fSTero Kristo */ 41813a6fe0fSTero Kristo if (omap_rev() >= OMAP3430_REV_ES3_0 && 41913a6fe0fSTero Kristo omap_type() != OMAP2_DEVICE_TYPE_GP && 420f265dc4cSRajendra Nayak core_next_state == PWRDM_POWER_OFF) 42113a6fe0fSTero Kristo sdrc_pwr = sdrc_read_reg(SDRC_POWER); 42213a6fe0fSTero Kristo 42313a6fe0fSTero Kristo /* 424076f2cc4SRussell King * omap3_arm_context is the location where some ARM context 425076f2cc4SRussell King * get saved. The rest is placed on the stack, and restored 426076f2cc4SRussell King * from there before resuming. 42761255ab9SRajendra Nayak */ 428cbe26349SRussell King if (save_state) 429cbe26349SRussell King omap34xx_save_context(omap3_arm_context); 430076f2cc4SRussell King if (save_state == 1 || save_state == 3) 4312c74a0ceSRussell King cpu_suspend(save_state, omap34xx_do_sram_idle); 432076f2cc4SRussell King else 433076f2cc4SRussell King omap34xx_do_sram_idle(save_state); 4348bd22949SKevin Hilman 435f265dc4cSRajendra Nayak /* Restore normal SDRC POWER settings */ 43613a6fe0fSTero Kristo if (omap_rev() >= OMAP3430_REV_ES3_0 && 43713a6fe0fSTero Kristo omap_type() != OMAP2_DEVICE_TYPE_GP && 43813a6fe0fSTero Kristo core_next_state == PWRDM_POWER_OFF) 43913a6fe0fSTero Kristo sdrc_write_reg(sdrc_pwr, SDRC_POWER); 44013a6fe0fSTero Kristo 441658ce97eSKevin Hilman /* CORE */ 442fa3c2a4fSRajendra Nayak if (core_next_state < PWRDM_POWER_ON) { 4432f5939c3SRajendra Nayak core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); 4442f5939c3SRajendra Nayak if (core_prev_state == PWRDM_POWER_OFF) { 4452f5939c3SRajendra Nayak omap3_core_restore_context(); 446f0611a5cSPaul Walmsley omap3_cm_restore_context(); 4472f5939c3SRajendra Nayak omap3_sram_restore_context(); 4488a917d2fSKalle Jokiniemi omap2_sms_restore_context(); 4492f5939c3SRajendra Nayak } 450658ce97eSKevin Hilman omap_uart_resume_idle(0); 451658ce97eSKevin Hilman omap_uart_resume_idle(1); 452658ce97eSKevin Hilman if (core_next_state == PWRDM_POWER_OFF) 453c4d7e58fSPaul Walmsley omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, 454658ce97eSKevin Hilman OMAP3430_GR_MOD, 455658ce97eSKevin Hilman OMAP3_PRM_VOLTCTRL_OFFSET); 456658ce97eSKevin Hilman } 457f18cc2ffSTero Kristo omap3_intc_resume_idle(); 458658ce97eSKevin Hilman 459ff2f8e5fSCharulatha V pwrdm_post_transition(); 460ff2f8e5fSCharulatha V 461658ce97eSKevin Hilman /* PER */ 4622f5939c3SRajendra Nayak if (per_next_state < PWRDM_POWER_ON) { 463658ce97eSKevin Hilman per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); 46443ffcd9aSKevin Hilman omap2_gpio_resume_after_idle(); 46543ffcd9aSKevin Hilman if (per_prev_state == PWRDM_POWER_OFF) 4662f5939c3SRajendra Nayak omap3_per_restore_context(); 467ecf157d0STero Kristo omap_uart_resume_idle(2); 468cd4f1faeSGovindraj.R omap_uart_resume_idle(3); 469fa3c2a4fSRajendra Nayak } 470fe617af7SPeter 'p2' De Schrijver 471e83df17fSKevin Hilman if (!is_suspending()) 472ac751efaSTorben Hohn console_unlock(); 4730d8e2d0dSPaul Walmsley 4740d8e2d0dSPaul Walmsley console_still_active: 4753a7ec26bSKalle Jokiniemi /* Disable IO-PAD and IO-CHAIN wakeup */ 47658a5559eSKevin Hilman if (omap3_has_io_wakeup() && 47758a5559eSKevin Hilman (per_next_state < PWRDM_POWER_ON || 47858a5559eSKevin Hilman core_next_state < PWRDM_POWER_ON)) { 479c4d7e58fSPaul Walmsley omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, 480c4d7e58fSPaul Walmsley PM_WKEN); 4813a7ec26bSKalle Jokiniemi omap3_disable_io_chain(); 4823a7ec26bSKalle Jokiniemi } 483658ce97eSKevin Hilman 4845cd1937bSRajendra Nayak clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); 4858bd22949SKevin Hilman } 4868bd22949SKevin Hilman 48720b01669SRajendra Nayak int omap3_can_sleep(void) 4888bd22949SKevin Hilman { 4894af4016cSKevin Hilman if (!omap_uart_can_sleep()) 4904af4016cSKevin Hilman return 0; 4918bd22949SKevin Hilman return 1; 4928bd22949SKevin Hilman } 4938bd22949SKevin Hilman 4948bd22949SKevin Hilman static void omap3_pm_idle(void) 4958bd22949SKevin Hilman { 4968bd22949SKevin Hilman local_irq_disable(); 4978bd22949SKevin Hilman local_fiq_disable(); 4988bd22949SKevin Hilman 4998bd22949SKevin Hilman if (!omap3_can_sleep()) 5008bd22949SKevin Hilman goto out; 5018bd22949SKevin Hilman 502cf22854cSTero Kristo if (omap_irq_pending() || need_resched()) 5038bd22949SKevin Hilman goto out; 5048bd22949SKevin Hilman 5055e7c58dcSJean Pihet trace_power_start(POWER_CSTATE, 1, smp_processor_id()); 5065e7c58dcSJean Pihet trace_cpu_idle(1, smp_processor_id()); 5075e7c58dcSJean Pihet 5088bd22949SKevin Hilman omap_sram_idle(); 5098bd22949SKevin Hilman 5105e7c58dcSJean Pihet trace_power_end(smp_processor_id()); 5115e7c58dcSJean Pihet trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); 5125e7c58dcSJean Pihet 5138bd22949SKevin Hilman out: 5148bd22949SKevin Hilman local_fiq_enable(); 5158bd22949SKevin Hilman local_irq_enable(); 5168bd22949SKevin Hilman } 5178bd22949SKevin Hilman 51810f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 5198bd22949SKevin Hilman static int omap3_pm_suspend(void) 5208bd22949SKevin Hilman { 5218bd22949SKevin Hilman struct power_state *pwrst; 5228bd22949SKevin Hilman int state, ret = 0; 5238bd22949SKevin Hilman 5248bd22949SKevin Hilman /* Read current next_pwrsts */ 5258bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) 5268bd22949SKevin Hilman pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 5278bd22949SKevin Hilman /* Set ones wanted by suspend */ 5288bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 529eb6a2c75SSantosh Shilimkar if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) 5308bd22949SKevin Hilman goto restore; 5318bd22949SKevin Hilman if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) 5328bd22949SKevin Hilman goto restore; 5338bd22949SKevin Hilman } 5348bd22949SKevin Hilman 5354af4016cSKevin Hilman omap_uart_prepare_suspend(); 5362bbe3af3STero Kristo omap3_intc_suspend(); 5372bbe3af3STero Kristo 5388bd22949SKevin Hilman omap_sram_idle(); 5398bd22949SKevin Hilman 5408bd22949SKevin Hilman restore: 5418bd22949SKevin Hilman /* Restore next_pwrsts */ 5428bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 5438bd22949SKevin Hilman state = pwrdm_read_prev_pwrst(pwrst->pwrdm); 5448bd22949SKevin Hilman if (state > pwrst->next_state) { 5458bd22949SKevin Hilman printk(KERN_INFO "Powerdomain (%s) didn't enter " 5468bd22949SKevin Hilman "target state %d\n", 5478bd22949SKevin Hilman pwrst->pwrdm->name, pwrst->next_state); 5488bd22949SKevin Hilman ret = -1; 5498bd22949SKevin Hilman } 550eb6a2c75SSantosh Shilimkar omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); 5518bd22949SKevin Hilman } 5528bd22949SKevin Hilman if (ret) 5538bd22949SKevin Hilman printk(KERN_ERR "Could not enter target state in pm_suspend\n"); 5548bd22949SKevin Hilman else 5558bd22949SKevin Hilman printk(KERN_INFO "Successfully put all powerdomains " 5568bd22949SKevin Hilman "to target state\n"); 5578bd22949SKevin Hilman 5588bd22949SKevin Hilman return ret; 5598bd22949SKevin Hilman } 5608bd22949SKevin Hilman 5612466211eSTero Kristo static int omap3_pm_enter(suspend_state_t unused) 5628bd22949SKevin Hilman { 5638bd22949SKevin Hilman int ret = 0; 5648bd22949SKevin Hilman 5652466211eSTero Kristo switch (suspend_state) { 5668bd22949SKevin Hilman case PM_SUSPEND_STANDBY: 5678bd22949SKevin Hilman case PM_SUSPEND_MEM: 5688bd22949SKevin Hilman ret = omap3_pm_suspend(); 5698bd22949SKevin Hilman break; 5708bd22949SKevin Hilman default: 5718bd22949SKevin Hilman ret = -EINVAL; 5728bd22949SKevin Hilman } 5738bd22949SKevin Hilman 5748bd22949SKevin Hilman return ret; 5758bd22949SKevin Hilman } 5768bd22949SKevin Hilman 5772466211eSTero Kristo /* Hooks to enable / disable UART interrupts during suspend */ 5782466211eSTero Kristo static int omap3_pm_begin(suspend_state_t state) 5792466211eSTero Kristo { 580c166381dSJean Pihet disable_hlt(); 5812466211eSTero Kristo suspend_state = state; 5822466211eSTero Kristo omap_uart_enable_irqs(0); 5832466211eSTero Kristo return 0; 5842466211eSTero Kristo } 5852466211eSTero Kristo 5862466211eSTero Kristo static void omap3_pm_end(void) 5872466211eSTero Kristo { 5882466211eSTero Kristo suspend_state = PM_SUSPEND_ON; 5892466211eSTero Kristo omap_uart_enable_irqs(1); 590c166381dSJean Pihet enable_hlt(); 5912466211eSTero Kristo return; 5922466211eSTero Kristo } 5932466211eSTero Kristo 5942f55ac07SLionel Debroux static const struct platform_suspend_ops omap_pm_ops = { 5952466211eSTero Kristo .begin = omap3_pm_begin, 5962466211eSTero Kristo .end = omap3_pm_end, 5978bd22949SKevin Hilman .enter = omap3_pm_enter, 5988bd22949SKevin Hilman .valid = suspend_valid_only_mem, 5998bd22949SKevin Hilman }; 60010f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 6018bd22949SKevin Hilman 6021155e426SKevin Hilman 6031155e426SKevin Hilman /** 6041155e426SKevin Hilman * omap3_iva_idle(): ensure IVA is in idle so it can be put into 6051155e426SKevin Hilman * retention 6061155e426SKevin Hilman * 6071155e426SKevin Hilman * In cases where IVA2 is activated by bootcode, it may prevent 6081155e426SKevin Hilman * full-chip retention or off-mode because it is not idle. This 6091155e426SKevin Hilman * function forces the IVA2 into idle state so it can go 6101155e426SKevin Hilman * into retention/off and thus allow full-chip retention/off. 6111155e426SKevin Hilman * 6121155e426SKevin Hilman **/ 6131155e426SKevin Hilman static void __init omap3_iva_idle(void) 6141155e426SKevin Hilman { 6151155e426SKevin Hilman /* ensure IVA2 clock is disabled */ 616c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 6171155e426SKevin Hilman 6181155e426SKevin Hilman /* if no clock activity, nothing else to do */ 619c4d7e58fSPaul Walmsley if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & 6201155e426SKevin Hilman OMAP3430_CLKACTIVITY_IVA2_MASK)) 6211155e426SKevin Hilman return; 6221155e426SKevin Hilman 6231155e426SKevin Hilman /* Reset IVA2 */ 624c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | 6252bc4ef71SPaul Walmsley OMAP3430_RST2_IVA2_MASK | 6262bc4ef71SPaul Walmsley OMAP3430_RST3_IVA2_MASK, 62737903009SAbhijit Pagare OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 6281155e426SKevin Hilman 6291155e426SKevin Hilman /* Enable IVA2 clock */ 630c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, 6311155e426SKevin Hilman OMAP3430_IVA2_MOD, CM_FCLKEN); 6321155e426SKevin Hilman 6331155e426SKevin Hilman /* Set IVA2 boot mode to 'idle' */ 6341155e426SKevin Hilman omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, 6351155e426SKevin Hilman OMAP343X_CONTROL_IVA2_BOOTMOD); 6361155e426SKevin Hilman 6371155e426SKevin Hilman /* Un-reset IVA2 */ 638c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 6391155e426SKevin Hilman 6401155e426SKevin Hilman /* Disable IVA2 clock */ 641c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 6421155e426SKevin Hilman 6431155e426SKevin Hilman /* Reset IVA2 */ 644c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | 6452bc4ef71SPaul Walmsley OMAP3430_RST2_IVA2_MASK | 6462bc4ef71SPaul Walmsley OMAP3430_RST3_IVA2_MASK, 64737903009SAbhijit Pagare OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 6481155e426SKevin Hilman } 6491155e426SKevin Hilman 6508111b221SKevin Hilman static void __init omap3_d2d_idle(void) 6518bd22949SKevin Hilman { 6528111b221SKevin Hilman u16 mask, padconf; 6538111b221SKevin Hilman 6548111b221SKevin Hilman /* In a stand alone OMAP3430 where there is not a stacked 6558111b221SKevin Hilman * modem for the D2D Idle Ack and D2D MStandby must be pulled 6568111b221SKevin Hilman * high. S CONTROL_PADCONF_SAD2D_IDLEACK and 6578111b221SKevin Hilman * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ 6588111b221SKevin Hilman mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ 6598111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); 6608111b221SKevin Hilman padconf |= mask; 6618111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); 6628111b221SKevin Hilman 6638111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); 6648111b221SKevin Hilman padconf |= mask; 6658111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 6668111b221SKevin Hilman 6678bd22949SKevin Hilman /* reset modem */ 668c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | 6692bc4ef71SPaul Walmsley OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, 67037903009SAbhijit Pagare CORE_MOD, OMAP2_RM_RSTCTRL); 671c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); 6728111b221SKevin Hilman } 6738bd22949SKevin Hilman 6748111b221SKevin Hilman static void __init prcm_setup_regs(void) 6758111b221SKevin Hilman { 676e5863689SGovindraj.R u32 omap3630_en_uart4_mask = cpu_is_omap3630() ? 677e5863689SGovindraj.R OMAP3630_EN_UART4_MASK : 0; 678e5863689SGovindraj.R u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ? 679e5863689SGovindraj.R OMAP3630_GRPSEL_UART4_MASK : 0; 680e5863689SGovindraj.R 6814ef70c06SPaul Walmsley /* XXX This should be handled by hwmod code or SCM init code */ 6822fd0f75cSPaul Walmsley omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); 683b296c811STero Kristo 6848bd22949SKevin Hilman /* 6858bd22949SKevin Hilman * Enable control of expternal oscillator through 6868bd22949SKevin Hilman * sys_clkreq. In the long run clock framework should 6878bd22949SKevin Hilman * take care of this. 6888bd22949SKevin Hilman */ 689c4d7e58fSPaul Walmsley omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 6908bd22949SKevin Hilman 1 << OMAP_AUTOEXTCLKMODE_SHIFT, 6918bd22949SKevin Hilman OMAP3430_GR_MOD, 6928bd22949SKevin Hilman OMAP3_PRM_CLKSRC_CTRL_OFFSET); 6938bd22949SKevin Hilman 6948bd22949SKevin Hilman /* setup wakup source */ 695c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | 6962fd0f75cSPaul Walmsley OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, 6978bd22949SKevin Hilman WKUP_MOD, PM_WKEN); 6988bd22949SKevin Hilman /* No need to write EN_IO, that is always enabled */ 699c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | 700275f675cSPaul Walmsley OMAP3430_GRPSEL_GPT1_MASK | 701275f675cSPaul Walmsley OMAP3430_GRPSEL_GPT12_MASK, 7028bd22949SKevin Hilman WKUP_MOD, OMAP3430_PM_MPUGRPSEL); 7038bd22949SKevin Hilman /* For some reason IO doesn't generate wakeup event even if 7048bd22949SKevin Hilman * it is selected to mpu wakeup goup */ 705c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK, 7068bd22949SKevin Hilman OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); 7071155e426SKevin Hilman 708b92c5721SSubramani Venkatesh /* Enable PM_WKEN to support DSS LPR */ 709c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, 710b92c5721SSubramani Venkatesh OMAP3430_DSS_MOD, PM_WKEN); 711b92c5721SSubramani Venkatesh 712b427f92fSKevin Hilman /* Enable wakeups in PER */ 713c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(omap3630_en_uart4_mask | 714e5863689SGovindraj.R OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | 7152fd0f75cSPaul Walmsley OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | 7162fd0f75cSPaul Walmsley OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | 7172fd0f75cSPaul Walmsley OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK | 7182fd0f75cSPaul Walmsley OMAP3430_EN_MCBSP4_MASK, 719b427f92fSKevin Hilman OMAP3430_PER_MOD, PM_WKEN); 720eb350f74SKevin Hilman /* and allow them to wake up MPU */ 721c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask | 722e5863689SGovindraj.R OMAP3430_GRPSEL_GPIO2_MASK | 723275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO3_MASK | 724275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO4_MASK | 725275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO5_MASK | 726275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO6_MASK | 727275f675cSPaul Walmsley OMAP3430_GRPSEL_UART3_MASK | 728275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP2_MASK | 729275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP3_MASK | 730275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP4_MASK, 731eb350f74SKevin Hilman OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); 732eb350f74SKevin Hilman 733d3fd3290SKevin Hilman /* Don't attach IVA interrupts */ 734c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 735c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 736c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 737c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); 738d3fd3290SKevin Hilman 739b1340d17SKevin Hilman /* Clear any pending 'reset' flags */ 740c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); 741c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); 742c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); 743c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); 744c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); 745c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); 746c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); 747b1340d17SKevin Hilman 748014c46dbSKevin Hilman /* Clear any pending PRCM interrupts */ 749c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 750014c46dbSKevin Hilman 7511155e426SKevin Hilman omap3_iva_idle(); 7528111b221SKevin Hilman omap3_d2d_idle(); 7538bd22949SKevin Hilman } 7548bd22949SKevin Hilman 755c40552bcSKevin Hilman void omap3_pm_off_mode_enable(int enable) 756c40552bcSKevin Hilman { 757c40552bcSKevin Hilman struct power_state *pwrst; 758c40552bcSKevin Hilman u32 state; 759c40552bcSKevin Hilman 760c40552bcSKevin Hilman if (enable) 761c40552bcSKevin Hilman state = PWRDM_POWER_OFF; 762c40552bcSKevin Hilman else 763c40552bcSKevin Hilman state = PWRDM_POWER_RET; 764c40552bcSKevin Hilman 765c40552bcSKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 766cc1b6028SEduardo Valentin if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) && 767cc1b6028SEduardo Valentin pwrst->pwrdm == core_pwrdm && 768cc1b6028SEduardo Valentin state == PWRDM_POWER_OFF) { 769cc1b6028SEduardo Valentin pwrst->next_state = PWRDM_POWER_RET; 770e16b41bfSRicardo Salveti de Araujo pr_warn("%s: Core OFF disabled due to errata i583\n", 771cc1b6028SEduardo Valentin __func__); 772cc1b6028SEduardo Valentin } else { 773c40552bcSKevin Hilman pwrst->next_state = state; 774cc1b6028SEduardo Valentin } 775cc1b6028SEduardo Valentin omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 776c40552bcSKevin Hilman } 777c40552bcSKevin Hilman } 778c40552bcSKevin Hilman 77968d4778cSTero Kristo int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) 78068d4778cSTero Kristo { 78168d4778cSTero Kristo struct power_state *pwrst; 78268d4778cSTero Kristo 78368d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 78468d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) 78568d4778cSTero Kristo return pwrst->next_state; 78668d4778cSTero Kristo } 78768d4778cSTero Kristo return -EINVAL; 78868d4778cSTero Kristo } 78968d4778cSTero Kristo 79068d4778cSTero Kristo int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) 79168d4778cSTero Kristo { 79268d4778cSTero Kristo struct power_state *pwrst; 79368d4778cSTero Kristo 79468d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 79568d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) { 79668d4778cSTero Kristo pwrst->next_state = state; 79768d4778cSTero Kristo return 0; 79868d4778cSTero Kristo } 79968d4778cSTero Kristo } 80068d4778cSTero Kristo return -EINVAL; 80168d4778cSTero Kristo } 80268d4778cSTero Kristo 803a23456e9SPeter 'p2' De Schrijver static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) 8048bd22949SKevin Hilman { 8058bd22949SKevin Hilman struct power_state *pwrst; 8068bd22949SKevin Hilman 8078bd22949SKevin Hilman if (!pwrdm->pwrsts) 8088bd22949SKevin Hilman return 0; 8098bd22949SKevin Hilman 810d3d381c6SMing Lei pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); 8118bd22949SKevin Hilman if (!pwrst) 8128bd22949SKevin Hilman return -ENOMEM; 8138bd22949SKevin Hilman pwrst->pwrdm = pwrdm; 8148bd22949SKevin Hilman pwrst->next_state = PWRDM_POWER_RET; 8158bd22949SKevin Hilman list_add(&pwrst->node, &pwrst_list); 8168bd22949SKevin Hilman 8178bd22949SKevin Hilman if (pwrdm_has_hdwr_sar(pwrdm)) 8188bd22949SKevin Hilman pwrdm_enable_hdwr_sar(pwrdm); 8198bd22949SKevin Hilman 820eb6a2c75SSantosh Shilimkar return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 8218bd22949SKevin Hilman } 8228bd22949SKevin Hilman 8238bd22949SKevin Hilman /* 8248bd22949SKevin Hilman * Enable hw supervised mode for all clockdomains if it's 8258bd22949SKevin Hilman * supported. Initiate sleep transition for other clockdomains, if 8268bd22949SKevin Hilman * they are not used 8278bd22949SKevin Hilman */ 828a23456e9SPeter 'p2' De Schrijver static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) 8298bd22949SKevin Hilman { 8308bd22949SKevin Hilman if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) 8315cd1937bSRajendra Nayak clkdm_allow_idle(clkdm); 8328bd22949SKevin Hilman else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && 8338bd22949SKevin Hilman atomic_read(&clkdm->usecount) == 0) 83468b921adSRajendra Nayak clkdm_sleep(clkdm); 8358bd22949SKevin Hilman return 0; 8368bd22949SKevin Hilman } 8378bd22949SKevin Hilman 83846e130d2SJean Pihet /* 83946e130d2SJean Pihet * Push functions to SRAM 84046e130d2SJean Pihet * 84146e130d2SJean Pihet * The minimum set of functions is pushed to SRAM for execution: 84246e130d2SJean Pihet * - omap3_do_wfi for erratum i581 WA, 84346e130d2SJean Pihet * - save_secure_ram_context for security extensions. 84446e130d2SJean Pihet */ 8453231fc88SRajendra Nayak void omap_push_sram_idle(void) 8463231fc88SRajendra Nayak { 84746e130d2SJean Pihet omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz); 84846e130d2SJean Pihet 84927d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) 85027d59a4aSTero Kristo _omap_save_secure_sram = omap_sram_push(save_secure_ram_context, 85127d59a4aSTero Kristo save_secure_ram_context_sz); 8523231fc88SRajendra Nayak } 8533231fc88SRajendra Nayak 8548cdfd834SNishanth Menon static void __init pm_errata_configure(void) 8558cdfd834SNishanth Menon { 856c4236d2eSPeter 'p2' De Schrijver if (cpu_is_omap3630()) { 857458e999eSNishanth Menon pm34xx_errata |= PM_RTA_ERRATUM_i608; 858c4236d2eSPeter 'p2' De Schrijver /* Enable the l2 cache toggling in sleep logic */ 859c4236d2eSPeter 'p2' De Schrijver enable_omap3630_toggle_l2_on_restore(); 860cc1b6028SEduardo Valentin if (omap_rev() < OMAP3630_REV_ES1_2) 861cc1b6028SEduardo Valentin pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583; 862c4236d2eSPeter 'p2' De Schrijver } 8638cdfd834SNishanth Menon } 8648cdfd834SNishanth Menon 8657cc515f7SKevin Hilman static int __init omap3_pm_init(void) 8668bd22949SKevin Hilman { 8678bd22949SKevin Hilman struct power_state *pwrst, *tmp; 86855ed9694SPaul Walmsley struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm; 8698bd22949SKevin Hilman int ret; 8708bd22949SKevin Hilman 8718bd22949SKevin Hilman if (!cpu_is_omap34xx()) 8728bd22949SKevin Hilman return -ENODEV; 8738bd22949SKevin Hilman 8748cdfd834SNishanth Menon pm_errata_configure(); 8758cdfd834SNishanth Menon 8768bd22949SKevin Hilman /* XXX prcm_setup_regs needs to be before enabling hw 8778bd22949SKevin Hilman * supervised mode for powerdomains */ 8788bd22949SKevin Hilman prcm_setup_regs(); 8798bd22949SKevin Hilman 8808bd22949SKevin Hilman ret = request_irq(INT_34XX_PRCM_MPU_IRQ, 8818bd22949SKevin Hilman (irq_handler_t)prcm_interrupt_handler, 8828bd22949SKevin Hilman IRQF_DISABLED, "prcm", NULL); 8838bd22949SKevin Hilman if (ret) { 8848bd22949SKevin Hilman printk(KERN_ERR "request_irq failed to register for 0x%x\n", 8858bd22949SKevin Hilman INT_34XX_PRCM_MPU_IRQ); 8868bd22949SKevin Hilman goto err1; 8878bd22949SKevin Hilman } 8888bd22949SKevin Hilman 889a23456e9SPeter 'p2' De Schrijver ret = pwrdm_for_each(pwrdms_setup, NULL); 8908bd22949SKevin Hilman if (ret) { 8918bd22949SKevin Hilman printk(KERN_ERR "Failed to setup powerdomains\n"); 8928bd22949SKevin Hilman goto err2; 8938bd22949SKevin Hilman } 8948bd22949SKevin Hilman 895a23456e9SPeter 'p2' De Schrijver (void) clkdm_for_each(clkdms_setup, NULL); 8968bd22949SKevin Hilman 8978bd22949SKevin Hilman mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); 8988bd22949SKevin Hilman if (mpu_pwrdm == NULL) { 8998bd22949SKevin Hilman printk(KERN_ERR "Failed to get mpu_pwrdm\n"); 9008bd22949SKevin Hilman goto err2; 9018bd22949SKevin Hilman } 9028bd22949SKevin Hilman 903fa3c2a4fSRajendra Nayak neon_pwrdm = pwrdm_lookup("neon_pwrdm"); 904fa3c2a4fSRajendra Nayak per_pwrdm = pwrdm_lookup("per_pwrdm"); 905fa3c2a4fSRajendra Nayak core_pwrdm = pwrdm_lookup("core_pwrdm"); 906c16c3f67STero Kristo cam_pwrdm = pwrdm_lookup("cam_pwrdm"); 907fa3c2a4fSRajendra Nayak 90855ed9694SPaul Walmsley neon_clkdm = clkdm_lookup("neon_clkdm"); 90955ed9694SPaul Walmsley mpu_clkdm = clkdm_lookup("mpu_clkdm"); 91055ed9694SPaul Walmsley per_clkdm = clkdm_lookup("per_clkdm"); 91155ed9694SPaul Walmsley core_clkdm = clkdm_lookup("core_clkdm"); 91255ed9694SPaul Walmsley 91310f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 9148bd22949SKevin Hilman suspend_set_ops(&omap_pm_ops); 91510f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 9168bd22949SKevin Hilman 9178bd22949SKevin Hilman pm_idle = omap3_pm_idle; 9180343371eSKalle Jokiniemi omap3_idle_init(); 9198bd22949SKevin Hilman 920458e999eSNishanth Menon /* 921458e999eSNishanth Menon * RTA is disabled during initialization as per erratum i608 922458e999eSNishanth Menon * it is safer to disable RTA by the bootloader, but we would like 923458e999eSNishanth Menon * to be doubly sure here and prevent any mishaps. 924458e999eSNishanth Menon */ 925458e999eSNishanth Menon if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608)) 926458e999eSNishanth Menon omap3630_ctrl_disable_rta(); 927458e999eSNishanth Menon 92855ed9694SPaul Walmsley clkdm_add_wkdep(neon_clkdm, mpu_clkdm); 92927d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 93027d59a4aSTero Kristo omap3_secure_ram_storage = 93127d59a4aSTero Kristo kmalloc(0x803F, GFP_KERNEL); 93227d59a4aSTero Kristo if (!omap3_secure_ram_storage) 93327d59a4aSTero Kristo printk(KERN_ERR "Memory allocation failed when" 93427d59a4aSTero Kristo "allocating for secure sram context\n"); 93527d59a4aSTero Kristo 9369d97140bSTero Kristo local_irq_disable(); 9379d97140bSTero Kristo local_fiq_disable(); 9389d97140bSTero Kristo 9399d97140bSTero Kristo omap_dma_global_context_save(); 940617fcc98SKevin Hilman omap3_save_secure_ram_context(); 9419d97140bSTero Kristo omap_dma_global_context_restore(); 9429d97140bSTero Kristo 9439d97140bSTero Kristo local_irq_enable(); 9449d97140bSTero Kristo local_fiq_enable(); 9459d97140bSTero Kristo } 9469d97140bSTero Kristo 9479d97140bSTero Kristo omap3_save_scratchpad_contents(); 9488bd22949SKevin Hilman err1: 9498bd22949SKevin Hilman return ret; 9508bd22949SKevin Hilman err2: 9518bd22949SKevin Hilman free_irq(INT_34XX_PRCM_MPU_IRQ, NULL); 9528bd22949SKevin Hilman list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { 9538bd22949SKevin Hilman list_del(&pwrst->node); 9548bd22949SKevin Hilman kfree(pwrst); 9558bd22949SKevin Hilman } 9568bd22949SKevin Hilman return ret; 9578bd22949SKevin Hilman } 9588bd22949SKevin Hilman 9598bd22949SKevin Hilman late_initcall(omap3_pm_init); 960