1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 28bd22949SKevin Hilman /* 38bd22949SKevin Hilman * OMAP3 Power Management Routines 48bd22949SKevin Hilman * 58bd22949SKevin Hilman * Copyright (C) 2006-2008 Nokia Corporation 68bd22949SKevin Hilman * Tony Lindgren <tony@atomide.com> 78bd22949SKevin Hilman * Jouni Hogander 88bd22949SKevin Hilman * 92f5939c3SRajendra Nayak * Copyright (C) 2007 Texas Instruments, Inc. 102f5939c3SRajendra Nayak * Rajendra Nayak <rnayak@ti.com> 112f5939c3SRajendra Nayak * 128bd22949SKevin Hilman * Copyright (C) 2005 Texas Instruments, Inc. 138bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 148bd22949SKevin Hilman * 158bd22949SKevin Hilman * Based on pm.c for omap1 168bd22949SKevin Hilman */ 178bd22949SKevin Hilman 18b764a586STony Lindgren #include <linux/cpu_pm.h> 198bd22949SKevin Hilman #include <linux/pm.h> 208bd22949SKevin Hilman #include <linux/suspend.h> 218bd22949SKevin Hilman #include <linux/interrupt.h> 228bd22949SKevin Hilman #include <linux/module.h> 238bd22949SKevin Hilman #include <linux/list.h> 248bd22949SKevin Hilman #include <linux/err.h> 25c40552bcSKevin Hilman #include <linux/clk.h> 26dccaad89STero Kristo #include <linux/delay.h> 275a0e3ad6STejun Heo #include <linux/slab.h> 28fb2c599fSAndreas Kemnade #include <linux/of.h> 29e639cd5bSTony Lindgren #include <linux/omap-gpmc.h> 304b25408fSTony Lindgren 315e7c58dcSJean Pihet #include <trace/events/power.h> 328bd22949SKevin Hilman 33bf027ca1STony Lindgren #include <asm/fncpy.h> 342c74a0ceSRussell King #include <asm/suspend.h> 359f97da78SDavid Howells #include <asm/system_misc.h> 362c74a0ceSRussell King 371540f214SPaul Walmsley #include "clockdomain.h" 3872e06d08SPaul Walmsley #include "powerdomain.h" 39e4c060dbSTony Lindgren #include "soc.h" 404e65331cSTony Lindgren #include "common.h" 41ff4ae5d9SPaul Walmsley #include "cm3xxx.h" 428bd22949SKevin Hilman #include "cm-regbits-34xx.h" 438bd22949SKevin Hilman #include "prm-regbits-34xx.h" 44139563adSPaul Walmsley #include "prm3xxx.h" 458bd22949SKevin Hilman #include "pm.h" 4613a6fe0fSTero Kristo #include "sdrc.h" 47d09220a8STony Lindgren #include "omap-secure.h" 48bf027ca1STony Lindgren #include "sram.h" 494814ced5SPaul Walmsley #include "control.h" 503b8c4ebbSTony Lindgren #include "vc.h" 5113a6fe0fSTero Kristo 528cdfd834SNishanth Menon /* pm34xx errata defined in pm.h */ 538cdfd834SNishanth Menon u16 pm34xx_errata; 548cdfd834SNishanth Menon 558bd22949SKevin Hilman struct power_state { 568bd22949SKevin Hilman struct powerdomain *pwrdm; 578bd22949SKevin Hilman u32 next_state; 5810f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 598bd22949SKevin Hilman u32 saved_state; 6010f90ed2SKevin Hilman #endif 618bd22949SKevin Hilman struct list_head node; 628bd22949SKevin Hilman }; 638bd22949SKevin Hilman 648bd22949SKevin Hilman static LIST_HEAD(pwrst_list); 658bd22949SKevin Hilman 6646e130d2SJean Pihet void (*omap3_do_wfi_sram)(void); 6727d59a4aSTero Kristo 68fa3c2a4fSRajendra Nayak static struct powerdomain *mpu_pwrdm, *neon_pwrdm; 69fa3c2a4fSRajendra Nayak static struct powerdomain *core_pwrdm, *per_pwrdm; 703a7ec26bSKalle Jokiniemi 712f5939c3SRajendra Nayak static void omap3_core_save_context(void) 722f5939c3SRajendra Nayak { 73596efe47SPaul Walmsley omap3_ctrl_save_padconf(); 74dccaad89STero Kristo 75dccaad89STero Kristo /* 76dccaad89STero Kristo * Force write last pad into memory, as this can fail in some 7783521291SJean Pihet * cases according to errata 1.157, 1.185 78dccaad89STero Kristo */ 79dccaad89STero Kristo omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), 80dccaad89STero Kristo OMAP343X_CONTROL_MEM_WKUP + 0x2a0); 81dccaad89STero Kristo 822f5939c3SRajendra Nayak /* Save the Interrupt controller context */ 832f5939c3SRajendra Nayak omap_intc_save_context(); 842f5939c3SRajendra Nayak /* Save the GPMC context */ 852f5939c3SRajendra Nayak omap3_gpmc_save_context(); 862f5939c3SRajendra Nayak /* Save the system control module context, padconf already save above*/ 872f5939c3SRajendra Nayak omap3_control_save_context(); 882f5939c3SRajendra Nayak } 892f5939c3SRajendra Nayak 902f5939c3SRajendra Nayak static void omap3_core_restore_context(void) 912f5939c3SRajendra Nayak { 922f5939c3SRajendra Nayak /* Restore the control module context, padconf restored by h/w */ 932f5939c3SRajendra Nayak omap3_control_restore_context(); 942f5939c3SRajendra Nayak /* Restore the GPMC context */ 952f5939c3SRajendra Nayak omap3_gpmc_restore_context(); 962f5939c3SRajendra Nayak /* Restore the interrupt controller context */ 972f5939c3SRajendra Nayak omap_intc_restore_context(); 982f5939c3SRajendra Nayak } 992f5939c3SRajendra Nayak 1009d97140bSTero Kristo /* 1019d97140bSTero Kristo * FIXME: This function should be called before entering off-mode after 1029d97140bSTero Kristo * OMAP3 secure services have been accessed. Currently it is only called 1039d97140bSTero Kristo * once during boot sequence, but this works as we are not using secure 1049d97140bSTero Kristo * services. 1059d97140bSTero Kristo */ 106617fcc98SKevin Hilman static void omap3_save_secure_ram_context(void) 10727d59a4aSTero Kristo { 10827d59a4aSTero Kristo u32 ret; 109617fcc98SKevin Hilman int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 11027d59a4aSTero Kristo 11127d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 11227d59a4aSTero Kristo /* 11327d59a4aSTero Kristo * MPU next state must be set to POWER_ON temporarily, 11427d59a4aSTero Kristo * otherwise the WFI executed inside the ROM code 11527d59a4aSTero Kristo * will hang the system. 11627d59a4aSTero Kristo */ 11727d59a4aSTero Kristo pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); 118d09220a8STony Lindgren ret = omap3_save_secure_ram(omap3_secure_ram_storage, 119d09220a8STony Lindgren OMAP3_SAVE_SECURE_RAM_SZ); 120617fcc98SKevin Hilman pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state); 12127d59a4aSTero Kristo /* Following is for error tracking, it should not happen */ 12227d59a4aSTero Kristo if (ret) { 12398179856SMark A. Greer pr_err("save_secure_sram() returns %08x\n", ret); 12427d59a4aSTero Kristo while (1) 12527d59a4aSTero Kristo ; 12627d59a4aSTero Kristo } 12727d59a4aSTero Kristo } 12827d59a4aSTero Kristo } 12927d59a4aSTero Kristo 13022f51371STero Kristo static irqreturn_t _prcm_int_handle_io(int irq, void *unused) 1318cb0ac99SPaul Walmsley { 1328cb0ac99SPaul Walmsley int c; 1338cb0ac99SPaul Walmsley 1349cb6d363STero Kristo c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, OMAP3430_ST_IO_MASK | 135f0caa527STero Kristo OMAP3430_ST_IO_CHAIN_MASK); 13622f51371STero Kristo 13722f51371STero Kristo return c ? IRQ_HANDLED : IRQ_NONE; 1388cb0ac99SPaul Walmsley } 1398cb0ac99SPaul Walmsley 14022f51371STero Kristo static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused) 1418bd22949SKevin Hilman { 14222f51371STero Kristo int c; 1438cb0ac99SPaul Walmsley 1448cb0ac99SPaul Walmsley /* 14522f51371STero Kristo * Clear all except ST_IO and ST_IO_CHAIN for wkup module, 14622f51371STero Kristo * these are handled in a separate handler to avoid acking 14722f51371STero Kristo * IO events before parsing in mux code 1488cb0ac99SPaul Walmsley */ 1499cb6d363STero Kristo c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, ~(OMAP3430_ST_IO_MASK | 150f0caa527STero Kristo OMAP3430_ST_IO_CHAIN_MASK)); 1519cb6d363STero Kristo c += omap_prm_clear_mod_irqs(CORE_MOD, 1, ~0); 1529cb6d363STero Kristo c += omap_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, ~0); 15322f51371STero Kristo if (omap_rev() > OMAP3430_REV_ES1_0) { 1549cb6d363STero Kristo c += omap_prm_clear_mod_irqs(CORE_MOD, 3, ~0); 1559cb6d363STero Kristo c += omap_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, ~0); 1568cb0ac99SPaul Walmsley } 1578cb0ac99SPaul Walmsley 15822f51371STero Kristo return c ? IRQ_HANDLED : IRQ_NONE; 1598bd22949SKevin Hilman } 1608bd22949SKevin Hilman 161cbe26349SRussell King static void omap34xx_save_context(u32 *save) 162cbe26349SRussell King { 163cbe26349SRussell King u32 val; 164cbe26349SRussell King 165cbe26349SRussell King /* Read Auxiliary Control Register */ 166cbe26349SRussell King asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val)); 167cbe26349SRussell King *save++ = 1; 168cbe26349SRussell King *save++ = val; 169cbe26349SRussell King 170cbe26349SRussell King /* Read L2 AUX ctrl register */ 171cbe26349SRussell King asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); 172cbe26349SRussell King *save++ = 1; 173cbe26349SRussell King *save++ = val; 174cbe26349SRussell King } 175cbe26349SRussell King 17629cb3cd2SRussell King static int omap34xx_do_sram_idle(unsigned long save_state) 17757f277b0SRajendra Nayak { 178cbe26349SRussell King omap34xx_cpu_suspend(save_state); 17929cb3cd2SRussell King return 0; 18057f277b0SRajendra Nayak } 18157f277b0SRajendra Nayak 18299e6a4d2SRajendra Nayak void omap_sram_idle(void) 1838bd22949SKevin Hilman { 1848bd22949SKevin Hilman /* Variable to tell what needs to be saved and restored 1858bd22949SKevin Hilman * in omap_sram_idle*/ 1868bd22949SKevin Hilman /* save_state = 0 => Nothing to save and restored */ 1878bd22949SKevin Hilman /* save_state = 1 => Only L1 and logic lost */ 1888bd22949SKevin Hilman /* save_state = 2 => Only L2 lost */ 1898bd22949SKevin Hilman /* save_state = 3 => L1, L2 and logic lost */ 190fa3c2a4fSRajendra Nayak int save_state = 0; 191fa3c2a4fSRajendra Nayak int mpu_next_state = PWRDM_POWER_ON; 192fa3c2a4fSRajendra Nayak int per_next_state = PWRDM_POWER_ON; 193fa3c2a4fSRajendra Nayak int core_next_state = PWRDM_POWER_ON; 19413a6fe0fSTero Kristo u32 sdrc_pwr = 0; 19555be2f50STony Lindgren int error; 1968bd22949SKevin Hilman 1978bd22949SKevin Hilman mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 1988bd22949SKevin Hilman switch (mpu_next_state) { 199fa3c2a4fSRajendra Nayak case PWRDM_POWER_ON: 2008bd22949SKevin Hilman case PWRDM_POWER_RET: 2018bd22949SKevin Hilman /* No need to save context */ 2028bd22949SKevin Hilman save_state = 0; 2038bd22949SKevin Hilman break; 20461255ab9SRajendra Nayak case PWRDM_POWER_OFF: 20561255ab9SRajendra Nayak save_state = 3; 20661255ab9SRajendra Nayak break; 2078bd22949SKevin Hilman default: 2088bd22949SKevin Hilman /* Invalid state */ 20998179856SMark A. Greer pr_err("Invalid mpu state in sram_idle\n"); 2108bd22949SKevin Hilman return; 2118bd22949SKevin Hilman } 212fe617af7SPeter 'p2' De Schrijver 213fa3c2a4fSRajendra Nayak /* NEON control */ 214fa3c2a4fSRajendra Nayak if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) 2157139178eSJouni Hogander pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); 216fa3c2a4fSRajendra Nayak 21740742fa8SMike Chan /* Enable IO-PAD and IO-CHAIN wakeups */ 218fa3c2a4fSRajendra Nayak per_next_state = pwrdm_read_next_pwrst(per_pwrdm); 219ecf157d0STero Kristo core_next_state = pwrdm_read_next_pwrst(core_pwrdm); 22040742fa8SMike Chan 221e0e29fd7SKevin Hilman pwrdm_pre_transition(NULL); 222ff2f8e5fSCharulatha V 22340742fa8SMike Chan /* PER */ 22455be2f50STony Lindgren if (per_next_state == PWRDM_POWER_OFF) { 22555be2f50STony Lindgren error = cpu_cluster_pm_enter(); 22655be2f50STony Lindgren if (error) 22755be2f50STony Lindgren return; 22855be2f50STony Lindgren } 229c16c3f67STero Kristo 230658ce97eSKevin Hilman /* CORE */ 231658ce97eSKevin Hilman if (core_next_state < PWRDM_POWER_ON) { 2322f5939c3SRajendra Nayak if (core_next_state == PWRDM_POWER_OFF) { 2332f5939c3SRajendra Nayak omap3_core_save_context(); 234f0611a5cSPaul Walmsley omap3_cm_save_context(); 2352f5939c3SRajendra Nayak } 236fa3c2a4fSRajendra Nayak } 23740742fa8SMike Chan 2383b8c4ebbSTony Lindgren /* Configure PMIC signaling for I2C4 or sys_off_mode */ 2393b8c4ebbSTony Lindgren omap3_vc_set_pmic_signaling(core_next_state); 2403b8c4ebbSTony Lindgren 241f18cc2ffSTero Kristo omap3_intc_prepare_idle(); 2428bd22949SKevin Hilman 24361255ab9SRajendra Nayak /* 244f265dc4cSRajendra Nayak * On EMU/HS devices ROM code restores a SRDC value 245f265dc4cSRajendra Nayak * from scratchpad which has automatic self refresh on timeout 24683521291SJean Pihet * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443. 247f265dc4cSRajendra Nayak * Hence store/restore the SDRC_POWER register here. 24813a6fe0fSTero Kristo */ 24930474544SPaul Walmsley if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && 25030474544SPaul Walmsley (omap_type() == OMAP2_DEVICE_TYPE_EMU || 25130474544SPaul Walmsley omap_type() == OMAP2_DEVICE_TYPE_SEC) && 252f265dc4cSRajendra Nayak core_next_state == PWRDM_POWER_OFF) 25313a6fe0fSTero Kristo sdrc_pwr = sdrc_read_reg(SDRC_POWER); 25413a6fe0fSTero Kristo 25513a6fe0fSTero Kristo /* 256076f2cc4SRussell King * omap3_arm_context is the location where some ARM context 257076f2cc4SRussell King * get saved. The rest is placed on the stack, and restored 258076f2cc4SRussell King * from there before resuming. 25961255ab9SRajendra Nayak */ 260cbe26349SRussell King if (save_state) 261cbe26349SRussell King omap34xx_save_context(omap3_arm_context); 262076f2cc4SRussell King if (save_state == 1 || save_state == 3) 2632c74a0ceSRussell King cpu_suspend(save_state, omap34xx_do_sram_idle); 264076f2cc4SRussell King else 265076f2cc4SRussell King omap34xx_do_sram_idle(save_state); 2668bd22949SKevin Hilman 267f265dc4cSRajendra Nayak /* Restore normal SDRC POWER settings */ 26830474544SPaul Walmsley if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && 26930474544SPaul Walmsley (omap_type() == OMAP2_DEVICE_TYPE_EMU || 27030474544SPaul Walmsley omap_type() == OMAP2_DEVICE_TYPE_SEC) && 27113a6fe0fSTero Kristo core_next_state == PWRDM_POWER_OFF) 27213a6fe0fSTero Kristo sdrc_write_reg(sdrc_pwr, SDRC_POWER); 27313a6fe0fSTero Kristo 274658ce97eSKevin Hilman /* CORE */ 2751560d158SDave Gerlach if (core_next_state < PWRDM_POWER_ON && 2761560d158SDave Gerlach pwrdm_read_prev_pwrst(core_pwrdm) == PWRDM_POWER_OFF) { 2772f5939c3SRajendra Nayak omap3_core_restore_context(); 278f0611a5cSPaul Walmsley omap3_cm_restore_context(); 2792f5939c3SRajendra Nayak omap3_sram_restore_context(); 2808a917d2fSKalle Jokiniemi omap2_sms_restore_context(); 2811560d158SDave Gerlach } else { 2821560d158SDave Gerlach /* 2831560d158SDave Gerlach * In off-mode resume path above, omap3_core_restore_context 2841560d158SDave Gerlach * also handles the INTC autoidle restore done here so limit 2851560d158SDave Gerlach * this to non-off mode resume paths so we don't do it twice. 2861560d158SDave Gerlach */ 287f18cc2ffSTero Kristo omap3_intc_resume_idle(); 2881560d158SDave Gerlach } 289658ce97eSKevin Hilman 290e0e29fd7SKevin Hilman pwrdm_post_transition(NULL); 291658ce97eSKevin Hilman 292e0e29fd7SKevin Hilman /* PER */ 293b764a586STony Lindgren if (per_next_state == PWRDM_POWER_OFF) 294b764a586STony Lindgren cpu_cluster_pm_exit(); 2958bd22949SKevin Hilman } 2968bd22949SKevin Hilman 2978bd22949SKevin Hilman static void omap3_pm_idle(void) 2988bd22949SKevin Hilman { 2990bcd24b0SNicolas Pitre if (omap_irq_pending()) 3006b85638bSSantosh Shilimkar return; 3018bd22949SKevin Hilman 3026ca22700SJisheng Zhang trace_cpu_idle_rcuidle(1, smp_processor_id()); 3035e7c58dcSJean Pihet 3048bd22949SKevin Hilman omap_sram_idle(); 3058bd22949SKevin Hilman 3066ca22700SJisheng Zhang trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); 3078bd22949SKevin Hilman } 3088bd22949SKevin Hilman 30910f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 3108bd22949SKevin Hilman static int omap3_pm_suspend(void) 3118bd22949SKevin Hilman { 3128bd22949SKevin Hilman struct power_state *pwrst; 3138bd22949SKevin Hilman int state, ret = 0; 3148bd22949SKevin Hilman 3158bd22949SKevin Hilman /* Read current next_pwrsts */ 3168bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) 3178bd22949SKevin Hilman pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 3188bd22949SKevin Hilman /* Set ones wanted by suspend */ 3198bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 320eb6a2c75SSantosh Shilimkar if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) 3218bd22949SKevin Hilman goto restore; 3228bd22949SKevin Hilman if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) 3238bd22949SKevin Hilman goto restore; 3248bd22949SKevin Hilman } 3258bd22949SKevin Hilman 3262bbe3af3STero Kristo omap3_intc_suspend(); 3272bbe3af3STero Kristo 3288bd22949SKevin Hilman omap_sram_idle(); 3298bd22949SKevin Hilman 3308bd22949SKevin Hilman restore: 3318bd22949SKevin Hilman /* Restore next_pwrsts */ 3328bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 3338bd22949SKevin Hilman state = pwrdm_read_prev_pwrst(pwrst->pwrdm); 3348bd22949SKevin Hilman if (state > pwrst->next_state) { 3357852ec05SPaul Walmsley pr_info("Powerdomain (%s) didn't enter target state %d\n", 3368bd22949SKevin Hilman pwrst->pwrdm->name, pwrst->next_state); 3378bd22949SKevin Hilman ret = -1; 3388bd22949SKevin Hilman } 339eb6a2c75SSantosh Shilimkar omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); 3408bd22949SKevin Hilman } 3418bd22949SKevin Hilman if (ret) 34298179856SMark A. Greer pr_err("Could not enter target state in pm_suspend\n"); 3438bd22949SKevin Hilman else 34498179856SMark A. Greer pr_info("Successfully put all powerdomains to target state\n"); 3458bd22949SKevin Hilman 3468bd22949SKevin Hilman return ret; 3478bd22949SKevin Hilman } 3482e4b62dcSDave Gerlach #else 3492e4b62dcSDave Gerlach #define omap3_pm_suspend NULL 35010f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 3518bd22949SKevin Hilman 3528111b221SKevin Hilman static void __init prcm_setup_regs(void) 3538111b221SKevin Hilman { 354ba12c242STero Kristo omap3_ctrl_init(); 355b296c811STero Kristo 356c5180a2bSTero Kristo omap3_prm_init_pm(cpu_is_omap3630(), omap3_has_iva()); 3578bd22949SKevin Hilman } 3588bd22949SKevin Hilman 359c40552bcSKevin Hilman void omap3_pm_off_mode_enable(int enable) 360c40552bcSKevin Hilman { 361c40552bcSKevin Hilman struct power_state *pwrst; 362c40552bcSKevin Hilman u32 state; 363c40552bcSKevin Hilman 364c40552bcSKevin Hilman if (enable) 365c40552bcSKevin Hilman state = PWRDM_POWER_OFF; 366c40552bcSKevin Hilman else 367c40552bcSKevin Hilman state = PWRDM_POWER_RET; 368c40552bcSKevin Hilman 369c40552bcSKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 370cc1b6028SEduardo Valentin if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) && 371cc1b6028SEduardo Valentin pwrst->pwrdm == core_pwrdm && 372cc1b6028SEduardo Valentin state == PWRDM_POWER_OFF) { 373cc1b6028SEduardo Valentin pwrst->next_state = PWRDM_POWER_RET; 374e16b41bfSRicardo Salveti de Araujo pr_warn("%s: Core OFF disabled due to errata i583\n", 375cc1b6028SEduardo Valentin __func__); 376cc1b6028SEduardo Valentin } else { 377c40552bcSKevin Hilman pwrst->next_state = state; 378cc1b6028SEduardo Valentin } 379cc1b6028SEduardo Valentin omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 380c40552bcSKevin Hilman } 381c40552bcSKevin Hilman } 382c40552bcSKevin Hilman 38368d4778cSTero Kristo int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) 38468d4778cSTero Kristo { 38568d4778cSTero Kristo struct power_state *pwrst; 38668d4778cSTero Kristo 38768d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 38868d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) 38968d4778cSTero Kristo return pwrst->next_state; 39068d4778cSTero Kristo } 39168d4778cSTero Kristo return -EINVAL; 39268d4778cSTero Kristo } 39368d4778cSTero Kristo 39468d4778cSTero Kristo int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) 39568d4778cSTero Kristo { 39668d4778cSTero Kristo struct power_state *pwrst; 39768d4778cSTero Kristo 39868d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 39968d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) { 40068d4778cSTero Kristo pwrst->next_state = state; 40168d4778cSTero Kristo return 0; 40268d4778cSTero Kristo } 40368d4778cSTero Kristo } 40468d4778cSTero Kristo return -EINVAL; 40568d4778cSTero Kristo } 40668d4778cSTero Kristo 407a23456e9SPeter 'p2' De Schrijver static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) 4088bd22949SKevin Hilman { 4098bd22949SKevin Hilman struct power_state *pwrst; 4108bd22949SKevin Hilman 4118bd22949SKevin Hilman if (!pwrdm->pwrsts) 4128bd22949SKevin Hilman return 0; 4138bd22949SKevin Hilman 414d3d381c6SMing Lei pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); 4158bd22949SKevin Hilman if (!pwrst) 4168bd22949SKevin Hilman return -ENOMEM; 4178bd22949SKevin Hilman pwrst->pwrdm = pwrdm; 418fb2c599fSAndreas Kemnade 419fb2c599fSAndreas Kemnade if (enable_off_mode) 420fb2c599fSAndreas Kemnade pwrst->next_state = PWRDM_POWER_OFF; 421fb2c599fSAndreas Kemnade else 4228bd22949SKevin Hilman pwrst->next_state = PWRDM_POWER_RET; 423fb2c599fSAndreas Kemnade 4248bd22949SKevin Hilman list_add(&pwrst->node, &pwrst_list); 4258bd22949SKevin Hilman 4268bd22949SKevin Hilman if (pwrdm_has_hdwr_sar(pwrdm)) 4278bd22949SKevin Hilman pwrdm_enable_hdwr_sar(pwrdm); 4288bd22949SKevin Hilman 429eb6a2c75SSantosh Shilimkar return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 4308bd22949SKevin Hilman } 4318bd22949SKevin Hilman 4328bd22949SKevin Hilman /* 43346e130d2SJean Pihet * Push functions to SRAM 43446e130d2SJean Pihet * 43546e130d2SJean Pihet * The minimum set of functions is pushed to SRAM for execution: 43646e130d2SJean Pihet * - omap3_do_wfi for erratum i581 WA, 43746e130d2SJean Pihet */ 4383231fc88SRajendra Nayak void omap_push_sram_idle(void) 4393231fc88SRajendra Nayak { 44046e130d2SJean Pihet omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz); 4413231fc88SRajendra Nayak } 4423231fc88SRajendra Nayak 4438cdfd834SNishanth Menon static void __init pm_errata_configure(void) 4448cdfd834SNishanth Menon { 445c4236d2eSPeter 'p2' De Schrijver if (cpu_is_omap3630()) { 446458e999eSNishanth Menon pm34xx_errata |= PM_RTA_ERRATUM_i608; 447c4236d2eSPeter 'p2' De Schrijver /* Enable the l2 cache toggling in sleep logic */ 448c4236d2eSPeter 'p2' De Schrijver enable_omap3630_toggle_l2_on_restore(); 449cc1b6028SEduardo Valentin if (omap_rev() < OMAP3630_REV_ES1_2) 450856c3c5bSPaul Walmsley pm34xx_errata |= (PM_SDRC_WAKEUP_ERRATUM_i583 | 451856c3c5bSPaul Walmsley PM_PER_MEMORIES_ERRATUM_i582); 452856c3c5bSPaul Walmsley } else if (cpu_is_omap34xx()) { 453856c3c5bSPaul Walmsley pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582; 454c4236d2eSPeter 'p2' De Schrijver } 4558cdfd834SNishanth Menon } 4568cdfd834SNishanth Menon 457fb2c599fSAndreas Kemnade static void __init omap3_pm_check_pmic(void) 458fb2c599fSAndreas Kemnade { 459fb2c599fSAndreas Kemnade struct device_node *np; 460fb2c599fSAndreas Kemnade 461fb2c599fSAndreas Kemnade np = of_find_compatible_node(NULL, NULL, "ti,twl4030-power-idle"); 462fb2c599fSAndreas Kemnade if (!np) 463fb2c599fSAndreas Kemnade np = of_find_compatible_node(NULL, NULL, "ti,twl4030-power-idle-osc-off"); 464fb2c599fSAndreas Kemnade 465fb2c599fSAndreas Kemnade if (np) { 466fb2c599fSAndreas Kemnade of_node_put(np); 467fb2c599fSAndreas Kemnade enable_off_mode = 1; 468fb2c599fSAndreas Kemnade } else { 469fb2c599fSAndreas Kemnade enable_off_mode = 0; 470fb2c599fSAndreas Kemnade } 471fb2c599fSAndreas Kemnade } 472fb2c599fSAndreas Kemnade 473bbd707acSShawn Guo int __init omap3_pm_init(void) 4748bd22949SKevin Hilman { 4758bd22949SKevin Hilman struct power_state *pwrst, *tmp; 476856c3c5bSPaul Walmsley struct clockdomain *neon_clkdm, *mpu_clkdm, *per_clkdm, *wkup_clkdm; 4778bd22949SKevin Hilman int ret; 4788bd22949SKevin Hilman 479b02b9172SPaul Walmsley if (!omap3_has_io_chain_ctrl()) 4803d0cb73eSJoe Perches pr_warn("PM: no software I/O chain control; some wakeups may be lost\n"); 481b02b9172SPaul Walmsley 4828cdfd834SNishanth Menon pm_errata_configure(); 4838cdfd834SNishanth Menon 4848bd22949SKevin Hilman /* XXX prcm_setup_regs needs to be before enabling hw 4858bd22949SKevin Hilman * supervised mode for powerdomains */ 4868bd22949SKevin Hilman prcm_setup_regs(); 4878bd22949SKevin Hilman 48822f51371STero Kristo ret = request_irq(omap_prcm_event_to_irq("wkup"), 48922f51371STero Kristo _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL); 49022f51371STero Kristo 4918bd22949SKevin Hilman if (ret) { 49222f51371STero Kristo pr_err("pm: Failed to request pm_wkup irq\n"); 49322f51371STero Kristo goto err1; 49422f51371STero Kristo } 49522f51371STero Kristo 49622f51371STero Kristo /* IO interrupt is shared with mux code */ 49722f51371STero Kristo ret = request_irq(omap_prcm_event_to_irq("io"), 49822f51371STero Kristo _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io", 49922f51371STero Kristo omap3_pm_init); 50022f51371STero Kristo 50122f51371STero Kristo if (ret) { 50222f51371STero Kristo pr_err("pm: Failed to request pm_io irq\n"); 503ce229c5dSMark A. Greer goto err2; 5048bd22949SKevin Hilman } 5058bd22949SKevin Hilman 506fb2c599fSAndreas Kemnade omap3_pm_check_pmic(); 507fb2c599fSAndreas Kemnade 508a23456e9SPeter 'p2' De Schrijver ret = pwrdm_for_each(pwrdms_setup, NULL); 5098bd22949SKevin Hilman if (ret) { 51098179856SMark A. Greer pr_err("Failed to setup powerdomains\n"); 511ce229c5dSMark A. Greer goto err3; 5128bd22949SKevin Hilman } 5138bd22949SKevin Hilman 51492206fd2SPaul Walmsley (void) clkdm_for_each(omap_pm_clkdms_setup, NULL); 5158bd22949SKevin Hilman 5168bd22949SKevin Hilman mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); 5178bd22949SKevin Hilman if (mpu_pwrdm == NULL) { 51898179856SMark A. Greer pr_err("Failed to get mpu_pwrdm\n"); 519ce229c5dSMark A. Greer ret = -EINVAL; 520ce229c5dSMark A. Greer goto err3; 5218bd22949SKevin Hilman } 5228bd22949SKevin Hilman 523fa3c2a4fSRajendra Nayak neon_pwrdm = pwrdm_lookup("neon_pwrdm"); 524fa3c2a4fSRajendra Nayak per_pwrdm = pwrdm_lookup("per_pwrdm"); 525fa3c2a4fSRajendra Nayak core_pwrdm = pwrdm_lookup("core_pwrdm"); 526fa3c2a4fSRajendra Nayak 52755ed9694SPaul Walmsley neon_clkdm = clkdm_lookup("neon_clkdm"); 52855ed9694SPaul Walmsley mpu_clkdm = clkdm_lookup("mpu_clkdm"); 529856c3c5bSPaul Walmsley per_clkdm = clkdm_lookup("per_clkdm"); 530856c3c5bSPaul Walmsley wkup_clkdm = clkdm_lookup("wkup_clkdm"); 53155ed9694SPaul Walmsley 5322e4b62dcSDave Gerlach omap_common_suspend_init(omap3_pm_suspend); 5338bd22949SKevin Hilman 5340bcd24b0SNicolas Pitre arm_pm_idle = omap3_pm_idle; 5350343371eSKalle Jokiniemi omap3_idle_init(); 5368bd22949SKevin Hilman 537458e999eSNishanth Menon /* 538458e999eSNishanth Menon * RTA is disabled during initialization as per erratum i608 539458e999eSNishanth Menon * it is safer to disable RTA by the bootloader, but we would like 540458e999eSNishanth Menon * to be doubly sure here and prevent any mishaps. 541458e999eSNishanth Menon */ 542458e999eSNishanth Menon if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608)) 543458e999eSNishanth Menon omap3630_ctrl_disable_rta(); 544458e999eSNishanth Menon 545856c3c5bSPaul Walmsley /* 546856c3c5bSPaul Walmsley * The UART3/4 FIFO and the sidetone memory in McBSP2/3 are 547856c3c5bSPaul Walmsley * not correctly reset when the PER powerdomain comes back 548856c3c5bSPaul Walmsley * from OFF or OSWR when the CORE powerdomain is kept active. 549856c3c5bSPaul Walmsley * See OMAP36xx Erratum i582 "PER Domain reset issue after 550856c3c5bSPaul Walmsley * Domain-OFF/OSWR Wakeup". This wakeup dependency is not a 551856c3c5bSPaul Walmsley * complete workaround. The kernel must also prevent the PER 552856c3c5bSPaul Walmsley * powerdomain from going to OSWR/OFF while the CORE 553856c3c5bSPaul Walmsley * powerdomain is not going to OSWR/OFF. And if PER last 554856c3c5bSPaul Walmsley * power state was off while CORE last power state was ON, the 555856c3c5bSPaul Walmsley * UART3/4 and McBSP2/3 SIDETONE devices need to run a 556856c3c5bSPaul Walmsley * self-test using their loopback tests; if that fails, those 557856c3c5bSPaul Walmsley * devices are unusable until the PER/CORE can complete a transition 558856c3c5bSPaul Walmsley * from ON to OSWR/OFF and then back to ON. 559856c3c5bSPaul Walmsley * 560856c3c5bSPaul Walmsley * XXX Technically this workaround is only needed if off-mode 561856c3c5bSPaul Walmsley * or OSWR is enabled. 562856c3c5bSPaul Walmsley */ 563856c3c5bSPaul Walmsley if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582)) 564856c3c5bSPaul Walmsley clkdm_add_wkdep(per_clkdm, wkup_clkdm); 565856c3c5bSPaul Walmsley 56655ed9694SPaul Walmsley clkdm_add_wkdep(neon_clkdm, mpu_clkdm); 56727d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 56827d59a4aSTero Kristo omap3_secure_ram_storage = 569d09220a8STony Lindgren kmalloc(OMAP3_SAVE_SECURE_RAM_SZ, GFP_KERNEL); 57027d59a4aSTero Kristo if (!omap3_secure_ram_storage) 5717852ec05SPaul Walmsley pr_err("Memory allocation failed when allocating for secure sram context\n"); 57227d59a4aSTero Kristo 5739d97140bSTero Kristo local_irq_disable(); 5749d97140bSTero Kristo 575617fcc98SKevin Hilman omap3_save_secure_ram_context(); 5769d97140bSTero Kristo 5779d97140bSTero Kristo local_irq_enable(); 5789d97140bSTero Kristo } 5799d97140bSTero Kristo 5809d97140bSTero Kristo omap3_save_scratchpad_contents(); 5818bd22949SKevin Hilman return ret; 582ce229c5dSMark A. Greer 583ce229c5dSMark A. Greer err3: 5848bd22949SKevin Hilman list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { 5858bd22949SKevin Hilman list_del(&pwrst->node); 5868bd22949SKevin Hilman kfree(pwrst); 5878bd22949SKevin Hilman } 588ce229c5dSMark A. Greer free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init); 589ce229c5dSMark A. Greer err2: 590ce229c5dSMark A. Greer free_irq(omap_prcm_event_to_irq("wkup"), NULL); 591ce229c5dSMark A. Greer err1: 5928bd22949SKevin Hilman return ret; 5938bd22949SKevin Hilman } 594