18bd22949SKevin Hilman /* 28bd22949SKevin Hilman * OMAP3 Power Management Routines 38bd22949SKevin Hilman * 48bd22949SKevin Hilman * Copyright (C) 2006-2008 Nokia Corporation 58bd22949SKevin Hilman * Tony Lindgren <tony@atomide.com> 68bd22949SKevin Hilman * Jouni Hogander 78bd22949SKevin Hilman * 82f5939c3SRajendra Nayak * Copyright (C) 2007 Texas Instruments, Inc. 92f5939c3SRajendra Nayak * Rajendra Nayak <rnayak@ti.com> 102f5939c3SRajendra Nayak * 118bd22949SKevin Hilman * Copyright (C) 2005 Texas Instruments, Inc. 128bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 138bd22949SKevin Hilman * 148bd22949SKevin Hilman * Based on pm.c for omap1 158bd22949SKevin Hilman * 168bd22949SKevin Hilman * This program is free software; you can redistribute it and/or modify 178bd22949SKevin Hilman * it under the terms of the GNU General Public License version 2 as 188bd22949SKevin Hilman * published by the Free Software Foundation. 198bd22949SKevin Hilman */ 208bd22949SKevin Hilman 218bd22949SKevin Hilman #include <linux/pm.h> 228bd22949SKevin Hilman #include <linux/suspend.h> 238bd22949SKevin Hilman #include <linux/interrupt.h> 248bd22949SKevin Hilman #include <linux/module.h> 258bd22949SKevin Hilman #include <linux/list.h> 268bd22949SKevin Hilman #include <linux/err.h> 278bd22949SKevin Hilman #include <linux/gpio.h> 28c40552bcSKevin Hilman #include <linux/clk.h> 298bd22949SKevin Hilman 30ce491cf8STony Lindgren #include <plat/sram.h> 31ce491cf8STony Lindgren #include <plat/clockdomain.h> 32ce491cf8STony Lindgren #include <plat/powerdomain.h> 33ce491cf8STony Lindgren #include <plat/control.h> 34ce491cf8STony Lindgren #include <plat/serial.h> 3561255ab9SRajendra Nayak #include <plat/sdrc.h> 362f5939c3SRajendra Nayak #include <plat/prcm.h> 372f5939c3SRajendra Nayak #include <plat/gpmc.h> 38f2d11858STero Kristo #include <plat/dma.h> 39d7814e4dSKevin Hilman #include <plat/dmtimer.h> 408bd22949SKevin Hilman 4157f277b0SRajendra Nayak #include <asm/tlbflush.h> 4257f277b0SRajendra Nayak 438bd22949SKevin Hilman #include "cm.h" 448bd22949SKevin Hilman #include "cm-regbits-34xx.h" 458bd22949SKevin Hilman #include "prm-regbits-34xx.h" 468bd22949SKevin Hilman 478bd22949SKevin Hilman #include "prm.h" 488bd22949SKevin Hilman #include "pm.h" 4913a6fe0fSTero Kristo #include "sdrc.h" 5013a6fe0fSTero Kristo 512f5939c3SRajendra Nayak /* Scratchpad offsets */ 522f5939c3SRajendra Nayak #define OMAP343X_TABLE_ADDRESS_OFFSET 0x31 532f5939c3SRajendra Nayak #define OMAP343X_TABLE_VALUE_OFFSET 0x30 542f5939c3SRajendra Nayak #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32 552f5939c3SRajendra Nayak 56c40552bcSKevin Hilman u32 enable_off_mode; 57c40552bcSKevin Hilman u32 sleep_while_idle; 58d7814e4dSKevin Hilman u32 wakeup_timer_seconds; 59c40552bcSKevin Hilman 608bd22949SKevin Hilman struct power_state { 618bd22949SKevin Hilman struct powerdomain *pwrdm; 628bd22949SKevin Hilman u32 next_state; 6310f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 648bd22949SKevin Hilman u32 saved_state; 6510f90ed2SKevin Hilman #endif 668bd22949SKevin Hilman struct list_head node; 678bd22949SKevin Hilman }; 688bd22949SKevin Hilman 698bd22949SKevin Hilman static LIST_HEAD(pwrst_list); 708bd22949SKevin Hilman 718bd22949SKevin Hilman static void (*_omap_sram_idle)(u32 *addr, int save_state); 728bd22949SKevin Hilman 7327d59a4aSTero Kristo static int (*_omap_save_secure_sram)(u32 *addr); 7427d59a4aSTero Kristo 75fa3c2a4fSRajendra Nayak static struct powerdomain *mpu_pwrdm, *neon_pwrdm; 76fa3c2a4fSRajendra Nayak static struct powerdomain *core_pwrdm, *per_pwrdm; 77c16c3f67STero Kristo static struct powerdomain *cam_pwrdm; 78fa3c2a4fSRajendra Nayak 79fa3c2a4fSRajendra Nayak static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state); 808bd22949SKevin Hilman 812f5939c3SRajendra Nayak static inline void omap3_per_save_context(void) 822f5939c3SRajendra Nayak { 832f5939c3SRajendra Nayak omap_gpio_save_context(); 842f5939c3SRajendra Nayak } 852f5939c3SRajendra Nayak 862f5939c3SRajendra Nayak static inline void omap3_per_restore_context(void) 872f5939c3SRajendra Nayak { 882f5939c3SRajendra Nayak omap_gpio_restore_context(); 892f5939c3SRajendra Nayak } 902f5939c3SRajendra Nayak 913a7ec26bSKalle Jokiniemi static void omap3_enable_io_chain(void) 923a7ec26bSKalle Jokiniemi { 933a7ec26bSKalle Jokiniemi int timeout = 0; 943a7ec26bSKalle Jokiniemi 953a7ec26bSKalle Jokiniemi if (omap_rev() >= OMAP3430_REV_ES3_1) { 963a7ec26bSKalle Jokiniemi prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN); 973a7ec26bSKalle Jokiniemi /* Do a readback to assure write has been done */ 983a7ec26bSKalle Jokiniemi prm_read_mod_reg(WKUP_MOD, PM_WKEN); 993a7ec26bSKalle Jokiniemi 1003a7ec26bSKalle Jokiniemi while (!(prm_read_mod_reg(WKUP_MOD, PM_WKST) & 1013a7ec26bSKalle Jokiniemi OMAP3430_ST_IO_CHAIN)) { 1023a7ec26bSKalle Jokiniemi timeout++; 1033a7ec26bSKalle Jokiniemi if (timeout > 1000) { 1043a7ec26bSKalle Jokiniemi printk(KERN_ERR "Wake up daisy chain " 1053a7ec26bSKalle Jokiniemi "activation failed.\n"); 1063a7ec26bSKalle Jokiniemi return; 1073a7ec26bSKalle Jokiniemi } 1083a7ec26bSKalle Jokiniemi prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN, 1093a7ec26bSKalle Jokiniemi WKUP_MOD, PM_WKST); 1103a7ec26bSKalle Jokiniemi } 1113a7ec26bSKalle Jokiniemi } 1123a7ec26bSKalle Jokiniemi } 1133a7ec26bSKalle Jokiniemi 1143a7ec26bSKalle Jokiniemi static void omap3_disable_io_chain(void) 1153a7ec26bSKalle Jokiniemi { 1163a7ec26bSKalle Jokiniemi if (omap_rev() >= OMAP3430_REV_ES3_1) 1173a7ec26bSKalle Jokiniemi prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN); 1183a7ec26bSKalle Jokiniemi } 1193a7ec26bSKalle Jokiniemi 1202f5939c3SRajendra Nayak static void omap3_core_save_context(void) 1212f5939c3SRajendra Nayak { 1222f5939c3SRajendra Nayak u32 control_padconf_off; 1232f5939c3SRajendra Nayak 1242f5939c3SRajendra Nayak /* Save the padconf registers */ 1252f5939c3SRajendra Nayak control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF); 1262f5939c3SRajendra Nayak control_padconf_off |= START_PADCONF_SAVE; 1272f5939c3SRajendra Nayak omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF); 1282f5939c3SRajendra Nayak /* wait for the save to complete */ 1292f5939c3SRajendra Nayak while (!omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) 1302f5939c3SRajendra Nayak & PADCONF_SAVE_DONE) 1312f5939c3SRajendra Nayak ; 1322f5939c3SRajendra Nayak /* Save the Interrupt controller context */ 1332f5939c3SRajendra Nayak omap_intc_save_context(); 1342f5939c3SRajendra Nayak /* Save the GPMC context */ 1352f5939c3SRajendra Nayak omap3_gpmc_save_context(); 1362f5939c3SRajendra Nayak /* Save the system control module context, padconf already save above*/ 1372f5939c3SRajendra Nayak omap3_control_save_context(); 138f2d11858STero Kristo omap_dma_global_context_save(); 1392f5939c3SRajendra Nayak } 1402f5939c3SRajendra Nayak 1412f5939c3SRajendra Nayak static void omap3_core_restore_context(void) 1422f5939c3SRajendra Nayak { 1432f5939c3SRajendra Nayak /* Restore the control module context, padconf restored by h/w */ 1442f5939c3SRajendra Nayak omap3_control_restore_context(); 1452f5939c3SRajendra Nayak /* Restore the GPMC context */ 1462f5939c3SRajendra Nayak omap3_gpmc_restore_context(); 1472f5939c3SRajendra Nayak /* Restore the interrupt controller context */ 1482f5939c3SRajendra Nayak omap_intc_restore_context(); 149f2d11858STero Kristo omap_dma_global_context_restore(); 1502f5939c3SRajendra Nayak } 1512f5939c3SRajendra Nayak 1529d97140bSTero Kristo /* 1539d97140bSTero Kristo * FIXME: This function should be called before entering off-mode after 1549d97140bSTero Kristo * OMAP3 secure services have been accessed. Currently it is only called 1559d97140bSTero Kristo * once during boot sequence, but this works as we are not using secure 1569d97140bSTero Kristo * services. 1579d97140bSTero Kristo */ 15827d59a4aSTero Kristo static void omap3_save_secure_ram_context(u32 target_mpu_state) 15927d59a4aSTero Kristo { 16027d59a4aSTero Kristo u32 ret; 16127d59a4aSTero Kristo 16227d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 16327d59a4aSTero Kristo /* 16427d59a4aSTero Kristo * MPU next state must be set to POWER_ON temporarily, 16527d59a4aSTero Kristo * otherwise the WFI executed inside the ROM code 16627d59a4aSTero Kristo * will hang the system. 16727d59a4aSTero Kristo */ 16827d59a4aSTero Kristo pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); 16927d59a4aSTero Kristo ret = _omap_save_secure_sram((u32 *) 17027d59a4aSTero Kristo __pa(omap3_secure_ram_storage)); 17127d59a4aSTero Kristo pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state); 17227d59a4aSTero Kristo /* Following is for error tracking, it should not happen */ 17327d59a4aSTero Kristo if (ret) { 17427d59a4aSTero Kristo printk(KERN_ERR "save_secure_sram() returns %08x\n", 17527d59a4aSTero Kristo ret); 17627d59a4aSTero Kristo while (1) 17727d59a4aSTero Kristo ; 17827d59a4aSTero Kristo } 17927d59a4aSTero Kristo } 18027d59a4aSTero Kristo } 18127d59a4aSTero Kristo 18277da2d91SJon Hunter /* 18377da2d91SJon Hunter * PRCM Interrupt Handler Helper Function 18477da2d91SJon Hunter * 18577da2d91SJon Hunter * The purpose of this function is to clear any wake-up events latched 18677da2d91SJon Hunter * in the PRCM PM_WKST_x registers. It is possible that a wake-up event 18777da2d91SJon Hunter * may occur whilst attempting to clear a PM_WKST_x register and thus 18877da2d91SJon Hunter * set another bit in this register. A while loop is used to ensure 18977da2d91SJon Hunter * that any peripheral wake-up events occurring while attempting to 19077da2d91SJon Hunter * clear the PM_WKST_x are detected and cleared. 19177da2d91SJon Hunter */ 1928cb0ac99SPaul Walmsley static int prcm_clear_mod_irqs(s16 module, u8 regs) 19377da2d91SJon Hunter { 19471a80775SVikram Pandita u32 wkst, fclk, iclk, clken; 19577da2d91SJon Hunter u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; 19677da2d91SJon Hunter u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; 19777da2d91SJon Hunter u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; 1985d805978SPaul Walmsley u16 grpsel_off = (regs == 3) ? 1995d805978SPaul Walmsley OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; 2008cb0ac99SPaul Walmsley int c = 0; 20177da2d91SJon Hunter 20277da2d91SJon Hunter wkst = prm_read_mod_reg(module, wkst_off); 2035d805978SPaul Walmsley wkst &= prm_read_mod_reg(module, grpsel_off); 20477da2d91SJon Hunter if (wkst) { 20577da2d91SJon Hunter iclk = cm_read_mod_reg(module, iclk_off); 20677da2d91SJon Hunter fclk = cm_read_mod_reg(module, fclk_off); 20777da2d91SJon Hunter while (wkst) { 20871a80775SVikram Pandita clken = wkst; 20971a80775SVikram Pandita cm_set_mod_reg_bits(clken, module, iclk_off); 21071a80775SVikram Pandita /* 21171a80775SVikram Pandita * For USBHOST, we don't know whether HOST1 or 21271a80775SVikram Pandita * HOST2 woke us up, so enable both f-clocks 21371a80775SVikram Pandita */ 21471a80775SVikram Pandita if (module == OMAP3430ES2_USBHOST_MOD) 21571a80775SVikram Pandita clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; 21671a80775SVikram Pandita cm_set_mod_reg_bits(clken, module, fclk_off); 21777da2d91SJon Hunter prm_write_mod_reg(wkst, module, wkst_off); 21877da2d91SJon Hunter wkst = prm_read_mod_reg(module, wkst_off); 2198cb0ac99SPaul Walmsley c++; 22077da2d91SJon Hunter } 22177da2d91SJon Hunter cm_write_mod_reg(iclk, module, iclk_off); 22277da2d91SJon Hunter cm_write_mod_reg(fclk, module, fclk_off); 22377da2d91SJon Hunter } 2248cb0ac99SPaul Walmsley 2258cb0ac99SPaul Walmsley return c; 2268cb0ac99SPaul Walmsley } 2278cb0ac99SPaul Walmsley 2288cb0ac99SPaul Walmsley static int _prcm_int_handle_wakeup(void) 2298cb0ac99SPaul Walmsley { 2308cb0ac99SPaul Walmsley int c; 2318cb0ac99SPaul Walmsley 2328cb0ac99SPaul Walmsley c = prcm_clear_mod_irqs(WKUP_MOD, 1); 2338cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(CORE_MOD, 1); 2348cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1); 2358cb0ac99SPaul Walmsley if (omap_rev() > OMAP3430_REV_ES1_0) { 2368cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(CORE_MOD, 3); 2378cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1); 2388cb0ac99SPaul Walmsley } 2398cb0ac99SPaul Walmsley 2408cb0ac99SPaul Walmsley return c; 24177da2d91SJon Hunter } 24277da2d91SJon Hunter 24377da2d91SJon Hunter /* 24477da2d91SJon Hunter * PRCM Interrupt Handler 24577da2d91SJon Hunter * 24677da2d91SJon Hunter * The PRM_IRQSTATUS_MPU register indicates if there are any pending 24777da2d91SJon Hunter * interrupts from the PRCM for the MPU. These bits must be cleared in 24877da2d91SJon Hunter * order to clear the PRCM interrupt. The PRCM interrupt handler is 24977da2d91SJon Hunter * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear 25077da2d91SJon Hunter * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU 25177da2d91SJon Hunter * register indicates that a wake-up event is pending for the MPU and 25277da2d91SJon Hunter * this bit can only be cleared if the all the wake-up events latched 25377da2d91SJon Hunter * in the various PM_WKST_x registers have been cleared. The interrupt 25477da2d91SJon Hunter * handler is implemented using a do-while loop so that if a wake-up 25577da2d91SJon Hunter * event occurred during the processing of the prcm interrupt handler 25677da2d91SJon Hunter * (setting a bit in the corresponding PM_WKST_x register and thus 25777da2d91SJon Hunter * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register) 25877da2d91SJon Hunter * this would be handled. 25977da2d91SJon Hunter */ 2608bd22949SKevin Hilman static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) 2618bd22949SKevin Hilman { 26277da2d91SJon Hunter u32 irqstatus_mpu; 2638cb0ac99SPaul Walmsley int c = 0; 2648bd22949SKevin Hilman 26577da2d91SJon Hunter do { 2668bd22949SKevin Hilman irqstatus_mpu = prm_read_mod_reg(OCP_MOD, 2678bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 2688cb0ac99SPaul Walmsley 2698cb0ac99SPaul Walmsley if (irqstatus_mpu & (OMAP3430_WKUP_ST | OMAP3430_IO_ST)) { 2708cb0ac99SPaul Walmsley c = _prcm_int_handle_wakeup(); 2718cb0ac99SPaul Walmsley 2728cb0ac99SPaul Walmsley /* 2738cb0ac99SPaul Walmsley * Is the MPU PRCM interrupt handler racing with the 2748cb0ac99SPaul Walmsley * IVA2 PRCM interrupt handler ? 2758cb0ac99SPaul Walmsley */ 2768cb0ac99SPaul Walmsley WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup " 2778cb0ac99SPaul Walmsley "but no wakeup sources are marked\n"); 2788cb0ac99SPaul Walmsley } else { 2798cb0ac99SPaul Walmsley /* XXX we need to expand our PRCM interrupt handler */ 2808cb0ac99SPaul Walmsley WARN(1, "prcm: WARNING: PRCM interrupt received, but " 2818cb0ac99SPaul Walmsley "no code to handle it (%08x)\n", irqstatus_mpu); 2828cb0ac99SPaul Walmsley } 2838cb0ac99SPaul Walmsley 2848bd22949SKevin Hilman prm_write_mod_reg(irqstatus_mpu, OCP_MOD, 2858bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 2868bd22949SKevin Hilman 28777da2d91SJon Hunter } while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET)); 2888bd22949SKevin Hilman 2898bd22949SKevin Hilman return IRQ_HANDLED; 2908bd22949SKevin Hilman } 2918bd22949SKevin Hilman 29257f277b0SRajendra Nayak static void restore_control_register(u32 val) 29357f277b0SRajendra Nayak { 29457f277b0SRajendra Nayak __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val)); 29557f277b0SRajendra Nayak } 29657f277b0SRajendra Nayak 29757f277b0SRajendra Nayak /* Function to restore the table entry that was modified for enabling MMU */ 29857f277b0SRajendra Nayak static void restore_table_entry(void) 29957f277b0SRajendra Nayak { 30057f277b0SRajendra Nayak u32 *scratchpad_address; 30157f277b0SRajendra Nayak u32 previous_value, control_reg_value; 30257f277b0SRajendra Nayak u32 *address; 30357f277b0SRajendra Nayak 30457f277b0SRajendra Nayak scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD); 30557f277b0SRajendra Nayak 30657f277b0SRajendra Nayak /* Get address of entry that was modified */ 30757f277b0SRajendra Nayak address = (u32 *)__raw_readl(scratchpad_address + 30857f277b0SRajendra Nayak OMAP343X_TABLE_ADDRESS_OFFSET); 30957f277b0SRajendra Nayak /* Get the previous value which needs to be restored */ 31057f277b0SRajendra Nayak previous_value = __raw_readl(scratchpad_address + 31157f277b0SRajendra Nayak OMAP343X_TABLE_VALUE_OFFSET); 31257f277b0SRajendra Nayak address = __va(address); 31357f277b0SRajendra Nayak *address = previous_value; 31457f277b0SRajendra Nayak flush_tlb_all(); 31557f277b0SRajendra Nayak control_reg_value = __raw_readl(scratchpad_address 31657f277b0SRajendra Nayak + OMAP343X_CONTROL_REG_VALUE_OFFSET); 31757f277b0SRajendra Nayak /* This will enable caches and prediction */ 31857f277b0SRajendra Nayak restore_control_register(control_reg_value); 31957f277b0SRajendra Nayak } 32057f277b0SRajendra Nayak 3218bd22949SKevin Hilman static void omap_sram_idle(void) 3228bd22949SKevin Hilman { 3238bd22949SKevin Hilman /* Variable to tell what needs to be saved and restored 3248bd22949SKevin Hilman * in omap_sram_idle*/ 3258bd22949SKevin Hilman /* save_state = 0 => Nothing to save and restored */ 3268bd22949SKevin Hilman /* save_state = 1 => Only L1 and logic lost */ 3278bd22949SKevin Hilman /* save_state = 2 => Only L2 lost */ 3288bd22949SKevin Hilman /* save_state = 3 => L1, L2 and logic lost */ 329fa3c2a4fSRajendra Nayak int save_state = 0; 330fa3c2a4fSRajendra Nayak int mpu_next_state = PWRDM_POWER_ON; 331fa3c2a4fSRajendra Nayak int per_next_state = PWRDM_POWER_ON; 332fa3c2a4fSRajendra Nayak int core_next_state = PWRDM_POWER_ON; 3332f5939c3SRajendra Nayak int core_prev_state, per_prev_state; 33413a6fe0fSTero Kristo u32 sdrc_pwr = 0; 335ecf157d0STero Kristo int per_state_modified = 0; 3368bd22949SKevin Hilman 3378bd22949SKevin Hilman if (!_omap_sram_idle) 3388bd22949SKevin Hilman return; 3398bd22949SKevin Hilman 340fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(mpu_pwrdm); 341fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(neon_pwrdm); 342fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(core_pwrdm); 343fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(per_pwrdm); 344fa3c2a4fSRajendra Nayak 3458bd22949SKevin Hilman mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 3468bd22949SKevin Hilman switch (mpu_next_state) { 347fa3c2a4fSRajendra Nayak case PWRDM_POWER_ON: 3488bd22949SKevin Hilman case PWRDM_POWER_RET: 3498bd22949SKevin Hilman /* No need to save context */ 3508bd22949SKevin Hilman save_state = 0; 3518bd22949SKevin Hilman break; 35261255ab9SRajendra Nayak case PWRDM_POWER_OFF: 35361255ab9SRajendra Nayak save_state = 3; 35461255ab9SRajendra Nayak break; 3558bd22949SKevin Hilman default: 3568bd22949SKevin Hilman /* Invalid state */ 3578bd22949SKevin Hilman printk(KERN_ERR "Invalid mpu state in sram_idle\n"); 3588bd22949SKevin Hilman return; 3598bd22949SKevin Hilman } 360fe617af7SPeter 'p2' De Schrijver pwrdm_pre_transition(); 361fe617af7SPeter 'p2' De Schrijver 362fa3c2a4fSRajendra Nayak /* NEON control */ 363fa3c2a4fSRajendra Nayak if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) 364fa3c2a4fSRajendra Nayak set_pwrdm_state(neon_pwrdm, mpu_next_state); 365fa3c2a4fSRajendra Nayak 366658ce97eSKevin Hilman /* PER */ 367fa3c2a4fSRajendra Nayak per_next_state = pwrdm_read_next_pwrst(per_pwrdm); 368ecf157d0STero Kristo core_next_state = pwrdm_read_next_pwrst(core_pwrdm); 3692f5939c3SRajendra Nayak if (per_next_state < PWRDM_POWER_ON) { 3704af4016cSKevin Hilman omap_uart_prepare_idle(2); 371ecf157d0STero Kristo omap2_gpio_prepare_for_retention(); 372ecf157d0STero Kristo if (per_next_state == PWRDM_POWER_OFF) { 373ecf157d0STero Kristo if (core_next_state == PWRDM_POWER_ON) { 374ecf157d0STero Kristo per_next_state = PWRDM_POWER_RET; 375ecf157d0STero Kristo pwrdm_set_next_pwrst(per_pwrdm, per_next_state); 376ecf157d0STero Kristo per_state_modified = 1; 377ecf157d0STero Kristo } else 3782f5939c3SRajendra Nayak omap3_per_save_context(); 3792f5939c3SRajendra Nayak } 380ecf157d0STero Kristo } 381658ce97eSKevin Hilman 382c16c3f67STero Kristo if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON) 383c16c3f67STero Kristo omap2_clkdm_deny_idle(mpu_pwrdm->pwrdm_clkdms[0]); 384c16c3f67STero Kristo 385658ce97eSKevin Hilman /* CORE */ 386658ce97eSKevin Hilman if (core_next_state < PWRDM_POWER_ON) { 387658ce97eSKevin Hilman omap_uart_prepare_idle(0); 388658ce97eSKevin Hilman omap_uart_prepare_idle(1); 3892f5939c3SRajendra Nayak if (core_next_state == PWRDM_POWER_OFF) { 3902f5939c3SRajendra Nayak omap3_core_save_context(); 3912f5939c3SRajendra Nayak omap3_prcm_save_context(); 3922f5939c3SRajendra Nayak } 3933a7ec26bSKalle Jokiniemi /* Enable IO-PAD and IO-CHAIN wakeups */ 394fa3c2a4fSRajendra Nayak prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN); 3953a7ec26bSKalle Jokiniemi omap3_enable_io_chain(); 396fa3c2a4fSRajendra Nayak } 3978bd22949SKevin Hilman 39861255ab9SRajendra Nayak /* 399f265dc4cSRajendra Nayak * On EMU/HS devices ROM code restores a SRDC value 400f265dc4cSRajendra Nayak * from scratchpad which has automatic self refresh on timeout 401f265dc4cSRajendra Nayak * of AUTO_CNT = 1 enabled. This takes care of errata 1.142. 402f265dc4cSRajendra Nayak * Hence store/restore the SDRC_POWER register here. 40313a6fe0fSTero Kristo */ 40413a6fe0fSTero Kristo if (omap_rev() >= OMAP3430_REV_ES3_0 && 40513a6fe0fSTero Kristo omap_type() != OMAP2_DEVICE_TYPE_GP && 406f265dc4cSRajendra Nayak core_next_state == PWRDM_POWER_OFF) 40713a6fe0fSTero Kristo sdrc_pwr = sdrc_read_reg(SDRC_POWER); 40813a6fe0fSTero Kristo 40913a6fe0fSTero Kristo /* 41061255ab9SRajendra Nayak * omap3_arm_context is the location where ARM registers 41161255ab9SRajendra Nayak * get saved. The restore path then reads from this 41261255ab9SRajendra Nayak * location and restores them back. 41361255ab9SRajendra Nayak */ 41461255ab9SRajendra Nayak _omap_sram_idle(omap3_arm_context, save_state); 4158bd22949SKevin Hilman cpu_init(); 4168bd22949SKevin Hilman 417f265dc4cSRajendra Nayak /* Restore normal SDRC POWER settings */ 41813a6fe0fSTero Kristo if (omap_rev() >= OMAP3430_REV_ES3_0 && 41913a6fe0fSTero Kristo omap_type() != OMAP2_DEVICE_TYPE_GP && 42013a6fe0fSTero Kristo core_next_state == PWRDM_POWER_OFF) 42113a6fe0fSTero Kristo sdrc_write_reg(sdrc_pwr, SDRC_POWER); 42213a6fe0fSTero Kristo 42357f277b0SRajendra Nayak /* Restore table entry modified during MMU restoration */ 42457f277b0SRajendra Nayak if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF) 42557f277b0SRajendra Nayak restore_table_entry(); 42657f277b0SRajendra Nayak 427658ce97eSKevin Hilman /* CORE */ 428fa3c2a4fSRajendra Nayak if (core_next_state < PWRDM_POWER_ON) { 4292f5939c3SRajendra Nayak core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); 4302f5939c3SRajendra Nayak if (core_prev_state == PWRDM_POWER_OFF) { 4312f5939c3SRajendra Nayak omap3_core_restore_context(); 4322f5939c3SRajendra Nayak omap3_prcm_restore_context(); 4332f5939c3SRajendra Nayak omap3_sram_restore_context(); 4348a917d2fSKalle Jokiniemi omap2_sms_restore_context(); 4352f5939c3SRajendra Nayak } 436658ce97eSKevin Hilman omap_uart_resume_idle(0); 437658ce97eSKevin Hilman omap_uart_resume_idle(1); 438658ce97eSKevin Hilman if (core_next_state == PWRDM_POWER_OFF) 439658ce97eSKevin Hilman prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF, 440658ce97eSKevin Hilman OMAP3430_GR_MOD, 441658ce97eSKevin Hilman OMAP3_PRM_VOLTCTRL_OFFSET); 442658ce97eSKevin Hilman } 443658ce97eSKevin Hilman 444658ce97eSKevin Hilman /* PER */ 4452f5939c3SRajendra Nayak if (per_next_state < PWRDM_POWER_ON) { 446658ce97eSKevin Hilman per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); 4472f5939c3SRajendra Nayak if (per_prev_state == PWRDM_POWER_OFF) 4482f5939c3SRajendra Nayak omap3_per_restore_context(); 4498bd22949SKevin Hilman omap2_gpio_resume_after_retention(); 450ecf157d0STero Kristo omap_uart_resume_idle(2); 451ecf157d0STero Kristo if (per_state_modified) 452ecf157d0STero Kristo pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF); 453fa3c2a4fSRajendra Nayak } 454fe617af7SPeter 'p2' De Schrijver 4553a7ec26bSKalle Jokiniemi /* Disable IO-PAD and IO-CHAIN wakeup */ 4563a7ec26bSKalle Jokiniemi if (core_next_state < PWRDM_POWER_ON) { 457658ce97eSKevin Hilman prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN); 4583a7ec26bSKalle Jokiniemi omap3_disable_io_chain(); 4593a7ec26bSKalle Jokiniemi } 460658ce97eSKevin Hilman 461fe617af7SPeter 'p2' De Schrijver pwrdm_post_transition(); 462fe617af7SPeter 'p2' De Schrijver 463c16c3f67STero Kristo omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); 4648bd22949SKevin Hilman } 4658bd22949SKevin Hilman 4668bd22949SKevin Hilman /* 4678bd22949SKevin Hilman * Check if functional clocks are enabled before entering 4688bd22949SKevin Hilman * sleep. This function could be behind CONFIG_PM_DEBUG 4698bd22949SKevin Hilman * when all drivers are configuring their sysconfig registers 4708bd22949SKevin Hilman * properly and using their clocks properly. 4718bd22949SKevin Hilman */ 4728bd22949SKevin Hilman static int omap3_fclks_active(void) 4738bd22949SKevin Hilman { 4748bd22949SKevin Hilman u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0, 4758bd22949SKevin Hilman fck_cam = 0, fck_per = 0, fck_usbhost = 0; 4768bd22949SKevin Hilman 4778bd22949SKevin Hilman fck_core1 = cm_read_mod_reg(CORE_MOD, 4788bd22949SKevin Hilman CM_FCLKEN1); 4798bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 4808bd22949SKevin Hilman fck_core3 = cm_read_mod_reg(CORE_MOD, 4818bd22949SKevin Hilman OMAP3430ES2_CM_FCLKEN3); 4828bd22949SKevin Hilman fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD, 4838bd22949SKevin Hilman CM_FCLKEN); 4848bd22949SKevin Hilman fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, 4858bd22949SKevin Hilman CM_FCLKEN); 4868bd22949SKevin Hilman } else 4878bd22949SKevin Hilman fck_sgx = cm_read_mod_reg(GFX_MOD, 4888bd22949SKevin Hilman OMAP3430ES2_CM_FCLKEN3); 4898bd22949SKevin Hilman fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD, 4908bd22949SKevin Hilman CM_FCLKEN); 4918bd22949SKevin Hilman fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD, 4928bd22949SKevin Hilman CM_FCLKEN); 4938bd22949SKevin Hilman fck_per = cm_read_mod_reg(OMAP3430_PER_MOD, 4948bd22949SKevin Hilman CM_FCLKEN); 4954af4016cSKevin Hilman 4964af4016cSKevin Hilman /* Ignore UART clocks. These are handled by UART core (serial.c) */ 4974af4016cSKevin Hilman fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2); 4984af4016cSKevin Hilman fck_per &= ~OMAP3430_EN_UART3; 4994af4016cSKevin Hilman 5008bd22949SKevin Hilman if (fck_core1 | fck_core3 | fck_sgx | fck_dss | 5018bd22949SKevin Hilman fck_cam | fck_per | fck_usbhost) 5028bd22949SKevin Hilman return 1; 5038bd22949SKevin Hilman return 0; 5048bd22949SKevin Hilman } 5058bd22949SKevin Hilman 5068bd22949SKevin Hilman static int omap3_can_sleep(void) 5078bd22949SKevin Hilman { 508c40552bcSKevin Hilman if (!sleep_while_idle) 509c40552bcSKevin Hilman return 0; 5104af4016cSKevin Hilman if (!omap_uart_can_sleep()) 5114af4016cSKevin Hilman return 0; 5128bd22949SKevin Hilman if (omap3_fclks_active()) 5138bd22949SKevin Hilman return 0; 5148bd22949SKevin Hilman return 1; 5158bd22949SKevin Hilman } 5168bd22949SKevin Hilman 5178bd22949SKevin Hilman /* This sets pwrdm state (other than mpu & core. Currently only ON & 5188bd22949SKevin Hilman * RET are supported. Function is assuming that clkdm doesn't have 5198bd22949SKevin Hilman * hw_sup mode enabled. */ 5208bd22949SKevin Hilman static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state) 5218bd22949SKevin Hilman { 5228bd22949SKevin Hilman u32 cur_state; 5238bd22949SKevin Hilman int sleep_switch = 0; 5248bd22949SKevin Hilman int ret = 0; 5258bd22949SKevin Hilman 5268bd22949SKevin Hilman if (pwrdm == NULL || IS_ERR(pwrdm)) 5278bd22949SKevin Hilman return -EINVAL; 5288bd22949SKevin Hilman 5298bd22949SKevin Hilman while (!(pwrdm->pwrsts & (1 << state))) { 5308bd22949SKevin Hilman if (state == PWRDM_POWER_OFF) 5318bd22949SKevin Hilman return ret; 5328bd22949SKevin Hilman state--; 5338bd22949SKevin Hilman } 5348bd22949SKevin Hilman 5358bd22949SKevin Hilman cur_state = pwrdm_read_next_pwrst(pwrdm); 5368bd22949SKevin Hilman if (cur_state == state) 5378bd22949SKevin Hilman return ret; 5388bd22949SKevin Hilman 5398bd22949SKevin Hilman if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) { 5408bd22949SKevin Hilman omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); 5418bd22949SKevin Hilman sleep_switch = 1; 5428bd22949SKevin Hilman pwrdm_wait_transition(pwrdm); 5438bd22949SKevin Hilman } 5448bd22949SKevin Hilman 5458bd22949SKevin Hilman ret = pwrdm_set_next_pwrst(pwrdm, state); 5468bd22949SKevin Hilman if (ret) { 5478bd22949SKevin Hilman printk(KERN_ERR "Unable to set state of powerdomain: %s\n", 5488bd22949SKevin Hilman pwrdm->name); 5498bd22949SKevin Hilman goto err; 5508bd22949SKevin Hilman } 5518bd22949SKevin Hilman 5528bd22949SKevin Hilman if (sleep_switch) { 5538bd22949SKevin Hilman omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); 5548bd22949SKevin Hilman pwrdm_wait_transition(pwrdm); 555fe617af7SPeter 'p2' De Schrijver pwrdm_state_switch(pwrdm); 5568bd22949SKevin Hilman } 5578bd22949SKevin Hilman 5588bd22949SKevin Hilman err: 5598bd22949SKevin Hilman return ret; 5608bd22949SKevin Hilman } 5618bd22949SKevin Hilman 5628bd22949SKevin Hilman static void omap3_pm_idle(void) 5638bd22949SKevin Hilman { 5648bd22949SKevin Hilman local_irq_disable(); 5658bd22949SKevin Hilman local_fiq_disable(); 5668bd22949SKevin Hilman 5678bd22949SKevin Hilman if (!omap3_can_sleep()) 5688bd22949SKevin Hilman goto out; 5698bd22949SKevin Hilman 5708bd22949SKevin Hilman if (omap_irq_pending()) 5718bd22949SKevin Hilman goto out; 5728bd22949SKevin Hilman 5738bd22949SKevin Hilman omap_sram_idle(); 5748bd22949SKevin Hilman 5758bd22949SKevin Hilman out: 5768bd22949SKevin Hilman local_fiq_enable(); 5778bd22949SKevin Hilman local_irq_enable(); 5788bd22949SKevin Hilman } 5798bd22949SKevin Hilman 58010f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 5812466211eSTero Kristo static suspend_state_t suspend_state; 5822466211eSTero Kristo 583d7814e4dSKevin Hilman static void omap2_pm_wakeup_on_timer(u32 seconds) 584d7814e4dSKevin Hilman { 585d7814e4dSKevin Hilman u32 tick_rate, cycles; 586d7814e4dSKevin Hilman 587d7814e4dSKevin Hilman if (!seconds) 588d7814e4dSKevin Hilman return; 589d7814e4dSKevin Hilman 590d7814e4dSKevin Hilman tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup)); 591d7814e4dSKevin Hilman cycles = tick_rate * seconds; 592d7814e4dSKevin Hilman omap_dm_timer_stop(gptimer_wakeup); 593d7814e4dSKevin Hilman omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles); 594d7814e4dSKevin Hilman 595d7814e4dSKevin Hilman pr_info("PM: Resume timer in %d secs (%d ticks at %d ticks/sec.)\n", 596d7814e4dSKevin Hilman seconds, cycles, tick_rate); 597d7814e4dSKevin Hilman } 598d7814e4dSKevin Hilman 5998bd22949SKevin Hilman static int omap3_pm_prepare(void) 6008bd22949SKevin Hilman { 6018bd22949SKevin Hilman disable_hlt(); 6028bd22949SKevin Hilman return 0; 6038bd22949SKevin Hilman } 6048bd22949SKevin Hilman 6058bd22949SKevin Hilman static int omap3_pm_suspend(void) 6068bd22949SKevin Hilman { 6078bd22949SKevin Hilman struct power_state *pwrst; 6088bd22949SKevin Hilman int state, ret = 0; 6098bd22949SKevin Hilman 610d7814e4dSKevin Hilman if (wakeup_timer_seconds) 611d7814e4dSKevin Hilman omap2_pm_wakeup_on_timer(wakeup_timer_seconds); 612d7814e4dSKevin Hilman 6138bd22949SKevin Hilman /* Read current next_pwrsts */ 6148bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) 6158bd22949SKevin Hilman pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 6168bd22949SKevin Hilman /* Set ones wanted by suspend */ 6178bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 6188bd22949SKevin Hilman if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) 6198bd22949SKevin Hilman goto restore; 6208bd22949SKevin Hilman if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) 6218bd22949SKevin Hilman goto restore; 6228bd22949SKevin Hilman } 6238bd22949SKevin Hilman 6244af4016cSKevin Hilman omap_uart_prepare_suspend(); 6258bd22949SKevin Hilman omap_sram_idle(); 6268bd22949SKevin Hilman 6278bd22949SKevin Hilman restore: 6288bd22949SKevin Hilman /* Restore next_pwrsts */ 6298bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 6308bd22949SKevin Hilman state = pwrdm_read_prev_pwrst(pwrst->pwrdm); 6318bd22949SKevin Hilman if (state > pwrst->next_state) { 6328bd22949SKevin Hilman printk(KERN_INFO "Powerdomain (%s) didn't enter " 6338bd22949SKevin Hilman "target state %d\n", 6348bd22949SKevin Hilman pwrst->pwrdm->name, pwrst->next_state); 6358bd22949SKevin Hilman ret = -1; 6368bd22949SKevin Hilman } 6376c5f8039SJouni Hogander set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); 6388bd22949SKevin Hilman } 6398bd22949SKevin Hilman if (ret) 6408bd22949SKevin Hilman printk(KERN_ERR "Could not enter target state in pm_suspend\n"); 6418bd22949SKevin Hilman else 6428bd22949SKevin Hilman printk(KERN_INFO "Successfully put all powerdomains " 6438bd22949SKevin Hilman "to target state\n"); 6448bd22949SKevin Hilman 6458bd22949SKevin Hilman return ret; 6468bd22949SKevin Hilman } 6478bd22949SKevin Hilman 6482466211eSTero Kristo static int omap3_pm_enter(suspend_state_t unused) 6498bd22949SKevin Hilman { 6508bd22949SKevin Hilman int ret = 0; 6518bd22949SKevin Hilman 6522466211eSTero Kristo switch (suspend_state) { 6538bd22949SKevin Hilman case PM_SUSPEND_STANDBY: 6548bd22949SKevin Hilman case PM_SUSPEND_MEM: 6558bd22949SKevin Hilman ret = omap3_pm_suspend(); 6568bd22949SKevin Hilman break; 6578bd22949SKevin Hilman default: 6588bd22949SKevin Hilman ret = -EINVAL; 6598bd22949SKevin Hilman } 6608bd22949SKevin Hilman 6618bd22949SKevin Hilman return ret; 6628bd22949SKevin Hilman } 6638bd22949SKevin Hilman 6648bd22949SKevin Hilman static void omap3_pm_finish(void) 6658bd22949SKevin Hilman { 6668bd22949SKevin Hilman enable_hlt(); 6678bd22949SKevin Hilman } 6688bd22949SKevin Hilman 6692466211eSTero Kristo /* Hooks to enable / disable UART interrupts during suspend */ 6702466211eSTero Kristo static int omap3_pm_begin(suspend_state_t state) 6712466211eSTero Kristo { 6722466211eSTero Kristo suspend_state = state; 6732466211eSTero Kristo omap_uart_enable_irqs(0); 6742466211eSTero Kristo return 0; 6752466211eSTero Kristo } 6762466211eSTero Kristo 6772466211eSTero Kristo static void omap3_pm_end(void) 6782466211eSTero Kristo { 6792466211eSTero Kristo suspend_state = PM_SUSPEND_ON; 6802466211eSTero Kristo omap_uart_enable_irqs(1); 6812466211eSTero Kristo return; 6822466211eSTero Kristo } 6832466211eSTero Kristo 6848bd22949SKevin Hilman static struct platform_suspend_ops omap_pm_ops = { 6852466211eSTero Kristo .begin = omap3_pm_begin, 6862466211eSTero Kristo .end = omap3_pm_end, 6878bd22949SKevin Hilman .prepare = omap3_pm_prepare, 6888bd22949SKevin Hilman .enter = omap3_pm_enter, 6898bd22949SKevin Hilman .finish = omap3_pm_finish, 6908bd22949SKevin Hilman .valid = suspend_valid_only_mem, 6918bd22949SKevin Hilman }; 69210f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 6938bd22949SKevin Hilman 6941155e426SKevin Hilman 6951155e426SKevin Hilman /** 6961155e426SKevin Hilman * omap3_iva_idle(): ensure IVA is in idle so it can be put into 6971155e426SKevin Hilman * retention 6981155e426SKevin Hilman * 6991155e426SKevin Hilman * In cases where IVA2 is activated by bootcode, it may prevent 7001155e426SKevin Hilman * full-chip retention or off-mode because it is not idle. This 7011155e426SKevin Hilman * function forces the IVA2 into idle state so it can go 7021155e426SKevin Hilman * into retention/off and thus allow full-chip retention/off. 7031155e426SKevin Hilman * 7041155e426SKevin Hilman **/ 7051155e426SKevin Hilman static void __init omap3_iva_idle(void) 7061155e426SKevin Hilman { 7071155e426SKevin Hilman /* ensure IVA2 clock is disabled */ 7081155e426SKevin Hilman cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 7091155e426SKevin Hilman 7101155e426SKevin Hilman /* if no clock activity, nothing else to do */ 7111155e426SKevin Hilman if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & 7121155e426SKevin Hilman OMAP3430_CLKACTIVITY_IVA2_MASK)) 7131155e426SKevin Hilman return; 7141155e426SKevin Hilman 7151155e426SKevin Hilman /* Reset IVA2 */ 7161155e426SKevin Hilman prm_write_mod_reg(OMAP3430_RST1_IVA2 | 7171155e426SKevin Hilman OMAP3430_RST2_IVA2 | 7181155e426SKevin Hilman OMAP3430_RST3_IVA2, 7191155e426SKevin Hilman OMAP3430_IVA2_MOD, RM_RSTCTRL); 7201155e426SKevin Hilman 7211155e426SKevin Hilman /* Enable IVA2 clock */ 7221155e426SKevin Hilman cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2, 7231155e426SKevin Hilman OMAP3430_IVA2_MOD, CM_FCLKEN); 7241155e426SKevin Hilman 7251155e426SKevin Hilman /* Set IVA2 boot mode to 'idle' */ 7261155e426SKevin Hilman omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, 7271155e426SKevin Hilman OMAP343X_CONTROL_IVA2_BOOTMOD); 7281155e426SKevin Hilman 7291155e426SKevin Hilman /* Un-reset IVA2 */ 7301155e426SKevin Hilman prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL); 7311155e426SKevin Hilman 7321155e426SKevin Hilman /* Disable IVA2 clock */ 7331155e426SKevin Hilman cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 7341155e426SKevin Hilman 7351155e426SKevin Hilman /* Reset IVA2 */ 7361155e426SKevin Hilman prm_write_mod_reg(OMAP3430_RST1_IVA2 | 7371155e426SKevin Hilman OMAP3430_RST2_IVA2 | 7381155e426SKevin Hilman OMAP3430_RST3_IVA2, 7391155e426SKevin Hilman OMAP3430_IVA2_MOD, RM_RSTCTRL); 7401155e426SKevin Hilman } 7411155e426SKevin Hilman 7428111b221SKevin Hilman static void __init omap3_d2d_idle(void) 7438bd22949SKevin Hilman { 7448111b221SKevin Hilman u16 mask, padconf; 7458111b221SKevin Hilman 7468111b221SKevin Hilman /* In a stand alone OMAP3430 where there is not a stacked 7478111b221SKevin Hilman * modem for the D2D Idle Ack and D2D MStandby must be pulled 7488111b221SKevin Hilman * high. S CONTROL_PADCONF_SAD2D_IDLEACK and 7498111b221SKevin Hilman * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ 7508111b221SKevin Hilman mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ 7518111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); 7528111b221SKevin Hilman padconf |= mask; 7538111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); 7548111b221SKevin Hilman 7558111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); 7568111b221SKevin Hilman padconf |= mask; 7578111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 7588111b221SKevin Hilman 7598bd22949SKevin Hilman /* reset modem */ 7608bd22949SKevin Hilman prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON | 7618bd22949SKevin Hilman OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST, 7628bd22949SKevin Hilman CORE_MOD, RM_RSTCTRL); 7638bd22949SKevin Hilman prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL); 7648111b221SKevin Hilman } 7658bd22949SKevin Hilman 7668111b221SKevin Hilman static void __init prcm_setup_regs(void) 7678111b221SKevin Hilman { 7688bd22949SKevin Hilman /* XXX Reset all wkdeps. This should be done when initializing 7698bd22949SKevin Hilman * powerdomains */ 7708bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); 7718bd22949SKevin Hilman prm_write_mod_reg(0, MPU_MOD, PM_WKDEP); 7728bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP); 7738bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP); 7748bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP); 7758bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP); 7768bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 7778bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP); 7788bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP); 7798bd22949SKevin Hilman } else 7808bd22949SKevin Hilman prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); 7818bd22949SKevin Hilman 7828bd22949SKevin Hilman /* 7838bd22949SKevin Hilman * Enable interface clock autoidle for all modules. 7848bd22949SKevin Hilman * Note that in the long run this should be done by clockfw 7858bd22949SKevin Hilman */ 7868bd22949SKevin Hilman cm_write_mod_reg( 7878111b221SKevin Hilman OMAP3430_AUTO_MODEM | 7888bd22949SKevin Hilman OMAP3430ES2_AUTO_MMC3 | 7898bd22949SKevin Hilman OMAP3430ES2_AUTO_ICR | 7908bd22949SKevin Hilman OMAP3430_AUTO_AES2 | 7918bd22949SKevin Hilman OMAP3430_AUTO_SHA12 | 7928bd22949SKevin Hilman OMAP3430_AUTO_DES2 | 7938bd22949SKevin Hilman OMAP3430_AUTO_MMC2 | 7948bd22949SKevin Hilman OMAP3430_AUTO_MMC1 | 7958bd22949SKevin Hilman OMAP3430_AUTO_MSPRO | 7968bd22949SKevin Hilman OMAP3430_AUTO_HDQ | 7978bd22949SKevin Hilman OMAP3430_AUTO_MCSPI4 | 7988bd22949SKevin Hilman OMAP3430_AUTO_MCSPI3 | 7998bd22949SKevin Hilman OMAP3430_AUTO_MCSPI2 | 8008bd22949SKevin Hilman OMAP3430_AUTO_MCSPI1 | 8018bd22949SKevin Hilman OMAP3430_AUTO_I2C3 | 8028bd22949SKevin Hilman OMAP3430_AUTO_I2C2 | 8038bd22949SKevin Hilman OMAP3430_AUTO_I2C1 | 8048bd22949SKevin Hilman OMAP3430_AUTO_UART2 | 8058bd22949SKevin Hilman OMAP3430_AUTO_UART1 | 8068bd22949SKevin Hilman OMAP3430_AUTO_GPT11 | 8078bd22949SKevin Hilman OMAP3430_AUTO_GPT10 | 8088bd22949SKevin Hilman OMAP3430_AUTO_MCBSP5 | 8098bd22949SKevin Hilman OMAP3430_AUTO_MCBSP1 | 8108bd22949SKevin Hilman OMAP3430ES1_AUTO_FAC | /* This is es1 only */ 8118bd22949SKevin Hilman OMAP3430_AUTO_MAILBOXES | 8128bd22949SKevin Hilman OMAP3430_AUTO_OMAPCTRL | 8138bd22949SKevin Hilman OMAP3430ES1_AUTO_FSHOSTUSB | 8148bd22949SKevin Hilman OMAP3430_AUTO_HSOTGUSB | 8158111b221SKevin Hilman OMAP3430_AUTO_SAD2D | 8168bd22949SKevin Hilman OMAP3430_AUTO_SSI, 8178bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE1); 8188bd22949SKevin Hilman 8198bd22949SKevin Hilman cm_write_mod_reg( 8208bd22949SKevin Hilman OMAP3430_AUTO_PKA | 8218bd22949SKevin Hilman OMAP3430_AUTO_AES1 | 8228bd22949SKevin Hilman OMAP3430_AUTO_RNG | 8238bd22949SKevin Hilman OMAP3430_AUTO_SHA11 | 8248bd22949SKevin Hilman OMAP3430_AUTO_DES1, 8258bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE2); 8268bd22949SKevin Hilman 8278bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 8288bd22949SKevin Hilman cm_write_mod_reg( 8298111b221SKevin Hilman OMAP3430_AUTO_MAD2D | 8308bd22949SKevin Hilman OMAP3430ES2_AUTO_USBTLL, 8318bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE3); 8328bd22949SKevin Hilman } 8338bd22949SKevin Hilman 8348bd22949SKevin Hilman cm_write_mod_reg( 8358bd22949SKevin Hilman OMAP3430_AUTO_WDT2 | 8368bd22949SKevin Hilman OMAP3430_AUTO_WDT1 | 8378bd22949SKevin Hilman OMAP3430_AUTO_GPIO1 | 8388bd22949SKevin Hilman OMAP3430_AUTO_32KSYNC | 8398bd22949SKevin Hilman OMAP3430_AUTO_GPT12 | 8408bd22949SKevin Hilman OMAP3430_AUTO_GPT1 , 8418bd22949SKevin Hilman WKUP_MOD, CM_AUTOIDLE); 8428bd22949SKevin Hilman 8438bd22949SKevin Hilman cm_write_mod_reg( 8448bd22949SKevin Hilman OMAP3430_AUTO_DSS, 8458bd22949SKevin Hilman OMAP3430_DSS_MOD, 8468bd22949SKevin Hilman CM_AUTOIDLE); 8478bd22949SKevin Hilman 8488bd22949SKevin Hilman cm_write_mod_reg( 8498bd22949SKevin Hilman OMAP3430_AUTO_CAM, 8508bd22949SKevin Hilman OMAP3430_CAM_MOD, 8518bd22949SKevin Hilman CM_AUTOIDLE); 8528bd22949SKevin Hilman 8538bd22949SKevin Hilman cm_write_mod_reg( 8548bd22949SKevin Hilman OMAP3430_AUTO_GPIO6 | 8558bd22949SKevin Hilman OMAP3430_AUTO_GPIO5 | 8568bd22949SKevin Hilman OMAP3430_AUTO_GPIO4 | 8578bd22949SKevin Hilman OMAP3430_AUTO_GPIO3 | 8588bd22949SKevin Hilman OMAP3430_AUTO_GPIO2 | 8598bd22949SKevin Hilman OMAP3430_AUTO_WDT3 | 8608bd22949SKevin Hilman OMAP3430_AUTO_UART3 | 8618bd22949SKevin Hilman OMAP3430_AUTO_GPT9 | 8628bd22949SKevin Hilman OMAP3430_AUTO_GPT8 | 8638bd22949SKevin Hilman OMAP3430_AUTO_GPT7 | 8648bd22949SKevin Hilman OMAP3430_AUTO_GPT6 | 8658bd22949SKevin Hilman OMAP3430_AUTO_GPT5 | 8668bd22949SKevin Hilman OMAP3430_AUTO_GPT4 | 8678bd22949SKevin Hilman OMAP3430_AUTO_GPT3 | 8688bd22949SKevin Hilman OMAP3430_AUTO_GPT2 | 8698bd22949SKevin Hilman OMAP3430_AUTO_MCBSP4 | 8708bd22949SKevin Hilman OMAP3430_AUTO_MCBSP3 | 8718bd22949SKevin Hilman OMAP3430_AUTO_MCBSP2, 8728bd22949SKevin Hilman OMAP3430_PER_MOD, 8738bd22949SKevin Hilman CM_AUTOIDLE); 8748bd22949SKevin Hilman 8758bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 8768bd22949SKevin Hilman cm_write_mod_reg( 8778bd22949SKevin Hilman OMAP3430ES2_AUTO_USBHOST, 8788bd22949SKevin Hilman OMAP3430ES2_USBHOST_MOD, 8798bd22949SKevin Hilman CM_AUTOIDLE); 8808bd22949SKevin Hilman } 8818bd22949SKevin Hilman 8828bd22949SKevin Hilman /* 8838bd22949SKevin Hilman * Set all plls to autoidle. This is needed until autoidle is 8848bd22949SKevin Hilman * enabled by clockfw 8858bd22949SKevin Hilman */ 8868bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, 8878bd22949SKevin Hilman OMAP3430_IVA2_MOD, CM_AUTOIDLE2); 8888bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT, 8898bd22949SKevin Hilman MPU_MOD, 8908bd22949SKevin Hilman CM_AUTOIDLE2); 8918bd22949SKevin Hilman cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | 8928bd22949SKevin Hilman (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT), 8938bd22949SKevin Hilman PLL_MOD, 8948bd22949SKevin Hilman CM_AUTOIDLE); 8958bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, 8968bd22949SKevin Hilman PLL_MOD, 8978bd22949SKevin Hilman CM_AUTOIDLE2); 8988bd22949SKevin Hilman 8998bd22949SKevin Hilman /* 9008bd22949SKevin Hilman * Enable control of expternal oscillator through 9018bd22949SKevin Hilman * sys_clkreq. In the long run clock framework should 9028bd22949SKevin Hilman * take care of this. 9038bd22949SKevin Hilman */ 9048bd22949SKevin Hilman prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 9058bd22949SKevin Hilman 1 << OMAP_AUTOEXTCLKMODE_SHIFT, 9068bd22949SKevin Hilman OMAP3430_GR_MOD, 9078bd22949SKevin Hilman OMAP3_PRM_CLKSRC_CTRL_OFFSET); 9088bd22949SKevin Hilman 9098bd22949SKevin Hilman /* setup wakup source */ 9108bd22949SKevin Hilman prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 | 9118bd22949SKevin Hilman OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12, 9128bd22949SKevin Hilman WKUP_MOD, PM_WKEN); 9138bd22949SKevin Hilman /* No need to write EN_IO, that is always enabled */ 9148bd22949SKevin Hilman prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 | 9158bd22949SKevin Hilman OMAP3430_EN_GPT12, 9168bd22949SKevin Hilman WKUP_MOD, OMAP3430_PM_MPUGRPSEL); 9178bd22949SKevin Hilman /* For some reason IO doesn't generate wakeup event even if 9188bd22949SKevin Hilman * it is selected to mpu wakeup goup */ 9198bd22949SKevin Hilman prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN, 9208bd22949SKevin Hilman OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); 9211155e426SKevin Hilman 922b427f92fSKevin Hilman /* Enable wakeups in PER */ 923eb350f74SKevin Hilman prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 | 924eb350f74SKevin Hilman OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 | 925b427f92fSKevin Hilman OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3, 926b427f92fSKevin Hilman OMAP3430_PER_MOD, PM_WKEN); 927eb350f74SKevin Hilman /* and allow them to wake up MPU */ 928eb350f74SKevin Hilman prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 | 929eb350f74SKevin Hilman OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 | 930b427f92fSKevin Hilman OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3, 931eb350f74SKevin Hilman OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); 932eb350f74SKevin Hilman 933d3fd3290SKevin Hilman /* Don't attach IVA interrupts */ 934d3fd3290SKevin Hilman prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 935d3fd3290SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 936d3fd3290SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 937d3fd3290SKevin Hilman prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); 938d3fd3290SKevin Hilman 939b1340d17SKevin Hilman /* Clear any pending 'reset' flags */ 940b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST); 941b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST); 942b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST); 943b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST); 944b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST); 945b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST); 946b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST); 947b1340d17SKevin Hilman 948014c46dbSKevin Hilman /* Clear any pending PRCM interrupts */ 949014c46dbSKevin Hilman prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 950014c46dbSKevin Hilman 951040fed05SKevin Hilman /* Don't attach IVA interrupts */ 952040fed05SKevin Hilman prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 953040fed05SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 954040fed05SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 955040fed05SKevin Hilman prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); 956040fed05SKevin Hilman 9573a07ae30SKevin Hilman /* Clear any pending 'reset' flags */ 9583a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST); 9593a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST); 9603a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST); 9613a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST); 9623a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST); 9633a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST); 9643a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST); 9653a07ae30SKevin Hilman 9663a6667acSKevin Hilman /* Clear any pending PRCM interrupts */ 9673a6667acSKevin Hilman prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 9683a6667acSKevin Hilman 9691155e426SKevin Hilman omap3_iva_idle(); 9708111b221SKevin Hilman omap3_d2d_idle(); 9718bd22949SKevin Hilman } 9728bd22949SKevin Hilman 973c40552bcSKevin Hilman void omap3_pm_off_mode_enable(int enable) 974c40552bcSKevin Hilman { 975c40552bcSKevin Hilman struct power_state *pwrst; 976c40552bcSKevin Hilman u32 state; 977c40552bcSKevin Hilman 978c40552bcSKevin Hilman if (enable) 979c40552bcSKevin Hilman state = PWRDM_POWER_OFF; 980c40552bcSKevin Hilman else 981c40552bcSKevin Hilman state = PWRDM_POWER_RET; 982c40552bcSKevin Hilman 983c40552bcSKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 984c40552bcSKevin Hilman pwrst->next_state = state; 985c40552bcSKevin Hilman set_pwrdm_state(pwrst->pwrdm, state); 986c40552bcSKevin Hilman } 987c40552bcSKevin Hilman } 988c40552bcSKevin Hilman 98968d4778cSTero Kristo int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) 99068d4778cSTero Kristo { 99168d4778cSTero Kristo struct power_state *pwrst; 99268d4778cSTero Kristo 99368d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 99468d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) 99568d4778cSTero Kristo return pwrst->next_state; 99668d4778cSTero Kristo } 99768d4778cSTero Kristo return -EINVAL; 99868d4778cSTero Kristo } 99968d4778cSTero Kristo 100068d4778cSTero Kristo int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) 100168d4778cSTero Kristo { 100268d4778cSTero Kristo struct power_state *pwrst; 100368d4778cSTero Kristo 100468d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 100568d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) { 100668d4778cSTero Kristo pwrst->next_state = state; 100768d4778cSTero Kristo return 0; 100868d4778cSTero Kristo } 100968d4778cSTero Kristo } 101068d4778cSTero Kristo return -EINVAL; 101168d4778cSTero Kristo } 101268d4778cSTero Kristo 1013a23456e9SPeter 'p2' De Schrijver static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) 10148bd22949SKevin Hilman { 10158bd22949SKevin Hilman struct power_state *pwrst; 10168bd22949SKevin Hilman 10178bd22949SKevin Hilman if (!pwrdm->pwrsts) 10188bd22949SKevin Hilman return 0; 10198bd22949SKevin Hilman 1020d3d381c6SMing Lei pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); 10218bd22949SKevin Hilman if (!pwrst) 10228bd22949SKevin Hilman return -ENOMEM; 10238bd22949SKevin Hilman pwrst->pwrdm = pwrdm; 10248bd22949SKevin Hilman pwrst->next_state = PWRDM_POWER_RET; 10258bd22949SKevin Hilman list_add(&pwrst->node, &pwrst_list); 10268bd22949SKevin Hilman 10278bd22949SKevin Hilman if (pwrdm_has_hdwr_sar(pwrdm)) 10288bd22949SKevin Hilman pwrdm_enable_hdwr_sar(pwrdm); 10298bd22949SKevin Hilman 10308bd22949SKevin Hilman return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 10318bd22949SKevin Hilman } 10328bd22949SKevin Hilman 10338bd22949SKevin Hilman /* 10348bd22949SKevin Hilman * Enable hw supervised mode for all clockdomains if it's 10358bd22949SKevin Hilman * supported. Initiate sleep transition for other clockdomains, if 10368bd22949SKevin Hilman * they are not used 10378bd22949SKevin Hilman */ 1038a23456e9SPeter 'p2' De Schrijver static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) 10398bd22949SKevin Hilman { 10408bd22949SKevin Hilman if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) 10418bd22949SKevin Hilman omap2_clkdm_allow_idle(clkdm); 10428bd22949SKevin Hilman else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && 10438bd22949SKevin Hilman atomic_read(&clkdm->usecount) == 0) 10448bd22949SKevin Hilman omap2_clkdm_sleep(clkdm); 10458bd22949SKevin Hilman return 0; 10468bd22949SKevin Hilman } 10478bd22949SKevin Hilman 10483231fc88SRajendra Nayak void omap_push_sram_idle(void) 10493231fc88SRajendra Nayak { 10503231fc88SRajendra Nayak _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend, 10513231fc88SRajendra Nayak omap34xx_cpu_suspend_sz); 105227d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) 105327d59a4aSTero Kristo _omap_save_secure_sram = omap_sram_push(save_secure_ram_context, 105427d59a4aSTero Kristo save_secure_ram_context_sz); 10553231fc88SRajendra Nayak } 10563231fc88SRajendra Nayak 10577cc515f7SKevin Hilman static int __init omap3_pm_init(void) 10588bd22949SKevin Hilman { 10598bd22949SKevin Hilman struct power_state *pwrst, *tmp; 10608bd22949SKevin Hilman int ret; 10618bd22949SKevin Hilman 10628bd22949SKevin Hilman if (!cpu_is_omap34xx()) 10638bd22949SKevin Hilman return -ENODEV; 10648bd22949SKevin Hilman 10658bd22949SKevin Hilman printk(KERN_ERR "Power Management for TI OMAP3.\n"); 10668bd22949SKevin Hilman 10678bd22949SKevin Hilman /* XXX prcm_setup_regs needs to be before enabling hw 10688bd22949SKevin Hilman * supervised mode for powerdomains */ 10698bd22949SKevin Hilman prcm_setup_regs(); 10708bd22949SKevin Hilman 10718bd22949SKevin Hilman ret = request_irq(INT_34XX_PRCM_MPU_IRQ, 10728bd22949SKevin Hilman (irq_handler_t)prcm_interrupt_handler, 10738bd22949SKevin Hilman IRQF_DISABLED, "prcm", NULL); 10748bd22949SKevin Hilman if (ret) { 10758bd22949SKevin Hilman printk(KERN_ERR "request_irq failed to register for 0x%x\n", 10768bd22949SKevin Hilman INT_34XX_PRCM_MPU_IRQ); 10778bd22949SKevin Hilman goto err1; 10788bd22949SKevin Hilman } 10798bd22949SKevin Hilman 1080a23456e9SPeter 'p2' De Schrijver ret = pwrdm_for_each(pwrdms_setup, NULL); 10818bd22949SKevin Hilman if (ret) { 10828bd22949SKevin Hilman printk(KERN_ERR "Failed to setup powerdomains\n"); 10838bd22949SKevin Hilman goto err2; 10848bd22949SKevin Hilman } 10858bd22949SKevin Hilman 1086a23456e9SPeter 'p2' De Schrijver (void) clkdm_for_each(clkdms_setup, NULL); 10878bd22949SKevin Hilman 10888bd22949SKevin Hilman mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); 10898bd22949SKevin Hilman if (mpu_pwrdm == NULL) { 10908bd22949SKevin Hilman printk(KERN_ERR "Failed to get mpu_pwrdm\n"); 10918bd22949SKevin Hilman goto err2; 10928bd22949SKevin Hilman } 10938bd22949SKevin Hilman 1094fa3c2a4fSRajendra Nayak neon_pwrdm = pwrdm_lookup("neon_pwrdm"); 1095fa3c2a4fSRajendra Nayak per_pwrdm = pwrdm_lookup("per_pwrdm"); 1096fa3c2a4fSRajendra Nayak core_pwrdm = pwrdm_lookup("core_pwrdm"); 1097c16c3f67STero Kristo cam_pwrdm = pwrdm_lookup("cam_pwrdm"); 1098fa3c2a4fSRajendra Nayak 10993231fc88SRajendra Nayak omap_push_sram_idle(); 110010f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 11018bd22949SKevin Hilman suspend_set_ops(&omap_pm_ops); 110210f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 11038bd22949SKevin Hilman 11048bd22949SKevin Hilman pm_idle = omap3_pm_idle; 11058bd22949SKevin Hilman 1106fa3c2a4fSRajendra Nayak pwrdm_add_wkdep(neon_pwrdm, mpu_pwrdm); 1107fa3c2a4fSRajendra Nayak /* 1108fa3c2a4fSRajendra Nayak * REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for 1109fa3c2a4fSRajendra Nayak * IO-pad wakeup. Otherwise it will unnecessarily waste power 1110fa3c2a4fSRajendra Nayak * waking up PER with every CORE wakeup - see 1111fa3c2a4fSRajendra Nayak * http://marc.info/?l=linux-omap&m=121852150710062&w=2 1112fa3c2a4fSRajendra Nayak */ 1113fa3c2a4fSRajendra Nayak pwrdm_add_wkdep(per_pwrdm, core_pwrdm); 1114fa3c2a4fSRajendra Nayak 111527d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 111627d59a4aSTero Kristo omap3_secure_ram_storage = 111727d59a4aSTero Kristo kmalloc(0x803F, GFP_KERNEL); 111827d59a4aSTero Kristo if (!omap3_secure_ram_storage) 111927d59a4aSTero Kristo printk(KERN_ERR "Memory allocation failed when" 112027d59a4aSTero Kristo "allocating for secure sram context\n"); 112127d59a4aSTero Kristo 11229d97140bSTero Kristo local_irq_disable(); 11239d97140bSTero Kristo local_fiq_disable(); 11249d97140bSTero Kristo 11259d97140bSTero Kristo omap_dma_global_context_save(); 11269d97140bSTero Kristo omap3_save_secure_ram_context(PWRDM_POWER_ON); 11279d97140bSTero Kristo omap_dma_global_context_restore(); 11289d97140bSTero Kristo 11299d97140bSTero Kristo local_irq_enable(); 11309d97140bSTero Kristo local_fiq_enable(); 11319d97140bSTero Kristo } 11329d97140bSTero Kristo 11339d97140bSTero Kristo omap3_save_scratchpad_contents(); 11348bd22949SKevin Hilman err1: 11358bd22949SKevin Hilman return ret; 11368bd22949SKevin Hilman err2: 11378bd22949SKevin Hilman free_irq(INT_34XX_PRCM_MPU_IRQ, NULL); 11388bd22949SKevin Hilman list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { 11398bd22949SKevin Hilman list_del(&pwrst->node); 11408bd22949SKevin Hilman kfree(pwrst); 11418bd22949SKevin Hilman } 11428bd22949SKevin Hilman return ret; 11438bd22949SKevin Hilman } 11448bd22949SKevin Hilman 11458bd22949SKevin Hilman late_initcall(omap3_pm_init); 1146