18bd22949SKevin Hilman /* 28bd22949SKevin Hilman * OMAP3 Power Management Routines 38bd22949SKevin Hilman * 48bd22949SKevin Hilman * Copyright (C) 2006-2008 Nokia Corporation 58bd22949SKevin Hilman * Tony Lindgren <tony@atomide.com> 68bd22949SKevin Hilman * Jouni Hogander 78bd22949SKevin Hilman * 88bd22949SKevin Hilman * Copyright (C) 2005 Texas Instruments, Inc. 98bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 108bd22949SKevin Hilman * 118bd22949SKevin Hilman * Based on pm.c for omap1 128bd22949SKevin Hilman * 138bd22949SKevin Hilman * This program is free software; you can redistribute it and/or modify 148bd22949SKevin Hilman * it under the terms of the GNU General Public License version 2 as 158bd22949SKevin Hilman * published by the Free Software Foundation. 168bd22949SKevin Hilman */ 178bd22949SKevin Hilman 188bd22949SKevin Hilman #include <linux/pm.h> 198bd22949SKevin Hilman #include <linux/suspend.h> 208bd22949SKevin Hilman #include <linux/interrupt.h> 218bd22949SKevin Hilman #include <linux/module.h> 228bd22949SKevin Hilman #include <linux/list.h> 238bd22949SKevin Hilman #include <linux/err.h> 248bd22949SKevin Hilman #include <linux/gpio.h> 258bd22949SKevin Hilman 268bd22949SKevin Hilman #include <mach/sram.h> 278bd22949SKevin Hilman #include <mach/clockdomain.h> 288bd22949SKevin Hilman #include <mach/powerdomain.h> 298bd22949SKevin Hilman #include <mach/control.h> 304af4016cSKevin Hilman #include <mach/serial.h> 318bd22949SKevin Hilman 328bd22949SKevin Hilman #include "cm.h" 338bd22949SKevin Hilman #include "cm-regbits-34xx.h" 348bd22949SKevin Hilman #include "prm-regbits-34xx.h" 358bd22949SKevin Hilman 368bd22949SKevin Hilman #include "prm.h" 378bd22949SKevin Hilman #include "pm.h" 388bd22949SKevin Hilman 398bd22949SKevin Hilman struct power_state { 408bd22949SKevin Hilman struct powerdomain *pwrdm; 418bd22949SKevin Hilman u32 next_state; 4210f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 438bd22949SKevin Hilman u32 saved_state; 4410f90ed2SKevin Hilman #endif 458bd22949SKevin Hilman struct list_head node; 468bd22949SKevin Hilman }; 478bd22949SKevin Hilman 488bd22949SKevin Hilman static LIST_HEAD(pwrst_list); 498bd22949SKevin Hilman 508bd22949SKevin Hilman static void (*_omap_sram_idle)(u32 *addr, int save_state); 518bd22949SKevin Hilman 528bd22949SKevin Hilman static struct powerdomain *mpu_pwrdm; 538bd22949SKevin Hilman 5477da2d91SJon Hunter /* 5577da2d91SJon Hunter * PRCM Interrupt Handler Helper Function 5677da2d91SJon Hunter * 5777da2d91SJon Hunter * The purpose of this function is to clear any wake-up events latched 5877da2d91SJon Hunter * in the PRCM PM_WKST_x registers. It is possible that a wake-up event 5977da2d91SJon Hunter * may occur whilst attempting to clear a PM_WKST_x register and thus 6077da2d91SJon Hunter * set another bit in this register. A while loop is used to ensure 6177da2d91SJon Hunter * that any peripheral wake-up events occurring while attempting to 6277da2d91SJon Hunter * clear the PM_WKST_x are detected and cleared. 6377da2d91SJon Hunter */ 648cb0ac99SPaul Walmsley static int prcm_clear_mod_irqs(s16 module, u8 regs) 6577da2d91SJon Hunter { 6671a80775SVikram Pandita u32 wkst, fclk, iclk, clken; 6777da2d91SJon Hunter u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; 6877da2d91SJon Hunter u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; 6977da2d91SJon Hunter u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; 705d805978SPaul Walmsley u16 grpsel_off = (regs == 3) ? 715d805978SPaul Walmsley OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; 728cb0ac99SPaul Walmsley int c = 0; 7377da2d91SJon Hunter 7477da2d91SJon Hunter wkst = prm_read_mod_reg(module, wkst_off); 755d805978SPaul Walmsley wkst &= prm_read_mod_reg(module, grpsel_off); 7677da2d91SJon Hunter if (wkst) { 7777da2d91SJon Hunter iclk = cm_read_mod_reg(module, iclk_off); 7877da2d91SJon Hunter fclk = cm_read_mod_reg(module, fclk_off); 7977da2d91SJon Hunter while (wkst) { 8071a80775SVikram Pandita clken = wkst; 8171a80775SVikram Pandita cm_set_mod_reg_bits(clken, module, iclk_off); 8271a80775SVikram Pandita /* 8371a80775SVikram Pandita * For USBHOST, we don't know whether HOST1 or 8471a80775SVikram Pandita * HOST2 woke us up, so enable both f-clocks 8571a80775SVikram Pandita */ 8671a80775SVikram Pandita if (module == OMAP3430ES2_USBHOST_MOD) 8771a80775SVikram Pandita clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; 8871a80775SVikram Pandita cm_set_mod_reg_bits(clken, module, fclk_off); 8977da2d91SJon Hunter prm_write_mod_reg(wkst, module, wkst_off); 9077da2d91SJon Hunter wkst = prm_read_mod_reg(module, wkst_off); 918cb0ac99SPaul Walmsley c++; 9277da2d91SJon Hunter } 9377da2d91SJon Hunter cm_write_mod_reg(iclk, module, iclk_off); 9477da2d91SJon Hunter cm_write_mod_reg(fclk, module, fclk_off); 9577da2d91SJon Hunter } 968cb0ac99SPaul Walmsley 978cb0ac99SPaul Walmsley return c; 988cb0ac99SPaul Walmsley } 998cb0ac99SPaul Walmsley 1008cb0ac99SPaul Walmsley static int _prcm_int_handle_wakeup(void) 1018cb0ac99SPaul Walmsley { 1028cb0ac99SPaul Walmsley int c; 1038cb0ac99SPaul Walmsley 1048cb0ac99SPaul Walmsley c = prcm_clear_mod_irqs(WKUP_MOD, 1); 1058cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(CORE_MOD, 1); 1068cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1); 1078cb0ac99SPaul Walmsley if (omap_rev() > OMAP3430_REV_ES1_0) { 1088cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(CORE_MOD, 3); 1098cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1); 1108cb0ac99SPaul Walmsley } 1118cb0ac99SPaul Walmsley 1128cb0ac99SPaul Walmsley return c; 11377da2d91SJon Hunter } 11477da2d91SJon Hunter 11577da2d91SJon Hunter /* 11677da2d91SJon Hunter * PRCM Interrupt Handler 11777da2d91SJon Hunter * 11877da2d91SJon Hunter * The PRM_IRQSTATUS_MPU register indicates if there are any pending 11977da2d91SJon Hunter * interrupts from the PRCM for the MPU. These bits must be cleared in 12077da2d91SJon Hunter * order to clear the PRCM interrupt. The PRCM interrupt handler is 12177da2d91SJon Hunter * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear 12277da2d91SJon Hunter * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU 12377da2d91SJon Hunter * register indicates that a wake-up event is pending for the MPU and 12477da2d91SJon Hunter * this bit can only be cleared if the all the wake-up events latched 12577da2d91SJon Hunter * in the various PM_WKST_x registers have been cleared. The interrupt 12677da2d91SJon Hunter * handler is implemented using a do-while loop so that if a wake-up 12777da2d91SJon Hunter * event occurred during the processing of the prcm interrupt handler 12877da2d91SJon Hunter * (setting a bit in the corresponding PM_WKST_x register and thus 12977da2d91SJon Hunter * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register) 13077da2d91SJon Hunter * this would be handled. 13177da2d91SJon Hunter */ 1328bd22949SKevin Hilman static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) 1338bd22949SKevin Hilman { 13477da2d91SJon Hunter u32 irqstatus_mpu; 1358cb0ac99SPaul Walmsley int c = 0; 1368bd22949SKevin Hilman 13777da2d91SJon Hunter do { 1388bd22949SKevin Hilman irqstatus_mpu = prm_read_mod_reg(OCP_MOD, 1398bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 1408cb0ac99SPaul Walmsley 1418cb0ac99SPaul Walmsley if (irqstatus_mpu & (OMAP3430_WKUP_ST | OMAP3430_IO_ST)) { 1428cb0ac99SPaul Walmsley c = _prcm_int_handle_wakeup(); 1438cb0ac99SPaul Walmsley 1448cb0ac99SPaul Walmsley /* 1458cb0ac99SPaul Walmsley * Is the MPU PRCM interrupt handler racing with the 1468cb0ac99SPaul Walmsley * IVA2 PRCM interrupt handler ? 1478cb0ac99SPaul Walmsley */ 1488cb0ac99SPaul Walmsley WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup " 1498cb0ac99SPaul Walmsley "but no wakeup sources are marked\n"); 1508cb0ac99SPaul Walmsley } else { 1518cb0ac99SPaul Walmsley /* XXX we need to expand our PRCM interrupt handler */ 1528cb0ac99SPaul Walmsley WARN(1, "prcm: WARNING: PRCM interrupt received, but " 1538cb0ac99SPaul Walmsley "no code to handle it (%08x)\n", irqstatus_mpu); 1548cb0ac99SPaul Walmsley } 1558cb0ac99SPaul Walmsley 1568bd22949SKevin Hilman prm_write_mod_reg(irqstatus_mpu, OCP_MOD, 1578bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 1588bd22949SKevin Hilman 15977da2d91SJon Hunter } while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET)); 1608bd22949SKevin Hilman 1618bd22949SKevin Hilman return IRQ_HANDLED; 1628bd22949SKevin Hilman } 1638bd22949SKevin Hilman 1648bd22949SKevin Hilman static void omap_sram_idle(void) 1658bd22949SKevin Hilman { 1668bd22949SKevin Hilman /* Variable to tell what needs to be saved and restored 1678bd22949SKevin Hilman * in omap_sram_idle*/ 1688bd22949SKevin Hilman /* save_state = 0 => Nothing to save and restored */ 1698bd22949SKevin Hilman /* save_state = 1 => Only L1 and logic lost */ 1708bd22949SKevin Hilman /* save_state = 2 => Only L2 lost */ 1718bd22949SKevin Hilman /* save_state = 3 => L1, L2 and logic lost */ 1728bd22949SKevin Hilman int save_state = 0, mpu_next_state; 1738bd22949SKevin Hilman 1748bd22949SKevin Hilman if (!_omap_sram_idle) 1758bd22949SKevin Hilman return; 1768bd22949SKevin Hilman 1778bd22949SKevin Hilman mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 1788bd22949SKevin Hilman switch (mpu_next_state) { 1798bd22949SKevin Hilman case PWRDM_POWER_RET: 1808bd22949SKevin Hilman /* No need to save context */ 1818bd22949SKevin Hilman save_state = 0; 1828bd22949SKevin Hilman break; 1838bd22949SKevin Hilman default: 1848bd22949SKevin Hilman /* Invalid state */ 1858bd22949SKevin Hilman printk(KERN_ERR "Invalid mpu state in sram_idle\n"); 1868bd22949SKevin Hilman return; 1878bd22949SKevin Hilman } 188fe617af7SPeter 'p2' De Schrijver pwrdm_pre_transition(); 189fe617af7SPeter 'p2' De Schrijver 1908bd22949SKevin Hilman omap2_gpio_prepare_for_retention(); 1914af4016cSKevin Hilman omap_uart_prepare_idle(0); 1924af4016cSKevin Hilman omap_uart_prepare_idle(1); 1934af4016cSKevin Hilman omap_uart_prepare_idle(2); 1948bd22949SKevin Hilman 1958bd22949SKevin Hilman _omap_sram_idle(NULL, save_state); 1968bd22949SKevin Hilman cpu_init(); 1978bd22949SKevin Hilman 1984af4016cSKevin Hilman omap_uart_resume_idle(2); 1994af4016cSKevin Hilman omap_uart_resume_idle(1); 2004af4016cSKevin Hilman omap_uart_resume_idle(0); 2018bd22949SKevin Hilman omap2_gpio_resume_after_retention(); 202fe617af7SPeter 'p2' De Schrijver 203fe617af7SPeter 'p2' De Schrijver pwrdm_post_transition(); 204fe617af7SPeter 'p2' De Schrijver 2058bd22949SKevin Hilman } 2068bd22949SKevin Hilman 2078bd22949SKevin Hilman /* 2088bd22949SKevin Hilman * Check if functional clocks are enabled before entering 2098bd22949SKevin Hilman * sleep. This function could be behind CONFIG_PM_DEBUG 2108bd22949SKevin Hilman * when all drivers are configuring their sysconfig registers 2118bd22949SKevin Hilman * properly and using their clocks properly. 2128bd22949SKevin Hilman */ 2138bd22949SKevin Hilman static int omap3_fclks_active(void) 2148bd22949SKevin Hilman { 2158bd22949SKevin Hilman u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0, 2168bd22949SKevin Hilman fck_cam = 0, fck_per = 0, fck_usbhost = 0; 2178bd22949SKevin Hilman 2188bd22949SKevin Hilman fck_core1 = cm_read_mod_reg(CORE_MOD, 2198bd22949SKevin Hilman CM_FCLKEN1); 2208bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 2218bd22949SKevin Hilman fck_core3 = cm_read_mod_reg(CORE_MOD, 2228bd22949SKevin Hilman OMAP3430ES2_CM_FCLKEN3); 2238bd22949SKevin Hilman fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD, 2248bd22949SKevin Hilman CM_FCLKEN); 2258bd22949SKevin Hilman fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, 2268bd22949SKevin Hilman CM_FCLKEN); 2278bd22949SKevin Hilman } else 2288bd22949SKevin Hilman fck_sgx = cm_read_mod_reg(GFX_MOD, 2298bd22949SKevin Hilman OMAP3430ES2_CM_FCLKEN3); 2308bd22949SKevin Hilman fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD, 2318bd22949SKevin Hilman CM_FCLKEN); 2328bd22949SKevin Hilman fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD, 2338bd22949SKevin Hilman CM_FCLKEN); 2348bd22949SKevin Hilman fck_per = cm_read_mod_reg(OMAP3430_PER_MOD, 2358bd22949SKevin Hilman CM_FCLKEN); 2364af4016cSKevin Hilman 2374af4016cSKevin Hilman /* Ignore UART clocks. These are handled by UART core (serial.c) */ 2384af4016cSKevin Hilman fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2); 2394af4016cSKevin Hilman fck_per &= ~OMAP3430_EN_UART3; 2404af4016cSKevin Hilman 2418bd22949SKevin Hilman if (fck_core1 | fck_core3 | fck_sgx | fck_dss | 2428bd22949SKevin Hilman fck_cam | fck_per | fck_usbhost) 2438bd22949SKevin Hilman return 1; 2448bd22949SKevin Hilman return 0; 2458bd22949SKevin Hilman } 2468bd22949SKevin Hilman 2478bd22949SKevin Hilman static int omap3_can_sleep(void) 2488bd22949SKevin Hilman { 2494af4016cSKevin Hilman if (!omap_uart_can_sleep()) 2504af4016cSKevin Hilman return 0; 2518bd22949SKevin Hilman if (omap3_fclks_active()) 2528bd22949SKevin Hilman return 0; 2538bd22949SKevin Hilman return 1; 2548bd22949SKevin Hilman } 2558bd22949SKevin Hilman 2568bd22949SKevin Hilman /* This sets pwrdm state (other than mpu & core. Currently only ON & 2578bd22949SKevin Hilman * RET are supported. Function is assuming that clkdm doesn't have 2588bd22949SKevin Hilman * hw_sup mode enabled. */ 2598bd22949SKevin Hilman static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state) 2608bd22949SKevin Hilman { 2618bd22949SKevin Hilman u32 cur_state; 2628bd22949SKevin Hilman int sleep_switch = 0; 2638bd22949SKevin Hilman int ret = 0; 2648bd22949SKevin Hilman 2658bd22949SKevin Hilman if (pwrdm == NULL || IS_ERR(pwrdm)) 2668bd22949SKevin Hilman return -EINVAL; 2678bd22949SKevin Hilman 2688bd22949SKevin Hilman while (!(pwrdm->pwrsts & (1 << state))) { 2698bd22949SKevin Hilman if (state == PWRDM_POWER_OFF) 2708bd22949SKevin Hilman return ret; 2718bd22949SKevin Hilman state--; 2728bd22949SKevin Hilman } 2738bd22949SKevin Hilman 2748bd22949SKevin Hilman cur_state = pwrdm_read_next_pwrst(pwrdm); 2758bd22949SKevin Hilman if (cur_state == state) 2768bd22949SKevin Hilman return ret; 2778bd22949SKevin Hilman 2788bd22949SKevin Hilman if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) { 2798bd22949SKevin Hilman omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); 2808bd22949SKevin Hilman sleep_switch = 1; 2818bd22949SKevin Hilman pwrdm_wait_transition(pwrdm); 2828bd22949SKevin Hilman } 2838bd22949SKevin Hilman 2848bd22949SKevin Hilman ret = pwrdm_set_next_pwrst(pwrdm, state); 2858bd22949SKevin Hilman if (ret) { 2868bd22949SKevin Hilman printk(KERN_ERR "Unable to set state of powerdomain: %s\n", 2878bd22949SKevin Hilman pwrdm->name); 2888bd22949SKevin Hilman goto err; 2898bd22949SKevin Hilman } 2908bd22949SKevin Hilman 2918bd22949SKevin Hilman if (sleep_switch) { 2928bd22949SKevin Hilman omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); 2938bd22949SKevin Hilman pwrdm_wait_transition(pwrdm); 294fe617af7SPeter 'p2' De Schrijver pwrdm_state_switch(pwrdm); 2958bd22949SKevin Hilman } 2968bd22949SKevin Hilman 2978bd22949SKevin Hilman err: 2988bd22949SKevin Hilman return ret; 2998bd22949SKevin Hilman } 3008bd22949SKevin Hilman 3018bd22949SKevin Hilman static void omap3_pm_idle(void) 3028bd22949SKevin Hilman { 3038bd22949SKevin Hilman local_irq_disable(); 3048bd22949SKevin Hilman local_fiq_disable(); 3058bd22949SKevin Hilman 3068bd22949SKevin Hilman if (!omap3_can_sleep()) 3078bd22949SKevin Hilman goto out; 3088bd22949SKevin Hilman 3098bd22949SKevin Hilman if (omap_irq_pending()) 3108bd22949SKevin Hilman goto out; 3118bd22949SKevin Hilman 3128bd22949SKevin Hilman omap_sram_idle(); 3138bd22949SKevin Hilman 3148bd22949SKevin Hilman out: 3158bd22949SKevin Hilman local_fiq_enable(); 3168bd22949SKevin Hilman local_irq_enable(); 3178bd22949SKevin Hilman } 3188bd22949SKevin Hilman 31910f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 3202466211eSTero Kristo static suspend_state_t suspend_state; 3212466211eSTero Kristo 3228bd22949SKevin Hilman static int omap3_pm_prepare(void) 3238bd22949SKevin Hilman { 3248bd22949SKevin Hilman disable_hlt(); 3258bd22949SKevin Hilman return 0; 3268bd22949SKevin Hilman } 3278bd22949SKevin Hilman 3288bd22949SKevin Hilman static int omap3_pm_suspend(void) 3298bd22949SKevin Hilman { 3308bd22949SKevin Hilman struct power_state *pwrst; 3318bd22949SKevin Hilman int state, ret = 0; 3328bd22949SKevin Hilman 3338bd22949SKevin Hilman /* Read current next_pwrsts */ 3348bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) 3358bd22949SKevin Hilman pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 3368bd22949SKevin Hilman /* Set ones wanted by suspend */ 3378bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 3388bd22949SKevin Hilman if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) 3398bd22949SKevin Hilman goto restore; 3408bd22949SKevin Hilman if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) 3418bd22949SKevin Hilman goto restore; 3428bd22949SKevin Hilman } 3438bd22949SKevin Hilman 3444af4016cSKevin Hilman omap_uart_prepare_suspend(); 3458bd22949SKevin Hilman omap_sram_idle(); 3468bd22949SKevin Hilman 3478bd22949SKevin Hilman restore: 3488bd22949SKevin Hilman /* Restore next_pwrsts */ 3498bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 3508bd22949SKevin Hilman state = pwrdm_read_prev_pwrst(pwrst->pwrdm); 3518bd22949SKevin Hilman if (state > pwrst->next_state) { 3528bd22949SKevin Hilman printk(KERN_INFO "Powerdomain (%s) didn't enter " 3538bd22949SKevin Hilman "target state %d\n", 3548bd22949SKevin Hilman pwrst->pwrdm->name, pwrst->next_state); 3558bd22949SKevin Hilman ret = -1; 3568bd22949SKevin Hilman } 3576c5f8039SJouni Hogander set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); 3588bd22949SKevin Hilman } 3598bd22949SKevin Hilman if (ret) 3608bd22949SKevin Hilman printk(KERN_ERR "Could not enter target state in pm_suspend\n"); 3618bd22949SKevin Hilman else 3628bd22949SKevin Hilman printk(KERN_INFO "Successfully put all powerdomains " 3638bd22949SKevin Hilman "to target state\n"); 3648bd22949SKevin Hilman 3658bd22949SKevin Hilman return ret; 3668bd22949SKevin Hilman } 3678bd22949SKevin Hilman 3682466211eSTero Kristo static int omap3_pm_enter(suspend_state_t unused) 3698bd22949SKevin Hilman { 3708bd22949SKevin Hilman int ret = 0; 3718bd22949SKevin Hilman 3722466211eSTero Kristo switch (suspend_state) { 3738bd22949SKevin Hilman case PM_SUSPEND_STANDBY: 3748bd22949SKevin Hilman case PM_SUSPEND_MEM: 3758bd22949SKevin Hilman ret = omap3_pm_suspend(); 3768bd22949SKevin Hilman break; 3778bd22949SKevin Hilman default: 3788bd22949SKevin Hilman ret = -EINVAL; 3798bd22949SKevin Hilman } 3808bd22949SKevin Hilman 3818bd22949SKevin Hilman return ret; 3828bd22949SKevin Hilman } 3838bd22949SKevin Hilman 3848bd22949SKevin Hilman static void omap3_pm_finish(void) 3858bd22949SKevin Hilman { 3868bd22949SKevin Hilman enable_hlt(); 3878bd22949SKevin Hilman } 3888bd22949SKevin Hilman 3892466211eSTero Kristo /* Hooks to enable / disable UART interrupts during suspend */ 3902466211eSTero Kristo static int omap3_pm_begin(suspend_state_t state) 3912466211eSTero Kristo { 3922466211eSTero Kristo suspend_state = state; 3932466211eSTero Kristo omap_uart_enable_irqs(0); 3942466211eSTero Kristo return 0; 3952466211eSTero Kristo } 3962466211eSTero Kristo 3972466211eSTero Kristo static void omap3_pm_end(void) 3982466211eSTero Kristo { 3992466211eSTero Kristo suspend_state = PM_SUSPEND_ON; 4002466211eSTero Kristo omap_uart_enable_irqs(1); 4012466211eSTero Kristo return; 4022466211eSTero Kristo } 4032466211eSTero Kristo 4048bd22949SKevin Hilman static struct platform_suspend_ops omap_pm_ops = { 4052466211eSTero Kristo .begin = omap3_pm_begin, 4062466211eSTero Kristo .end = omap3_pm_end, 4078bd22949SKevin Hilman .prepare = omap3_pm_prepare, 4088bd22949SKevin Hilman .enter = omap3_pm_enter, 4098bd22949SKevin Hilman .finish = omap3_pm_finish, 4108bd22949SKevin Hilman .valid = suspend_valid_only_mem, 4118bd22949SKevin Hilman }; 41210f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 4138bd22949SKevin Hilman 4141155e426SKevin Hilman 4151155e426SKevin Hilman /** 4161155e426SKevin Hilman * omap3_iva_idle(): ensure IVA is in idle so it can be put into 4171155e426SKevin Hilman * retention 4181155e426SKevin Hilman * 4191155e426SKevin Hilman * In cases where IVA2 is activated by bootcode, it may prevent 4201155e426SKevin Hilman * full-chip retention or off-mode because it is not idle. This 4211155e426SKevin Hilman * function forces the IVA2 into idle state so it can go 4221155e426SKevin Hilman * into retention/off and thus allow full-chip retention/off. 4231155e426SKevin Hilman * 4241155e426SKevin Hilman **/ 4251155e426SKevin Hilman static void __init omap3_iva_idle(void) 4261155e426SKevin Hilman { 4271155e426SKevin Hilman /* ensure IVA2 clock is disabled */ 4281155e426SKevin Hilman cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 4291155e426SKevin Hilman 4301155e426SKevin Hilman /* if no clock activity, nothing else to do */ 4311155e426SKevin Hilman if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & 4321155e426SKevin Hilman OMAP3430_CLKACTIVITY_IVA2_MASK)) 4331155e426SKevin Hilman return; 4341155e426SKevin Hilman 4351155e426SKevin Hilman /* Reset IVA2 */ 4361155e426SKevin Hilman prm_write_mod_reg(OMAP3430_RST1_IVA2 | 4371155e426SKevin Hilman OMAP3430_RST2_IVA2 | 4381155e426SKevin Hilman OMAP3430_RST3_IVA2, 4391155e426SKevin Hilman OMAP3430_IVA2_MOD, RM_RSTCTRL); 4401155e426SKevin Hilman 4411155e426SKevin Hilman /* Enable IVA2 clock */ 4421155e426SKevin Hilman cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2, 4431155e426SKevin Hilman OMAP3430_IVA2_MOD, CM_FCLKEN); 4441155e426SKevin Hilman 4451155e426SKevin Hilman /* Set IVA2 boot mode to 'idle' */ 4461155e426SKevin Hilman omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, 4471155e426SKevin Hilman OMAP343X_CONTROL_IVA2_BOOTMOD); 4481155e426SKevin Hilman 4491155e426SKevin Hilman /* Un-reset IVA2 */ 4501155e426SKevin Hilman prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL); 4511155e426SKevin Hilman 4521155e426SKevin Hilman /* Disable IVA2 clock */ 4531155e426SKevin Hilman cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 4541155e426SKevin Hilman 4551155e426SKevin Hilman /* Reset IVA2 */ 4561155e426SKevin Hilman prm_write_mod_reg(OMAP3430_RST1_IVA2 | 4571155e426SKevin Hilman OMAP3430_RST2_IVA2 | 4581155e426SKevin Hilman OMAP3430_RST3_IVA2, 4591155e426SKevin Hilman OMAP3430_IVA2_MOD, RM_RSTCTRL); 4601155e426SKevin Hilman } 4611155e426SKevin Hilman 4628111b221SKevin Hilman static void __init omap3_d2d_idle(void) 4638bd22949SKevin Hilman { 4648111b221SKevin Hilman u16 mask, padconf; 4658111b221SKevin Hilman 4668111b221SKevin Hilman /* In a stand alone OMAP3430 where there is not a stacked 4678111b221SKevin Hilman * modem for the D2D Idle Ack and D2D MStandby must be pulled 4688111b221SKevin Hilman * high. S CONTROL_PADCONF_SAD2D_IDLEACK and 4698111b221SKevin Hilman * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ 4708111b221SKevin Hilman mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ 4718111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); 4728111b221SKevin Hilman padconf |= mask; 4738111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); 4748111b221SKevin Hilman 4758111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); 4768111b221SKevin Hilman padconf |= mask; 4778111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 4788111b221SKevin Hilman 4798bd22949SKevin Hilman /* reset modem */ 4808bd22949SKevin Hilman prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON | 4818bd22949SKevin Hilman OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST, 4828bd22949SKevin Hilman CORE_MOD, RM_RSTCTRL); 4838bd22949SKevin Hilman prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL); 4848111b221SKevin Hilman } 4858bd22949SKevin Hilman 4868111b221SKevin Hilman static void __init prcm_setup_regs(void) 4878111b221SKevin Hilman { 4888bd22949SKevin Hilman /* XXX Reset all wkdeps. This should be done when initializing 4898bd22949SKevin Hilman * powerdomains */ 4908bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); 4918bd22949SKevin Hilman prm_write_mod_reg(0, MPU_MOD, PM_WKDEP); 4928bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP); 4938bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP); 4948bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP); 4958bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP); 4968bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 4978bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP); 4988bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP); 4998bd22949SKevin Hilman } else 5008bd22949SKevin Hilman prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); 5018bd22949SKevin Hilman 5028bd22949SKevin Hilman /* 5038bd22949SKevin Hilman * Enable interface clock autoidle for all modules. 5048bd22949SKevin Hilman * Note that in the long run this should be done by clockfw 5058bd22949SKevin Hilman */ 5068bd22949SKevin Hilman cm_write_mod_reg( 5078111b221SKevin Hilman OMAP3430_AUTO_MODEM | 5088bd22949SKevin Hilman OMAP3430ES2_AUTO_MMC3 | 5098bd22949SKevin Hilman OMAP3430ES2_AUTO_ICR | 5108bd22949SKevin Hilman OMAP3430_AUTO_AES2 | 5118bd22949SKevin Hilman OMAP3430_AUTO_SHA12 | 5128bd22949SKevin Hilman OMAP3430_AUTO_DES2 | 5138bd22949SKevin Hilman OMAP3430_AUTO_MMC2 | 5148bd22949SKevin Hilman OMAP3430_AUTO_MMC1 | 5158bd22949SKevin Hilman OMAP3430_AUTO_MSPRO | 5168bd22949SKevin Hilman OMAP3430_AUTO_HDQ | 5178bd22949SKevin Hilman OMAP3430_AUTO_MCSPI4 | 5188bd22949SKevin Hilman OMAP3430_AUTO_MCSPI3 | 5198bd22949SKevin Hilman OMAP3430_AUTO_MCSPI2 | 5208bd22949SKevin Hilman OMAP3430_AUTO_MCSPI1 | 5218bd22949SKevin Hilman OMAP3430_AUTO_I2C3 | 5228bd22949SKevin Hilman OMAP3430_AUTO_I2C2 | 5238bd22949SKevin Hilman OMAP3430_AUTO_I2C1 | 5248bd22949SKevin Hilman OMAP3430_AUTO_UART2 | 5258bd22949SKevin Hilman OMAP3430_AUTO_UART1 | 5268bd22949SKevin Hilman OMAP3430_AUTO_GPT11 | 5278bd22949SKevin Hilman OMAP3430_AUTO_GPT10 | 5288bd22949SKevin Hilman OMAP3430_AUTO_MCBSP5 | 5298bd22949SKevin Hilman OMAP3430_AUTO_MCBSP1 | 5308bd22949SKevin Hilman OMAP3430ES1_AUTO_FAC | /* This is es1 only */ 5318bd22949SKevin Hilman OMAP3430_AUTO_MAILBOXES | 5328bd22949SKevin Hilman OMAP3430_AUTO_OMAPCTRL | 5338bd22949SKevin Hilman OMAP3430ES1_AUTO_FSHOSTUSB | 5348bd22949SKevin Hilman OMAP3430_AUTO_HSOTGUSB | 5358111b221SKevin Hilman OMAP3430_AUTO_SAD2D | 5368bd22949SKevin Hilman OMAP3430_AUTO_SSI, 5378bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE1); 5388bd22949SKevin Hilman 5398bd22949SKevin Hilman cm_write_mod_reg( 5408bd22949SKevin Hilman OMAP3430_AUTO_PKA | 5418bd22949SKevin Hilman OMAP3430_AUTO_AES1 | 5428bd22949SKevin Hilman OMAP3430_AUTO_RNG | 5438bd22949SKevin Hilman OMAP3430_AUTO_SHA11 | 5448bd22949SKevin Hilman OMAP3430_AUTO_DES1, 5458bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE2); 5468bd22949SKevin Hilman 5478bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 5488bd22949SKevin Hilman cm_write_mod_reg( 5498111b221SKevin Hilman OMAP3430_AUTO_MAD2D | 5508bd22949SKevin Hilman OMAP3430ES2_AUTO_USBTLL, 5518bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE3); 5528bd22949SKevin Hilman } 5538bd22949SKevin Hilman 5548bd22949SKevin Hilman cm_write_mod_reg( 5558bd22949SKevin Hilman OMAP3430_AUTO_WDT2 | 5568bd22949SKevin Hilman OMAP3430_AUTO_WDT1 | 5578bd22949SKevin Hilman OMAP3430_AUTO_GPIO1 | 5588bd22949SKevin Hilman OMAP3430_AUTO_32KSYNC | 5598bd22949SKevin Hilman OMAP3430_AUTO_GPT12 | 5608bd22949SKevin Hilman OMAP3430_AUTO_GPT1 , 5618bd22949SKevin Hilman WKUP_MOD, CM_AUTOIDLE); 5628bd22949SKevin Hilman 5638bd22949SKevin Hilman cm_write_mod_reg( 5648bd22949SKevin Hilman OMAP3430_AUTO_DSS, 5658bd22949SKevin Hilman OMAP3430_DSS_MOD, 5668bd22949SKevin Hilman CM_AUTOIDLE); 5678bd22949SKevin Hilman 5688bd22949SKevin Hilman cm_write_mod_reg( 5698bd22949SKevin Hilman OMAP3430_AUTO_CAM, 5708bd22949SKevin Hilman OMAP3430_CAM_MOD, 5718bd22949SKevin Hilman CM_AUTOIDLE); 5728bd22949SKevin Hilman 5738bd22949SKevin Hilman cm_write_mod_reg( 5748bd22949SKevin Hilman OMAP3430_AUTO_GPIO6 | 5758bd22949SKevin Hilman OMAP3430_AUTO_GPIO5 | 5768bd22949SKevin Hilman OMAP3430_AUTO_GPIO4 | 5778bd22949SKevin Hilman OMAP3430_AUTO_GPIO3 | 5788bd22949SKevin Hilman OMAP3430_AUTO_GPIO2 | 5798bd22949SKevin Hilman OMAP3430_AUTO_WDT3 | 5808bd22949SKevin Hilman OMAP3430_AUTO_UART3 | 5818bd22949SKevin Hilman OMAP3430_AUTO_GPT9 | 5828bd22949SKevin Hilman OMAP3430_AUTO_GPT8 | 5838bd22949SKevin Hilman OMAP3430_AUTO_GPT7 | 5848bd22949SKevin Hilman OMAP3430_AUTO_GPT6 | 5858bd22949SKevin Hilman OMAP3430_AUTO_GPT5 | 5868bd22949SKevin Hilman OMAP3430_AUTO_GPT4 | 5878bd22949SKevin Hilman OMAP3430_AUTO_GPT3 | 5888bd22949SKevin Hilman OMAP3430_AUTO_GPT2 | 5898bd22949SKevin Hilman OMAP3430_AUTO_MCBSP4 | 5908bd22949SKevin Hilman OMAP3430_AUTO_MCBSP3 | 5918bd22949SKevin Hilman OMAP3430_AUTO_MCBSP2, 5928bd22949SKevin Hilman OMAP3430_PER_MOD, 5938bd22949SKevin Hilman CM_AUTOIDLE); 5948bd22949SKevin Hilman 5958bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 5968bd22949SKevin Hilman cm_write_mod_reg( 5978bd22949SKevin Hilman OMAP3430ES2_AUTO_USBHOST, 5988bd22949SKevin Hilman OMAP3430ES2_USBHOST_MOD, 5998bd22949SKevin Hilman CM_AUTOIDLE); 6008bd22949SKevin Hilman } 6018bd22949SKevin Hilman 6028bd22949SKevin Hilman /* 6038bd22949SKevin Hilman * Set all plls to autoidle. This is needed until autoidle is 6048bd22949SKevin Hilman * enabled by clockfw 6058bd22949SKevin Hilman */ 6068bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, 6078bd22949SKevin Hilman OMAP3430_IVA2_MOD, CM_AUTOIDLE2); 6088bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT, 6098bd22949SKevin Hilman MPU_MOD, 6108bd22949SKevin Hilman CM_AUTOIDLE2); 6118bd22949SKevin Hilman cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | 6128bd22949SKevin Hilman (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT), 6138bd22949SKevin Hilman PLL_MOD, 6148bd22949SKevin Hilman CM_AUTOIDLE); 6158bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, 6168bd22949SKevin Hilman PLL_MOD, 6178bd22949SKevin Hilman CM_AUTOIDLE2); 6188bd22949SKevin Hilman 6198bd22949SKevin Hilman /* 6208bd22949SKevin Hilman * Enable control of expternal oscillator through 6218bd22949SKevin Hilman * sys_clkreq. In the long run clock framework should 6228bd22949SKevin Hilman * take care of this. 6238bd22949SKevin Hilman */ 6248bd22949SKevin Hilman prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 6258bd22949SKevin Hilman 1 << OMAP_AUTOEXTCLKMODE_SHIFT, 6268bd22949SKevin Hilman OMAP3430_GR_MOD, 6278bd22949SKevin Hilman OMAP3_PRM_CLKSRC_CTRL_OFFSET); 6288bd22949SKevin Hilman 6298bd22949SKevin Hilman /* setup wakup source */ 6308bd22949SKevin Hilman prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 | 6318bd22949SKevin Hilman OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12, 6328bd22949SKevin Hilman WKUP_MOD, PM_WKEN); 6338bd22949SKevin Hilman /* No need to write EN_IO, that is always enabled */ 6348bd22949SKevin Hilman prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 | 6358bd22949SKevin Hilman OMAP3430_EN_GPT12, 6368bd22949SKevin Hilman WKUP_MOD, OMAP3430_PM_MPUGRPSEL); 6378bd22949SKevin Hilman /* For some reason IO doesn't generate wakeup event even if 6388bd22949SKevin Hilman * it is selected to mpu wakeup goup */ 6398bd22949SKevin Hilman prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN, 6408bd22949SKevin Hilman OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); 6411155e426SKevin Hilman 642eb350f74SKevin Hilman /* Enable GPIO wakeups in PER */ 643eb350f74SKevin Hilman prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 | 644eb350f74SKevin Hilman OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 | 645eb350f74SKevin Hilman OMAP3430_EN_GPIO6, OMAP3430_PER_MOD, PM_WKEN); 646eb350f74SKevin Hilman /* and allow them to wake up MPU */ 647eb350f74SKevin Hilman prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 | 648eb350f74SKevin Hilman OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 | 649eb350f74SKevin Hilman OMAP3430_GRPSEL_GPIO6, 650eb350f74SKevin Hilman OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); 651eb350f74SKevin Hilman 652d3fd3290SKevin Hilman /* Don't attach IVA interrupts */ 653d3fd3290SKevin Hilman prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 654d3fd3290SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 655d3fd3290SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 656d3fd3290SKevin Hilman prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); 657d3fd3290SKevin Hilman 658b1340d17SKevin Hilman /* Clear any pending 'reset' flags */ 659b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST); 660b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST); 661b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST); 662b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST); 663b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST); 664b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST); 665b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST); 666b1340d17SKevin Hilman 667014c46dbSKevin Hilman /* Clear any pending PRCM interrupts */ 668014c46dbSKevin Hilman prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 669014c46dbSKevin Hilman 670040fed05SKevin Hilman /* Don't attach IVA interrupts */ 671040fed05SKevin Hilman prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 672040fed05SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 673040fed05SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 674040fed05SKevin Hilman prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); 675040fed05SKevin Hilman 6763a07ae30SKevin Hilman /* Clear any pending 'reset' flags */ 6773a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST); 6783a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST); 6793a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST); 6803a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST); 6813a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST); 6823a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST); 6833a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST); 6843a07ae30SKevin Hilman 6853a6667acSKevin Hilman /* Clear any pending PRCM interrupts */ 6863a6667acSKevin Hilman prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 6873a6667acSKevin Hilman 6881155e426SKevin Hilman omap3_iva_idle(); 6898111b221SKevin Hilman omap3_d2d_idle(); 6908bd22949SKevin Hilman } 6918bd22949SKevin Hilman 69268d4778cSTero Kristo int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) 69368d4778cSTero Kristo { 69468d4778cSTero Kristo struct power_state *pwrst; 69568d4778cSTero Kristo 69668d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 69768d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) 69868d4778cSTero Kristo return pwrst->next_state; 69968d4778cSTero Kristo } 70068d4778cSTero Kristo return -EINVAL; 70168d4778cSTero Kristo } 70268d4778cSTero Kristo 70368d4778cSTero Kristo int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) 70468d4778cSTero Kristo { 70568d4778cSTero Kristo struct power_state *pwrst; 70668d4778cSTero Kristo 70768d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 70868d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) { 70968d4778cSTero Kristo pwrst->next_state = state; 71068d4778cSTero Kristo return 0; 71168d4778cSTero Kristo } 71268d4778cSTero Kristo } 71368d4778cSTero Kristo return -EINVAL; 71468d4778cSTero Kristo } 71568d4778cSTero Kristo 716a23456e9SPeter 'p2' De Schrijver static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) 7178bd22949SKevin Hilman { 7188bd22949SKevin Hilman struct power_state *pwrst; 7198bd22949SKevin Hilman 7208bd22949SKevin Hilman if (!pwrdm->pwrsts) 7218bd22949SKevin Hilman return 0; 7228bd22949SKevin Hilman 723d3d381c6SMing Lei pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); 7248bd22949SKevin Hilman if (!pwrst) 7258bd22949SKevin Hilman return -ENOMEM; 7268bd22949SKevin Hilman pwrst->pwrdm = pwrdm; 7278bd22949SKevin Hilman pwrst->next_state = PWRDM_POWER_RET; 7288bd22949SKevin Hilman list_add(&pwrst->node, &pwrst_list); 7298bd22949SKevin Hilman 7308bd22949SKevin Hilman if (pwrdm_has_hdwr_sar(pwrdm)) 7318bd22949SKevin Hilman pwrdm_enable_hdwr_sar(pwrdm); 7328bd22949SKevin Hilman 7338bd22949SKevin Hilman return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 7348bd22949SKevin Hilman } 7358bd22949SKevin Hilman 7368bd22949SKevin Hilman /* 7378bd22949SKevin Hilman * Enable hw supervised mode for all clockdomains if it's 7388bd22949SKevin Hilman * supported. Initiate sleep transition for other clockdomains, if 7398bd22949SKevin Hilman * they are not used 7408bd22949SKevin Hilman */ 741a23456e9SPeter 'p2' De Schrijver static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) 7428bd22949SKevin Hilman { 7438bd22949SKevin Hilman if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) 7448bd22949SKevin Hilman omap2_clkdm_allow_idle(clkdm); 7458bd22949SKevin Hilman else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && 7468bd22949SKevin Hilman atomic_read(&clkdm->usecount) == 0) 7478bd22949SKevin Hilman omap2_clkdm_sleep(clkdm); 7488bd22949SKevin Hilman return 0; 7498bd22949SKevin Hilman } 7508bd22949SKevin Hilman 7517cc515f7SKevin Hilman static int __init omap3_pm_init(void) 7528bd22949SKevin Hilman { 7538bd22949SKevin Hilman struct power_state *pwrst, *tmp; 7548bd22949SKevin Hilman int ret; 7558bd22949SKevin Hilman 7568bd22949SKevin Hilman if (!cpu_is_omap34xx()) 7578bd22949SKevin Hilman return -ENODEV; 7588bd22949SKevin Hilman 7598bd22949SKevin Hilman printk(KERN_ERR "Power Management for TI OMAP3.\n"); 7608bd22949SKevin Hilman 7618bd22949SKevin Hilman /* XXX prcm_setup_regs needs to be before enabling hw 7628bd22949SKevin Hilman * supervised mode for powerdomains */ 7638bd22949SKevin Hilman prcm_setup_regs(); 7648bd22949SKevin Hilman 7658bd22949SKevin Hilman ret = request_irq(INT_34XX_PRCM_MPU_IRQ, 7668bd22949SKevin Hilman (irq_handler_t)prcm_interrupt_handler, 7678bd22949SKevin Hilman IRQF_DISABLED, "prcm", NULL); 7688bd22949SKevin Hilman if (ret) { 7698bd22949SKevin Hilman printk(KERN_ERR "request_irq failed to register for 0x%x\n", 7708bd22949SKevin Hilman INT_34XX_PRCM_MPU_IRQ); 7718bd22949SKevin Hilman goto err1; 7728bd22949SKevin Hilman } 7738bd22949SKevin Hilman 774a23456e9SPeter 'p2' De Schrijver ret = pwrdm_for_each(pwrdms_setup, NULL); 7758bd22949SKevin Hilman if (ret) { 7768bd22949SKevin Hilman printk(KERN_ERR "Failed to setup powerdomains\n"); 7778bd22949SKevin Hilman goto err2; 7788bd22949SKevin Hilman } 7798bd22949SKevin Hilman 780a23456e9SPeter 'p2' De Schrijver (void) clkdm_for_each(clkdms_setup, NULL); 7818bd22949SKevin Hilman 7828bd22949SKevin Hilman mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); 7838bd22949SKevin Hilman if (mpu_pwrdm == NULL) { 7848bd22949SKevin Hilman printk(KERN_ERR "Failed to get mpu_pwrdm\n"); 7858bd22949SKevin Hilman goto err2; 7868bd22949SKevin Hilman } 7878bd22949SKevin Hilman 7888bd22949SKevin Hilman _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend, 7898bd22949SKevin Hilman omap34xx_cpu_suspend_sz); 7908bd22949SKevin Hilman 79110f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 7928bd22949SKevin Hilman suspend_set_ops(&omap_pm_ops); 79310f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 7948bd22949SKevin Hilman 7958bd22949SKevin Hilman pm_idle = omap3_pm_idle; 7968bd22949SKevin Hilman 7978bd22949SKevin Hilman err1: 7988bd22949SKevin Hilman return ret; 7998bd22949SKevin Hilman err2: 8008bd22949SKevin Hilman free_irq(INT_34XX_PRCM_MPU_IRQ, NULL); 8018bd22949SKevin Hilman list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { 8028bd22949SKevin Hilman list_del(&pwrst->node); 8038bd22949SKevin Hilman kfree(pwrst); 8048bd22949SKevin Hilman } 8058bd22949SKevin Hilman return ret; 8068bd22949SKevin Hilman } 8078bd22949SKevin Hilman 8088bd22949SKevin Hilman late_initcall(omap3_pm_init); 809