18bd22949SKevin Hilman /* 28bd22949SKevin Hilman * OMAP3 Power Management Routines 38bd22949SKevin Hilman * 48bd22949SKevin Hilman * Copyright (C) 2006-2008 Nokia Corporation 58bd22949SKevin Hilman * Tony Lindgren <tony@atomide.com> 68bd22949SKevin Hilman * Jouni Hogander 78bd22949SKevin Hilman * 82f5939c3SRajendra Nayak * Copyright (C) 2007 Texas Instruments, Inc. 92f5939c3SRajendra Nayak * Rajendra Nayak <rnayak@ti.com> 102f5939c3SRajendra Nayak * 118bd22949SKevin Hilman * Copyright (C) 2005 Texas Instruments, Inc. 128bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 138bd22949SKevin Hilman * 148bd22949SKevin Hilman * Based on pm.c for omap1 158bd22949SKevin Hilman * 168bd22949SKevin Hilman * This program is free software; you can redistribute it and/or modify 178bd22949SKevin Hilman * it under the terms of the GNU General Public License version 2 as 188bd22949SKevin Hilman * published by the Free Software Foundation. 198bd22949SKevin Hilman */ 208bd22949SKevin Hilman 218bd22949SKevin Hilman #include <linux/pm.h> 228bd22949SKevin Hilman #include <linux/suspend.h> 238bd22949SKevin Hilman #include <linux/interrupt.h> 248bd22949SKevin Hilman #include <linux/module.h> 258bd22949SKevin Hilman #include <linux/list.h> 268bd22949SKevin Hilman #include <linux/err.h> 278bd22949SKevin Hilman #include <linux/gpio.h> 28c40552bcSKevin Hilman #include <linux/clk.h> 29dccaad89STero Kristo #include <linux/delay.h> 305a0e3ad6STejun Heo #include <linux/slab.h> 314b25408fSTony Lindgren #include <linux/platform_data/gpio-omap.h> 324b25408fSTony Lindgren 335e7c58dcSJean Pihet #include <trace/events/power.h> 348bd22949SKevin Hilman 352c74a0ceSRussell King #include <asm/suspend.h> 369f97da78SDavid Howells #include <asm/system_misc.h> 372c74a0ceSRussell King 381540f214SPaul Walmsley #include "clockdomain.h" 3972e06d08SPaul Walmsley #include "powerdomain.h" 402f5939c3SRajendra Nayak #include <plat/prcm.h> 412b6c4e73SLokesh Vutla #include <plat-omap/dma-omap.h> 428bd22949SKevin Hilman 43622297fdSTony Lindgren #include "../plat-omap/sram.h" 44622297fdSTony Lindgren 45e4c060dbSTony Lindgren #include "soc.h" 464e65331cSTony Lindgren #include "common.h" 4759fb659bSPaul Walmsley #include "cm2xxx_3xxx.h" 488bd22949SKevin Hilman #include "cm-regbits-34xx.h" 4999f0b8d6STony Lindgren #include "gpmc.h" 508bd22949SKevin Hilman #include "prm-regbits-34xx.h" 518bd22949SKevin Hilman 5259fb659bSPaul Walmsley #include "prm2xxx_3xxx.h" 538bd22949SKevin Hilman #include "pm.h" 5413a6fe0fSTero Kristo #include "sdrc.h" 554814ced5SPaul Walmsley #include "control.h" 5613a6fe0fSTero Kristo 578cdfd834SNishanth Menon /* pm34xx errata defined in pm.h */ 588cdfd834SNishanth Menon u16 pm34xx_errata; 598cdfd834SNishanth Menon 608bd22949SKevin Hilman struct power_state { 618bd22949SKevin Hilman struct powerdomain *pwrdm; 628bd22949SKevin Hilman u32 next_state; 6310f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 648bd22949SKevin Hilman u32 saved_state; 6510f90ed2SKevin Hilman #endif 668bd22949SKevin Hilman struct list_head node; 678bd22949SKevin Hilman }; 688bd22949SKevin Hilman 698bd22949SKevin Hilman static LIST_HEAD(pwrst_list); 708bd22949SKevin Hilman 7127d59a4aSTero Kristo static int (*_omap_save_secure_sram)(u32 *addr); 7246e130d2SJean Pihet void (*omap3_do_wfi_sram)(void); 7327d59a4aSTero Kristo 74fa3c2a4fSRajendra Nayak static struct powerdomain *mpu_pwrdm, *neon_pwrdm; 75fa3c2a4fSRajendra Nayak static struct powerdomain *core_pwrdm, *per_pwrdm; 763a7ec26bSKalle Jokiniemi 772f5939c3SRajendra Nayak static void omap3_core_save_context(void) 782f5939c3SRajendra Nayak { 79596efe47SPaul Walmsley omap3_ctrl_save_padconf(); 80dccaad89STero Kristo 81dccaad89STero Kristo /* 82dccaad89STero Kristo * Force write last pad into memory, as this can fail in some 8383521291SJean Pihet * cases according to errata 1.157, 1.185 84dccaad89STero Kristo */ 85dccaad89STero Kristo omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), 86dccaad89STero Kristo OMAP343X_CONTROL_MEM_WKUP + 0x2a0); 87dccaad89STero Kristo 882f5939c3SRajendra Nayak /* Save the Interrupt controller context */ 892f5939c3SRajendra Nayak omap_intc_save_context(); 902f5939c3SRajendra Nayak /* Save the GPMC context */ 912f5939c3SRajendra Nayak omap3_gpmc_save_context(); 922f5939c3SRajendra Nayak /* Save the system control module context, padconf already save above*/ 932f5939c3SRajendra Nayak omap3_control_save_context(); 94f2d11858STero Kristo omap_dma_global_context_save(); 952f5939c3SRajendra Nayak } 962f5939c3SRajendra Nayak 972f5939c3SRajendra Nayak static void omap3_core_restore_context(void) 982f5939c3SRajendra Nayak { 992f5939c3SRajendra Nayak /* Restore the control module context, padconf restored by h/w */ 1002f5939c3SRajendra Nayak omap3_control_restore_context(); 1012f5939c3SRajendra Nayak /* Restore the GPMC context */ 1022f5939c3SRajendra Nayak omap3_gpmc_restore_context(); 1032f5939c3SRajendra Nayak /* Restore the interrupt controller context */ 1042f5939c3SRajendra Nayak omap_intc_restore_context(); 105f2d11858STero Kristo omap_dma_global_context_restore(); 1062f5939c3SRajendra Nayak } 1072f5939c3SRajendra Nayak 1089d97140bSTero Kristo /* 1099d97140bSTero Kristo * FIXME: This function should be called before entering off-mode after 1109d97140bSTero Kristo * OMAP3 secure services have been accessed. Currently it is only called 1119d97140bSTero Kristo * once during boot sequence, but this works as we are not using secure 1129d97140bSTero Kristo * services. 1139d97140bSTero Kristo */ 114617fcc98SKevin Hilman static void omap3_save_secure_ram_context(void) 11527d59a4aSTero Kristo { 11627d59a4aSTero Kristo u32 ret; 117617fcc98SKevin Hilman int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 11827d59a4aSTero Kristo 11927d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 12027d59a4aSTero Kristo /* 12127d59a4aSTero Kristo * MPU next state must be set to POWER_ON temporarily, 12227d59a4aSTero Kristo * otherwise the WFI executed inside the ROM code 12327d59a4aSTero Kristo * will hang the system. 12427d59a4aSTero Kristo */ 12527d59a4aSTero Kristo pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); 12627d59a4aSTero Kristo ret = _omap_save_secure_sram((u32 *) 12727d59a4aSTero Kristo __pa(omap3_secure_ram_storage)); 128617fcc98SKevin Hilman pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state); 12927d59a4aSTero Kristo /* Following is for error tracking, it should not happen */ 13027d59a4aSTero Kristo if (ret) { 13198179856SMark A. Greer pr_err("save_secure_sram() returns %08x\n", ret); 13227d59a4aSTero Kristo while (1) 13327d59a4aSTero Kristo ; 13427d59a4aSTero Kristo } 13527d59a4aSTero Kristo } 13627d59a4aSTero Kristo } 13727d59a4aSTero Kristo 13877da2d91SJon Hunter /* 13977da2d91SJon Hunter * PRCM Interrupt Handler Helper Function 14077da2d91SJon Hunter * 14177da2d91SJon Hunter * The purpose of this function is to clear any wake-up events latched 14277da2d91SJon Hunter * in the PRCM PM_WKST_x registers. It is possible that a wake-up event 14377da2d91SJon Hunter * may occur whilst attempting to clear a PM_WKST_x register and thus 14477da2d91SJon Hunter * set another bit in this register. A while loop is used to ensure 14577da2d91SJon Hunter * that any peripheral wake-up events occurring while attempting to 14677da2d91SJon Hunter * clear the PM_WKST_x are detected and cleared. 14777da2d91SJon Hunter */ 14822f51371STero Kristo static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits) 14977da2d91SJon Hunter { 15071a80775SVikram Pandita u32 wkst, fclk, iclk, clken; 15177da2d91SJon Hunter u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; 15277da2d91SJon Hunter u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; 15377da2d91SJon Hunter u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; 1545d805978SPaul Walmsley u16 grpsel_off = (regs == 3) ? 1555d805978SPaul Walmsley OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; 1568cb0ac99SPaul Walmsley int c = 0; 15777da2d91SJon Hunter 158c4d7e58fSPaul Walmsley wkst = omap2_prm_read_mod_reg(module, wkst_off); 159c4d7e58fSPaul Walmsley wkst &= omap2_prm_read_mod_reg(module, grpsel_off); 16022f51371STero Kristo wkst &= ~ignore_bits; 16177da2d91SJon Hunter if (wkst) { 162c4d7e58fSPaul Walmsley iclk = omap2_cm_read_mod_reg(module, iclk_off); 163c4d7e58fSPaul Walmsley fclk = omap2_cm_read_mod_reg(module, fclk_off); 16477da2d91SJon Hunter while (wkst) { 16571a80775SVikram Pandita clken = wkst; 166c4d7e58fSPaul Walmsley omap2_cm_set_mod_reg_bits(clken, module, iclk_off); 16771a80775SVikram Pandita /* 16871a80775SVikram Pandita * For USBHOST, we don't know whether HOST1 or 16971a80775SVikram Pandita * HOST2 woke us up, so enable both f-clocks 17071a80775SVikram Pandita */ 17171a80775SVikram Pandita if (module == OMAP3430ES2_USBHOST_MOD) 17271a80775SVikram Pandita clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; 173c4d7e58fSPaul Walmsley omap2_cm_set_mod_reg_bits(clken, module, fclk_off); 174c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(wkst, module, wkst_off); 175c4d7e58fSPaul Walmsley wkst = omap2_prm_read_mod_reg(module, wkst_off); 17622f51371STero Kristo wkst &= ~ignore_bits; 1778cb0ac99SPaul Walmsley c++; 17877da2d91SJon Hunter } 179c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(iclk, module, iclk_off); 180c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(fclk, module, fclk_off); 18177da2d91SJon Hunter } 1828cb0ac99SPaul Walmsley 1838cb0ac99SPaul Walmsley return c; 1848cb0ac99SPaul Walmsley } 1858cb0ac99SPaul Walmsley 18622f51371STero Kristo static irqreturn_t _prcm_int_handle_io(int irq, void *unused) 1878cb0ac99SPaul Walmsley { 1888cb0ac99SPaul Walmsley int c; 1898cb0ac99SPaul Walmsley 19022f51371STero Kristo c = prcm_clear_mod_irqs(WKUP_MOD, 1, 19122f51371STero Kristo ~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK)); 19222f51371STero Kristo 19322f51371STero Kristo return c ? IRQ_HANDLED : IRQ_NONE; 1948cb0ac99SPaul Walmsley } 1958cb0ac99SPaul Walmsley 19622f51371STero Kristo static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused) 1978bd22949SKevin Hilman { 19822f51371STero Kristo int c; 1998cb0ac99SPaul Walmsley 2008cb0ac99SPaul Walmsley /* 20122f51371STero Kristo * Clear all except ST_IO and ST_IO_CHAIN for wkup module, 20222f51371STero Kristo * these are handled in a separate handler to avoid acking 20322f51371STero Kristo * IO events before parsing in mux code 2048cb0ac99SPaul Walmsley */ 20522f51371STero Kristo c = prcm_clear_mod_irqs(WKUP_MOD, 1, 20622f51371STero Kristo OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK); 20722f51371STero Kristo c += prcm_clear_mod_irqs(CORE_MOD, 1, 0); 20822f51371STero Kristo c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0); 20922f51371STero Kristo if (omap_rev() > OMAP3430_REV_ES1_0) { 21022f51371STero Kristo c += prcm_clear_mod_irqs(CORE_MOD, 3, 0); 21122f51371STero Kristo c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0); 2128cb0ac99SPaul Walmsley } 2138cb0ac99SPaul Walmsley 21422f51371STero Kristo return c ? IRQ_HANDLED : IRQ_NONE; 2158bd22949SKevin Hilman } 2168bd22949SKevin Hilman 217cbe26349SRussell King static void omap34xx_save_context(u32 *save) 218cbe26349SRussell King { 219cbe26349SRussell King u32 val; 220cbe26349SRussell King 221cbe26349SRussell King /* Read Auxiliary Control Register */ 222cbe26349SRussell King asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val)); 223cbe26349SRussell King *save++ = 1; 224cbe26349SRussell King *save++ = val; 225cbe26349SRussell King 226cbe26349SRussell King /* Read L2 AUX ctrl register */ 227cbe26349SRussell King asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); 228cbe26349SRussell King *save++ = 1; 229cbe26349SRussell King *save++ = val; 230cbe26349SRussell King } 231cbe26349SRussell King 23229cb3cd2SRussell King static int omap34xx_do_sram_idle(unsigned long save_state) 23357f277b0SRajendra Nayak { 234cbe26349SRussell King omap34xx_cpu_suspend(save_state); 23529cb3cd2SRussell King return 0; 23657f277b0SRajendra Nayak } 23757f277b0SRajendra Nayak 23899e6a4d2SRajendra Nayak void omap_sram_idle(void) 2398bd22949SKevin Hilman { 2408bd22949SKevin Hilman /* Variable to tell what needs to be saved and restored 2418bd22949SKevin Hilman * in omap_sram_idle*/ 2428bd22949SKevin Hilman /* save_state = 0 => Nothing to save and restored */ 2438bd22949SKevin Hilman /* save_state = 1 => Only L1 and logic lost */ 2448bd22949SKevin Hilman /* save_state = 2 => Only L2 lost */ 2458bd22949SKevin Hilman /* save_state = 3 => L1, L2 and logic lost */ 246fa3c2a4fSRajendra Nayak int save_state = 0; 247fa3c2a4fSRajendra Nayak int mpu_next_state = PWRDM_POWER_ON; 248fa3c2a4fSRajendra Nayak int per_next_state = PWRDM_POWER_ON; 249fa3c2a4fSRajendra Nayak int core_next_state = PWRDM_POWER_ON; 25072e06d08SPaul Walmsley int per_going_off; 251eeb3711bSPaul Walmsley int core_prev_state; 25213a6fe0fSTero Kristo u32 sdrc_pwr = 0; 2538bd22949SKevin Hilman 2548bd22949SKevin Hilman mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 2558bd22949SKevin Hilman switch (mpu_next_state) { 256fa3c2a4fSRajendra Nayak case PWRDM_POWER_ON: 2578bd22949SKevin Hilman case PWRDM_POWER_RET: 2588bd22949SKevin Hilman /* No need to save context */ 2598bd22949SKevin Hilman save_state = 0; 2608bd22949SKevin Hilman break; 26161255ab9SRajendra Nayak case PWRDM_POWER_OFF: 26261255ab9SRajendra Nayak save_state = 3; 26361255ab9SRajendra Nayak break; 2648bd22949SKevin Hilman default: 2658bd22949SKevin Hilman /* Invalid state */ 26698179856SMark A. Greer pr_err("Invalid mpu state in sram_idle\n"); 2678bd22949SKevin Hilman return; 2688bd22949SKevin Hilman } 269fe617af7SPeter 'p2' De Schrijver 270fa3c2a4fSRajendra Nayak /* NEON control */ 271fa3c2a4fSRajendra Nayak if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) 2727139178eSJouni Hogander pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); 273fa3c2a4fSRajendra Nayak 27440742fa8SMike Chan /* Enable IO-PAD and IO-CHAIN wakeups */ 275fa3c2a4fSRajendra Nayak per_next_state = pwrdm_read_next_pwrst(per_pwrdm); 276ecf157d0STero Kristo core_next_state = pwrdm_read_next_pwrst(core_pwrdm); 27740742fa8SMike Chan 278e0e29fd7SKevin Hilman pwrdm_pre_transition(NULL); 279ff2f8e5fSCharulatha V 28040742fa8SMike Chan /* PER */ 2812f5939c3SRajendra Nayak if (per_next_state < PWRDM_POWER_ON) { 28272e06d08SPaul Walmsley per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0; 28372e06d08SPaul Walmsley omap2_gpio_prepare_for_idle(per_going_off); 2842f5939c3SRajendra Nayak } 285c16c3f67STero Kristo 286658ce97eSKevin Hilman /* CORE */ 287658ce97eSKevin Hilman if (core_next_state < PWRDM_POWER_ON) { 2882f5939c3SRajendra Nayak if (core_next_state == PWRDM_POWER_OFF) { 2892f5939c3SRajendra Nayak omap3_core_save_context(); 290f0611a5cSPaul Walmsley omap3_cm_save_context(); 2912f5939c3SRajendra Nayak } 292fa3c2a4fSRajendra Nayak } 29340742fa8SMike Chan 294f18cc2ffSTero Kristo omap3_intc_prepare_idle(); 2958bd22949SKevin Hilman 29661255ab9SRajendra Nayak /* 297f265dc4cSRajendra Nayak * On EMU/HS devices ROM code restores a SRDC value 298f265dc4cSRajendra Nayak * from scratchpad which has automatic self refresh on timeout 29983521291SJean Pihet * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443. 300f265dc4cSRajendra Nayak * Hence store/restore the SDRC_POWER register here. 30113a6fe0fSTero Kristo */ 30230474544SPaul Walmsley if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && 30330474544SPaul Walmsley (omap_type() == OMAP2_DEVICE_TYPE_EMU || 30430474544SPaul Walmsley omap_type() == OMAP2_DEVICE_TYPE_SEC) && 305f265dc4cSRajendra Nayak core_next_state == PWRDM_POWER_OFF) 30613a6fe0fSTero Kristo sdrc_pwr = sdrc_read_reg(SDRC_POWER); 30713a6fe0fSTero Kristo 30813a6fe0fSTero Kristo /* 309076f2cc4SRussell King * omap3_arm_context is the location where some ARM context 310076f2cc4SRussell King * get saved. The rest is placed on the stack, and restored 311076f2cc4SRussell King * from there before resuming. 31261255ab9SRajendra Nayak */ 313cbe26349SRussell King if (save_state) 314cbe26349SRussell King omap34xx_save_context(omap3_arm_context); 315076f2cc4SRussell King if (save_state == 1 || save_state == 3) 3162c74a0ceSRussell King cpu_suspend(save_state, omap34xx_do_sram_idle); 317076f2cc4SRussell King else 318076f2cc4SRussell King omap34xx_do_sram_idle(save_state); 3198bd22949SKevin Hilman 320f265dc4cSRajendra Nayak /* Restore normal SDRC POWER settings */ 32130474544SPaul Walmsley if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && 32230474544SPaul Walmsley (omap_type() == OMAP2_DEVICE_TYPE_EMU || 32330474544SPaul Walmsley omap_type() == OMAP2_DEVICE_TYPE_SEC) && 32413a6fe0fSTero Kristo core_next_state == PWRDM_POWER_OFF) 32513a6fe0fSTero Kristo sdrc_write_reg(sdrc_pwr, SDRC_POWER); 32613a6fe0fSTero Kristo 327658ce97eSKevin Hilman /* CORE */ 328fa3c2a4fSRajendra Nayak if (core_next_state < PWRDM_POWER_ON) { 3292f5939c3SRajendra Nayak core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); 3302f5939c3SRajendra Nayak if (core_prev_state == PWRDM_POWER_OFF) { 3312f5939c3SRajendra Nayak omap3_core_restore_context(); 332f0611a5cSPaul Walmsley omap3_cm_restore_context(); 3332f5939c3SRajendra Nayak omap3_sram_restore_context(); 3348a917d2fSKalle Jokiniemi omap2_sms_restore_context(); 3352f5939c3SRajendra Nayak } 336658ce97eSKevin Hilman if (core_next_state == PWRDM_POWER_OFF) 337c4d7e58fSPaul Walmsley omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, 338658ce97eSKevin Hilman OMAP3430_GR_MOD, 339658ce97eSKevin Hilman OMAP3_PRM_VOLTCTRL_OFFSET); 340658ce97eSKevin Hilman } 341f18cc2ffSTero Kristo omap3_intc_resume_idle(); 342658ce97eSKevin Hilman 343e0e29fd7SKevin Hilman pwrdm_post_transition(NULL); 344658ce97eSKevin Hilman 345e0e29fd7SKevin Hilman /* PER */ 346e0e29fd7SKevin Hilman if (per_next_state < PWRDM_POWER_ON) 347e0e29fd7SKevin Hilman omap2_gpio_resume_after_idle(); 3488bd22949SKevin Hilman } 3498bd22949SKevin Hilman 3508bd22949SKevin Hilman static void omap3_pm_idle(void) 3518bd22949SKevin Hilman { 3528bd22949SKevin Hilman local_fiq_disable(); 3538bd22949SKevin Hilman 3540bcd24b0SNicolas Pitre if (omap_irq_pending()) 3558bd22949SKevin Hilman goto out; 3568bd22949SKevin Hilman 3575e7c58dcSJean Pihet trace_power_start(POWER_CSTATE, 1, smp_processor_id()); 3585e7c58dcSJean Pihet trace_cpu_idle(1, smp_processor_id()); 3595e7c58dcSJean Pihet 3608bd22949SKevin Hilman omap_sram_idle(); 3618bd22949SKevin Hilman 3625e7c58dcSJean Pihet trace_power_end(smp_processor_id()); 3635e7c58dcSJean Pihet trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); 3645e7c58dcSJean Pihet 3658bd22949SKevin Hilman out: 3668bd22949SKevin Hilman local_fiq_enable(); 3678bd22949SKevin Hilman } 3688bd22949SKevin Hilman 36910f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 3708bd22949SKevin Hilman static int omap3_pm_suspend(void) 3718bd22949SKevin Hilman { 3728bd22949SKevin Hilman struct power_state *pwrst; 3738bd22949SKevin Hilman int state, ret = 0; 3748bd22949SKevin Hilman 3758bd22949SKevin Hilman /* Read current next_pwrsts */ 3768bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) 3778bd22949SKevin Hilman pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 3788bd22949SKevin Hilman /* Set ones wanted by suspend */ 3798bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 380eb6a2c75SSantosh Shilimkar if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) 3818bd22949SKevin Hilman goto restore; 3828bd22949SKevin Hilman if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) 3838bd22949SKevin Hilman goto restore; 3848bd22949SKevin Hilman } 3858bd22949SKevin Hilman 3862bbe3af3STero Kristo omap3_intc_suspend(); 3872bbe3af3STero Kristo 3888bd22949SKevin Hilman omap_sram_idle(); 3898bd22949SKevin Hilman 3908bd22949SKevin Hilman restore: 3918bd22949SKevin Hilman /* Restore next_pwrsts */ 3928bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 3938bd22949SKevin Hilman state = pwrdm_read_prev_pwrst(pwrst->pwrdm); 3948bd22949SKevin Hilman if (state > pwrst->next_state) { 3957852ec05SPaul Walmsley pr_info("Powerdomain (%s) didn't enter target state %d\n", 3968bd22949SKevin Hilman pwrst->pwrdm->name, pwrst->next_state); 3978bd22949SKevin Hilman ret = -1; 3988bd22949SKevin Hilman } 399eb6a2c75SSantosh Shilimkar omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); 4008bd22949SKevin Hilman } 4018bd22949SKevin Hilman if (ret) 40298179856SMark A. Greer pr_err("Could not enter target state in pm_suspend\n"); 4038bd22949SKevin Hilman else 40498179856SMark A. Greer pr_info("Successfully put all powerdomains to target state\n"); 4058bd22949SKevin Hilman 4068bd22949SKevin Hilman return ret; 4078bd22949SKevin Hilman } 4088bd22949SKevin Hilman 40910f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 4108bd22949SKevin Hilman 4111155e426SKevin Hilman 4121155e426SKevin Hilman /** 4131155e426SKevin Hilman * omap3_iva_idle(): ensure IVA is in idle so it can be put into 4141155e426SKevin Hilman * retention 4151155e426SKevin Hilman * 4161155e426SKevin Hilman * In cases where IVA2 is activated by bootcode, it may prevent 4171155e426SKevin Hilman * full-chip retention or off-mode because it is not idle. This 4181155e426SKevin Hilman * function forces the IVA2 into idle state so it can go 4191155e426SKevin Hilman * into retention/off and thus allow full-chip retention/off. 4201155e426SKevin Hilman * 4211155e426SKevin Hilman **/ 4221155e426SKevin Hilman static void __init omap3_iva_idle(void) 4231155e426SKevin Hilman { 4241155e426SKevin Hilman /* ensure IVA2 clock is disabled */ 425c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 4261155e426SKevin Hilman 4271155e426SKevin Hilman /* if no clock activity, nothing else to do */ 428c4d7e58fSPaul Walmsley if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & 4291155e426SKevin Hilman OMAP3430_CLKACTIVITY_IVA2_MASK)) 4301155e426SKevin Hilman return; 4311155e426SKevin Hilman 4321155e426SKevin Hilman /* Reset IVA2 */ 433c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | 4342bc4ef71SPaul Walmsley OMAP3430_RST2_IVA2_MASK | 4352bc4ef71SPaul Walmsley OMAP3430_RST3_IVA2_MASK, 43637903009SAbhijit Pagare OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 4371155e426SKevin Hilman 4381155e426SKevin Hilman /* Enable IVA2 clock */ 439c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, 4401155e426SKevin Hilman OMAP3430_IVA2_MOD, CM_FCLKEN); 4411155e426SKevin Hilman 4421155e426SKevin Hilman /* Set IVA2 boot mode to 'idle' */ 4431155e426SKevin Hilman omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, 4441155e426SKevin Hilman OMAP343X_CONTROL_IVA2_BOOTMOD); 4451155e426SKevin Hilman 4461155e426SKevin Hilman /* Un-reset IVA2 */ 447c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 4481155e426SKevin Hilman 4491155e426SKevin Hilman /* Disable IVA2 clock */ 450c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 4511155e426SKevin Hilman 4521155e426SKevin Hilman /* Reset IVA2 */ 453c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | 4542bc4ef71SPaul Walmsley OMAP3430_RST2_IVA2_MASK | 4552bc4ef71SPaul Walmsley OMAP3430_RST3_IVA2_MASK, 45637903009SAbhijit Pagare OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 4571155e426SKevin Hilman } 4581155e426SKevin Hilman 4598111b221SKevin Hilman static void __init omap3_d2d_idle(void) 4608bd22949SKevin Hilman { 4618111b221SKevin Hilman u16 mask, padconf; 4628111b221SKevin Hilman 4638111b221SKevin Hilman /* In a stand alone OMAP3430 where there is not a stacked 4648111b221SKevin Hilman * modem for the D2D Idle Ack and D2D MStandby must be pulled 4658111b221SKevin Hilman * high. S CONTROL_PADCONF_SAD2D_IDLEACK and 4668111b221SKevin Hilman * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ 4678111b221SKevin Hilman mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ 4688111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); 4698111b221SKevin Hilman padconf |= mask; 4708111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); 4718111b221SKevin Hilman 4728111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); 4738111b221SKevin Hilman padconf |= mask; 4748111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 4758111b221SKevin Hilman 4768bd22949SKevin Hilman /* reset modem */ 477c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | 4782bc4ef71SPaul Walmsley OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, 47937903009SAbhijit Pagare CORE_MOD, OMAP2_RM_RSTCTRL); 480c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); 4818111b221SKevin Hilman } 4828bd22949SKevin Hilman 4838111b221SKevin Hilman static void __init prcm_setup_regs(void) 4848111b221SKevin Hilman { 485e5863689SGovindraj.R u32 omap3630_en_uart4_mask = cpu_is_omap3630() ? 486e5863689SGovindraj.R OMAP3630_EN_UART4_MASK : 0; 487e5863689SGovindraj.R u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ? 488e5863689SGovindraj.R OMAP3630_GRPSEL_UART4_MASK : 0; 489e5863689SGovindraj.R 4904ef70c06SPaul Walmsley /* XXX This should be handled by hwmod code or SCM init code */ 4912fd0f75cSPaul Walmsley omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); 492b296c811STero Kristo 4938bd22949SKevin Hilman /* 4948bd22949SKevin Hilman * Enable control of expternal oscillator through 4958bd22949SKevin Hilman * sys_clkreq. In the long run clock framework should 4968bd22949SKevin Hilman * take care of this. 4978bd22949SKevin Hilman */ 498c4d7e58fSPaul Walmsley omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 4998bd22949SKevin Hilman 1 << OMAP_AUTOEXTCLKMODE_SHIFT, 5008bd22949SKevin Hilman OMAP3430_GR_MOD, 5018bd22949SKevin Hilman OMAP3_PRM_CLKSRC_CTRL_OFFSET); 5028bd22949SKevin Hilman 5038bd22949SKevin Hilman /* setup wakup source */ 504c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | 5052fd0f75cSPaul Walmsley OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, 5068bd22949SKevin Hilman WKUP_MOD, PM_WKEN); 5078bd22949SKevin Hilman /* No need to write EN_IO, that is always enabled */ 508c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | 509275f675cSPaul Walmsley OMAP3430_GRPSEL_GPT1_MASK | 510275f675cSPaul Walmsley OMAP3430_GRPSEL_GPT12_MASK, 5118bd22949SKevin Hilman WKUP_MOD, OMAP3430_PM_MPUGRPSEL); 5121155e426SKevin Hilman 513b92c5721SSubramani Venkatesh /* Enable PM_WKEN to support DSS LPR */ 514c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, 515b92c5721SSubramani Venkatesh OMAP3430_DSS_MOD, PM_WKEN); 516b92c5721SSubramani Venkatesh 517b427f92fSKevin Hilman /* Enable wakeups in PER */ 518c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(omap3630_en_uart4_mask | 519e5863689SGovindraj.R OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | 5202fd0f75cSPaul Walmsley OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | 5212fd0f75cSPaul Walmsley OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | 5222fd0f75cSPaul Walmsley OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK | 5232fd0f75cSPaul Walmsley OMAP3430_EN_MCBSP4_MASK, 524b427f92fSKevin Hilman OMAP3430_PER_MOD, PM_WKEN); 525eb350f74SKevin Hilman /* and allow them to wake up MPU */ 526c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask | 527e5863689SGovindraj.R OMAP3430_GRPSEL_GPIO2_MASK | 528275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO3_MASK | 529275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO4_MASK | 530275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO5_MASK | 531275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO6_MASK | 532275f675cSPaul Walmsley OMAP3430_GRPSEL_UART3_MASK | 533275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP2_MASK | 534275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP3_MASK | 535275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP4_MASK, 536eb350f74SKevin Hilman OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); 537eb350f74SKevin Hilman 538d3fd3290SKevin Hilman /* Don't attach IVA interrupts */ 539a819c4f1SMark A. Greer if (omap3_has_iva()) { 540c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 541c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 542c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 543a819c4f1SMark A. Greer omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, 544a819c4f1SMark A. Greer OMAP3430_PM_IVAGRPSEL); 545a819c4f1SMark A. Greer } 546d3fd3290SKevin Hilman 547b1340d17SKevin Hilman /* Clear any pending 'reset' flags */ 548c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); 549c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); 550c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); 551c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); 552c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); 553c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); 554c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); 555b1340d17SKevin Hilman 556014c46dbSKevin Hilman /* Clear any pending PRCM interrupts */ 557c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 558014c46dbSKevin Hilman 559a819c4f1SMark A. Greer if (omap3_has_iva()) 5601155e426SKevin Hilman omap3_iva_idle(); 561a819c4f1SMark A. Greer 5628111b221SKevin Hilman omap3_d2d_idle(); 5638bd22949SKevin Hilman } 5648bd22949SKevin Hilman 565c40552bcSKevin Hilman void omap3_pm_off_mode_enable(int enable) 566c40552bcSKevin Hilman { 567c40552bcSKevin Hilman struct power_state *pwrst; 568c40552bcSKevin Hilman u32 state; 569c40552bcSKevin Hilman 570c40552bcSKevin Hilman if (enable) 571c40552bcSKevin Hilman state = PWRDM_POWER_OFF; 572c40552bcSKevin Hilman else 573c40552bcSKevin Hilman state = PWRDM_POWER_RET; 574c40552bcSKevin Hilman 575c40552bcSKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 576cc1b6028SEduardo Valentin if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) && 577cc1b6028SEduardo Valentin pwrst->pwrdm == core_pwrdm && 578cc1b6028SEduardo Valentin state == PWRDM_POWER_OFF) { 579cc1b6028SEduardo Valentin pwrst->next_state = PWRDM_POWER_RET; 580e16b41bfSRicardo Salveti de Araujo pr_warn("%s: Core OFF disabled due to errata i583\n", 581cc1b6028SEduardo Valentin __func__); 582cc1b6028SEduardo Valentin } else { 583c40552bcSKevin Hilman pwrst->next_state = state; 584cc1b6028SEduardo Valentin } 585cc1b6028SEduardo Valentin omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 586c40552bcSKevin Hilman } 587c40552bcSKevin Hilman } 588c40552bcSKevin Hilman 58968d4778cSTero Kristo int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) 59068d4778cSTero Kristo { 59168d4778cSTero Kristo struct power_state *pwrst; 59268d4778cSTero Kristo 59368d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 59468d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) 59568d4778cSTero Kristo return pwrst->next_state; 59668d4778cSTero Kristo } 59768d4778cSTero Kristo return -EINVAL; 59868d4778cSTero Kristo } 59968d4778cSTero Kristo 60068d4778cSTero Kristo int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) 60168d4778cSTero Kristo { 60268d4778cSTero Kristo struct power_state *pwrst; 60368d4778cSTero Kristo 60468d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 60568d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) { 60668d4778cSTero Kristo pwrst->next_state = state; 60768d4778cSTero Kristo return 0; 60868d4778cSTero Kristo } 60968d4778cSTero Kristo } 61068d4778cSTero Kristo return -EINVAL; 61168d4778cSTero Kristo } 61268d4778cSTero Kristo 613a23456e9SPeter 'p2' De Schrijver static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) 6148bd22949SKevin Hilman { 6158bd22949SKevin Hilman struct power_state *pwrst; 6168bd22949SKevin Hilman 6178bd22949SKevin Hilman if (!pwrdm->pwrsts) 6188bd22949SKevin Hilman return 0; 6198bd22949SKevin Hilman 620d3d381c6SMing Lei pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); 6218bd22949SKevin Hilman if (!pwrst) 6228bd22949SKevin Hilman return -ENOMEM; 6238bd22949SKevin Hilman pwrst->pwrdm = pwrdm; 6248bd22949SKevin Hilman pwrst->next_state = PWRDM_POWER_RET; 6258bd22949SKevin Hilman list_add(&pwrst->node, &pwrst_list); 6268bd22949SKevin Hilman 6278bd22949SKevin Hilman if (pwrdm_has_hdwr_sar(pwrdm)) 6288bd22949SKevin Hilman pwrdm_enable_hdwr_sar(pwrdm); 6298bd22949SKevin Hilman 630eb6a2c75SSantosh Shilimkar return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 6318bd22949SKevin Hilman } 6328bd22949SKevin Hilman 6338bd22949SKevin Hilman /* 63446e130d2SJean Pihet * Push functions to SRAM 63546e130d2SJean Pihet * 63646e130d2SJean Pihet * The minimum set of functions is pushed to SRAM for execution: 63746e130d2SJean Pihet * - omap3_do_wfi for erratum i581 WA, 63846e130d2SJean Pihet * - save_secure_ram_context for security extensions. 63946e130d2SJean Pihet */ 6403231fc88SRajendra Nayak void omap_push_sram_idle(void) 6413231fc88SRajendra Nayak { 64246e130d2SJean Pihet omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz); 64346e130d2SJean Pihet 64427d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) 64527d59a4aSTero Kristo _omap_save_secure_sram = omap_sram_push(save_secure_ram_context, 64627d59a4aSTero Kristo save_secure_ram_context_sz); 6473231fc88SRajendra Nayak } 6483231fc88SRajendra Nayak 6498cdfd834SNishanth Menon static void __init pm_errata_configure(void) 6508cdfd834SNishanth Menon { 651c4236d2eSPeter 'p2' De Schrijver if (cpu_is_omap3630()) { 652458e999eSNishanth Menon pm34xx_errata |= PM_RTA_ERRATUM_i608; 653c4236d2eSPeter 'p2' De Schrijver /* Enable the l2 cache toggling in sleep logic */ 654c4236d2eSPeter 'p2' De Schrijver enable_omap3630_toggle_l2_on_restore(); 655cc1b6028SEduardo Valentin if (omap_rev() < OMAP3630_REV_ES1_2) 656cc1b6028SEduardo Valentin pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583; 657c4236d2eSPeter 'p2' De Schrijver } 6588cdfd834SNishanth Menon } 6598cdfd834SNishanth Menon 660bbd707acSShawn Guo int __init omap3_pm_init(void) 6618bd22949SKevin Hilman { 6628bd22949SKevin Hilman struct power_state *pwrst, *tmp; 663eeb3711bSPaul Walmsley struct clockdomain *neon_clkdm, *mpu_clkdm; 6648bd22949SKevin Hilman int ret; 6658bd22949SKevin Hilman 666b02b9172SPaul Walmsley if (!omap3_has_io_chain_ctrl()) 667b02b9172SPaul Walmsley pr_warning("PM: no software I/O chain control; some wakeups may be lost\n"); 668b02b9172SPaul Walmsley 6698cdfd834SNishanth Menon pm_errata_configure(); 6708cdfd834SNishanth Menon 6718bd22949SKevin Hilman /* XXX prcm_setup_regs needs to be before enabling hw 6728bd22949SKevin Hilman * supervised mode for powerdomains */ 6738bd22949SKevin Hilman prcm_setup_regs(); 6748bd22949SKevin Hilman 67522f51371STero Kristo ret = request_irq(omap_prcm_event_to_irq("wkup"), 67622f51371STero Kristo _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL); 67722f51371STero Kristo 6788bd22949SKevin Hilman if (ret) { 67922f51371STero Kristo pr_err("pm: Failed to request pm_wkup irq\n"); 68022f51371STero Kristo goto err1; 68122f51371STero Kristo } 68222f51371STero Kristo 68322f51371STero Kristo /* IO interrupt is shared with mux code */ 68422f51371STero Kristo ret = request_irq(omap_prcm_event_to_irq("io"), 68522f51371STero Kristo _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io", 68622f51371STero Kristo omap3_pm_init); 68799b59df0SKevin Hilman enable_irq(omap_prcm_event_to_irq("io")); 68822f51371STero Kristo 68922f51371STero Kristo if (ret) { 69022f51371STero Kristo pr_err("pm: Failed to request pm_io irq\n"); 691ce229c5dSMark A. Greer goto err2; 6928bd22949SKevin Hilman } 6938bd22949SKevin Hilman 694a23456e9SPeter 'p2' De Schrijver ret = pwrdm_for_each(pwrdms_setup, NULL); 6958bd22949SKevin Hilman if (ret) { 69698179856SMark A. Greer pr_err("Failed to setup powerdomains\n"); 697ce229c5dSMark A. Greer goto err3; 6988bd22949SKevin Hilman } 6998bd22949SKevin Hilman 70092206fd2SPaul Walmsley (void) clkdm_for_each(omap_pm_clkdms_setup, NULL); 7018bd22949SKevin Hilman 7028bd22949SKevin Hilman mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); 7038bd22949SKevin Hilman if (mpu_pwrdm == NULL) { 70498179856SMark A. Greer pr_err("Failed to get mpu_pwrdm\n"); 705ce229c5dSMark A. Greer ret = -EINVAL; 706ce229c5dSMark A. Greer goto err3; 7078bd22949SKevin Hilman } 7088bd22949SKevin Hilman 709fa3c2a4fSRajendra Nayak neon_pwrdm = pwrdm_lookup("neon_pwrdm"); 710fa3c2a4fSRajendra Nayak per_pwrdm = pwrdm_lookup("per_pwrdm"); 711fa3c2a4fSRajendra Nayak core_pwrdm = pwrdm_lookup("core_pwrdm"); 712fa3c2a4fSRajendra Nayak 71355ed9694SPaul Walmsley neon_clkdm = clkdm_lookup("neon_clkdm"); 71455ed9694SPaul Walmsley mpu_clkdm = clkdm_lookup("mpu_clkdm"); 71555ed9694SPaul Walmsley 71610f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 7171416408dSPaul Walmsley omap_pm_suspend = omap3_pm_suspend; 7181416408dSPaul Walmsley #endif 7198bd22949SKevin Hilman 7200bcd24b0SNicolas Pitre arm_pm_idle = omap3_pm_idle; 7210343371eSKalle Jokiniemi omap3_idle_init(); 7228bd22949SKevin Hilman 723458e999eSNishanth Menon /* 724458e999eSNishanth Menon * RTA is disabled during initialization as per erratum i608 725458e999eSNishanth Menon * it is safer to disable RTA by the bootloader, but we would like 726458e999eSNishanth Menon * to be doubly sure here and prevent any mishaps. 727458e999eSNishanth Menon */ 728458e999eSNishanth Menon if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608)) 729458e999eSNishanth Menon omap3630_ctrl_disable_rta(); 730458e999eSNishanth Menon 73155ed9694SPaul Walmsley clkdm_add_wkdep(neon_clkdm, mpu_clkdm); 73227d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 73327d59a4aSTero Kristo omap3_secure_ram_storage = 73427d59a4aSTero Kristo kmalloc(0x803F, GFP_KERNEL); 73527d59a4aSTero Kristo if (!omap3_secure_ram_storage) 7367852ec05SPaul Walmsley pr_err("Memory allocation failed when allocating for secure sram context\n"); 73727d59a4aSTero Kristo 7389d97140bSTero Kristo local_irq_disable(); 7399d97140bSTero Kristo local_fiq_disable(); 7409d97140bSTero Kristo 7419d97140bSTero Kristo omap_dma_global_context_save(); 742617fcc98SKevin Hilman omap3_save_secure_ram_context(); 7439d97140bSTero Kristo omap_dma_global_context_restore(); 7449d97140bSTero Kristo 7459d97140bSTero Kristo local_irq_enable(); 7469d97140bSTero Kristo local_fiq_enable(); 7479d97140bSTero Kristo } 7489d97140bSTero Kristo 7499d97140bSTero Kristo omap3_save_scratchpad_contents(); 7508bd22949SKevin Hilman return ret; 751ce229c5dSMark A. Greer 752ce229c5dSMark A. Greer err3: 7538bd22949SKevin Hilman list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { 7548bd22949SKevin Hilman list_del(&pwrst->node); 7558bd22949SKevin Hilman kfree(pwrst); 7568bd22949SKevin Hilman } 757ce229c5dSMark A. Greer free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init); 758ce229c5dSMark A. Greer err2: 759ce229c5dSMark A. Greer free_irq(omap_prcm_event_to_irq("wkup"), NULL); 760ce229c5dSMark A. Greer err1: 7618bd22949SKevin Hilman return ret; 7628bd22949SKevin Hilman } 763