18bd22949SKevin Hilman /* 28bd22949SKevin Hilman * OMAP3 Power Management Routines 38bd22949SKevin Hilman * 48bd22949SKevin Hilman * Copyright (C) 2006-2008 Nokia Corporation 58bd22949SKevin Hilman * Tony Lindgren <tony@atomide.com> 68bd22949SKevin Hilman * Jouni Hogander 78bd22949SKevin Hilman * 82f5939c3SRajendra Nayak * Copyright (C) 2007 Texas Instruments, Inc. 92f5939c3SRajendra Nayak * Rajendra Nayak <rnayak@ti.com> 102f5939c3SRajendra Nayak * 118bd22949SKevin Hilman * Copyright (C) 2005 Texas Instruments, Inc. 128bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 138bd22949SKevin Hilman * 148bd22949SKevin Hilman * Based on pm.c for omap1 158bd22949SKevin Hilman * 168bd22949SKevin Hilman * This program is free software; you can redistribute it and/or modify 178bd22949SKevin Hilman * it under the terms of the GNU General Public License version 2 as 188bd22949SKevin Hilman * published by the Free Software Foundation. 198bd22949SKevin Hilman */ 208bd22949SKevin Hilman 218bd22949SKevin Hilman #include <linux/pm.h> 228bd22949SKevin Hilman #include <linux/suspend.h> 238bd22949SKevin Hilman #include <linux/interrupt.h> 248bd22949SKevin Hilman #include <linux/module.h> 258bd22949SKevin Hilman #include <linux/list.h> 268bd22949SKevin Hilman #include <linux/err.h> 278bd22949SKevin Hilman #include <linux/gpio.h> 28c40552bcSKevin Hilman #include <linux/clk.h> 29dccaad89STero Kristo #include <linux/delay.h> 305a0e3ad6STejun Heo #include <linux/slab.h> 310d8e2d0dSPaul Walmsley #include <linux/console.h> 328bd22949SKevin Hilman 33ce491cf8STony Lindgren #include <plat/sram.h> 34ce491cf8STony Lindgren #include <plat/clockdomain.h> 35ce491cf8STony Lindgren #include <plat/powerdomain.h> 36ce491cf8STony Lindgren #include <plat/serial.h> 3761255ab9SRajendra Nayak #include <plat/sdrc.h> 382f5939c3SRajendra Nayak #include <plat/prcm.h> 392f5939c3SRajendra Nayak #include <plat/gpmc.h> 40f2d11858STero Kristo #include <plat/dma.h> 418bd22949SKevin Hilman 4257f277b0SRajendra Nayak #include <asm/tlbflush.h> 4357f277b0SRajendra Nayak 448bd22949SKevin Hilman #include "cm.h" 458bd22949SKevin Hilman #include "cm-regbits-34xx.h" 468bd22949SKevin Hilman #include "prm-regbits-34xx.h" 478bd22949SKevin Hilman 488bd22949SKevin Hilman #include "prm.h" 498bd22949SKevin Hilman #include "pm.h" 5013a6fe0fSTero Kristo #include "sdrc.h" 514814ced5SPaul Walmsley #include "control.h" 5213a6fe0fSTero Kristo 53e83df17fSKevin Hilman #ifdef CONFIG_SUSPEND 54e83df17fSKevin Hilman static suspend_state_t suspend_state = PM_SUSPEND_ON; 55e83df17fSKevin Hilman static inline bool is_suspending(void) 56e83df17fSKevin Hilman { 57e83df17fSKevin Hilman return (suspend_state != PM_SUSPEND_ON); 58e83df17fSKevin Hilman } 59e83df17fSKevin Hilman #else 60e83df17fSKevin Hilman static inline bool is_suspending(void) 61e83df17fSKevin Hilman { 62e83df17fSKevin Hilman return false; 63e83df17fSKevin Hilman } 64e83df17fSKevin Hilman #endif 65e83df17fSKevin Hilman 662f5939c3SRajendra Nayak /* Scratchpad offsets */ 67de658158SKevin Hilman #define OMAP343X_TABLE_ADDRESS_OFFSET 0xc4 68de658158SKevin Hilman #define OMAP343X_TABLE_VALUE_OFFSET 0xc0 69de658158SKevin Hilman #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8 702f5939c3SRajendra Nayak 718bd22949SKevin Hilman struct power_state { 728bd22949SKevin Hilman struct powerdomain *pwrdm; 738bd22949SKevin Hilman u32 next_state; 7410f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 758bd22949SKevin Hilman u32 saved_state; 7610f90ed2SKevin Hilman #endif 778bd22949SKevin Hilman struct list_head node; 788bd22949SKevin Hilman }; 798bd22949SKevin Hilman 808bd22949SKevin Hilman static LIST_HEAD(pwrst_list); 818bd22949SKevin Hilman 828bd22949SKevin Hilman static void (*_omap_sram_idle)(u32 *addr, int save_state); 838bd22949SKevin Hilman 8427d59a4aSTero Kristo static int (*_omap_save_secure_sram)(u32 *addr); 8527d59a4aSTero Kristo 86fa3c2a4fSRajendra Nayak static struct powerdomain *mpu_pwrdm, *neon_pwrdm; 87fa3c2a4fSRajendra Nayak static struct powerdomain *core_pwrdm, *per_pwrdm; 88c16c3f67STero Kristo static struct powerdomain *cam_pwrdm; 89fa3c2a4fSRajendra Nayak 902f5939c3SRajendra Nayak static inline void omap3_per_save_context(void) 912f5939c3SRajendra Nayak { 922f5939c3SRajendra Nayak omap_gpio_save_context(); 932f5939c3SRajendra Nayak } 942f5939c3SRajendra Nayak 952f5939c3SRajendra Nayak static inline void omap3_per_restore_context(void) 962f5939c3SRajendra Nayak { 972f5939c3SRajendra Nayak omap_gpio_restore_context(); 982f5939c3SRajendra Nayak } 992f5939c3SRajendra Nayak 1003a7ec26bSKalle Jokiniemi static void omap3_enable_io_chain(void) 1013a7ec26bSKalle Jokiniemi { 1023a7ec26bSKalle Jokiniemi int timeout = 0; 1033a7ec26bSKalle Jokiniemi 1043a7ec26bSKalle Jokiniemi if (omap_rev() >= OMAP3430_REV_ES3_1) { 1052bc4ef71SPaul Walmsley prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, 1062bc4ef71SPaul Walmsley PM_WKEN); 1073a7ec26bSKalle Jokiniemi /* Do a readback to assure write has been done */ 1083a7ec26bSKalle Jokiniemi prm_read_mod_reg(WKUP_MOD, PM_WKEN); 1093a7ec26bSKalle Jokiniemi 1100b96a3a3SKevin Hilman while (!(prm_read_mod_reg(WKUP_MOD, PM_WKEN) & 1112bc4ef71SPaul Walmsley OMAP3430_ST_IO_CHAIN_MASK)) { 1123a7ec26bSKalle Jokiniemi timeout++; 1133a7ec26bSKalle Jokiniemi if (timeout > 1000) { 1143a7ec26bSKalle Jokiniemi printk(KERN_ERR "Wake up daisy chain " 1153a7ec26bSKalle Jokiniemi "activation failed.\n"); 1163a7ec26bSKalle Jokiniemi return; 1173a7ec26bSKalle Jokiniemi } 1182bc4ef71SPaul Walmsley prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, 1190b96a3a3SKevin Hilman WKUP_MOD, PM_WKEN); 1203a7ec26bSKalle Jokiniemi } 1213a7ec26bSKalle Jokiniemi } 1223a7ec26bSKalle Jokiniemi } 1233a7ec26bSKalle Jokiniemi 1243a7ec26bSKalle Jokiniemi static void omap3_disable_io_chain(void) 1253a7ec26bSKalle Jokiniemi { 1263a7ec26bSKalle Jokiniemi if (omap_rev() >= OMAP3430_REV_ES3_1) 1272bc4ef71SPaul Walmsley prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, 1282bc4ef71SPaul Walmsley PM_WKEN); 1293a7ec26bSKalle Jokiniemi } 1303a7ec26bSKalle Jokiniemi 1312f5939c3SRajendra Nayak static void omap3_core_save_context(void) 1322f5939c3SRajendra Nayak { 1332f5939c3SRajendra Nayak u32 control_padconf_off; 1342f5939c3SRajendra Nayak 1352f5939c3SRajendra Nayak /* Save the padconf registers */ 1362f5939c3SRajendra Nayak control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF); 1372f5939c3SRajendra Nayak control_padconf_off |= START_PADCONF_SAVE; 1382f5939c3SRajendra Nayak omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF); 1392f5939c3SRajendra Nayak /* wait for the save to complete */ 1401b6e821fSRoel Kluin while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) 1411b6e821fSRoel Kluin & PADCONF_SAVE_DONE)) 142dccaad89STero Kristo udelay(1); 143dccaad89STero Kristo 144dccaad89STero Kristo /* 145dccaad89STero Kristo * Force write last pad into memory, as this can fail in some 146dccaad89STero Kristo * cases according to erratas 1.157, 1.185 147dccaad89STero Kristo */ 148dccaad89STero Kristo omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), 149dccaad89STero Kristo OMAP343X_CONTROL_MEM_WKUP + 0x2a0); 150dccaad89STero Kristo 1512f5939c3SRajendra Nayak /* Save the Interrupt controller context */ 1522f5939c3SRajendra Nayak omap_intc_save_context(); 1532f5939c3SRajendra Nayak /* Save the GPMC context */ 1542f5939c3SRajendra Nayak omap3_gpmc_save_context(); 1552f5939c3SRajendra Nayak /* Save the system control module context, padconf already save above*/ 1562f5939c3SRajendra Nayak omap3_control_save_context(); 157f2d11858STero Kristo omap_dma_global_context_save(); 1582f5939c3SRajendra Nayak } 1592f5939c3SRajendra Nayak 1602f5939c3SRajendra Nayak static void omap3_core_restore_context(void) 1612f5939c3SRajendra Nayak { 1622f5939c3SRajendra Nayak /* Restore the control module context, padconf restored by h/w */ 1632f5939c3SRajendra Nayak omap3_control_restore_context(); 1642f5939c3SRajendra Nayak /* Restore the GPMC context */ 1652f5939c3SRajendra Nayak omap3_gpmc_restore_context(); 1662f5939c3SRajendra Nayak /* Restore the interrupt controller context */ 1672f5939c3SRajendra Nayak omap_intc_restore_context(); 168f2d11858STero Kristo omap_dma_global_context_restore(); 1692f5939c3SRajendra Nayak } 1702f5939c3SRajendra Nayak 1719d97140bSTero Kristo /* 1729d97140bSTero Kristo * FIXME: This function should be called before entering off-mode after 1739d97140bSTero Kristo * OMAP3 secure services have been accessed. Currently it is only called 1749d97140bSTero Kristo * once during boot sequence, but this works as we are not using secure 1759d97140bSTero Kristo * services. 1769d97140bSTero Kristo */ 17727d59a4aSTero Kristo static void omap3_save_secure_ram_context(u32 target_mpu_state) 17827d59a4aSTero Kristo { 17927d59a4aSTero Kristo u32 ret; 18027d59a4aSTero Kristo 18127d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 18227d59a4aSTero Kristo /* 18327d59a4aSTero Kristo * MPU next state must be set to POWER_ON temporarily, 18427d59a4aSTero Kristo * otherwise the WFI executed inside the ROM code 18527d59a4aSTero Kristo * will hang the system. 18627d59a4aSTero Kristo */ 18727d59a4aSTero Kristo pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); 18827d59a4aSTero Kristo ret = _omap_save_secure_sram((u32 *) 18927d59a4aSTero Kristo __pa(omap3_secure_ram_storage)); 19027d59a4aSTero Kristo pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state); 19127d59a4aSTero Kristo /* Following is for error tracking, it should not happen */ 19227d59a4aSTero Kristo if (ret) { 19327d59a4aSTero Kristo printk(KERN_ERR "save_secure_sram() returns %08x\n", 19427d59a4aSTero Kristo ret); 19527d59a4aSTero Kristo while (1) 19627d59a4aSTero Kristo ; 19727d59a4aSTero Kristo } 19827d59a4aSTero Kristo } 19927d59a4aSTero Kristo } 20027d59a4aSTero Kristo 20177da2d91SJon Hunter /* 20277da2d91SJon Hunter * PRCM Interrupt Handler Helper Function 20377da2d91SJon Hunter * 20477da2d91SJon Hunter * The purpose of this function is to clear any wake-up events latched 20577da2d91SJon Hunter * in the PRCM PM_WKST_x registers. It is possible that a wake-up event 20677da2d91SJon Hunter * may occur whilst attempting to clear a PM_WKST_x register and thus 20777da2d91SJon Hunter * set another bit in this register. A while loop is used to ensure 20877da2d91SJon Hunter * that any peripheral wake-up events occurring while attempting to 20977da2d91SJon Hunter * clear the PM_WKST_x are detected and cleared. 21077da2d91SJon Hunter */ 2118cb0ac99SPaul Walmsley static int prcm_clear_mod_irqs(s16 module, u8 regs) 21277da2d91SJon Hunter { 21371a80775SVikram Pandita u32 wkst, fclk, iclk, clken; 21477da2d91SJon Hunter u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; 21577da2d91SJon Hunter u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; 21677da2d91SJon Hunter u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; 2175d805978SPaul Walmsley u16 grpsel_off = (regs == 3) ? 2185d805978SPaul Walmsley OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; 2198cb0ac99SPaul Walmsley int c = 0; 22077da2d91SJon Hunter 22177da2d91SJon Hunter wkst = prm_read_mod_reg(module, wkst_off); 2225d805978SPaul Walmsley wkst &= prm_read_mod_reg(module, grpsel_off); 22377da2d91SJon Hunter if (wkst) { 22477da2d91SJon Hunter iclk = cm_read_mod_reg(module, iclk_off); 22577da2d91SJon Hunter fclk = cm_read_mod_reg(module, fclk_off); 22677da2d91SJon Hunter while (wkst) { 22771a80775SVikram Pandita clken = wkst; 22871a80775SVikram Pandita cm_set_mod_reg_bits(clken, module, iclk_off); 22971a80775SVikram Pandita /* 23071a80775SVikram Pandita * For USBHOST, we don't know whether HOST1 or 23171a80775SVikram Pandita * HOST2 woke us up, so enable both f-clocks 23271a80775SVikram Pandita */ 23371a80775SVikram Pandita if (module == OMAP3430ES2_USBHOST_MOD) 23471a80775SVikram Pandita clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; 23571a80775SVikram Pandita cm_set_mod_reg_bits(clken, module, fclk_off); 23677da2d91SJon Hunter prm_write_mod_reg(wkst, module, wkst_off); 23777da2d91SJon Hunter wkst = prm_read_mod_reg(module, wkst_off); 2388cb0ac99SPaul Walmsley c++; 23977da2d91SJon Hunter } 24077da2d91SJon Hunter cm_write_mod_reg(iclk, module, iclk_off); 24177da2d91SJon Hunter cm_write_mod_reg(fclk, module, fclk_off); 24277da2d91SJon Hunter } 2438cb0ac99SPaul Walmsley 2448cb0ac99SPaul Walmsley return c; 2458cb0ac99SPaul Walmsley } 2468cb0ac99SPaul Walmsley 2478cb0ac99SPaul Walmsley static int _prcm_int_handle_wakeup(void) 2488cb0ac99SPaul Walmsley { 2498cb0ac99SPaul Walmsley int c; 2508cb0ac99SPaul Walmsley 2518cb0ac99SPaul Walmsley c = prcm_clear_mod_irqs(WKUP_MOD, 1); 2528cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(CORE_MOD, 1); 2538cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1); 2548cb0ac99SPaul Walmsley if (omap_rev() > OMAP3430_REV_ES1_0) { 2558cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(CORE_MOD, 3); 2568cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1); 2578cb0ac99SPaul Walmsley } 2588cb0ac99SPaul Walmsley 2598cb0ac99SPaul Walmsley return c; 26077da2d91SJon Hunter } 26177da2d91SJon Hunter 26277da2d91SJon Hunter /* 26377da2d91SJon Hunter * PRCM Interrupt Handler 26477da2d91SJon Hunter * 26577da2d91SJon Hunter * The PRM_IRQSTATUS_MPU register indicates if there are any pending 26677da2d91SJon Hunter * interrupts from the PRCM for the MPU. These bits must be cleared in 26777da2d91SJon Hunter * order to clear the PRCM interrupt. The PRCM interrupt handler is 26877da2d91SJon Hunter * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear 26977da2d91SJon Hunter * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU 27077da2d91SJon Hunter * register indicates that a wake-up event is pending for the MPU and 27177da2d91SJon Hunter * this bit can only be cleared if the all the wake-up events latched 27277da2d91SJon Hunter * in the various PM_WKST_x registers have been cleared. The interrupt 27377da2d91SJon Hunter * handler is implemented using a do-while loop so that if a wake-up 27477da2d91SJon Hunter * event occurred during the processing of the prcm interrupt handler 27577da2d91SJon Hunter * (setting a bit in the corresponding PM_WKST_x register and thus 27677da2d91SJon Hunter * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register) 27777da2d91SJon Hunter * this would be handled. 27877da2d91SJon Hunter */ 2798bd22949SKevin Hilman static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) 2808bd22949SKevin Hilman { 281d6290a3eSKevin Hilman u32 irqenable_mpu, irqstatus_mpu; 2828cb0ac99SPaul Walmsley int c = 0; 2838bd22949SKevin Hilman 284d6290a3eSKevin Hilman irqenable_mpu = prm_read_mod_reg(OCP_MOD, 285d6290a3eSKevin Hilman OMAP3_PRM_IRQENABLE_MPU_OFFSET); 2868bd22949SKevin Hilman irqstatus_mpu = prm_read_mod_reg(OCP_MOD, 2878bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 288d6290a3eSKevin Hilman irqstatus_mpu &= irqenable_mpu; 2898cb0ac99SPaul Walmsley 290d6290a3eSKevin Hilman do { 2912bc4ef71SPaul Walmsley if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK | 2922bc4ef71SPaul Walmsley OMAP3430_IO_ST_MASK)) { 2938cb0ac99SPaul Walmsley c = _prcm_int_handle_wakeup(); 2948cb0ac99SPaul Walmsley 2958cb0ac99SPaul Walmsley /* 2968cb0ac99SPaul Walmsley * Is the MPU PRCM interrupt handler racing with the 2978cb0ac99SPaul Walmsley * IVA2 PRCM interrupt handler ? 2988cb0ac99SPaul Walmsley */ 2998cb0ac99SPaul Walmsley WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup " 3008cb0ac99SPaul Walmsley "but no wakeup sources are marked\n"); 3018cb0ac99SPaul Walmsley } else { 3028cb0ac99SPaul Walmsley /* XXX we need to expand our PRCM interrupt handler */ 3038cb0ac99SPaul Walmsley WARN(1, "prcm: WARNING: PRCM interrupt received, but " 3048cb0ac99SPaul Walmsley "no code to handle it (%08x)\n", irqstatus_mpu); 3058cb0ac99SPaul Walmsley } 3068cb0ac99SPaul Walmsley 3078bd22949SKevin Hilman prm_write_mod_reg(irqstatus_mpu, OCP_MOD, 3088bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 3098bd22949SKevin Hilman 310d6290a3eSKevin Hilman irqstatus_mpu = prm_read_mod_reg(OCP_MOD, 311d6290a3eSKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 312d6290a3eSKevin Hilman irqstatus_mpu &= irqenable_mpu; 313d6290a3eSKevin Hilman 314d6290a3eSKevin Hilman } while (irqstatus_mpu); 3158bd22949SKevin Hilman 3168bd22949SKevin Hilman return IRQ_HANDLED; 3178bd22949SKevin Hilman } 3188bd22949SKevin Hilman 31957f277b0SRajendra Nayak static void restore_control_register(u32 val) 32057f277b0SRajendra Nayak { 32157f277b0SRajendra Nayak __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val)); 32257f277b0SRajendra Nayak } 32357f277b0SRajendra Nayak 32457f277b0SRajendra Nayak /* Function to restore the table entry that was modified for enabling MMU */ 32557f277b0SRajendra Nayak static void restore_table_entry(void) 32657f277b0SRajendra Nayak { 3274d63bc1dSManjunath Kondaiah G void __iomem *scratchpad_address; 32857f277b0SRajendra Nayak u32 previous_value, control_reg_value; 32957f277b0SRajendra Nayak u32 *address; 33057f277b0SRajendra Nayak 33157f277b0SRajendra Nayak scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD); 33257f277b0SRajendra Nayak 33357f277b0SRajendra Nayak /* Get address of entry that was modified */ 33457f277b0SRajendra Nayak address = (u32 *)__raw_readl(scratchpad_address + 33557f277b0SRajendra Nayak OMAP343X_TABLE_ADDRESS_OFFSET); 33657f277b0SRajendra Nayak /* Get the previous value which needs to be restored */ 33757f277b0SRajendra Nayak previous_value = __raw_readl(scratchpad_address + 33857f277b0SRajendra Nayak OMAP343X_TABLE_VALUE_OFFSET); 33957f277b0SRajendra Nayak address = __va(address); 34057f277b0SRajendra Nayak *address = previous_value; 34157f277b0SRajendra Nayak flush_tlb_all(); 34257f277b0SRajendra Nayak control_reg_value = __raw_readl(scratchpad_address 34357f277b0SRajendra Nayak + OMAP343X_CONTROL_REG_VALUE_OFFSET); 34457f277b0SRajendra Nayak /* This will enable caches and prediction */ 34557f277b0SRajendra Nayak restore_control_register(control_reg_value); 34657f277b0SRajendra Nayak } 34757f277b0SRajendra Nayak 34899e6a4d2SRajendra Nayak void omap_sram_idle(void) 3498bd22949SKevin Hilman { 3508bd22949SKevin Hilman /* Variable to tell what needs to be saved and restored 3518bd22949SKevin Hilman * in omap_sram_idle*/ 3528bd22949SKevin Hilman /* save_state = 0 => Nothing to save and restored */ 3538bd22949SKevin Hilman /* save_state = 1 => Only L1 and logic lost */ 3548bd22949SKevin Hilman /* save_state = 2 => Only L2 lost */ 3558bd22949SKevin Hilman /* save_state = 3 => L1, L2 and logic lost */ 356fa3c2a4fSRajendra Nayak int save_state = 0; 357fa3c2a4fSRajendra Nayak int mpu_next_state = PWRDM_POWER_ON; 358fa3c2a4fSRajendra Nayak int per_next_state = PWRDM_POWER_ON; 359fa3c2a4fSRajendra Nayak int core_next_state = PWRDM_POWER_ON; 3602f5939c3SRajendra Nayak int core_prev_state, per_prev_state; 36113a6fe0fSTero Kristo u32 sdrc_pwr = 0; 3628bd22949SKevin Hilman 3638bd22949SKevin Hilman if (!_omap_sram_idle) 3648bd22949SKevin Hilman return; 3658bd22949SKevin Hilman 366fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(mpu_pwrdm); 367fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(neon_pwrdm); 368fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(core_pwrdm); 369fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(per_pwrdm); 370fa3c2a4fSRajendra Nayak 3718bd22949SKevin Hilman mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 3728bd22949SKevin Hilman switch (mpu_next_state) { 373fa3c2a4fSRajendra Nayak case PWRDM_POWER_ON: 3748bd22949SKevin Hilman case PWRDM_POWER_RET: 3758bd22949SKevin Hilman /* No need to save context */ 3768bd22949SKevin Hilman save_state = 0; 3778bd22949SKevin Hilman break; 37861255ab9SRajendra Nayak case PWRDM_POWER_OFF: 37961255ab9SRajendra Nayak save_state = 3; 38061255ab9SRajendra Nayak break; 3818bd22949SKevin Hilman default: 3828bd22949SKevin Hilman /* Invalid state */ 3838bd22949SKevin Hilman printk(KERN_ERR "Invalid mpu state in sram_idle\n"); 3848bd22949SKevin Hilman return; 3858bd22949SKevin Hilman } 386fe617af7SPeter 'p2' De Schrijver pwrdm_pre_transition(); 387fe617af7SPeter 'p2' De Schrijver 388fa3c2a4fSRajendra Nayak /* NEON control */ 389fa3c2a4fSRajendra Nayak if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) 3907139178eSJouni Hogander pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); 391fa3c2a4fSRajendra Nayak 39240742fa8SMike Chan /* Enable IO-PAD and IO-CHAIN wakeups */ 393fa3c2a4fSRajendra Nayak per_next_state = pwrdm_read_next_pwrst(per_pwrdm); 394ecf157d0STero Kristo core_next_state = pwrdm_read_next_pwrst(core_pwrdm); 395d5c47d7eSKevin Hilman if (omap3_has_io_wakeup() && 396ad0c63f1Sstanley.miao (per_next_state < PWRDM_POWER_ON || 397ad0c63f1Sstanley.miao core_next_state < PWRDM_POWER_ON)) { 3982bc4ef71SPaul Walmsley prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); 39940742fa8SMike Chan omap3_enable_io_chain(); 40040742fa8SMike Chan } 40140742fa8SMike Chan 4020d8e2d0dSPaul Walmsley /* Block console output in case it is on one of the OMAP UARTs */ 403e83df17fSKevin Hilman if (!is_suspending()) 4040d8e2d0dSPaul Walmsley if (per_next_state < PWRDM_POWER_ON || 4050d8e2d0dSPaul Walmsley core_next_state < PWRDM_POWER_ON) 4060d8e2d0dSPaul Walmsley if (try_acquire_console_sem()) 4070d8e2d0dSPaul Walmsley goto console_still_active; 4080d8e2d0dSPaul Walmsley 40940742fa8SMike Chan /* PER */ 4102f5939c3SRajendra Nayak if (per_next_state < PWRDM_POWER_ON) { 4114af4016cSKevin Hilman omap_uart_prepare_idle(2); 412cd4f1faeSGovindraj.R omap_uart_prepare_idle(3); 41343ffcd9aSKevin Hilman omap2_gpio_prepare_for_idle(per_next_state); 414e7410cf7SKevin Hilman if (per_next_state == PWRDM_POWER_OFF) 4152f5939c3SRajendra Nayak omap3_per_save_context(); 4162f5939c3SRajendra Nayak } 417c16c3f67STero Kristo 418658ce97eSKevin Hilman /* CORE */ 419658ce97eSKevin Hilman if (core_next_state < PWRDM_POWER_ON) { 420658ce97eSKevin Hilman omap_uart_prepare_idle(0); 421658ce97eSKevin Hilman omap_uart_prepare_idle(1); 4222f5939c3SRajendra Nayak if (core_next_state == PWRDM_POWER_OFF) { 4232f5939c3SRajendra Nayak omap3_core_save_context(); 4242f5939c3SRajendra Nayak omap3_prcm_save_context(); 4252f5939c3SRajendra Nayak } 426fa3c2a4fSRajendra Nayak } 42740742fa8SMike Chan 428f18cc2ffSTero Kristo omap3_intc_prepare_idle(); 4298bd22949SKevin Hilman 43061255ab9SRajendra Nayak /* 431f265dc4cSRajendra Nayak * On EMU/HS devices ROM code restores a SRDC value 432f265dc4cSRajendra Nayak * from scratchpad which has automatic self refresh on timeout 433f265dc4cSRajendra Nayak * of AUTO_CNT = 1 enabled. This takes care of errata 1.142. 434f265dc4cSRajendra Nayak * Hence store/restore the SDRC_POWER register here. 43513a6fe0fSTero Kristo */ 43613a6fe0fSTero Kristo if (omap_rev() >= OMAP3430_REV_ES3_0 && 43713a6fe0fSTero Kristo omap_type() != OMAP2_DEVICE_TYPE_GP && 438f265dc4cSRajendra Nayak core_next_state == PWRDM_POWER_OFF) 43913a6fe0fSTero Kristo sdrc_pwr = sdrc_read_reg(SDRC_POWER); 44013a6fe0fSTero Kristo 44113a6fe0fSTero Kristo /* 44261255ab9SRajendra Nayak * omap3_arm_context is the location where ARM registers 44361255ab9SRajendra Nayak * get saved. The restore path then reads from this 44461255ab9SRajendra Nayak * location and restores them back. 44561255ab9SRajendra Nayak */ 44661255ab9SRajendra Nayak _omap_sram_idle(omap3_arm_context, save_state); 4478bd22949SKevin Hilman cpu_init(); 4488bd22949SKevin Hilman 449f265dc4cSRajendra Nayak /* Restore normal SDRC POWER settings */ 45013a6fe0fSTero Kristo if (omap_rev() >= OMAP3430_REV_ES3_0 && 45113a6fe0fSTero Kristo omap_type() != OMAP2_DEVICE_TYPE_GP && 45213a6fe0fSTero Kristo core_next_state == PWRDM_POWER_OFF) 45313a6fe0fSTero Kristo sdrc_write_reg(sdrc_pwr, SDRC_POWER); 45413a6fe0fSTero Kristo 45557f277b0SRajendra Nayak /* Restore table entry modified during MMU restoration */ 45657f277b0SRajendra Nayak if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF) 45757f277b0SRajendra Nayak restore_table_entry(); 45857f277b0SRajendra Nayak 459658ce97eSKevin Hilman /* CORE */ 460fa3c2a4fSRajendra Nayak if (core_next_state < PWRDM_POWER_ON) { 4612f5939c3SRajendra Nayak core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); 4622f5939c3SRajendra Nayak if (core_prev_state == PWRDM_POWER_OFF) { 4632f5939c3SRajendra Nayak omap3_core_restore_context(); 4642f5939c3SRajendra Nayak omap3_prcm_restore_context(); 4652f5939c3SRajendra Nayak omap3_sram_restore_context(); 4668a917d2fSKalle Jokiniemi omap2_sms_restore_context(); 4672f5939c3SRajendra Nayak } 468658ce97eSKevin Hilman omap_uart_resume_idle(0); 469658ce97eSKevin Hilman omap_uart_resume_idle(1); 470658ce97eSKevin Hilman if (core_next_state == PWRDM_POWER_OFF) 4712bc4ef71SPaul Walmsley prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, 472658ce97eSKevin Hilman OMAP3430_GR_MOD, 473658ce97eSKevin Hilman OMAP3_PRM_VOLTCTRL_OFFSET); 474658ce97eSKevin Hilman } 475f18cc2ffSTero Kristo omap3_intc_resume_idle(); 476658ce97eSKevin Hilman 477658ce97eSKevin Hilman /* PER */ 4782f5939c3SRajendra Nayak if (per_next_state < PWRDM_POWER_ON) { 479658ce97eSKevin Hilman per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); 48043ffcd9aSKevin Hilman omap2_gpio_resume_after_idle(); 48143ffcd9aSKevin Hilman if (per_prev_state == PWRDM_POWER_OFF) 4822f5939c3SRajendra Nayak omap3_per_restore_context(); 483ecf157d0STero Kristo omap_uart_resume_idle(2); 484cd4f1faeSGovindraj.R omap_uart_resume_idle(3); 485fa3c2a4fSRajendra Nayak } 486fe617af7SPeter 'p2' De Schrijver 487e83df17fSKevin Hilman if (!is_suspending()) 4880d8e2d0dSPaul Walmsley release_console_sem(); 4890d8e2d0dSPaul Walmsley 4900d8e2d0dSPaul Walmsley console_still_active: 4913a7ec26bSKalle Jokiniemi /* Disable IO-PAD and IO-CHAIN wakeup */ 49258a5559eSKevin Hilman if (omap3_has_io_wakeup() && 49358a5559eSKevin Hilman (per_next_state < PWRDM_POWER_ON || 49458a5559eSKevin Hilman core_next_state < PWRDM_POWER_ON)) { 4952bc4ef71SPaul Walmsley prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); 4963a7ec26bSKalle Jokiniemi omap3_disable_io_chain(); 4973a7ec26bSKalle Jokiniemi } 498658ce97eSKevin Hilman 499fe617af7SPeter 'p2' De Schrijver pwrdm_post_transition(); 500fe617af7SPeter 'p2' De Schrijver 501c16c3f67STero Kristo omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); 5028bd22949SKevin Hilman } 5038bd22949SKevin Hilman 50420b01669SRajendra Nayak int omap3_can_sleep(void) 5058bd22949SKevin Hilman { 506c40552bcSKevin Hilman if (!sleep_while_idle) 507c40552bcSKevin Hilman return 0; 5084af4016cSKevin Hilman if (!omap_uart_can_sleep()) 5094af4016cSKevin Hilman return 0; 5108bd22949SKevin Hilman return 1; 5118bd22949SKevin Hilman } 5128bd22949SKevin Hilman 5138bd22949SKevin Hilman static void omap3_pm_idle(void) 5148bd22949SKevin Hilman { 5158bd22949SKevin Hilman local_irq_disable(); 5168bd22949SKevin Hilman local_fiq_disable(); 5178bd22949SKevin Hilman 5188bd22949SKevin Hilman if (!omap3_can_sleep()) 5198bd22949SKevin Hilman goto out; 5208bd22949SKevin Hilman 521cf22854cSTero Kristo if (omap_irq_pending() || need_resched()) 5228bd22949SKevin Hilman goto out; 5238bd22949SKevin Hilman 5248bd22949SKevin Hilman omap_sram_idle(); 5258bd22949SKevin Hilman 5268bd22949SKevin Hilman out: 5278bd22949SKevin Hilman local_fiq_enable(); 5288bd22949SKevin Hilman local_irq_enable(); 5298bd22949SKevin Hilman } 5308bd22949SKevin Hilman 53110f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 5328bd22949SKevin Hilman static int omap3_pm_suspend(void) 5338bd22949SKevin Hilman { 5348bd22949SKevin Hilman struct power_state *pwrst; 5358bd22949SKevin Hilman int state, ret = 0; 5368bd22949SKevin Hilman 5378e2efde9SAri Kauppi if (wakeup_timer_seconds || wakeup_timer_milliseconds) 5388e2efde9SAri Kauppi omap2_pm_wakeup_on_timer(wakeup_timer_seconds, 5398e2efde9SAri Kauppi wakeup_timer_milliseconds); 540d7814e4dSKevin Hilman 5418bd22949SKevin Hilman /* Read current next_pwrsts */ 5428bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) 5438bd22949SKevin Hilman pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 5448bd22949SKevin Hilman /* Set ones wanted by suspend */ 5458bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 546eb6a2c75SSantosh Shilimkar if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) 5478bd22949SKevin Hilman goto restore; 5488bd22949SKevin Hilman if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) 5498bd22949SKevin Hilman goto restore; 5508bd22949SKevin Hilman } 5518bd22949SKevin Hilman 5524af4016cSKevin Hilman omap_uart_prepare_suspend(); 5532bbe3af3STero Kristo omap3_intc_suspend(); 5542bbe3af3STero Kristo 5558bd22949SKevin Hilman omap_sram_idle(); 5568bd22949SKevin Hilman 5578bd22949SKevin Hilman restore: 5588bd22949SKevin Hilman /* Restore next_pwrsts */ 5598bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 5608bd22949SKevin Hilman state = pwrdm_read_prev_pwrst(pwrst->pwrdm); 5618bd22949SKevin Hilman if (state > pwrst->next_state) { 5628bd22949SKevin Hilman printk(KERN_INFO "Powerdomain (%s) didn't enter " 5638bd22949SKevin Hilman "target state %d\n", 5648bd22949SKevin Hilman pwrst->pwrdm->name, pwrst->next_state); 5658bd22949SKevin Hilman ret = -1; 5668bd22949SKevin Hilman } 567eb6a2c75SSantosh Shilimkar omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); 5688bd22949SKevin Hilman } 5698bd22949SKevin Hilman if (ret) 5708bd22949SKevin Hilman printk(KERN_ERR "Could not enter target state in pm_suspend\n"); 5718bd22949SKevin Hilman else 5728bd22949SKevin Hilman printk(KERN_INFO "Successfully put all powerdomains " 5738bd22949SKevin Hilman "to target state\n"); 5748bd22949SKevin Hilman 5758bd22949SKevin Hilman return ret; 5768bd22949SKevin Hilman } 5778bd22949SKevin Hilman 5782466211eSTero Kristo static int omap3_pm_enter(suspend_state_t unused) 5798bd22949SKevin Hilman { 5808bd22949SKevin Hilman int ret = 0; 5818bd22949SKevin Hilman 5822466211eSTero Kristo switch (suspend_state) { 5838bd22949SKevin Hilman case PM_SUSPEND_STANDBY: 5848bd22949SKevin Hilman case PM_SUSPEND_MEM: 5858bd22949SKevin Hilman ret = omap3_pm_suspend(); 5868bd22949SKevin Hilman break; 5878bd22949SKevin Hilman default: 5888bd22949SKevin Hilman ret = -EINVAL; 5898bd22949SKevin Hilman } 5908bd22949SKevin Hilman 5918bd22949SKevin Hilman return ret; 5928bd22949SKevin Hilman } 5938bd22949SKevin Hilman 5942466211eSTero Kristo /* Hooks to enable / disable UART interrupts during suspend */ 5952466211eSTero Kristo static int omap3_pm_begin(suspend_state_t state) 5962466211eSTero Kristo { 597c166381dSJean Pihet disable_hlt(); 5982466211eSTero Kristo suspend_state = state; 5992466211eSTero Kristo omap_uart_enable_irqs(0); 6002466211eSTero Kristo return 0; 6012466211eSTero Kristo } 6022466211eSTero Kristo 6032466211eSTero Kristo static void omap3_pm_end(void) 6042466211eSTero Kristo { 6052466211eSTero Kristo suspend_state = PM_SUSPEND_ON; 6062466211eSTero Kristo omap_uart_enable_irqs(1); 607c166381dSJean Pihet enable_hlt(); 6082466211eSTero Kristo return; 6092466211eSTero Kristo } 6102466211eSTero Kristo 6118bd22949SKevin Hilman static struct platform_suspend_ops omap_pm_ops = { 6122466211eSTero Kristo .begin = omap3_pm_begin, 6132466211eSTero Kristo .end = omap3_pm_end, 6148bd22949SKevin Hilman .enter = omap3_pm_enter, 6158bd22949SKevin Hilman .valid = suspend_valid_only_mem, 6168bd22949SKevin Hilman }; 61710f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 6188bd22949SKevin Hilman 6191155e426SKevin Hilman 6201155e426SKevin Hilman /** 6211155e426SKevin Hilman * omap3_iva_idle(): ensure IVA is in idle so it can be put into 6221155e426SKevin Hilman * retention 6231155e426SKevin Hilman * 6241155e426SKevin Hilman * In cases where IVA2 is activated by bootcode, it may prevent 6251155e426SKevin Hilman * full-chip retention or off-mode because it is not idle. This 6261155e426SKevin Hilman * function forces the IVA2 into idle state so it can go 6271155e426SKevin Hilman * into retention/off and thus allow full-chip retention/off. 6281155e426SKevin Hilman * 6291155e426SKevin Hilman **/ 6301155e426SKevin Hilman static void __init omap3_iva_idle(void) 6311155e426SKevin Hilman { 6321155e426SKevin Hilman /* ensure IVA2 clock is disabled */ 6331155e426SKevin Hilman cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 6341155e426SKevin Hilman 6351155e426SKevin Hilman /* if no clock activity, nothing else to do */ 6361155e426SKevin Hilman if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & 6371155e426SKevin Hilman OMAP3430_CLKACTIVITY_IVA2_MASK)) 6381155e426SKevin Hilman return; 6391155e426SKevin Hilman 6401155e426SKevin Hilman /* Reset IVA2 */ 6412bc4ef71SPaul Walmsley prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | 6422bc4ef71SPaul Walmsley OMAP3430_RST2_IVA2_MASK | 6432bc4ef71SPaul Walmsley OMAP3430_RST3_IVA2_MASK, 64437903009SAbhijit Pagare OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 6451155e426SKevin Hilman 6461155e426SKevin Hilman /* Enable IVA2 clock */ 647dfa6d6f8SKevin Hilman cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, 6481155e426SKevin Hilman OMAP3430_IVA2_MOD, CM_FCLKEN); 6491155e426SKevin Hilman 6501155e426SKevin Hilman /* Set IVA2 boot mode to 'idle' */ 6511155e426SKevin Hilman omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, 6521155e426SKevin Hilman OMAP343X_CONTROL_IVA2_BOOTMOD); 6531155e426SKevin Hilman 6541155e426SKevin Hilman /* Un-reset IVA2 */ 65537903009SAbhijit Pagare prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 6561155e426SKevin Hilman 6571155e426SKevin Hilman /* Disable IVA2 clock */ 6581155e426SKevin Hilman cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 6591155e426SKevin Hilman 6601155e426SKevin Hilman /* Reset IVA2 */ 6612bc4ef71SPaul Walmsley prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | 6622bc4ef71SPaul Walmsley OMAP3430_RST2_IVA2_MASK | 6632bc4ef71SPaul Walmsley OMAP3430_RST3_IVA2_MASK, 66437903009SAbhijit Pagare OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 6651155e426SKevin Hilman } 6661155e426SKevin Hilman 6678111b221SKevin Hilman static void __init omap3_d2d_idle(void) 6688bd22949SKevin Hilman { 6698111b221SKevin Hilman u16 mask, padconf; 6708111b221SKevin Hilman 6718111b221SKevin Hilman /* In a stand alone OMAP3430 where there is not a stacked 6728111b221SKevin Hilman * modem for the D2D Idle Ack and D2D MStandby must be pulled 6738111b221SKevin Hilman * high. S CONTROL_PADCONF_SAD2D_IDLEACK and 6748111b221SKevin Hilman * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ 6758111b221SKevin Hilman mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ 6768111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); 6778111b221SKevin Hilman padconf |= mask; 6788111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); 6798111b221SKevin Hilman 6808111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); 6818111b221SKevin Hilman padconf |= mask; 6828111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 6838111b221SKevin Hilman 6848bd22949SKevin Hilman /* reset modem */ 6852bc4ef71SPaul Walmsley prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | 6862bc4ef71SPaul Walmsley OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, 68737903009SAbhijit Pagare CORE_MOD, OMAP2_RM_RSTCTRL); 68837903009SAbhijit Pagare prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); 6898111b221SKevin Hilman } 6908bd22949SKevin Hilman 6918111b221SKevin Hilman static void __init prcm_setup_regs(void) 6928111b221SKevin Hilman { 693e5863689SGovindraj.R u32 omap3630_auto_uart4_mask = cpu_is_omap3630() ? 694e5863689SGovindraj.R OMAP3630_AUTO_UART4_MASK : 0; 695e5863689SGovindraj.R u32 omap3630_en_uart4_mask = cpu_is_omap3630() ? 696e5863689SGovindraj.R OMAP3630_EN_UART4_MASK : 0; 697e5863689SGovindraj.R u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ? 698e5863689SGovindraj.R OMAP3630_GRPSEL_UART4_MASK : 0; 699e5863689SGovindraj.R 700e5863689SGovindraj.R 7018bd22949SKevin Hilman /* XXX Reset all wkdeps. This should be done when initializing 7028bd22949SKevin Hilman * powerdomains */ 7038bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); 7048bd22949SKevin Hilman prm_write_mod_reg(0, MPU_MOD, PM_WKDEP); 7058bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP); 7068bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP); 7078bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP); 7088bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP); 7098bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 7108bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP); 7118bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP); 7128bd22949SKevin Hilman } else 7138bd22949SKevin Hilman prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); 7148bd22949SKevin Hilman 7158bd22949SKevin Hilman /* 7168bd22949SKevin Hilman * Enable interface clock autoidle for all modules. 7178bd22949SKevin Hilman * Note that in the long run this should be done by clockfw 7188bd22949SKevin Hilman */ 7198bd22949SKevin Hilman cm_write_mod_reg( 7202bc4ef71SPaul Walmsley OMAP3430_AUTO_MODEM_MASK | 7212bc4ef71SPaul Walmsley OMAP3430ES2_AUTO_MMC3_MASK | 7222bc4ef71SPaul Walmsley OMAP3430ES2_AUTO_ICR_MASK | 7232bc4ef71SPaul Walmsley OMAP3430_AUTO_AES2_MASK | 7242bc4ef71SPaul Walmsley OMAP3430_AUTO_SHA12_MASK | 7252bc4ef71SPaul Walmsley OMAP3430_AUTO_DES2_MASK | 7262bc4ef71SPaul Walmsley OMAP3430_AUTO_MMC2_MASK | 7272bc4ef71SPaul Walmsley OMAP3430_AUTO_MMC1_MASK | 7282bc4ef71SPaul Walmsley OMAP3430_AUTO_MSPRO_MASK | 7292bc4ef71SPaul Walmsley OMAP3430_AUTO_HDQ_MASK | 7302bc4ef71SPaul Walmsley OMAP3430_AUTO_MCSPI4_MASK | 7312bc4ef71SPaul Walmsley OMAP3430_AUTO_MCSPI3_MASK | 7322bc4ef71SPaul Walmsley OMAP3430_AUTO_MCSPI2_MASK | 7332bc4ef71SPaul Walmsley OMAP3430_AUTO_MCSPI1_MASK | 7342bc4ef71SPaul Walmsley OMAP3430_AUTO_I2C3_MASK | 7352bc4ef71SPaul Walmsley OMAP3430_AUTO_I2C2_MASK | 7362bc4ef71SPaul Walmsley OMAP3430_AUTO_I2C1_MASK | 7372bc4ef71SPaul Walmsley OMAP3430_AUTO_UART2_MASK | 7382bc4ef71SPaul Walmsley OMAP3430_AUTO_UART1_MASK | 7392bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT11_MASK | 7402bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT10_MASK | 7412bc4ef71SPaul Walmsley OMAP3430_AUTO_MCBSP5_MASK | 7422bc4ef71SPaul Walmsley OMAP3430_AUTO_MCBSP1_MASK | 7432bc4ef71SPaul Walmsley OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */ 7442bc4ef71SPaul Walmsley OMAP3430_AUTO_MAILBOXES_MASK | 7452bc4ef71SPaul Walmsley OMAP3430_AUTO_OMAPCTRL_MASK | 7462bc4ef71SPaul Walmsley OMAP3430ES1_AUTO_FSHOSTUSB_MASK | 7472bc4ef71SPaul Walmsley OMAP3430_AUTO_HSOTGUSB_MASK | 7482bc4ef71SPaul Walmsley OMAP3430_AUTO_SAD2D_MASK | 7492bc4ef71SPaul Walmsley OMAP3430_AUTO_SSI_MASK, 7508bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE1); 7518bd22949SKevin Hilman 7528bd22949SKevin Hilman cm_write_mod_reg( 7532bc4ef71SPaul Walmsley OMAP3430_AUTO_PKA_MASK | 7542bc4ef71SPaul Walmsley OMAP3430_AUTO_AES1_MASK | 7552bc4ef71SPaul Walmsley OMAP3430_AUTO_RNG_MASK | 7562bc4ef71SPaul Walmsley OMAP3430_AUTO_SHA11_MASK | 7572bc4ef71SPaul Walmsley OMAP3430_AUTO_DES1_MASK, 7588bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE2); 7598bd22949SKevin Hilman 7608bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 7618bd22949SKevin Hilman cm_write_mod_reg( 7622bc4ef71SPaul Walmsley OMAP3430_AUTO_MAD2D_MASK | 7632bc4ef71SPaul Walmsley OMAP3430ES2_AUTO_USBTLL_MASK, 7648bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE3); 7658bd22949SKevin Hilman } 7668bd22949SKevin Hilman 7678bd22949SKevin Hilman cm_write_mod_reg( 7682bc4ef71SPaul Walmsley OMAP3430_AUTO_WDT2_MASK | 7692bc4ef71SPaul Walmsley OMAP3430_AUTO_WDT1_MASK | 7702bc4ef71SPaul Walmsley OMAP3430_AUTO_GPIO1_MASK | 7712bc4ef71SPaul Walmsley OMAP3430_AUTO_32KSYNC_MASK | 7722bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT12_MASK | 7732bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT1_MASK, 7748bd22949SKevin Hilman WKUP_MOD, CM_AUTOIDLE); 7758bd22949SKevin Hilman 7768bd22949SKevin Hilman cm_write_mod_reg( 7772bc4ef71SPaul Walmsley OMAP3430_AUTO_DSS_MASK, 7788bd22949SKevin Hilman OMAP3430_DSS_MOD, 7798bd22949SKevin Hilman CM_AUTOIDLE); 7808bd22949SKevin Hilman 7818bd22949SKevin Hilman cm_write_mod_reg( 7822bc4ef71SPaul Walmsley OMAP3430_AUTO_CAM_MASK, 7838bd22949SKevin Hilman OMAP3430_CAM_MOD, 7848bd22949SKevin Hilman CM_AUTOIDLE); 7858bd22949SKevin Hilman 7868bd22949SKevin Hilman cm_write_mod_reg( 787e5863689SGovindraj.R omap3630_auto_uart4_mask | 7882bc4ef71SPaul Walmsley OMAP3430_AUTO_GPIO6_MASK | 7892bc4ef71SPaul Walmsley OMAP3430_AUTO_GPIO5_MASK | 7902bc4ef71SPaul Walmsley OMAP3430_AUTO_GPIO4_MASK | 7912bc4ef71SPaul Walmsley OMAP3430_AUTO_GPIO3_MASK | 7922bc4ef71SPaul Walmsley OMAP3430_AUTO_GPIO2_MASK | 7932bc4ef71SPaul Walmsley OMAP3430_AUTO_WDT3_MASK | 7942bc4ef71SPaul Walmsley OMAP3430_AUTO_UART3_MASK | 7952bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT9_MASK | 7962bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT8_MASK | 7972bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT7_MASK | 7982bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT6_MASK | 7992bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT5_MASK | 8002bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT4_MASK | 8012bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT3_MASK | 8022bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT2_MASK | 8032bc4ef71SPaul Walmsley OMAP3430_AUTO_MCBSP4_MASK | 8042bc4ef71SPaul Walmsley OMAP3430_AUTO_MCBSP3_MASK | 8052bc4ef71SPaul Walmsley OMAP3430_AUTO_MCBSP2_MASK, 8068bd22949SKevin Hilman OMAP3430_PER_MOD, 8078bd22949SKevin Hilman CM_AUTOIDLE); 8088bd22949SKevin Hilman 8098bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 8108bd22949SKevin Hilman cm_write_mod_reg( 8112bc4ef71SPaul Walmsley OMAP3430ES2_AUTO_USBHOST_MASK, 8128bd22949SKevin Hilman OMAP3430ES2_USBHOST_MOD, 8138bd22949SKevin Hilman CM_AUTOIDLE); 8148bd22949SKevin Hilman } 8158bd22949SKevin Hilman 8162fd0f75cSPaul Walmsley omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); 817b296c811STero Kristo 8188bd22949SKevin Hilman /* 8198bd22949SKevin Hilman * Set all plls to autoidle. This is needed until autoidle is 8208bd22949SKevin Hilman * enabled by clockfw 8218bd22949SKevin Hilman */ 8228bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, 8238bd22949SKevin Hilman OMAP3430_IVA2_MOD, CM_AUTOIDLE2); 8248bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT, 8258bd22949SKevin Hilman MPU_MOD, 8268bd22949SKevin Hilman CM_AUTOIDLE2); 8278bd22949SKevin Hilman cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | 8288bd22949SKevin Hilman (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT), 8298bd22949SKevin Hilman PLL_MOD, 8308bd22949SKevin Hilman CM_AUTOIDLE); 8318bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, 8328bd22949SKevin Hilman PLL_MOD, 8338bd22949SKevin Hilman CM_AUTOIDLE2); 8348bd22949SKevin Hilman 8358bd22949SKevin Hilman /* 8368bd22949SKevin Hilman * Enable control of expternal oscillator through 8378bd22949SKevin Hilman * sys_clkreq. In the long run clock framework should 8388bd22949SKevin Hilman * take care of this. 8398bd22949SKevin Hilman */ 8408bd22949SKevin Hilman prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 8418bd22949SKevin Hilman 1 << OMAP_AUTOEXTCLKMODE_SHIFT, 8428bd22949SKevin Hilman OMAP3430_GR_MOD, 8438bd22949SKevin Hilman OMAP3_PRM_CLKSRC_CTRL_OFFSET); 8448bd22949SKevin Hilman 8458bd22949SKevin Hilman /* setup wakup source */ 8462fd0f75cSPaul Walmsley prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | 8472fd0f75cSPaul Walmsley OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, 8488bd22949SKevin Hilman WKUP_MOD, PM_WKEN); 8498bd22949SKevin Hilman /* No need to write EN_IO, that is always enabled */ 850275f675cSPaul Walmsley prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | 851275f675cSPaul Walmsley OMAP3430_GRPSEL_GPT1_MASK | 852275f675cSPaul Walmsley OMAP3430_GRPSEL_GPT12_MASK, 8538bd22949SKevin Hilman WKUP_MOD, OMAP3430_PM_MPUGRPSEL); 8548bd22949SKevin Hilman /* For some reason IO doesn't generate wakeup event even if 8558bd22949SKevin Hilman * it is selected to mpu wakeup goup */ 8562bc4ef71SPaul Walmsley prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK, 8578bd22949SKevin Hilman OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); 8581155e426SKevin Hilman 859b92c5721SSubramani Venkatesh /* Enable PM_WKEN to support DSS LPR */ 8602bc4ef71SPaul Walmsley prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, 861b92c5721SSubramani Venkatesh OMAP3430_DSS_MOD, PM_WKEN); 862b92c5721SSubramani Venkatesh 863b427f92fSKevin Hilman /* Enable wakeups in PER */ 864e5863689SGovindraj.R prm_write_mod_reg(omap3630_en_uart4_mask | 865e5863689SGovindraj.R OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | 8662fd0f75cSPaul Walmsley OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | 8672fd0f75cSPaul Walmsley OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | 8682fd0f75cSPaul Walmsley OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK | 8692fd0f75cSPaul Walmsley OMAP3430_EN_MCBSP4_MASK, 870b427f92fSKevin Hilman OMAP3430_PER_MOD, PM_WKEN); 871eb350f74SKevin Hilman /* and allow them to wake up MPU */ 872e5863689SGovindraj.R prm_write_mod_reg(omap3630_grpsel_uart4_mask | 873e5863689SGovindraj.R OMAP3430_GRPSEL_GPIO2_MASK | 874275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO3_MASK | 875275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO4_MASK | 876275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO5_MASK | 877275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO6_MASK | 878275f675cSPaul Walmsley OMAP3430_GRPSEL_UART3_MASK | 879275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP2_MASK | 880275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP3_MASK | 881275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP4_MASK, 882eb350f74SKevin Hilman OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); 883eb350f74SKevin Hilman 884d3fd3290SKevin Hilman /* Don't attach IVA interrupts */ 885d3fd3290SKevin Hilman prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 886d3fd3290SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 887d3fd3290SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 888d3fd3290SKevin Hilman prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); 889d3fd3290SKevin Hilman 890b1340d17SKevin Hilman /* Clear any pending 'reset' flags */ 89137903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); 89237903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); 89337903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); 89437903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); 89537903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); 89637903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); 89737903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); 898b1340d17SKevin Hilman 899014c46dbSKevin Hilman /* Clear any pending PRCM interrupts */ 900014c46dbSKevin Hilman prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 901014c46dbSKevin Hilman 9021155e426SKevin Hilman omap3_iva_idle(); 9038111b221SKevin Hilman omap3_d2d_idle(); 9048bd22949SKevin Hilman } 9058bd22949SKevin Hilman 906c40552bcSKevin Hilman void omap3_pm_off_mode_enable(int enable) 907c40552bcSKevin Hilman { 908c40552bcSKevin Hilman struct power_state *pwrst; 909c40552bcSKevin Hilman u32 state; 910c40552bcSKevin Hilman 911c40552bcSKevin Hilman if (enable) 912c40552bcSKevin Hilman state = PWRDM_POWER_OFF; 913c40552bcSKevin Hilman else 914c40552bcSKevin Hilman state = PWRDM_POWER_RET; 915c40552bcSKevin Hilman 9166af83b38SSanjeev Premi #ifdef CONFIG_CPU_IDLE 9176af83b38SSanjeev Premi omap3_cpuidle_update_states(); 9186af83b38SSanjeev Premi #endif 9196af83b38SSanjeev Premi 920c40552bcSKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 921c40552bcSKevin Hilman pwrst->next_state = state; 922eb6a2c75SSantosh Shilimkar omap_set_pwrdm_state(pwrst->pwrdm, state); 923c40552bcSKevin Hilman } 924c40552bcSKevin Hilman } 925c40552bcSKevin Hilman 92668d4778cSTero Kristo int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) 92768d4778cSTero Kristo { 92868d4778cSTero Kristo struct power_state *pwrst; 92968d4778cSTero Kristo 93068d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 93168d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) 93268d4778cSTero Kristo return pwrst->next_state; 93368d4778cSTero Kristo } 93468d4778cSTero Kristo return -EINVAL; 93568d4778cSTero Kristo } 93668d4778cSTero Kristo 93768d4778cSTero Kristo int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) 93868d4778cSTero Kristo { 93968d4778cSTero Kristo struct power_state *pwrst; 94068d4778cSTero Kristo 94168d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 94268d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) { 94368d4778cSTero Kristo pwrst->next_state = state; 94468d4778cSTero Kristo return 0; 94568d4778cSTero Kristo } 94668d4778cSTero Kristo } 94768d4778cSTero Kristo return -EINVAL; 94868d4778cSTero Kristo } 94968d4778cSTero Kristo 950a23456e9SPeter 'p2' De Schrijver static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) 9518bd22949SKevin Hilman { 9528bd22949SKevin Hilman struct power_state *pwrst; 9538bd22949SKevin Hilman 9548bd22949SKevin Hilman if (!pwrdm->pwrsts) 9558bd22949SKevin Hilman return 0; 9568bd22949SKevin Hilman 957d3d381c6SMing Lei pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); 9588bd22949SKevin Hilman if (!pwrst) 9598bd22949SKevin Hilman return -ENOMEM; 9608bd22949SKevin Hilman pwrst->pwrdm = pwrdm; 9618bd22949SKevin Hilman pwrst->next_state = PWRDM_POWER_RET; 9628bd22949SKevin Hilman list_add(&pwrst->node, &pwrst_list); 9638bd22949SKevin Hilman 9648bd22949SKevin Hilman if (pwrdm_has_hdwr_sar(pwrdm)) 9658bd22949SKevin Hilman pwrdm_enable_hdwr_sar(pwrdm); 9668bd22949SKevin Hilman 967eb6a2c75SSantosh Shilimkar return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 9688bd22949SKevin Hilman } 9698bd22949SKevin Hilman 9708bd22949SKevin Hilman /* 9718bd22949SKevin Hilman * Enable hw supervised mode for all clockdomains if it's 9728bd22949SKevin Hilman * supported. Initiate sleep transition for other clockdomains, if 9738bd22949SKevin Hilman * they are not used 9748bd22949SKevin Hilman */ 975a23456e9SPeter 'p2' De Schrijver static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) 9768bd22949SKevin Hilman { 9778bd22949SKevin Hilman if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) 9788bd22949SKevin Hilman omap2_clkdm_allow_idle(clkdm); 9798bd22949SKevin Hilman else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && 9808bd22949SKevin Hilman atomic_read(&clkdm->usecount) == 0) 9818bd22949SKevin Hilman omap2_clkdm_sleep(clkdm); 9828bd22949SKevin Hilman return 0; 9838bd22949SKevin Hilman } 9848bd22949SKevin Hilman 9853231fc88SRajendra Nayak void omap_push_sram_idle(void) 9863231fc88SRajendra Nayak { 9873231fc88SRajendra Nayak _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend, 9883231fc88SRajendra Nayak omap34xx_cpu_suspend_sz); 98927d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) 99027d59a4aSTero Kristo _omap_save_secure_sram = omap_sram_push(save_secure_ram_context, 99127d59a4aSTero Kristo save_secure_ram_context_sz); 9923231fc88SRajendra Nayak } 9933231fc88SRajendra Nayak 9947cc515f7SKevin Hilman static int __init omap3_pm_init(void) 9958bd22949SKevin Hilman { 9968bd22949SKevin Hilman struct power_state *pwrst, *tmp; 99755ed9694SPaul Walmsley struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm; 9988bd22949SKevin Hilman int ret; 9998bd22949SKevin Hilman 10008bd22949SKevin Hilman if (!cpu_is_omap34xx()) 10018bd22949SKevin Hilman return -ENODEV; 10028bd22949SKevin Hilman 10038bd22949SKevin Hilman printk(KERN_ERR "Power Management for TI OMAP3.\n"); 10048bd22949SKevin Hilman 10058bd22949SKevin Hilman /* XXX prcm_setup_regs needs to be before enabling hw 10068bd22949SKevin Hilman * supervised mode for powerdomains */ 10078bd22949SKevin Hilman prcm_setup_regs(); 10088bd22949SKevin Hilman 10098bd22949SKevin Hilman ret = request_irq(INT_34XX_PRCM_MPU_IRQ, 10108bd22949SKevin Hilman (irq_handler_t)prcm_interrupt_handler, 10118bd22949SKevin Hilman IRQF_DISABLED, "prcm", NULL); 10128bd22949SKevin Hilman if (ret) { 10138bd22949SKevin Hilman printk(KERN_ERR "request_irq failed to register for 0x%x\n", 10148bd22949SKevin Hilman INT_34XX_PRCM_MPU_IRQ); 10158bd22949SKevin Hilman goto err1; 10168bd22949SKevin Hilman } 10178bd22949SKevin Hilman 1018a23456e9SPeter 'p2' De Schrijver ret = pwrdm_for_each(pwrdms_setup, NULL); 10198bd22949SKevin Hilman if (ret) { 10208bd22949SKevin Hilman printk(KERN_ERR "Failed to setup powerdomains\n"); 10218bd22949SKevin Hilman goto err2; 10228bd22949SKevin Hilman } 10238bd22949SKevin Hilman 1024a23456e9SPeter 'p2' De Schrijver (void) clkdm_for_each(clkdms_setup, NULL); 10258bd22949SKevin Hilman 10268bd22949SKevin Hilman mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); 10278bd22949SKevin Hilman if (mpu_pwrdm == NULL) { 10288bd22949SKevin Hilman printk(KERN_ERR "Failed to get mpu_pwrdm\n"); 10298bd22949SKevin Hilman goto err2; 10308bd22949SKevin Hilman } 10318bd22949SKevin Hilman 1032fa3c2a4fSRajendra Nayak neon_pwrdm = pwrdm_lookup("neon_pwrdm"); 1033fa3c2a4fSRajendra Nayak per_pwrdm = pwrdm_lookup("per_pwrdm"); 1034fa3c2a4fSRajendra Nayak core_pwrdm = pwrdm_lookup("core_pwrdm"); 1035c16c3f67STero Kristo cam_pwrdm = pwrdm_lookup("cam_pwrdm"); 1036fa3c2a4fSRajendra Nayak 103755ed9694SPaul Walmsley neon_clkdm = clkdm_lookup("neon_clkdm"); 103855ed9694SPaul Walmsley mpu_clkdm = clkdm_lookup("mpu_clkdm"); 103955ed9694SPaul Walmsley per_clkdm = clkdm_lookup("per_clkdm"); 104055ed9694SPaul Walmsley core_clkdm = clkdm_lookup("core_clkdm"); 104155ed9694SPaul Walmsley 10423231fc88SRajendra Nayak omap_push_sram_idle(); 104310f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 10448bd22949SKevin Hilman suspend_set_ops(&omap_pm_ops); 104510f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 10468bd22949SKevin Hilman 10478bd22949SKevin Hilman pm_idle = omap3_pm_idle; 10480343371eSKalle Jokiniemi omap3_idle_init(); 10498bd22949SKevin Hilman 105055ed9694SPaul Walmsley clkdm_add_wkdep(neon_clkdm, mpu_clkdm); 105127d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 105227d59a4aSTero Kristo omap3_secure_ram_storage = 105327d59a4aSTero Kristo kmalloc(0x803F, GFP_KERNEL); 105427d59a4aSTero Kristo if (!omap3_secure_ram_storage) 105527d59a4aSTero Kristo printk(KERN_ERR "Memory allocation failed when" 105627d59a4aSTero Kristo "allocating for secure sram context\n"); 105727d59a4aSTero Kristo 10589d97140bSTero Kristo local_irq_disable(); 10599d97140bSTero Kristo local_fiq_disable(); 10609d97140bSTero Kristo 10619d97140bSTero Kristo omap_dma_global_context_save(); 10629d97140bSTero Kristo omap3_save_secure_ram_context(PWRDM_POWER_ON); 10639d97140bSTero Kristo omap_dma_global_context_restore(); 10649d97140bSTero Kristo 10659d97140bSTero Kristo local_irq_enable(); 10669d97140bSTero Kristo local_fiq_enable(); 10679d97140bSTero Kristo } 10689d97140bSTero Kristo 10699d97140bSTero Kristo omap3_save_scratchpad_contents(); 10708bd22949SKevin Hilman err1: 10718bd22949SKevin Hilman return ret; 10728bd22949SKevin Hilman err2: 10738bd22949SKevin Hilman free_irq(INT_34XX_PRCM_MPU_IRQ, NULL); 10748bd22949SKevin Hilman list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { 10758bd22949SKevin Hilman list_del(&pwrst->node); 10768bd22949SKevin Hilman kfree(pwrst); 10778bd22949SKevin Hilman } 10788bd22949SKevin Hilman return ret; 10798bd22949SKevin Hilman } 10808bd22949SKevin Hilman 10818bd22949SKevin Hilman late_initcall(omap3_pm_init); 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