18bd22949SKevin Hilman /* 28bd22949SKevin Hilman * OMAP3 Power Management Routines 38bd22949SKevin Hilman * 48bd22949SKevin Hilman * Copyright (C) 2006-2008 Nokia Corporation 58bd22949SKevin Hilman * Tony Lindgren <tony@atomide.com> 68bd22949SKevin Hilman * Jouni Hogander 78bd22949SKevin Hilman * 82f5939c3SRajendra Nayak * Copyright (C) 2007 Texas Instruments, Inc. 92f5939c3SRajendra Nayak * Rajendra Nayak <rnayak@ti.com> 102f5939c3SRajendra Nayak * 118bd22949SKevin Hilman * Copyright (C) 2005 Texas Instruments, Inc. 128bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 138bd22949SKevin Hilman * 148bd22949SKevin Hilman * Based on pm.c for omap1 158bd22949SKevin Hilman * 168bd22949SKevin Hilman * This program is free software; you can redistribute it and/or modify 178bd22949SKevin Hilman * it under the terms of the GNU General Public License version 2 as 188bd22949SKevin Hilman * published by the Free Software Foundation. 198bd22949SKevin Hilman */ 208bd22949SKevin Hilman 21b764a586STony Lindgren #include <linux/cpu_pm.h> 228bd22949SKevin Hilman #include <linux/pm.h> 238bd22949SKevin Hilman #include <linux/suspend.h> 248bd22949SKevin Hilman #include <linux/interrupt.h> 258bd22949SKevin Hilman #include <linux/module.h> 268bd22949SKevin Hilman #include <linux/list.h> 278bd22949SKevin Hilman #include <linux/err.h> 28c40552bcSKevin Hilman #include <linux/clk.h> 29dccaad89STero Kristo #include <linux/delay.h> 305a0e3ad6STejun Heo #include <linux/slab.h> 3145c3eb7dSTony Lindgren #include <linux/omap-dma.h> 32e639cd5bSTony Lindgren #include <linux/omap-gpmc.h> 334b25408fSTony Lindgren 345e7c58dcSJean Pihet #include <trace/events/power.h> 358bd22949SKevin Hilman 36bf027ca1STony Lindgren #include <asm/fncpy.h> 372c74a0ceSRussell King #include <asm/suspend.h> 389f97da78SDavid Howells #include <asm/system_misc.h> 392c74a0ceSRussell King 401540f214SPaul Walmsley #include "clockdomain.h" 4172e06d08SPaul Walmsley #include "powerdomain.h" 42e4c060dbSTony Lindgren #include "soc.h" 434e65331cSTony Lindgren #include "common.h" 44ff4ae5d9SPaul Walmsley #include "cm3xxx.h" 458bd22949SKevin Hilman #include "cm-regbits-34xx.h" 468bd22949SKevin Hilman #include "prm-regbits-34xx.h" 47139563adSPaul Walmsley #include "prm3xxx.h" 488bd22949SKevin Hilman #include "pm.h" 4913a6fe0fSTero Kristo #include "sdrc.h" 50d09220a8STony Lindgren #include "omap-secure.h" 51bf027ca1STony Lindgren #include "sram.h" 524814ced5SPaul Walmsley #include "control.h" 533b8c4ebbSTony Lindgren #include "vc.h" 5413a6fe0fSTero Kristo 558cdfd834SNishanth Menon /* pm34xx errata defined in pm.h */ 568cdfd834SNishanth Menon u16 pm34xx_errata; 578cdfd834SNishanth Menon 588bd22949SKevin Hilman struct power_state { 598bd22949SKevin Hilman struct powerdomain *pwrdm; 608bd22949SKevin Hilman u32 next_state; 6110f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 628bd22949SKevin Hilman u32 saved_state; 6310f90ed2SKevin Hilman #endif 648bd22949SKevin Hilman struct list_head node; 658bd22949SKevin Hilman }; 668bd22949SKevin Hilman 678bd22949SKevin Hilman static LIST_HEAD(pwrst_list); 688bd22949SKevin Hilman 6946e130d2SJean Pihet void (*omap3_do_wfi_sram)(void); 7027d59a4aSTero Kristo 71fa3c2a4fSRajendra Nayak static struct powerdomain *mpu_pwrdm, *neon_pwrdm; 72fa3c2a4fSRajendra Nayak static struct powerdomain *core_pwrdm, *per_pwrdm; 733a7ec26bSKalle Jokiniemi 742f5939c3SRajendra Nayak static void omap3_core_save_context(void) 752f5939c3SRajendra Nayak { 76596efe47SPaul Walmsley omap3_ctrl_save_padconf(); 77dccaad89STero Kristo 78dccaad89STero Kristo /* 79dccaad89STero Kristo * Force write last pad into memory, as this can fail in some 8083521291SJean Pihet * cases according to errata 1.157, 1.185 81dccaad89STero Kristo */ 82dccaad89STero Kristo omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), 83dccaad89STero Kristo OMAP343X_CONTROL_MEM_WKUP + 0x2a0); 84dccaad89STero Kristo 852f5939c3SRajendra Nayak /* Save the Interrupt controller context */ 862f5939c3SRajendra Nayak omap_intc_save_context(); 872f5939c3SRajendra Nayak /* Save the GPMC context */ 882f5939c3SRajendra Nayak omap3_gpmc_save_context(); 892f5939c3SRajendra Nayak /* Save the system control module context, padconf already save above*/ 902f5939c3SRajendra Nayak omap3_control_save_context(); 91f2d11858STero Kristo omap_dma_global_context_save(); 922f5939c3SRajendra Nayak } 932f5939c3SRajendra Nayak 942f5939c3SRajendra Nayak static void omap3_core_restore_context(void) 952f5939c3SRajendra Nayak { 962f5939c3SRajendra Nayak /* Restore the control module context, padconf restored by h/w */ 972f5939c3SRajendra Nayak omap3_control_restore_context(); 982f5939c3SRajendra Nayak /* Restore the GPMC context */ 992f5939c3SRajendra Nayak omap3_gpmc_restore_context(); 1002f5939c3SRajendra Nayak /* Restore the interrupt controller context */ 1012f5939c3SRajendra Nayak omap_intc_restore_context(); 102f2d11858STero Kristo omap_dma_global_context_restore(); 1032f5939c3SRajendra Nayak } 1042f5939c3SRajendra Nayak 1059d97140bSTero Kristo /* 1069d97140bSTero Kristo * FIXME: This function should be called before entering off-mode after 1079d97140bSTero Kristo * OMAP3 secure services have been accessed. Currently it is only called 1089d97140bSTero Kristo * once during boot sequence, but this works as we are not using secure 1099d97140bSTero Kristo * services. 1109d97140bSTero Kristo */ 111617fcc98SKevin Hilman static void omap3_save_secure_ram_context(void) 11227d59a4aSTero Kristo { 11327d59a4aSTero Kristo u32 ret; 114617fcc98SKevin Hilman int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 11527d59a4aSTero Kristo 11627d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 11727d59a4aSTero Kristo /* 11827d59a4aSTero Kristo * MPU next state must be set to POWER_ON temporarily, 11927d59a4aSTero Kristo * otherwise the WFI executed inside the ROM code 12027d59a4aSTero Kristo * will hang the system. 12127d59a4aSTero Kristo */ 12227d59a4aSTero Kristo pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); 123d09220a8STony Lindgren ret = omap3_save_secure_ram(omap3_secure_ram_storage, 124d09220a8STony Lindgren OMAP3_SAVE_SECURE_RAM_SZ); 125617fcc98SKevin Hilman pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state); 12627d59a4aSTero Kristo /* Following is for error tracking, it should not happen */ 12727d59a4aSTero Kristo if (ret) { 12898179856SMark A. Greer pr_err("save_secure_sram() returns %08x\n", ret); 12927d59a4aSTero Kristo while (1) 13027d59a4aSTero Kristo ; 13127d59a4aSTero Kristo } 13227d59a4aSTero Kristo } 13327d59a4aSTero Kristo } 13427d59a4aSTero Kristo 13522f51371STero Kristo static irqreturn_t _prcm_int_handle_io(int irq, void *unused) 1368cb0ac99SPaul Walmsley { 1378cb0ac99SPaul Walmsley int c; 1388cb0ac99SPaul Walmsley 1399cb6d363STero Kristo c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, OMAP3430_ST_IO_MASK | 140f0caa527STero Kristo OMAP3430_ST_IO_CHAIN_MASK); 14122f51371STero Kristo 14222f51371STero Kristo return c ? IRQ_HANDLED : IRQ_NONE; 1438cb0ac99SPaul Walmsley } 1448cb0ac99SPaul Walmsley 14522f51371STero Kristo static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused) 1468bd22949SKevin Hilman { 14722f51371STero Kristo int c; 1488cb0ac99SPaul Walmsley 1498cb0ac99SPaul Walmsley /* 15022f51371STero Kristo * Clear all except ST_IO and ST_IO_CHAIN for wkup module, 15122f51371STero Kristo * these are handled in a separate handler to avoid acking 15222f51371STero Kristo * IO events before parsing in mux code 1538cb0ac99SPaul Walmsley */ 1549cb6d363STero Kristo c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, ~(OMAP3430_ST_IO_MASK | 155f0caa527STero Kristo OMAP3430_ST_IO_CHAIN_MASK)); 1569cb6d363STero Kristo c += omap_prm_clear_mod_irqs(CORE_MOD, 1, ~0); 1579cb6d363STero Kristo c += omap_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, ~0); 15822f51371STero Kristo if (omap_rev() > OMAP3430_REV_ES1_0) { 1599cb6d363STero Kristo c += omap_prm_clear_mod_irqs(CORE_MOD, 3, ~0); 1609cb6d363STero Kristo c += omap_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, ~0); 1618cb0ac99SPaul Walmsley } 1628cb0ac99SPaul Walmsley 16322f51371STero Kristo return c ? IRQ_HANDLED : IRQ_NONE; 1648bd22949SKevin Hilman } 1658bd22949SKevin Hilman 166cbe26349SRussell King static void omap34xx_save_context(u32 *save) 167cbe26349SRussell King { 168cbe26349SRussell King u32 val; 169cbe26349SRussell King 170cbe26349SRussell King /* Read Auxiliary Control Register */ 171cbe26349SRussell King asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val)); 172cbe26349SRussell King *save++ = 1; 173cbe26349SRussell King *save++ = val; 174cbe26349SRussell King 175cbe26349SRussell King /* Read L2 AUX ctrl register */ 176cbe26349SRussell King asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); 177cbe26349SRussell King *save++ = 1; 178cbe26349SRussell King *save++ = val; 179cbe26349SRussell King } 180cbe26349SRussell King 18129cb3cd2SRussell King static int omap34xx_do_sram_idle(unsigned long save_state) 18257f277b0SRajendra Nayak { 183cbe26349SRussell King omap34xx_cpu_suspend(save_state); 18429cb3cd2SRussell King return 0; 18557f277b0SRajendra Nayak } 18657f277b0SRajendra Nayak 18799e6a4d2SRajendra Nayak void omap_sram_idle(void) 1888bd22949SKevin Hilman { 1898bd22949SKevin Hilman /* Variable to tell what needs to be saved and restored 1908bd22949SKevin Hilman * in omap_sram_idle*/ 1918bd22949SKevin Hilman /* save_state = 0 => Nothing to save and restored */ 1928bd22949SKevin Hilman /* save_state = 1 => Only L1 and logic lost */ 1938bd22949SKevin Hilman /* save_state = 2 => Only L2 lost */ 1948bd22949SKevin Hilman /* save_state = 3 => L1, L2 and logic lost */ 195fa3c2a4fSRajendra Nayak int save_state = 0; 196fa3c2a4fSRajendra Nayak int mpu_next_state = PWRDM_POWER_ON; 197fa3c2a4fSRajendra Nayak int per_next_state = PWRDM_POWER_ON; 198fa3c2a4fSRajendra Nayak int core_next_state = PWRDM_POWER_ON; 19913a6fe0fSTero Kristo u32 sdrc_pwr = 0; 2008bd22949SKevin Hilman 2018bd22949SKevin Hilman mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 2028bd22949SKevin Hilman switch (mpu_next_state) { 203fa3c2a4fSRajendra Nayak case PWRDM_POWER_ON: 2048bd22949SKevin Hilman case PWRDM_POWER_RET: 2058bd22949SKevin Hilman /* No need to save context */ 2068bd22949SKevin Hilman save_state = 0; 2078bd22949SKevin Hilman break; 20861255ab9SRajendra Nayak case PWRDM_POWER_OFF: 20961255ab9SRajendra Nayak save_state = 3; 21061255ab9SRajendra Nayak break; 2118bd22949SKevin Hilman default: 2128bd22949SKevin Hilman /* Invalid state */ 21398179856SMark A. Greer pr_err("Invalid mpu state in sram_idle\n"); 2148bd22949SKevin Hilman return; 2158bd22949SKevin Hilman } 216fe617af7SPeter 'p2' De Schrijver 217fa3c2a4fSRajendra Nayak /* NEON control */ 218fa3c2a4fSRajendra Nayak if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) 2197139178eSJouni Hogander pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); 220fa3c2a4fSRajendra Nayak 22140742fa8SMike Chan /* Enable IO-PAD and IO-CHAIN wakeups */ 222fa3c2a4fSRajendra Nayak per_next_state = pwrdm_read_next_pwrst(per_pwrdm); 223ecf157d0STero Kristo core_next_state = pwrdm_read_next_pwrst(core_pwrdm); 22440742fa8SMike Chan 225e0e29fd7SKevin Hilman pwrdm_pre_transition(NULL); 226ff2f8e5fSCharulatha V 22740742fa8SMike Chan /* PER */ 228b764a586STony Lindgren if (per_next_state == PWRDM_POWER_OFF) 229b764a586STony Lindgren cpu_cluster_pm_enter(); 230c16c3f67STero Kristo 231658ce97eSKevin Hilman /* CORE */ 232658ce97eSKevin Hilman if (core_next_state < PWRDM_POWER_ON) { 2332f5939c3SRajendra Nayak if (core_next_state == PWRDM_POWER_OFF) { 2342f5939c3SRajendra Nayak omap3_core_save_context(); 235f0611a5cSPaul Walmsley omap3_cm_save_context(); 2362f5939c3SRajendra Nayak } 237fa3c2a4fSRajendra Nayak } 23840742fa8SMike Chan 2393b8c4ebbSTony Lindgren /* Configure PMIC signaling for I2C4 or sys_off_mode */ 2403b8c4ebbSTony Lindgren omap3_vc_set_pmic_signaling(core_next_state); 2413b8c4ebbSTony Lindgren 242f18cc2ffSTero Kristo omap3_intc_prepare_idle(); 2438bd22949SKevin Hilman 24461255ab9SRajendra Nayak /* 245f265dc4cSRajendra Nayak * On EMU/HS devices ROM code restores a SRDC value 246f265dc4cSRajendra Nayak * from scratchpad which has automatic self refresh on timeout 24783521291SJean Pihet * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443. 248f265dc4cSRajendra Nayak * Hence store/restore the SDRC_POWER register here. 24913a6fe0fSTero Kristo */ 25030474544SPaul Walmsley if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && 25130474544SPaul Walmsley (omap_type() == OMAP2_DEVICE_TYPE_EMU || 25230474544SPaul Walmsley omap_type() == OMAP2_DEVICE_TYPE_SEC) && 253f265dc4cSRajendra Nayak core_next_state == PWRDM_POWER_OFF) 25413a6fe0fSTero Kristo sdrc_pwr = sdrc_read_reg(SDRC_POWER); 25513a6fe0fSTero Kristo 25613a6fe0fSTero Kristo /* 257076f2cc4SRussell King * omap3_arm_context is the location where some ARM context 258076f2cc4SRussell King * get saved. The rest is placed on the stack, and restored 259076f2cc4SRussell King * from there before resuming. 26061255ab9SRajendra Nayak */ 261cbe26349SRussell King if (save_state) 262cbe26349SRussell King omap34xx_save_context(omap3_arm_context); 263076f2cc4SRussell King if (save_state == 1 || save_state == 3) 2642c74a0ceSRussell King cpu_suspend(save_state, omap34xx_do_sram_idle); 265076f2cc4SRussell King else 266076f2cc4SRussell King omap34xx_do_sram_idle(save_state); 2678bd22949SKevin Hilman 268f265dc4cSRajendra Nayak /* Restore normal SDRC POWER settings */ 26930474544SPaul Walmsley if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && 27030474544SPaul Walmsley (omap_type() == OMAP2_DEVICE_TYPE_EMU || 27130474544SPaul Walmsley omap_type() == OMAP2_DEVICE_TYPE_SEC) && 27213a6fe0fSTero Kristo core_next_state == PWRDM_POWER_OFF) 27313a6fe0fSTero Kristo sdrc_write_reg(sdrc_pwr, SDRC_POWER); 27413a6fe0fSTero Kristo 275658ce97eSKevin Hilman /* CORE */ 2761560d158SDave Gerlach if (core_next_state < PWRDM_POWER_ON && 2771560d158SDave Gerlach pwrdm_read_prev_pwrst(core_pwrdm) == PWRDM_POWER_OFF) { 2782f5939c3SRajendra Nayak omap3_core_restore_context(); 279f0611a5cSPaul Walmsley omap3_cm_restore_context(); 2802f5939c3SRajendra Nayak omap3_sram_restore_context(); 2818a917d2fSKalle Jokiniemi omap2_sms_restore_context(); 2821560d158SDave Gerlach } else { 2831560d158SDave Gerlach /* 2841560d158SDave Gerlach * In off-mode resume path above, omap3_core_restore_context 2851560d158SDave Gerlach * also handles the INTC autoidle restore done here so limit 2861560d158SDave Gerlach * this to non-off mode resume paths so we don't do it twice. 2871560d158SDave Gerlach */ 288f18cc2ffSTero Kristo omap3_intc_resume_idle(); 2891560d158SDave Gerlach } 290658ce97eSKevin Hilman 291e0e29fd7SKevin Hilman pwrdm_post_transition(NULL); 292658ce97eSKevin Hilman 293e0e29fd7SKevin Hilman /* PER */ 294b764a586STony Lindgren if (per_next_state == PWRDM_POWER_OFF) 295b764a586STony Lindgren cpu_cluster_pm_exit(); 2968bd22949SKevin Hilman } 2978bd22949SKevin Hilman 2988bd22949SKevin Hilman static void omap3_pm_idle(void) 2998bd22949SKevin Hilman { 3000bcd24b0SNicolas Pitre if (omap_irq_pending()) 3016b85638bSSantosh Shilimkar return; 3028bd22949SKevin Hilman 3036ca22700SJisheng Zhang trace_cpu_idle_rcuidle(1, smp_processor_id()); 3045e7c58dcSJean Pihet 3058bd22949SKevin Hilman omap_sram_idle(); 3068bd22949SKevin Hilman 3076ca22700SJisheng Zhang trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); 3088bd22949SKevin Hilman } 3098bd22949SKevin Hilman 31010f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 3118bd22949SKevin Hilman static int omap3_pm_suspend(void) 3128bd22949SKevin Hilman { 3138bd22949SKevin Hilman struct power_state *pwrst; 3148bd22949SKevin Hilman int state, ret = 0; 3158bd22949SKevin Hilman 3168bd22949SKevin Hilman /* Read current next_pwrsts */ 3178bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) 3188bd22949SKevin Hilman pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 3198bd22949SKevin Hilman /* Set ones wanted by suspend */ 3208bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 321eb6a2c75SSantosh Shilimkar if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) 3228bd22949SKevin Hilman goto restore; 3238bd22949SKevin Hilman if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) 3248bd22949SKevin Hilman goto restore; 3258bd22949SKevin Hilman } 3268bd22949SKevin Hilman 3272bbe3af3STero Kristo omap3_intc_suspend(); 3282bbe3af3STero Kristo 3298bd22949SKevin Hilman omap_sram_idle(); 3308bd22949SKevin Hilman 3318bd22949SKevin Hilman restore: 3328bd22949SKevin Hilman /* Restore next_pwrsts */ 3338bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 3348bd22949SKevin Hilman state = pwrdm_read_prev_pwrst(pwrst->pwrdm); 3358bd22949SKevin Hilman if (state > pwrst->next_state) { 3367852ec05SPaul Walmsley pr_info("Powerdomain (%s) didn't enter target state %d\n", 3378bd22949SKevin Hilman pwrst->pwrdm->name, pwrst->next_state); 3388bd22949SKevin Hilman ret = -1; 3398bd22949SKevin Hilman } 340eb6a2c75SSantosh Shilimkar omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); 3418bd22949SKevin Hilman } 3428bd22949SKevin Hilman if (ret) 34398179856SMark A. Greer pr_err("Could not enter target state in pm_suspend\n"); 3448bd22949SKevin Hilman else 34598179856SMark A. Greer pr_info("Successfully put all powerdomains to target state\n"); 3468bd22949SKevin Hilman 3478bd22949SKevin Hilman return ret; 3488bd22949SKevin Hilman } 3492e4b62dcSDave Gerlach #else 3502e4b62dcSDave Gerlach #define omap3_pm_suspend NULL 35110f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 3528bd22949SKevin Hilman 3538111b221SKevin Hilman static void __init prcm_setup_regs(void) 3548111b221SKevin Hilman { 355ba12c242STero Kristo omap3_ctrl_init(); 356b296c811STero Kristo 357c5180a2bSTero Kristo omap3_prm_init_pm(cpu_is_omap3630(), omap3_has_iva()); 3588bd22949SKevin Hilman } 3598bd22949SKevin Hilman 360c40552bcSKevin Hilman void omap3_pm_off_mode_enable(int enable) 361c40552bcSKevin Hilman { 362c40552bcSKevin Hilman struct power_state *pwrst; 363c40552bcSKevin Hilman u32 state; 364c40552bcSKevin Hilman 365c40552bcSKevin Hilman if (enable) 366c40552bcSKevin Hilman state = PWRDM_POWER_OFF; 367c40552bcSKevin Hilman else 368c40552bcSKevin Hilman state = PWRDM_POWER_RET; 369c40552bcSKevin Hilman 370c40552bcSKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 371cc1b6028SEduardo Valentin if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) && 372cc1b6028SEduardo Valentin pwrst->pwrdm == core_pwrdm && 373cc1b6028SEduardo Valentin state == PWRDM_POWER_OFF) { 374cc1b6028SEduardo Valentin pwrst->next_state = PWRDM_POWER_RET; 375e16b41bfSRicardo Salveti de Araujo pr_warn("%s: Core OFF disabled due to errata i583\n", 376cc1b6028SEduardo Valentin __func__); 377cc1b6028SEduardo Valentin } else { 378c40552bcSKevin Hilman pwrst->next_state = state; 379cc1b6028SEduardo Valentin } 380cc1b6028SEduardo Valentin omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 381c40552bcSKevin Hilman } 382c40552bcSKevin Hilman } 383c40552bcSKevin Hilman 38468d4778cSTero Kristo int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) 38568d4778cSTero Kristo { 38668d4778cSTero Kristo struct power_state *pwrst; 38768d4778cSTero Kristo 38868d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 38968d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) 39068d4778cSTero Kristo return pwrst->next_state; 39168d4778cSTero Kristo } 39268d4778cSTero Kristo return -EINVAL; 39368d4778cSTero Kristo } 39468d4778cSTero Kristo 39568d4778cSTero Kristo int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) 39668d4778cSTero Kristo { 39768d4778cSTero Kristo struct power_state *pwrst; 39868d4778cSTero Kristo 39968d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 40068d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) { 40168d4778cSTero Kristo pwrst->next_state = state; 40268d4778cSTero Kristo return 0; 40368d4778cSTero Kristo } 40468d4778cSTero Kristo } 40568d4778cSTero Kristo return -EINVAL; 40668d4778cSTero Kristo } 40768d4778cSTero Kristo 408a23456e9SPeter 'p2' De Schrijver static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) 4098bd22949SKevin Hilman { 4108bd22949SKevin Hilman struct power_state *pwrst; 4118bd22949SKevin Hilman 4128bd22949SKevin Hilman if (!pwrdm->pwrsts) 4138bd22949SKevin Hilman return 0; 4148bd22949SKevin Hilman 415d3d381c6SMing Lei pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); 4168bd22949SKevin Hilman if (!pwrst) 4178bd22949SKevin Hilman return -ENOMEM; 4188bd22949SKevin Hilman pwrst->pwrdm = pwrdm; 4198bd22949SKevin Hilman pwrst->next_state = PWRDM_POWER_RET; 4208bd22949SKevin Hilman list_add(&pwrst->node, &pwrst_list); 4218bd22949SKevin Hilman 4228bd22949SKevin Hilman if (pwrdm_has_hdwr_sar(pwrdm)) 4238bd22949SKevin Hilman pwrdm_enable_hdwr_sar(pwrdm); 4248bd22949SKevin Hilman 425eb6a2c75SSantosh Shilimkar return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 4268bd22949SKevin Hilman } 4278bd22949SKevin Hilman 4288bd22949SKevin Hilman /* 42946e130d2SJean Pihet * Push functions to SRAM 43046e130d2SJean Pihet * 43146e130d2SJean Pihet * The minimum set of functions is pushed to SRAM for execution: 43246e130d2SJean Pihet * - omap3_do_wfi for erratum i581 WA, 43346e130d2SJean Pihet */ 4343231fc88SRajendra Nayak void omap_push_sram_idle(void) 4353231fc88SRajendra Nayak { 43646e130d2SJean Pihet omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz); 4373231fc88SRajendra Nayak } 4383231fc88SRajendra Nayak 4398cdfd834SNishanth Menon static void __init pm_errata_configure(void) 4408cdfd834SNishanth Menon { 441c4236d2eSPeter 'p2' De Schrijver if (cpu_is_omap3630()) { 442458e999eSNishanth Menon pm34xx_errata |= PM_RTA_ERRATUM_i608; 443c4236d2eSPeter 'p2' De Schrijver /* Enable the l2 cache toggling in sleep logic */ 444c4236d2eSPeter 'p2' De Schrijver enable_omap3630_toggle_l2_on_restore(); 445cc1b6028SEduardo Valentin if (omap_rev() < OMAP3630_REV_ES1_2) 446856c3c5bSPaul Walmsley pm34xx_errata |= (PM_SDRC_WAKEUP_ERRATUM_i583 | 447856c3c5bSPaul Walmsley PM_PER_MEMORIES_ERRATUM_i582); 448856c3c5bSPaul Walmsley } else if (cpu_is_omap34xx()) { 449856c3c5bSPaul Walmsley pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582; 450c4236d2eSPeter 'p2' De Schrijver } 4518cdfd834SNishanth Menon } 4528cdfd834SNishanth Menon 453bbd707acSShawn Guo int __init omap3_pm_init(void) 4548bd22949SKevin Hilman { 4558bd22949SKevin Hilman struct power_state *pwrst, *tmp; 456856c3c5bSPaul Walmsley struct clockdomain *neon_clkdm, *mpu_clkdm, *per_clkdm, *wkup_clkdm; 4578bd22949SKevin Hilman int ret; 4588bd22949SKevin Hilman 459b02b9172SPaul Walmsley if (!omap3_has_io_chain_ctrl()) 4603d0cb73eSJoe Perches pr_warn("PM: no software I/O chain control; some wakeups may be lost\n"); 461b02b9172SPaul Walmsley 4628cdfd834SNishanth Menon pm_errata_configure(); 4638cdfd834SNishanth Menon 4648bd22949SKevin Hilman /* XXX prcm_setup_regs needs to be before enabling hw 4658bd22949SKevin Hilman * supervised mode for powerdomains */ 4668bd22949SKevin Hilman prcm_setup_regs(); 4678bd22949SKevin Hilman 46822f51371STero Kristo ret = request_irq(omap_prcm_event_to_irq("wkup"), 46922f51371STero Kristo _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL); 47022f51371STero Kristo 4718bd22949SKevin Hilman if (ret) { 47222f51371STero Kristo pr_err("pm: Failed to request pm_wkup irq\n"); 47322f51371STero Kristo goto err1; 47422f51371STero Kristo } 47522f51371STero Kristo 47622f51371STero Kristo /* IO interrupt is shared with mux code */ 47722f51371STero Kristo ret = request_irq(omap_prcm_event_to_irq("io"), 47822f51371STero Kristo _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io", 47922f51371STero Kristo omap3_pm_init); 48022f51371STero Kristo 48122f51371STero Kristo if (ret) { 48222f51371STero Kristo pr_err("pm: Failed to request pm_io irq\n"); 483ce229c5dSMark A. Greer goto err2; 4848bd22949SKevin Hilman } 4858bd22949SKevin Hilman 486a23456e9SPeter 'p2' De Schrijver ret = pwrdm_for_each(pwrdms_setup, NULL); 4878bd22949SKevin Hilman if (ret) { 48898179856SMark A. Greer pr_err("Failed to setup powerdomains\n"); 489ce229c5dSMark A. Greer goto err3; 4908bd22949SKevin Hilman } 4918bd22949SKevin Hilman 49292206fd2SPaul Walmsley (void) clkdm_for_each(omap_pm_clkdms_setup, NULL); 4938bd22949SKevin Hilman 4948bd22949SKevin Hilman mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); 4958bd22949SKevin Hilman if (mpu_pwrdm == NULL) { 49698179856SMark A. Greer pr_err("Failed to get mpu_pwrdm\n"); 497ce229c5dSMark A. Greer ret = -EINVAL; 498ce229c5dSMark A. Greer goto err3; 4998bd22949SKevin Hilman } 5008bd22949SKevin Hilman 501fa3c2a4fSRajendra Nayak neon_pwrdm = pwrdm_lookup("neon_pwrdm"); 502fa3c2a4fSRajendra Nayak per_pwrdm = pwrdm_lookup("per_pwrdm"); 503fa3c2a4fSRajendra Nayak core_pwrdm = pwrdm_lookup("core_pwrdm"); 504fa3c2a4fSRajendra Nayak 50555ed9694SPaul Walmsley neon_clkdm = clkdm_lookup("neon_clkdm"); 50655ed9694SPaul Walmsley mpu_clkdm = clkdm_lookup("mpu_clkdm"); 507856c3c5bSPaul Walmsley per_clkdm = clkdm_lookup("per_clkdm"); 508856c3c5bSPaul Walmsley wkup_clkdm = clkdm_lookup("wkup_clkdm"); 50955ed9694SPaul Walmsley 5102e4b62dcSDave Gerlach omap_common_suspend_init(omap3_pm_suspend); 5118bd22949SKevin Hilman 5120bcd24b0SNicolas Pitre arm_pm_idle = omap3_pm_idle; 5130343371eSKalle Jokiniemi omap3_idle_init(); 5148bd22949SKevin Hilman 515458e999eSNishanth Menon /* 516458e999eSNishanth Menon * RTA is disabled during initialization as per erratum i608 517458e999eSNishanth Menon * it is safer to disable RTA by the bootloader, but we would like 518458e999eSNishanth Menon * to be doubly sure here and prevent any mishaps. 519458e999eSNishanth Menon */ 520458e999eSNishanth Menon if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608)) 521458e999eSNishanth Menon omap3630_ctrl_disable_rta(); 522458e999eSNishanth Menon 523856c3c5bSPaul Walmsley /* 524856c3c5bSPaul Walmsley * The UART3/4 FIFO and the sidetone memory in McBSP2/3 are 525856c3c5bSPaul Walmsley * not correctly reset when the PER powerdomain comes back 526856c3c5bSPaul Walmsley * from OFF or OSWR when the CORE powerdomain is kept active. 527856c3c5bSPaul Walmsley * See OMAP36xx Erratum i582 "PER Domain reset issue after 528856c3c5bSPaul Walmsley * Domain-OFF/OSWR Wakeup". This wakeup dependency is not a 529856c3c5bSPaul Walmsley * complete workaround. The kernel must also prevent the PER 530856c3c5bSPaul Walmsley * powerdomain from going to OSWR/OFF while the CORE 531856c3c5bSPaul Walmsley * powerdomain is not going to OSWR/OFF. And if PER last 532856c3c5bSPaul Walmsley * power state was off while CORE last power state was ON, the 533856c3c5bSPaul Walmsley * UART3/4 and McBSP2/3 SIDETONE devices need to run a 534856c3c5bSPaul Walmsley * self-test using their loopback tests; if that fails, those 535856c3c5bSPaul Walmsley * devices are unusable until the PER/CORE can complete a transition 536856c3c5bSPaul Walmsley * from ON to OSWR/OFF and then back to ON. 537856c3c5bSPaul Walmsley * 538856c3c5bSPaul Walmsley * XXX Technically this workaround is only needed if off-mode 539856c3c5bSPaul Walmsley * or OSWR is enabled. 540856c3c5bSPaul Walmsley */ 541856c3c5bSPaul Walmsley if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582)) 542856c3c5bSPaul Walmsley clkdm_add_wkdep(per_clkdm, wkup_clkdm); 543856c3c5bSPaul Walmsley 54455ed9694SPaul Walmsley clkdm_add_wkdep(neon_clkdm, mpu_clkdm); 54527d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 54627d59a4aSTero Kristo omap3_secure_ram_storage = 547d09220a8STony Lindgren kmalloc(OMAP3_SAVE_SECURE_RAM_SZ, GFP_KERNEL); 54827d59a4aSTero Kristo if (!omap3_secure_ram_storage) 5497852ec05SPaul Walmsley pr_err("Memory allocation failed when allocating for secure sram context\n"); 55027d59a4aSTero Kristo 5519d97140bSTero Kristo local_irq_disable(); 5529d97140bSTero Kristo 5539d97140bSTero Kristo omap_dma_global_context_save(); 554617fcc98SKevin Hilman omap3_save_secure_ram_context(); 5559d97140bSTero Kristo omap_dma_global_context_restore(); 5569d97140bSTero Kristo 5579d97140bSTero Kristo local_irq_enable(); 5589d97140bSTero Kristo } 5599d97140bSTero Kristo 5609d97140bSTero Kristo omap3_save_scratchpad_contents(); 5618bd22949SKevin Hilman return ret; 562ce229c5dSMark A. Greer 563ce229c5dSMark A. Greer err3: 5648bd22949SKevin Hilman list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { 5658bd22949SKevin Hilman list_del(&pwrst->node); 5668bd22949SKevin Hilman kfree(pwrst); 5678bd22949SKevin Hilman } 568ce229c5dSMark A. Greer free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init); 569ce229c5dSMark A. Greer err2: 570ce229c5dSMark A. Greer free_irq(omap_prcm_event_to_irq("wkup"), NULL); 571ce229c5dSMark A. Greer err1: 5728bd22949SKevin Hilman return ret; 5738bd22949SKevin Hilman } 574