18bd22949SKevin Hilman /* 28bd22949SKevin Hilman * OMAP3 Power Management Routines 38bd22949SKevin Hilman * 48bd22949SKevin Hilman * Copyright (C) 2006-2008 Nokia Corporation 58bd22949SKevin Hilman * Tony Lindgren <tony@atomide.com> 68bd22949SKevin Hilman * Jouni Hogander 78bd22949SKevin Hilman * 82f5939c3SRajendra Nayak * Copyright (C) 2007 Texas Instruments, Inc. 92f5939c3SRajendra Nayak * Rajendra Nayak <rnayak@ti.com> 102f5939c3SRajendra Nayak * 118bd22949SKevin Hilman * Copyright (C) 2005 Texas Instruments, Inc. 128bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 138bd22949SKevin Hilman * 148bd22949SKevin Hilman * Based on pm.c for omap1 158bd22949SKevin Hilman * 168bd22949SKevin Hilman * This program is free software; you can redistribute it and/or modify 178bd22949SKevin Hilman * it under the terms of the GNU General Public License version 2 as 188bd22949SKevin Hilman * published by the Free Software Foundation. 198bd22949SKevin Hilman */ 208bd22949SKevin Hilman 218bd22949SKevin Hilman #include <linux/pm.h> 228bd22949SKevin Hilman #include <linux/suspend.h> 238bd22949SKevin Hilman #include <linux/interrupt.h> 248bd22949SKevin Hilman #include <linux/module.h> 258bd22949SKevin Hilman #include <linux/list.h> 268bd22949SKevin Hilman #include <linux/err.h> 278bd22949SKevin Hilman #include <linux/gpio.h> 28c40552bcSKevin Hilman #include <linux/clk.h> 29dccaad89STero Kristo #include <linux/delay.h> 305a0e3ad6STejun Heo #include <linux/slab.h> 310d8e2d0dSPaul Walmsley #include <linux/console.h> 325e7c58dcSJean Pihet #include <trace/events/power.h> 338bd22949SKevin Hilman 342c74a0ceSRussell King #include <asm/suspend.h> 352c74a0ceSRussell King 36ce491cf8STony Lindgren #include <plat/sram.h> 371540f214SPaul Walmsley #include "clockdomain.h" 3872e06d08SPaul Walmsley #include "powerdomain.h" 39ce491cf8STony Lindgren #include <plat/serial.h> 4061255ab9SRajendra Nayak #include <plat/sdrc.h> 412f5939c3SRajendra Nayak #include <plat/prcm.h> 422f5939c3SRajendra Nayak #include <plat/gpmc.h> 43f2d11858STero Kristo #include <plat/dma.h> 448bd22949SKevin Hilman 4559fb659bSPaul Walmsley #include "cm2xxx_3xxx.h" 468bd22949SKevin Hilman #include "cm-regbits-34xx.h" 478bd22949SKevin Hilman #include "prm-regbits-34xx.h" 488bd22949SKevin Hilman 4959fb659bSPaul Walmsley #include "prm2xxx_3xxx.h" 508bd22949SKevin Hilman #include "pm.h" 5113a6fe0fSTero Kristo #include "sdrc.h" 524814ced5SPaul Walmsley #include "control.h" 5313a6fe0fSTero Kristo 54e83df17fSKevin Hilman #ifdef CONFIG_SUSPEND 55e83df17fSKevin Hilman static suspend_state_t suspend_state = PM_SUSPEND_ON; 56e83df17fSKevin Hilman static inline bool is_suspending(void) 57e83df17fSKevin Hilman { 58e83df17fSKevin Hilman return (suspend_state != PM_SUSPEND_ON); 59e83df17fSKevin Hilman } 60e83df17fSKevin Hilman #else 61e83df17fSKevin Hilman static inline bool is_suspending(void) 62e83df17fSKevin Hilman { 63e83df17fSKevin Hilman return false; 64e83df17fSKevin Hilman } 65e83df17fSKevin Hilman #endif 66e83df17fSKevin Hilman 678cdfd834SNishanth Menon /* pm34xx errata defined in pm.h */ 688cdfd834SNishanth Menon u16 pm34xx_errata; 698cdfd834SNishanth Menon 708bd22949SKevin Hilman struct power_state { 718bd22949SKevin Hilman struct powerdomain *pwrdm; 728bd22949SKevin Hilman u32 next_state; 7310f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 748bd22949SKevin Hilman u32 saved_state; 7510f90ed2SKevin Hilman #endif 768bd22949SKevin Hilman struct list_head node; 778bd22949SKevin Hilman }; 788bd22949SKevin Hilman 798bd22949SKevin Hilman static LIST_HEAD(pwrst_list); 808bd22949SKevin Hilman 8127d59a4aSTero Kristo static int (*_omap_save_secure_sram)(u32 *addr); 8246e130d2SJean Pihet void (*omap3_do_wfi_sram)(void); 8327d59a4aSTero Kristo 84fa3c2a4fSRajendra Nayak static struct powerdomain *mpu_pwrdm, *neon_pwrdm; 85fa3c2a4fSRajendra Nayak static struct powerdomain *core_pwrdm, *per_pwrdm; 86c16c3f67STero Kristo static struct powerdomain *cam_pwrdm; 87fa3c2a4fSRajendra Nayak 882f5939c3SRajendra Nayak static inline void omap3_per_save_context(void) 892f5939c3SRajendra Nayak { 902f5939c3SRajendra Nayak omap_gpio_save_context(); 912f5939c3SRajendra Nayak } 922f5939c3SRajendra Nayak 932f5939c3SRajendra Nayak static inline void omap3_per_restore_context(void) 942f5939c3SRajendra Nayak { 952f5939c3SRajendra Nayak omap_gpio_restore_context(); 962f5939c3SRajendra Nayak } 972f5939c3SRajendra Nayak 983a7ec26bSKalle Jokiniemi static void omap3_enable_io_chain(void) 993a7ec26bSKalle Jokiniemi { 1003a7ec26bSKalle Jokiniemi int timeout = 0; 1013a7ec26bSKalle Jokiniemi 102c4d7e58fSPaul Walmsley omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, 1032bc4ef71SPaul Walmsley PM_WKEN); 1043a7ec26bSKalle Jokiniemi /* Do a readback to assure write has been done */ 105c4d7e58fSPaul Walmsley omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN); 1063a7ec26bSKalle Jokiniemi 107c4d7e58fSPaul Walmsley while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) & 1082bc4ef71SPaul Walmsley OMAP3430_ST_IO_CHAIN_MASK)) { 1093a7ec26bSKalle Jokiniemi timeout++; 1103a7ec26bSKalle Jokiniemi if (timeout > 1000) { 111b02b9172SPaul Walmsley pr_err("Wake up daisy chain activation failed.\n"); 1123a7ec26bSKalle Jokiniemi return; 1133a7ec26bSKalle Jokiniemi } 114c4d7e58fSPaul Walmsley omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, 1150b96a3a3SKevin Hilman WKUP_MOD, PM_WKEN); 1163a7ec26bSKalle Jokiniemi } 1173a7ec26bSKalle Jokiniemi } 1183a7ec26bSKalle Jokiniemi 1193a7ec26bSKalle Jokiniemi static void omap3_disable_io_chain(void) 1203a7ec26bSKalle Jokiniemi { 121c4d7e58fSPaul Walmsley omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, 1222bc4ef71SPaul Walmsley PM_WKEN); 1233a7ec26bSKalle Jokiniemi } 1243a7ec26bSKalle Jokiniemi 1252f5939c3SRajendra Nayak static void omap3_core_save_context(void) 1262f5939c3SRajendra Nayak { 127596efe47SPaul Walmsley omap3_ctrl_save_padconf(); 128dccaad89STero Kristo 129dccaad89STero Kristo /* 130dccaad89STero Kristo * Force write last pad into memory, as this can fail in some 13183521291SJean Pihet * cases according to errata 1.157, 1.185 132dccaad89STero Kristo */ 133dccaad89STero Kristo omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), 134dccaad89STero Kristo OMAP343X_CONTROL_MEM_WKUP + 0x2a0); 135dccaad89STero Kristo 1362f5939c3SRajendra Nayak /* Save the Interrupt controller context */ 1372f5939c3SRajendra Nayak omap_intc_save_context(); 1382f5939c3SRajendra Nayak /* Save the GPMC context */ 1392f5939c3SRajendra Nayak omap3_gpmc_save_context(); 1402f5939c3SRajendra Nayak /* Save the system control module context, padconf already save above*/ 1412f5939c3SRajendra Nayak omap3_control_save_context(); 142f2d11858STero Kristo omap_dma_global_context_save(); 1432f5939c3SRajendra Nayak } 1442f5939c3SRajendra Nayak 1452f5939c3SRajendra Nayak static void omap3_core_restore_context(void) 1462f5939c3SRajendra Nayak { 1472f5939c3SRajendra Nayak /* Restore the control module context, padconf restored by h/w */ 1482f5939c3SRajendra Nayak omap3_control_restore_context(); 1492f5939c3SRajendra Nayak /* Restore the GPMC context */ 1502f5939c3SRajendra Nayak omap3_gpmc_restore_context(); 1512f5939c3SRajendra Nayak /* Restore the interrupt controller context */ 1522f5939c3SRajendra Nayak omap_intc_restore_context(); 153f2d11858STero Kristo omap_dma_global_context_restore(); 1542f5939c3SRajendra Nayak } 1552f5939c3SRajendra Nayak 1569d97140bSTero Kristo /* 1579d97140bSTero Kristo * FIXME: This function should be called before entering off-mode after 1589d97140bSTero Kristo * OMAP3 secure services have been accessed. Currently it is only called 1599d97140bSTero Kristo * once during boot sequence, but this works as we are not using secure 1609d97140bSTero Kristo * services. 1619d97140bSTero Kristo */ 162617fcc98SKevin Hilman static void omap3_save_secure_ram_context(void) 16327d59a4aSTero Kristo { 16427d59a4aSTero Kristo u32 ret; 165617fcc98SKevin Hilman int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 16627d59a4aSTero Kristo 16727d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 16827d59a4aSTero Kristo /* 16927d59a4aSTero Kristo * MPU next state must be set to POWER_ON temporarily, 17027d59a4aSTero Kristo * otherwise the WFI executed inside the ROM code 17127d59a4aSTero Kristo * will hang the system. 17227d59a4aSTero Kristo */ 17327d59a4aSTero Kristo pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); 17427d59a4aSTero Kristo ret = _omap_save_secure_sram((u32 *) 17527d59a4aSTero Kristo __pa(omap3_secure_ram_storage)); 176617fcc98SKevin Hilman pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state); 17727d59a4aSTero Kristo /* Following is for error tracking, it should not happen */ 17827d59a4aSTero Kristo if (ret) { 17927d59a4aSTero Kristo printk(KERN_ERR "save_secure_sram() returns %08x\n", 18027d59a4aSTero Kristo ret); 18127d59a4aSTero Kristo while (1) 18227d59a4aSTero Kristo ; 18327d59a4aSTero Kristo } 18427d59a4aSTero Kristo } 18527d59a4aSTero Kristo } 18627d59a4aSTero Kristo 18777da2d91SJon Hunter /* 18877da2d91SJon Hunter * PRCM Interrupt Handler Helper Function 18977da2d91SJon Hunter * 19077da2d91SJon Hunter * The purpose of this function is to clear any wake-up events latched 19177da2d91SJon Hunter * in the PRCM PM_WKST_x registers. It is possible that a wake-up event 19277da2d91SJon Hunter * may occur whilst attempting to clear a PM_WKST_x register and thus 19377da2d91SJon Hunter * set another bit in this register. A while loop is used to ensure 19477da2d91SJon Hunter * that any peripheral wake-up events occurring while attempting to 19577da2d91SJon Hunter * clear the PM_WKST_x are detected and cleared. 19677da2d91SJon Hunter */ 1978cb0ac99SPaul Walmsley static int prcm_clear_mod_irqs(s16 module, u8 regs) 19877da2d91SJon Hunter { 19971a80775SVikram Pandita u32 wkst, fclk, iclk, clken; 20077da2d91SJon Hunter u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; 20177da2d91SJon Hunter u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; 20277da2d91SJon Hunter u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; 2035d805978SPaul Walmsley u16 grpsel_off = (regs == 3) ? 2045d805978SPaul Walmsley OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; 2058cb0ac99SPaul Walmsley int c = 0; 20677da2d91SJon Hunter 207c4d7e58fSPaul Walmsley wkst = omap2_prm_read_mod_reg(module, wkst_off); 208c4d7e58fSPaul Walmsley wkst &= omap2_prm_read_mod_reg(module, grpsel_off); 20977da2d91SJon Hunter if (wkst) { 210c4d7e58fSPaul Walmsley iclk = omap2_cm_read_mod_reg(module, iclk_off); 211c4d7e58fSPaul Walmsley fclk = omap2_cm_read_mod_reg(module, fclk_off); 21277da2d91SJon Hunter while (wkst) { 21371a80775SVikram Pandita clken = wkst; 214c4d7e58fSPaul Walmsley omap2_cm_set_mod_reg_bits(clken, module, iclk_off); 21571a80775SVikram Pandita /* 21671a80775SVikram Pandita * For USBHOST, we don't know whether HOST1 or 21771a80775SVikram Pandita * HOST2 woke us up, so enable both f-clocks 21871a80775SVikram Pandita */ 21971a80775SVikram Pandita if (module == OMAP3430ES2_USBHOST_MOD) 22071a80775SVikram Pandita clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; 221c4d7e58fSPaul Walmsley omap2_cm_set_mod_reg_bits(clken, module, fclk_off); 222c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(wkst, module, wkst_off); 223c4d7e58fSPaul Walmsley wkst = omap2_prm_read_mod_reg(module, wkst_off); 2248cb0ac99SPaul Walmsley c++; 22577da2d91SJon Hunter } 226c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(iclk, module, iclk_off); 227c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(fclk, module, fclk_off); 22877da2d91SJon Hunter } 2298cb0ac99SPaul Walmsley 2308cb0ac99SPaul Walmsley return c; 2318cb0ac99SPaul Walmsley } 2328cb0ac99SPaul Walmsley 2338cb0ac99SPaul Walmsley static int _prcm_int_handle_wakeup(void) 2348cb0ac99SPaul Walmsley { 2358cb0ac99SPaul Walmsley int c; 2368cb0ac99SPaul Walmsley 2378cb0ac99SPaul Walmsley c = prcm_clear_mod_irqs(WKUP_MOD, 1); 2388cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(CORE_MOD, 1); 2398cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1); 2408cb0ac99SPaul Walmsley if (omap_rev() > OMAP3430_REV_ES1_0) { 2418cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(CORE_MOD, 3); 2428cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1); 2438cb0ac99SPaul Walmsley } 2448cb0ac99SPaul Walmsley 2458cb0ac99SPaul Walmsley return c; 24677da2d91SJon Hunter } 24777da2d91SJon Hunter 24877da2d91SJon Hunter /* 24977da2d91SJon Hunter * PRCM Interrupt Handler 25077da2d91SJon Hunter * 25177da2d91SJon Hunter * The PRM_IRQSTATUS_MPU register indicates if there are any pending 25277da2d91SJon Hunter * interrupts from the PRCM for the MPU. These bits must be cleared in 25377da2d91SJon Hunter * order to clear the PRCM interrupt. The PRCM interrupt handler is 25477da2d91SJon Hunter * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear 25577da2d91SJon Hunter * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU 25677da2d91SJon Hunter * register indicates that a wake-up event is pending for the MPU and 25777da2d91SJon Hunter * this bit can only be cleared if the all the wake-up events latched 25877da2d91SJon Hunter * in the various PM_WKST_x registers have been cleared. The interrupt 25977da2d91SJon Hunter * handler is implemented using a do-while loop so that if a wake-up 26077da2d91SJon Hunter * event occurred during the processing of the prcm interrupt handler 26177da2d91SJon Hunter * (setting a bit in the corresponding PM_WKST_x register and thus 26277da2d91SJon Hunter * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register) 26377da2d91SJon Hunter * this would be handled. 26477da2d91SJon Hunter */ 2658bd22949SKevin Hilman static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) 2668bd22949SKevin Hilman { 267d6290a3eSKevin Hilman u32 irqenable_mpu, irqstatus_mpu; 2688cb0ac99SPaul Walmsley int c = 0; 2698bd22949SKevin Hilman 270c4d7e58fSPaul Walmsley irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD, 271d6290a3eSKevin Hilman OMAP3_PRM_IRQENABLE_MPU_OFFSET); 272c4d7e58fSPaul Walmsley irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD, 2738bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 274d6290a3eSKevin Hilman irqstatus_mpu &= irqenable_mpu; 2758cb0ac99SPaul Walmsley 276d6290a3eSKevin Hilman do { 2772bc4ef71SPaul Walmsley if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK | 2782bc4ef71SPaul Walmsley OMAP3430_IO_ST_MASK)) { 2798cb0ac99SPaul Walmsley c = _prcm_int_handle_wakeup(); 2808cb0ac99SPaul Walmsley 2818cb0ac99SPaul Walmsley /* 2828cb0ac99SPaul Walmsley * Is the MPU PRCM interrupt handler racing with the 2838cb0ac99SPaul Walmsley * IVA2 PRCM interrupt handler ? 2848cb0ac99SPaul Walmsley */ 2858cb0ac99SPaul Walmsley WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup " 2868cb0ac99SPaul Walmsley "but no wakeup sources are marked\n"); 2878cb0ac99SPaul Walmsley } else { 2888cb0ac99SPaul Walmsley /* XXX we need to expand our PRCM interrupt handler */ 2898cb0ac99SPaul Walmsley WARN(1, "prcm: WARNING: PRCM interrupt received, but " 2908cb0ac99SPaul Walmsley "no code to handle it (%08x)\n", irqstatus_mpu); 2918cb0ac99SPaul Walmsley } 2928cb0ac99SPaul Walmsley 293c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD, 2948bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 2958bd22949SKevin Hilman 296c4d7e58fSPaul Walmsley irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD, 297d6290a3eSKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 298d6290a3eSKevin Hilman irqstatus_mpu &= irqenable_mpu; 299d6290a3eSKevin Hilman 300d6290a3eSKevin Hilman } while (irqstatus_mpu); 3018bd22949SKevin Hilman 3028bd22949SKevin Hilman return IRQ_HANDLED; 3038bd22949SKevin Hilman } 3048bd22949SKevin Hilman 305cbe26349SRussell King static void omap34xx_save_context(u32 *save) 306cbe26349SRussell King { 307cbe26349SRussell King u32 val; 308cbe26349SRussell King 309cbe26349SRussell King /* Read Auxiliary Control Register */ 310cbe26349SRussell King asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val)); 311cbe26349SRussell King *save++ = 1; 312cbe26349SRussell King *save++ = val; 313cbe26349SRussell King 314cbe26349SRussell King /* Read L2 AUX ctrl register */ 315cbe26349SRussell King asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); 316cbe26349SRussell King *save++ = 1; 317cbe26349SRussell King *save++ = val; 318cbe26349SRussell King } 319cbe26349SRussell King 32029cb3cd2SRussell King static int omap34xx_do_sram_idle(unsigned long save_state) 32157f277b0SRajendra Nayak { 322cbe26349SRussell King omap34xx_cpu_suspend(save_state); 32329cb3cd2SRussell King return 0; 32457f277b0SRajendra Nayak } 32557f277b0SRajendra Nayak 32699e6a4d2SRajendra Nayak void omap_sram_idle(void) 3278bd22949SKevin Hilman { 3288bd22949SKevin Hilman /* Variable to tell what needs to be saved and restored 3298bd22949SKevin Hilman * in omap_sram_idle*/ 3308bd22949SKevin Hilman /* save_state = 0 => Nothing to save and restored */ 3318bd22949SKevin Hilman /* save_state = 1 => Only L1 and logic lost */ 3328bd22949SKevin Hilman /* save_state = 2 => Only L2 lost */ 3338bd22949SKevin Hilman /* save_state = 3 => L1, L2 and logic lost */ 334fa3c2a4fSRajendra Nayak int save_state = 0; 335fa3c2a4fSRajendra Nayak int mpu_next_state = PWRDM_POWER_ON; 336fa3c2a4fSRajendra Nayak int per_next_state = PWRDM_POWER_ON; 337fa3c2a4fSRajendra Nayak int core_next_state = PWRDM_POWER_ON; 33872e06d08SPaul Walmsley int per_going_off; 3392f5939c3SRajendra Nayak int core_prev_state, per_prev_state; 34013a6fe0fSTero Kristo u32 sdrc_pwr = 0; 3418bd22949SKevin Hilman 342fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(mpu_pwrdm); 343fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(neon_pwrdm); 344fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(core_pwrdm); 345fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(per_pwrdm); 346fa3c2a4fSRajendra Nayak 3478bd22949SKevin Hilman mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 3488bd22949SKevin Hilman switch (mpu_next_state) { 349fa3c2a4fSRajendra Nayak case PWRDM_POWER_ON: 3508bd22949SKevin Hilman case PWRDM_POWER_RET: 3518bd22949SKevin Hilman /* No need to save context */ 3528bd22949SKevin Hilman save_state = 0; 3538bd22949SKevin Hilman break; 35461255ab9SRajendra Nayak case PWRDM_POWER_OFF: 35561255ab9SRajendra Nayak save_state = 3; 35661255ab9SRajendra Nayak break; 3578bd22949SKevin Hilman default: 3588bd22949SKevin Hilman /* Invalid state */ 3598bd22949SKevin Hilman printk(KERN_ERR "Invalid mpu state in sram_idle\n"); 3608bd22949SKevin Hilman return; 3618bd22949SKevin Hilman } 362fe617af7SPeter 'p2' De Schrijver 363fa3c2a4fSRajendra Nayak /* NEON control */ 364fa3c2a4fSRajendra Nayak if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) 3657139178eSJouni Hogander pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); 366fa3c2a4fSRajendra Nayak 36740742fa8SMike Chan /* Enable IO-PAD and IO-CHAIN wakeups */ 368fa3c2a4fSRajendra Nayak per_next_state = pwrdm_read_next_pwrst(per_pwrdm); 369ecf157d0STero Kristo core_next_state = pwrdm_read_next_pwrst(core_pwrdm); 370d5c47d7eSKevin Hilman if (omap3_has_io_wakeup() && 371ad0c63f1Sstanley.miao (per_next_state < PWRDM_POWER_ON || 372ad0c63f1Sstanley.miao core_next_state < PWRDM_POWER_ON)) { 373c4d7e58fSPaul Walmsley omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); 374b02b9172SPaul Walmsley if (omap3_has_io_chain_ctrl()) 37540742fa8SMike Chan omap3_enable_io_chain(); 37640742fa8SMike Chan } 37740742fa8SMike Chan 3780d8e2d0dSPaul Walmsley /* Block console output in case it is on one of the OMAP UARTs */ 379e83df17fSKevin Hilman if (!is_suspending()) 3800d8e2d0dSPaul Walmsley if (per_next_state < PWRDM_POWER_ON || 3810d8e2d0dSPaul Walmsley core_next_state < PWRDM_POWER_ON) 382ac751efaSTorben Hohn if (!console_trylock()) 3830d8e2d0dSPaul Walmsley goto console_still_active; 3840d8e2d0dSPaul Walmsley 385ff2f8e5fSCharulatha V pwrdm_pre_transition(); 386ff2f8e5fSCharulatha V 38740742fa8SMike Chan /* PER */ 3882f5939c3SRajendra Nayak if (per_next_state < PWRDM_POWER_ON) { 38972e06d08SPaul Walmsley per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0; 3904af4016cSKevin Hilman omap_uart_prepare_idle(2); 391cd4f1faeSGovindraj.R omap_uart_prepare_idle(3); 39272e06d08SPaul Walmsley omap2_gpio_prepare_for_idle(per_going_off); 393e7410cf7SKevin Hilman if (per_next_state == PWRDM_POWER_OFF) 3942f5939c3SRajendra Nayak omap3_per_save_context(); 3952f5939c3SRajendra Nayak } 396c16c3f67STero Kristo 397658ce97eSKevin Hilman /* CORE */ 398658ce97eSKevin Hilman if (core_next_state < PWRDM_POWER_ON) { 399658ce97eSKevin Hilman omap_uart_prepare_idle(0); 400658ce97eSKevin Hilman omap_uart_prepare_idle(1); 4012f5939c3SRajendra Nayak if (core_next_state == PWRDM_POWER_OFF) { 4022f5939c3SRajendra Nayak omap3_core_save_context(); 403f0611a5cSPaul Walmsley omap3_cm_save_context(); 4042f5939c3SRajendra Nayak } 405fa3c2a4fSRajendra Nayak } 40640742fa8SMike Chan 407f18cc2ffSTero Kristo omap3_intc_prepare_idle(); 4088bd22949SKevin Hilman 40961255ab9SRajendra Nayak /* 410f265dc4cSRajendra Nayak * On EMU/HS devices ROM code restores a SRDC value 411f265dc4cSRajendra Nayak * from scratchpad which has automatic self refresh on timeout 41283521291SJean Pihet * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443. 413f265dc4cSRajendra Nayak * Hence store/restore the SDRC_POWER register here. 41413a6fe0fSTero Kristo */ 41513a6fe0fSTero Kristo if (omap_rev() >= OMAP3430_REV_ES3_0 && 41613a6fe0fSTero Kristo omap_type() != OMAP2_DEVICE_TYPE_GP && 417f265dc4cSRajendra Nayak core_next_state == PWRDM_POWER_OFF) 41813a6fe0fSTero Kristo sdrc_pwr = sdrc_read_reg(SDRC_POWER); 41913a6fe0fSTero Kristo 42013a6fe0fSTero Kristo /* 421076f2cc4SRussell King * omap3_arm_context is the location where some ARM context 422076f2cc4SRussell King * get saved. The rest is placed on the stack, and restored 423076f2cc4SRussell King * from there before resuming. 42461255ab9SRajendra Nayak */ 425cbe26349SRussell King if (save_state) 426cbe26349SRussell King omap34xx_save_context(omap3_arm_context); 427076f2cc4SRussell King if (save_state == 1 || save_state == 3) 4282c74a0ceSRussell King cpu_suspend(save_state, omap34xx_do_sram_idle); 429076f2cc4SRussell King else 430076f2cc4SRussell King omap34xx_do_sram_idle(save_state); 4318bd22949SKevin Hilman 432f265dc4cSRajendra Nayak /* Restore normal SDRC POWER settings */ 43313a6fe0fSTero Kristo if (omap_rev() >= OMAP3430_REV_ES3_0 && 43413a6fe0fSTero Kristo omap_type() != OMAP2_DEVICE_TYPE_GP && 43513a6fe0fSTero Kristo core_next_state == PWRDM_POWER_OFF) 43613a6fe0fSTero Kristo sdrc_write_reg(sdrc_pwr, SDRC_POWER); 43713a6fe0fSTero Kristo 438658ce97eSKevin Hilman /* CORE */ 439fa3c2a4fSRajendra Nayak if (core_next_state < PWRDM_POWER_ON) { 4402f5939c3SRajendra Nayak core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); 4412f5939c3SRajendra Nayak if (core_prev_state == PWRDM_POWER_OFF) { 4422f5939c3SRajendra Nayak omap3_core_restore_context(); 443f0611a5cSPaul Walmsley omap3_cm_restore_context(); 4442f5939c3SRajendra Nayak omap3_sram_restore_context(); 4458a917d2fSKalle Jokiniemi omap2_sms_restore_context(); 4462f5939c3SRajendra Nayak } 447658ce97eSKevin Hilman omap_uart_resume_idle(0); 448658ce97eSKevin Hilman omap_uart_resume_idle(1); 449658ce97eSKevin Hilman if (core_next_state == PWRDM_POWER_OFF) 450c4d7e58fSPaul Walmsley omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, 451658ce97eSKevin Hilman OMAP3430_GR_MOD, 452658ce97eSKevin Hilman OMAP3_PRM_VOLTCTRL_OFFSET); 453658ce97eSKevin Hilman } 454f18cc2ffSTero Kristo omap3_intc_resume_idle(); 455658ce97eSKevin Hilman 456ff2f8e5fSCharulatha V pwrdm_post_transition(); 457ff2f8e5fSCharulatha V 458658ce97eSKevin Hilman /* PER */ 4592f5939c3SRajendra Nayak if (per_next_state < PWRDM_POWER_ON) { 460658ce97eSKevin Hilman per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); 46143ffcd9aSKevin Hilman omap2_gpio_resume_after_idle(); 46243ffcd9aSKevin Hilman if (per_prev_state == PWRDM_POWER_OFF) 4632f5939c3SRajendra Nayak omap3_per_restore_context(); 464ecf157d0STero Kristo omap_uart_resume_idle(2); 465cd4f1faeSGovindraj.R omap_uart_resume_idle(3); 466fa3c2a4fSRajendra Nayak } 467fe617af7SPeter 'p2' De Schrijver 468e83df17fSKevin Hilman if (!is_suspending()) 469ac751efaSTorben Hohn console_unlock(); 4700d8e2d0dSPaul Walmsley 4710d8e2d0dSPaul Walmsley console_still_active: 4723a7ec26bSKalle Jokiniemi /* Disable IO-PAD and IO-CHAIN wakeup */ 47358a5559eSKevin Hilman if (omap3_has_io_wakeup() && 47458a5559eSKevin Hilman (per_next_state < PWRDM_POWER_ON || 47558a5559eSKevin Hilman core_next_state < PWRDM_POWER_ON)) { 476c4d7e58fSPaul Walmsley omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, 477c4d7e58fSPaul Walmsley PM_WKEN); 478b02b9172SPaul Walmsley if (omap3_has_io_chain_ctrl()) 4793a7ec26bSKalle Jokiniemi omap3_disable_io_chain(); 4803a7ec26bSKalle Jokiniemi } 481658ce97eSKevin Hilman 4825cd1937bSRajendra Nayak clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); 4838bd22949SKevin Hilman } 4848bd22949SKevin Hilman 48520b01669SRajendra Nayak int omap3_can_sleep(void) 4868bd22949SKevin Hilman { 4874af4016cSKevin Hilman if (!omap_uart_can_sleep()) 4884af4016cSKevin Hilman return 0; 4898bd22949SKevin Hilman return 1; 4908bd22949SKevin Hilman } 4918bd22949SKevin Hilman 4928bd22949SKevin Hilman static void omap3_pm_idle(void) 4938bd22949SKevin Hilman { 4948bd22949SKevin Hilman local_irq_disable(); 4958bd22949SKevin Hilman local_fiq_disable(); 4968bd22949SKevin Hilman 4978bd22949SKevin Hilman if (!omap3_can_sleep()) 4988bd22949SKevin Hilman goto out; 4998bd22949SKevin Hilman 500cf22854cSTero Kristo if (omap_irq_pending() || need_resched()) 5018bd22949SKevin Hilman goto out; 5028bd22949SKevin Hilman 5035e7c58dcSJean Pihet trace_power_start(POWER_CSTATE, 1, smp_processor_id()); 5045e7c58dcSJean Pihet trace_cpu_idle(1, smp_processor_id()); 5055e7c58dcSJean Pihet 5068bd22949SKevin Hilman omap_sram_idle(); 5078bd22949SKevin Hilman 5085e7c58dcSJean Pihet trace_power_end(smp_processor_id()); 5095e7c58dcSJean Pihet trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); 5105e7c58dcSJean Pihet 5118bd22949SKevin Hilman out: 5128bd22949SKevin Hilman local_fiq_enable(); 5138bd22949SKevin Hilman local_irq_enable(); 5148bd22949SKevin Hilman } 5158bd22949SKevin Hilman 51610f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 5178bd22949SKevin Hilman static int omap3_pm_suspend(void) 5188bd22949SKevin Hilman { 5198bd22949SKevin Hilman struct power_state *pwrst; 5208bd22949SKevin Hilman int state, ret = 0; 5218bd22949SKevin Hilman 5228bd22949SKevin Hilman /* Read current next_pwrsts */ 5238bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) 5248bd22949SKevin Hilman pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 5258bd22949SKevin Hilman /* Set ones wanted by suspend */ 5268bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 527eb6a2c75SSantosh Shilimkar if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) 5288bd22949SKevin Hilman goto restore; 5298bd22949SKevin Hilman if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) 5308bd22949SKevin Hilman goto restore; 5318bd22949SKevin Hilman } 5328bd22949SKevin Hilman 5334af4016cSKevin Hilman omap_uart_prepare_suspend(); 5342bbe3af3STero Kristo omap3_intc_suspend(); 5352bbe3af3STero Kristo 5368bd22949SKevin Hilman omap_sram_idle(); 5378bd22949SKevin Hilman 5388bd22949SKevin Hilman restore: 5398bd22949SKevin Hilman /* Restore next_pwrsts */ 5408bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 5418bd22949SKevin Hilman state = pwrdm_read_prev_pwrst(pwrst->pwrdm); 5428bd22949SKevin Hilman if (state > pwrst->next_state) { 5438bd22949SKevin Hilman printk(KERN_INFO "Powerdomain (%s) didn't enter " 5448bd22949SKevin Hilman "target state %d\n", 5458bd22949SKevin Hilman pwrst->pwrdm->name, pwrst->next_state); 5468bd22949SKevin Hilman ret = -1; 5478bd22949SKevin Hilman } 548eb6a2c75SSantosh Shilimkar omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); 5498bd22949SKevin Hilman } 5508bd22949SKevin Hilman if (ret) 5518bd22949SKevin Hilman printk(KERN_ERR "Could not enter target state in pm_suspend\n"); 5528bd22949SKevin Hilman else 5538bd22949SKevin Hilman printk(KERN_INFO "Successfully put all powerdomains " 5548bd22949SKevin Hilman "to target state\n"); 5558bd22949SKevin Hilman 5568bd22949SKevin Hilman return ret; 5578bd22949SKevin Hilman } 5588bd22949SKevin Hilman 5592466211eSTero Kristo static int omap3_pm_enter(suspend_state_t unused) 5608bd22949SKevin Hilman { 5618bd22949SKevin Hilman int ret = 0; 5628bd22949SKevin Hilman 5632466211eSTero Kristo switch (suspend_state) { 5648bd22949SKevin Hilman case PM_SUSPEND_STANDBY: 5658bd22949SKevin Hilman case PM_SUSPEND_MEM: 5668bd22949SKevin Hilman ret = omap3_pm_suspend(); 5678bd22949SKevin Hilman break; 5688bd22949SKevin Hilman default: 5698bd22949SKevin Hilman ret = -EINVAL; 5708bd22949SKevin Hilman } 5718bd22949SKevin Hilman 5728bd22949SKevin Hilman return ret; 5738bd22949SKevin Hilman } 5748bd22949SKevin Hilman 5752466211eSTero Kristo /* Hooks to enable / disable UART interrupts during suspend */ 5762466211eSTero Kristo static int omap3_pm_begin(suspend_state_t state) 5772466211eSTero Kristo { 578c166381dSJean Pihet disable_hlt(); 5792466211eSTero Kristo suspend_state = state; 5802466211eSTero Kristo omap_uart_enable_irqs(0); 5812466211eSTero Kristo return 0; 5822466211eSTero Kristo } 5832466211eSTero Kristo 5842466211eSTero Kristo static void omap3_pm_end(void) 5852466211eSTero Kristo { 5862466211eSTero Kristo suspend_state = PM_SUSPEND_ON; 5872466211eSTero Kristo omap_uart_enable_irqs(1); 588c166381dSJean Pihet enable_hlt(); 5892466211eSTero Kristo return; 5902466211eSTero Kristo } 5912466211eSTero Kristo 5922f55ac07SLionel Debroux static const struct platform_suspend_ops omap_pm_ops = { 5932466211eSTero Kristo .begin = omap3_pm_begin, 5942466211eSTero Kristo .end = omap3_pm_end, 5958bd22949SKevin Hilman .enter = omap3_pm_enter, 5968bd22949SKevin Hilman .valid = suspend_valid_only_mem, 5978bd22949SKevin Hilman }; 59810f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 5998bd22949SKevin Hilman 6001155e426SKevin Hilman 6011155e426SKevin Hilman /** 6021155e426SKevin Hilman * omap3_iva_idle(): ensure IVA is in idle so it can be put into 6031155e426SKevin Hilman * retention 6041155e426SKevin Hilman * 6051155e426SKevin Hilman * In cases where IVA2 is activated by bootcode, it may prevent 6061155e426SKevin Hilman * full-chip retention or off-mode because it is not idle. This 6071155e426SKevin Hilman * function forces the IVA2 into idle state so it can go 6081155e426SKevin Hilman * into retention/off and thus allow full-chip retention/off. 6091155e426SKevin Hilman * 6101155e426SKevin Hilman **/ 6111155e426SKevin Hilman static void __init omap3_iva_idle(void) 6121155e426SKevin Hilman { 6131155e426SKevin Hilman /* ensure IVA2 clock is disabled */ 614c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 6151155e426SKevin Hilman 6161155e426SKevin Hilman /* if no clock activity, nothing else to do */ 617c4d7e58fSPaul Walmsley if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & 6181155e426SKevin Hilman OMAP3430_CLKACTIVITY_IVA2_MASK)) 6191155e426SKevin Hilman return; 6201155e426SKevin Hilman 6211155e426SKevin Hilman /* Reset IVA2 */ 622c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | 6232bc4ef71SPaul Walmsley OMAP3430_RST2_IVA2_MASK | 6242bc4ef71SPaul Walmsley OMAP3430_RST3_IVA2_MASK, 62537903009SAbhijit Pagare OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 6261155e426SKevin Hilman 6271155e426SKevin Hilman /* Enable IVA2 clock */ 628c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, 6291155e426SKevin Hilman OMAP3430_IVA2_MOD, CM_FCLKEN); 6301155e426SKevin Hilman 6311155e426SKevin Hilman /* Set IVA2 boot mode to 'idle' */ 6321155e426SKevin Hilman omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, 6331155e426SKevin Hilman OMAP343X_CONTROL_IVA2_BOOTMOD); 6341155e426SKevin Hilman 6351155e426SKevin Hilman /* Un-reset IVA2 */ 636c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 6371155e426SKevin Hilman 6381155e426SKevin Hilman /* Disable IVA2 clock */ 639c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 6401155e426SKevin Hilman 6411155e426SKevin Hilman /* Reset IVA2 */ 642c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | 6432bc4ef71SPaul Walmsley OMAP3430_RST2_IVA2_MASK | 6442bc4ef71SPaul Walmsley OMAP3430_RST3_IVA2_MASK, 64537903009SAbhijit Pagare OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 6461155e426SKevin Hilman } 6471155e426SKevin Hilman 6488111b221SKevin Hilman static void __init omap3_d2d_idle(void) 6498bd22949SKevin Hilman { 6508111b221SKevin Hilman u16 mask, padconf; 6518111b221SKevin Hilman 6528111b221SKevin Hilman /* In a stand alone OMAP3430 where there is not a stacked 6538111b221SKevin Hilman * modem for the D2D Idle Ack and D2D MStandby must be pulled 6548111b221SKevin Hilman * high. S CONTROL_PADCONF_SAD2D_IDLEACK and 6558111b221SKevin Hilman * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ 6568111b221SKevin Hilman mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ 6578111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); 6588111b221SKevin Hilman padconf |= mask; 6598111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); 6608111b221SKevin Hilman 6618111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); 6628111b221SKevin Hilman padconf |= mask; 6638111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 6648111b221SKevin Hilman 6658bd22949SKevin Hilman /* reset modem */ 666c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | 6672bc4ef71SPaul Walmsley OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, 66837903009SAbhijit Pagare CORE_MOD, OMAP2_RM_RSTCTRL); 669c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); 6708111b221SKevin Hilman } 6718bd22949SKevin Hilman 6728111b221SKevin Hilman static void __init prcm_setup_regs(void) 6738111b221SKevin Hilman { 674e5863689SGovindraj.R u32 omap3630_en_uart4_mask = cpu_is_omap3630() ? 675e5863689SGovindraj.R OMAP3630_EN_UART4_MASK : 0; 676e5863689SGovindraj.R u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ? 677e5863689SGovindraj.R OMAP3630_GRPSEL_UART4_MASK : 0; 678e5863689SGovindraj.R 6794ef70c06SPaul Walmsley /* XXX This should be handled by hwmod code or SCM init code */ 6802fd0f75cSPaul Walmsley omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); 681b296c811STero Kristo 6828bd22949SKevin Hilman /* 6838bd22949SKevin Hilman * Enable control of expternal oscillator through 6848bd22949SKevin Hilman * sys_clkreq. In the long run clock framework should 6858bd22949SKevin Hilman * take care of this. 6868bd22949SKevin Hilman */ 687c4d7e58fSPaul Walmsley omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 6888bd22949SKevin Hilman 1 << OMAP_AUTOEXTCLKMODE_SHIFT, 6898bd22949SKevin Hilman OMAP3430_GR_MOD, 6908bd22949SKevin Hilman OMAP3_PRM_CLKSRC_CTRL_OFFSET); 6918bd22949SKevin Hilman 6928bd22949SKevin Hilman /* setup wakup source */ 693c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | 6942fd0f75cSPaul Walmsley OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, 6958bd22949SKevin Hilman WKUP_MOD, PM_WKEN); 6968bd22949SKevin Hilman /* No need to write EN_IO, that is always enabled */ 697c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | 698275f675cSPaul Walmsley OMAP3430_GRPSEL_GPT1_MASK | 699275f675cSPaul Walmsley OMAP3430_GRPSEL_GPT12_MASK, 7008bd22949SKevin Hilman WKUP_MOD, OMAP3430_PM_MPUGRPSEL); 7018bd22949SKevin Hilman /* For some reason IO doesn't generate wakeup event even if 7028bd22949SKevin Hilman * it is selected to mpu wakeup goup */ 703c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK, 7048bd22949SKevin Hilman OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); 7051155e426SKevin Hilman 706b92c5721SSubramani Venkatesh /* Enable PM_WKEN to support DSS LPR */ 707c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, 708b92c5721SSubramani Venkatesh OMAP3430_DSS_MOD, PM_WKEN); 709b92c5721SSubramani Venkatesh 710b427f92fSKevin Hilman /* Enable wakeups in PER */ 711c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(omap3630_en_uart4_mask | 712e5863689SGovindraj.R OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | 7132fd0f75cSPaul Walmsley OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | 7142fd0f75cSPaul Walmsley OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | 7152fd0f75cSPaul Walmsley OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK | 7162fd0f75cSPaul Walmsley OMAP3430_EN_MCBSP4_MASK, 717b427f92fSKevin Hilman OMAP3430_PER_MOD, PM_WKEN); 718eb350f74SKevin Hilman /* and allow them to wake up MPU */ 719c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask | 720e5863689SGovindraj.R OMAP3430_GRPSEL_GPIO2_MASK | 721275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO3_MASK | 722275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO4_MASK | 723275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO5_MASK | 724275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO6_MASK | 725275f675cSPaul Walmsley OMAP3430_GRPSEL_UART3_MASK | 726275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP2_MASK | 727275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP3_MASK | 728275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP4_MASK, 729eb350f74SKevin Hilman OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); 730eb350f74SKevin Hilman 731d3fd3290SKevin Hilman /* Don't attach IVA interrupts */ 732c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 733c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 734c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 735c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); 736d3fd3290SKevin Hilman 737b1340d17SKevin Hilman /* Clear any pending 'reset' flags */ 738c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); 739c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); 740c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); 741c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); 742c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); 743c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); 744c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); 745b1340d17SKevin Hilman 746014c46dbSKevin Hilman /* Clear any pending PRCM interrupts */ 747c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 748014c46dbSKevin Hilman 7491155e426SKevin Hilman omap3_iva_idle(); 7508111b221SKevin Hilman omap3_d2d_idle(); 7518bd22949SKevin Hilman } 7528bd22949SKevin Hilman 753c40552bcSKevin Hilman void omap3_pm_off_mode_enable(int enable) 754c40552bcSKevin Hilman { 755c40552bcSKevin Hilman struct power_state *pwrst; 756c40552bcSKevin Hilman u32 state; 757c40552bcSKevin Hilman 758c40552bcSKevin Hilman if (enable) 759c40552bcSKevin Hilman state = PWRDM_POWER_OFF; 760c40552bcSKevin Hilman else 761c40552bcSKevin Hilman state = PWRDM_POWER_RET; 762c40552bcSKevin Hilman 763c40552bcSKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 764cc1b6028SEduardo Valentin if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) && 765cc1b6028SEduardo Valentin pwrst->pwrdm == core_pwrdm && 766cc1b6028SEduardo Valentin state == PWRDM_POWER_OFF) { 767cc1b6028SEduardo Valentin pwrst->next_state = PWRDM_POWER_RET; 768e16b41bfSRicardo Salveti de Araujo pr_warn("%s: Core OFF disabled due to errata i583\n", 769cc1b6028SEduardo Valentin __func__); 770cc1b6028SEduardo Valentin } else { 771c40552bcSKevin Hilman pwrst->next_state = state; 772cc1b6028SEduardo Valentin } 773cc1b6028SEduardo Valentin omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 774c40552bcSKevin Hilman } 775c40552bcSKevin Hilman } 776c40552bcSKevin Hilman 77768d4778cSTero Kristo int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) 77868d4778cSTero Kristo { 77968d4778cSTero Kristo struct power_state *pwrst; 78068d4778cSTero Kristo 78168d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 78268d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) 78368d4778cSTero Kristo return pwrst->next_state; 78468d4778cSTero Kristo } 78568d4778cSTero Kristo return -EINVAL; 78668d4778cSTero Kristo } 78768d4778cSTero Kristo 78868d4778cSTero Kristo int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) 78968d4778cSTero Kristo { 79068d4778cSTero Kristo struct power_state *pwrst; 79168d4778cSTero Kristo 79268d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 79368d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) { 79468d4778cSTero Kristo pwrst->next_state = state; 79568d4778cSTero Kristo return 0; 79668d4778cSTero Kristo } 79768d4778cSTero Kristo } 79868d4778cSTero Kristo return -EINVAL; 79968d4778cSTero Kristo } 80068d4778cSTero Kristo 801a23456e9SPeter 'p2' De Schrijver static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) 8028bd22949SKevin Hilman { 8038bd22949SKevin Hilman struct power_state *pwrst; 8048bd22949SKevin Hilman 8058bd22949SKevin Hilman if (!pwrdm->pwrsts) 8068bd22949SKevin Hilman return 0; 8078bd22949SKevin Hilman 808d3d381c6SMing Lei pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); 8098bd22949SKevin Hilman if (!pwrst) 8108bd22949SKevin Hilman return -ENOMEM; 8118bd22949SKevin Hilman pwrst->pwrdm = pwrdm; 8128bd22949SKevin Hilman pwrst->next_state = PWRDM_POWER_RET; 8138bd22949SKevin Hilman list_add(&pwrst->node, &pwrst_list); 8148bd22949SKevin Hilman 8158bd22949SKevin Hilman if (pwrdm_has_hdwr_sar(pwrdm)) 8168bd22949SKevin Hilman pwrdm_enable_hdwr_sar(pwrdm); 8178bd22949SKevin Hilman 818eb6a2c75SSantosh Shilimkar return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 8198bd22949SKevin Hilman } 8208bd22949SKevin Hilman 8218bd22949SKevin Hilman /* 8228bd22949SKevin Hilman * Enable hw supervised mode for all clockdomains if it's 8238bd22949SKevin Hilman * supported. Initiate sleep transition for other clockdomains, if 8248bd22949SKevin Hilman * they are not used 8258bd22949SKevin Hilman */ 826a23456e9SPeter 'p2' De Schrijver static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) 8278bd22949SKevin Hilman { 8288bd22949SKevin Hilman if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) 8295cd1937bSRajendra Nayak clkdm_allow_idle(clkdm); 8308bd22949SKevin Hilman else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && 8318bd22949SKevin Hilman atomic_read(&clkdm->usecount) == 0) 83268b921adSRajendra Nayak clkdm_sleep(clkdm); 8338bd22949SKevin Hilman return 0; 8348bd22949SKevin Hilman } 8358bd22949SKevin Hilman 83646e130d2SJean Pihet /* 83746e130d2SJean Pihet * Push functions to SRAM 83846e130d2SJean Pihet * 83946e130d2SJean Pihet * The minimum set of functions is pushed to SRAM for execution: 84046e130d2SJean Pihet * - omap3_do_wfi for erratum i581 WA, 84146e130d2SJean Pihet * - save_secure_ram_context for security extensions. 84246e130d2SJean Pihet */ 8433231fc88SRajendra Nayak void omap_push_sram_idle(void) 8443231fc88SRajendra Nayak { 84546e130d2SJean Pihet omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz); 84646e130d2SJean Pihet 84727d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) 84827d59a4aSTero Kristo _omap_save_secure_sram = omap_sram_push(save_secure_ram_context, 84927d59a4aSTero Kristo save_secure_ram_context_sz); 8503231fc88SRajendra Nayak } 8513231fc88SRajendra Nayak 8528cdfd834SNishanth Menon static void __init pm_errata_configure(void) 8538cdfd834SNishanth Menon { 854c4236d2eSPeter 'p2' De Schrijver if (cpu_is_omap3630()) { 855458e999eSNishanth Menon pm34xx_errata |= PM_RTA_ERRATUM_i608; 856c4236d2eSPeter 'p2' De Schrijver /* Enable the l2 cache toggling in sleep logic */ 857c4236d2eSPeter 'p2' De Schrijver enable_omap3630_toggle_l2_on_restore(); 858cc1b6028SEduardo Valentin if (omap_rev() < OMAP3630_REV_ES1_2) 859cc1b6028SEduardo Valentin pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583; 860c4236d2eSPeter 'p2' De Schrijver } 8618cdfd834SNishanth Menon } 8628cdfd834SNishanth Menon 8637cc515f7SKevin Hilman static int __init omap3_pm_init(void) 8648bd22949SKevin Hilman { 8658bd22949SKevin Hilman struct power_state *pwrst, *tmp; 86655ed9694SPaul Walmsley struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm; 8678bd22949SKevin Hilman int ret; 8688bd22949SKevin Hilman 8698bd22949SKevin Hilman if (!cpu_is_omap34xx()) 8708bd22949SKevin Hilman return -ENODEV; 8718bd22949SKevin Hilman 872b02b9172SPaul Walmsley if (!omap3_has_io_chain_ctrl()) 873b02b9172SPaul Walmsley pr_warning("PM: no software I/O chain control; some wakeups may be lost\n"); 874b02b9172SPaul Walmsley 8758cdfd834SNishanth Menon pm_errata_configure(); 8768cdfd834SNishanth Menon 8778bd22949SKevin Hilman /* XXX prcm_setup_regs needs to be before enabling hw 8788bd22949SKevin Hilman * supervised mode for powerdomains */ 8798bd22949SKevin Hilman prcm_setup_regs(); 8808bd22949SKevin Hilman 8818bd22949SKevin Hilman ret = request_irq(INT_34XX_PRCM_MPU_IRQ, 8828bd22949SKevin Hilman (irq_handler_t)prcm_interrupt_handler, 8838bd22949SKevin Hilman IRQF_DISABLED, "prcm", NULL); 8848bd22949SKevin Hilman if (ret) { 8858bd22949SKevin Hilman printk(KERN_ERR "request_irq failed to register for 0x%x\n", 8868bd22949SKevin Hilman INT_34XX_PRCM_MPU_IRQ); 8878bd22949SKevin Hilman goto err1; 8888bd22949SKevin Hilman } 8898bd22949SKevin Hilman 890a23456e9SPeter 'p2' De Schrijver ret = pwrdm_for_each(pwrdms_setup, NULL); 8918bd22949SKevin Hilman if (ret) { 8928bd22949SKevin Hilman printk(KERN_ERR "Failed to setup powerdomains\n"); 8938bd22949SKevin Hilman goto err2; 8948bd22949SKevin Hilman } 8958bd22949SKevin Hilman 896a23456e9SPeter 'p2' De Schrijver (void) clkdm_for_each(clkdms_setup, NULL); 8978bd22949SKevin Hilman 8988bd22949SKevin Hilman mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); 8998bd22949SKevin Hilman if (mpu_pwrdm == NULL) { 9008bd22949SKevin Hilman printk(KERN_ERR "Failed to get mpu_pwrdm\n"); 9018bd22949SKevin Hilman goto err2; 9028bd22949SKevin Hilman } 9038bd22949SKevin Hilman 904fa3c2a4fSRajendra Nayak neon_pwrdm = pwrdm_lookup("neon_pwrdm"); 905fa3c2a4fSRajendra Nayak per_pwrdm = pwrdm_lookup("per_pwrdm"); 906fa3c2a4fSRajendra Nayak core_pwrdm = pwrdm_lookup("core_pwrdm"); 907c16c3f67STero Kristo cam_pwrdm = pwrdm_lookup("cam_pwrdm"); 908fa3c2a4fSRajendra Nayak 90955ed9694SPaul Walmsley neon_clkdm = clkdm_lookup("neon_clkdm"); 91055ed9694SPaul Walmsley mpu_clkdm = clkdm_lookup("mpu_clkdm"); 91155ed9694SPaul Walmsley per_clkdm = clkdm_lookup("per_clkdm"); 91255ed9694SPaul Walmsley core_clkdm = clkdm_lookup("core_clkdm"); 91355ed9694SPaul Walmsley 91410f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 9158bd22949SKevin Hilman suspend_set_ops(&omap_pm_ops); 91610f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 9178bd22949SKevin Hilman 9188bd22949SKevin Hilman pm_idle = omap3_pm_idle; 9190343371eSKalle Jokiniemi omap3_idle_init(); 9208bd22949SKevin Hilman 921458e999eSNishanth Menon /* 922458e999eSNishanth Menon * RTA is disabled during initialization as per erratum i608 923458e999eSNishanth Menon * it is safer to disable RTA by the bootloader, but we would like 924458e999eSNishanth Menon * to be doubly sure here and prevent any mishaps. 925458e999eSNishanth Menon */ 926458e999eSNishanth Menon if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608)) 927458e999eSNishanth Menon omap3630_ctrl_disable_rta(); 928458e999eSNishanth Menon 92955ed9694SPaul Walmsley clkdm_add_wkdep(neon_clkdm, mpu_clkdm); 93027d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 93127d59a4aSTero Kristo omap3_secure_ram_storage = 93227d59a4aSTero Kristo kmalloc(0x803F, GFP_KERNEL); 93327d59a4aSTero Kristo if (!omap3_secure_ram_storage) 93427d59a4aSTero Kristo printk(KERN_ERR "Memory allocation failed when" 93527d59a4aSTero Kristo "allocating for secure sram context\n"); 93627d59a4aSTero Kristo 9379d97140bSTero Kristo local_irq_disable(); 9389d97140bSTero Kristo local_fiq_disable(); 9399d97140bSTero Kristo 9409d97140bSTero Kristo omap_dma_global_context_save(); 941617fcc98SKevin Hilman omap3_save_secure_ram_context(); 9429d97140bSTero Kristo omap_dma_global_context_restore(); 9439d97140bSTero Kristo 9449d97140bSTero Kristo local_irq_enable(); 9459d97140bSTero Kristo local_fiq_enable(); 9469d97140bSTero Kristo } 9479d97140bSTero Kristo 9489d97140bSTero Kristo omap3_save_scratchpad_contents(); 9498bd22949SKevin Hilman err1: 9508bd22949SKevin Hilman return ret; 9518bd22949SKevin Hilman err2: 9528bd22949SKevin Hilman free_irq(INT_34XX_PRCM_MPU_IRQ, NULL); 9538bd22949SKevin Hilman list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { 9548bd22949SKevin Hilman list_del(&pwrst->node); 9558bd22949SKevin Hilman kfree(pwrst); 9568bd22949SKevin Hilman } 9578bd22949SKevin Hilman return ret; 9588bd22949SKevin Hilman } 9598bd22949SKevin Hilman 9608bd22949SKevin Hilman late_initcall(omap3_pm_init); 961