18bd22949SKevin Hilman /* 28bd22949SKevin Hilman * OMAP3 Power Management Routines 38bd22949SKevin Hilman * 48bd22949SKevin Hilman * Copyright (C) 2006-2008 Nokia Corporation 58bd22949SKevin Hilman * Tony Lindgren <tony@atomide.com> 68bd22949SKevin Hilman * Jouni Hogander 78bd22949SKevin Hilman * 82f5939c3SRajendra Nayak * Copyright (C) 2007 Texas Instruments, Inc. 92f5939c3SRajendra Nayak * Rajendra Nayak <rnayak@ti.com> 102f5939c3SRajendra Nayak * 118bd22949SKevin Hilman * Copyright (C) 2005 Texas Instruments, Inc. 128bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 138bd22949SKevin Hilman * 148bd22949SKevin Hilman * Based on pm.c for omap1 158bd22949SKevin Hilman * 168bd22949SKevin Hilman * This program is free software; you can redistribute it and/or modify 178bd22949SKevin Hilman * it under the terms of the GNU General Public License version 2 as 188bd22949SKevin Hilman * published by the Free Software Foundation. 198bd22949SKevin Hilman */ 208bd22949SKevin Hilman 218bd22949SKevin Hilman #include <linux/pm.h> 228bd22949SKevin Hilman #include <linux/suspend.h> 238bd22949SKevin Hilman #include <linux/interrupt.h> 248bd22949SKevin Hilman #include <linux/module.h> 258bd22949SKevin Hilman #include <linux/list.h> 268bd22949SKevin Hilman #include <linux/err.h> 278bd22949SKevin Hilman #include <linux/gpio.h> 28c40552bcSKevin Hilman #include <linux/clk.h> 29dccaad89STero Kristo #include <linux/delay.h> 305a0e3ad6STejun Heo #include <linux/slab.h> 318bd22949SKevin Hilman 32ce491cf8STony Lindgren #include <plat/sram.h> 33ce491cf8STony Lindgren #include <plat/clockdomain.h> 34ce491cf8STony Lindgren #include <plat/powerdomain.h> 35ce491cf8STony Lindgren #include <plat/control.h> 36ce491cf8STony Lindgren #include <plat/serial.h> 3761255ab9SRajendra Nayak #include <plat/sdrc.h> 382f5939c3SRajendra Nayak #include <plat/prcm.h> 392f5939c3SRajendra Nayak #include <plat/gpmc.h> 40f2d11858STero Kristo #include <plat/dma.h> 41d7814e4dSKevin Hilman #include <plat/dmtimer.h> 428bd22949SKevin Hilman 4357f277b0SRajendra Nayak #include <asm/tlbflush.h> 4457f277b0SRajendra Nayak 458bd22949SKevin Hilman #include "cm.h" 468bd22949SKevin Hilman #include "cm-regbits-34xx.h" 478bd22949SKevin Hilman #include "prm-regbits-34xx.h" 488bd22949SKevin Hilman 498bd22949SKevin Hilman #include "prm.h" 508bd22949SKevin Hilman #include "pm.h" 5113a6fe0fSTero Kristo #include "sdrc.h" 5213a6fe0fSTero Kristo 532f5939c3SRajendra Nayak /* Scratchpad offsets */ 542f5939c3SRajendra Nayak #define OMAP343X_TABLE_ADDRESS_OFFSET 0x31 552f5939c3SRajendra Nayak #define OMAP343X_TABLE_VALUE_OFFSET 0x30 562f5939c3SRajendra Nayak #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32 572f5939c3SRajendra Nayak 58c40552bcSKevin Hilman u32 enable_off_mode; 59c40552bcSKevin Hilman u32 sleep_while_idle; 60d7814e4dSKevin Hilman u32 wakeup_timer_seconds; 618e2efde9SAri Kauppi u32 wakeup_timer_milliseconds; 62c40552bcSKevin Hilman 638bd22949SKevin Hilman struct power_state { 648bd22949SKevin Hilman struct powerdomain *pwrdm; 658bd22949SKevin Hilman u32 next_state; 6610f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 678bd22949SKevin Hilman u32 saved_state; 6810f90ed2SKevin Hilman #endif 698bd22949SKevin Hilman struct list_head node; 708bd22949SKevin Hilman }; 718bd22949SKevin Hilman 728bd22949SKevin Hilman static LIST_HEAD(pwrst_list); 738bd22949SKevin Hilman 748bd22949SKevin Hilman static void (*_omap_sram_idle)(u32 *addr, int save_state); 758bd22949SKevin Hilman 7627d59a4aSTero Kristo static int (*_omap_save_secure_sram)(u32 *addr); 7727d59a4aSTero Kristo 78fa3c2a4fSRajendra Nayak static struct powerdomain *mpu_pwrdm, *neon_pwrdm; 79fa3c2a4fSRajendra Nayak static struct powerdomain *core_pwrdm, *per_pwrdm; 80c16c3f67STero Kristo static struct powerdomain *cam_pwrdm; 81fa3c2a4fSRajendra Nayak 822f5939c3SRajendra Nayak static inline void omap3_per_save_context(void) 832f5939c3SRajendra Nayak { 842f5939c3SRajendra Nayak omap_gpio_save_context(); 852f5939c3SRajendra Nayak } 862f5939c3SRajendra Nayak 872f5939c3SRajendra Nayak static inline void omap3_per_restore_context(void) 882f5939c3SRajendra Nayak { 892f5939c3SRajendra Nayak omap_gpio_restore_context(); 902f5939c3SRajendra Nayak } 912f5939c3SRajendra Nayak 923a7ec26bSKalle Jokiniemi static void omap3_enable_io_chain(void) 933a7ec26bSKalle Jokiniemi { 943a7ec26bSKalle Jokiniemi int timeout = 0; 953a7ec26bSKalle Jokiniemi 963a7ec26bSKalle Jokiniemi if (omap_rev() >= OMAP3430_REV_ES3_1) { 972bc4ef71SPaul Walmsley prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, 982bc4ef71SPaul Walmsley PM_WKEN); 993a7ec26bSKalle Jokiniemi /* Do a readback to assure write has been done */ 1003a7ec26bSKalle Jokiniemi prm_read_mod_reg(WKUP_MOD, PM_WKEN); 1013a7ec26bSKalle Jokiniemi 1020b96a3a3SKevin Hilman while (!(prm_read_mod_reg(WKUP_MOD, PM_WKEN) & 1032bc4ef71SPaul Walmsley OMAP3430_ST_IO_CHAIN_MASK)) { 1043a7ec26bSKalle Jokiniemi timeout++; 1053a7ec26bSKalle Jokiniemi if (timeout > 1000) { 1063a7ec26bSKalle Jokiniemi printk(KERN_ERR "Wake up daisy chain " 1073a7ec26bSKalle Jokiniemi "activation failed.\n"); 1083a7ec26bSKalle Jokiniemi return; 1093a7ec26bSKalle Jokiniemi } 1102bc4ef71SPaul Walmsley prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, 1110b96a3a3SKevin Hilman WKUP_MOD, PM_WKEN); 1123a7ec26bSKalle Jokiniemi } 1133a7ec26bSKalle Jokiniemi } 1143a7ec26bSKalle Jokiniemi } 1153a7ec26bSKalle Jokiniemi 1163a7ec26bSKalle Jokiniemi static void omap3_disable_io_chain(void) 1173a7ec26bSKalle Jokiniemi { 1183a7ec26bSKalle Jokiniemi if (omap_rev() >= OMAP3430_REV_ES3_1) 1192bc4ef71SPaul Walmsley prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, 1202bc4ef71SPaul Walmsley PM_WKEN); 1213a7ec26bSKalle Jokiniemi } 1223a7ec26bSKalle Jokiniemi 1232f5939c3SRajendra Nayak static void omap3_core_save_context(void) 1242f5939c3SRajendra Nayak { 1252f5939c3SRajendra Nayak u32 control_padconf_off; 1262f5939c3SRajendra Nayak 1272f5939c3SRajendra Nayak /* Save the padconf registers */ 1282f5939c3SRajendra Nayak control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF); 1292f5939c3SRajendra Nayak control_padconf_off |= START_PADCONF_SAVE; 1302f5939c3SRajendra Nayak omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF); 1312f5939c3SRajendra Nayak /* wait for the save to complete */ 1321b6e821fSRoel Kluin while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) 1331b6e821fSRoel Kluin & PADCONF_SAVE_DONE)) 134dccaad89STero Kristo udelay(1); 135dccaad89STero Kristo 136dccaad89STero Kristo /* 137dccaad89STero Kristo * Force write last pad into memory, as this can fail in some 138dccaad89STero Kristo * cases according to erratas 1.157, 1.185 139dccaad89STero Kristo */ 140dccaad89STero Kristo omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), 141dccaad89STero Kristo OMAP343X_CONTROL_MEM_WKUP + 0x2a0); 142dccaad89STero Kristo 1432f5939c3SRajendra Nayak /* Save the Interrupt controller context */ 1442f5939c3SRajendra Nayak omap_intc_save_context(); 1452f5939c3SRajendra Nayak /* Save the GPMC context */ 1462f5939c3SRajendra Nayak omap3_gpmc_save_context(); 1472f5939c3SRajendra Nayak /* Save the system control module context, padconf already save above*/ 1482f5939c3SRajendra Nayak omap3_control_save_context(); 149f2d11858STero Kristo omap_dma_global_context_save(); 1502f5939c3SRajendra Nayak } 1512f5939c3SRajendra Nayak 1522f5939c3SRajendra Nayak static void omap3_core_restore_context(void) 1532f5939c3SRajendra Nayak { 1542f5939c3SRajendra Nayak /* Restore the control module context, padconf restored by h/w */ 1552f5939c3SRajendra Nayak omap3_control_restore_context(); 1562f5939c3SRajendra Nayak /* Restore the GPMC context */ 1572f5939c3SRajendra Nayak omap3_gpmc_restore_context(); 1582f5939c3SRajendra Nayak /* Restore the interrupt controller context */ 1592f5939c3SRajendra Nayak omap_intc_restore_context(); 160f2d11858STero Kristo omap_dma_global_context_restore(); 1612f5939c3SRajendra Nayak } 1622f5939c3SRajendra Nayak 1639d97140bSTero Kristo /* 1649d97140bSTero Kristo * FIXME: This function should be called before entering off-mode after 1659d97140bSTero Kristo * OMAP3 secure services have been accessed. Currently it is only called 1669d97140bSTero Kristo * once during boot sequence, but this works as we are not using secure 1679d97140bSTero Kristo * services. 1689d97140bSTero Kristo */ 16927d59a4aSTero Kristo static void omap3_save_secure_ram_context(u32 target_mpu_state) 17027d59a4aSTero Kristo { 17127d59a4aSTero Kristo u32 ret; 17227d59a4aSTero Kristo 17327d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 17427d59a4aSTero Kristo /* 17527d59a4aSTero Kristo * MPU next state must be set to POWER_ON temporarily, 17627d59a4aSTero Kristo * otherwise the WFI executed inside the ROM code 17727d59a4aSTero Kristo * will hang the system. 17827d59a4aSTero Kristo */ 17927d59a4aSTero Kristo pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); 18027d59a4aSTero Kristo ret = _omap_save_secure_sram((u32 *) 18127d59a4aSTero Kristo __pa(omap3_secure_ram_storage)); 18227d59a4aSTero Kristo pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state); 18327d59a4aSTero Kristo /* Following is for error tracking, it should not happen */ 18427d59a4aSTero Kristo if (ret) { 18527d59a4aSTero Kristo printk(KERN_ERR "save_secure_sram() returns %08x\n", 18627d59a4aSTero Kristo ret); 18727d59a4aSTero Kristo while (1) 18827d59a4aSTero Kristo ; 18927d59a4aSTero Kristo } 19027d59a4aSTero Kristo } 19127d59a4aSTero Kristo } 19227d59a4aSTero Kristo 19377da2d91SJon Hunter /* 19477da2d91SJon Hunter * PRCM Interrupt Handler Helper Function 19577da2d91SJon Hunter * 19677da2d91SJon Hunter * The purpose of this function is to clear any wake-up events latched 19777da2d91SJon Hunter * in the PRCM PM_WKST_x registers. It is possible that a wake-up event 19877da2d91SJon Hunter * may occur whilst attempting to clear a PM_WKST_x register and thus 19977da2d91SJon Hunter * set another bit in this register. A while loop is used to ensure 20077da2d91SJon Hunter * that any peripheral wake-up events occurring while attempting to 20177da2d91SJon Hunter * clear the PM_WKST_x are detected and cleared. 20277da2d91SJon Hunter */ 2038cb0ac99SPaul Walmsley static int prcm_clear_mod_irqs(s16 module, u8 regs) 20477da2d91SJon Hunter { 20571a80775SVikram Pandita u32 wkst, fclk, iclk, clken; 20677da2d91SJon Hunter u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; 20777da2d91SJon Hunter u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; 20877da2d91SJon Hunter u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; 2095d805978SPaul Walmsley u16 grpsel_off = (regs == 3) ? 2105d805978SPaul Walmsley OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; 2118cb0ac99SPaul Walmsley int c = 0; 21277da2d91SJon Hunter 21377da2d91SJon Hunter wkst = prm_read_mod_reg(module, wkst_off); 2145d805978SPaul Walmsley wkst &= prm_read_mod_reg(module, grpsel_off); 21577da2d91SJon Hunter if (wkst) { 21677da2d91SJon Hunter iclk = cm_read_mod_reg(module, iclk_off); 21777da2d91SJon Hunter fclk = cm_read_mod_reg(module, fclk_off); 21877da2d91SJon Hunter while (wkst) { 21971a80775SVikram Pandita clken = wkst; 22071a80775SVikram Pandita cm_set_mod_reg_bits(clken, module, iclk_off); 22171a80775SVikram Pandita /* 22271a80775SVikram Pandita * For USBHOST, we don't know whether HOST1 or 22371a80775SVikram Pandita * HOST2 woke us up, so enable both f-clocks 22471a80775SVikram Pandita */ 22571a80775SVikram Pandita if (module == OMAP3430ES2_USBHOST_MOD) 22671a80775SVikram Pandita clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; 22771a80775SVikram Pandita cm_set_mod_reg_bits(clken, module, fclk_off); 22877da2d91SJon Hunter prm_write_mod_reg(wkst, module, wkst_off); 22977da2d91SJon Hunter wkst = prm_read_mod_reg(module, wkst_off); 2308cb0ac99SPaul Walmsley c++; 23177da2d91SJon Hunter } 23277da2d91SJon Hunter cm_write_mod_reg(iclk, module, iclk_off); 23377da2d91SJon Hunter cm_write_mod_reg(fclk, module, fclk_off); 23477da2d91SJon Hunter } 2358cb0ac99SPaul Walmsley 2368cb0ac99SPaul Walmsley return c; 2378cb0ac99SPaul Walmsley } 2388cb0ac99SPaul Walmsley 2398cb0ac99SPaul Walmsley static int _prcm_int_handle_wakeup(void) 2408cb0ac99SPaul Walmsley { 2418cb0ac99SPaul Walmsley int c; 2428cb0ac99SPaul Walmsley 2438cb0ac99SPaul Walmsley c = prcm_clear_mod_irqs(WKUP_MOD, 1); 2448cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(CORE_MOD, 1); 2458cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1); 2468cb0ac99SPaul Walmsley if (omap_rev() > OMAP3430_REV_ES1_0) { 2478cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(CORE_MOD, 3); 2488cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1); 2498cb0ac99SPaul Walmsley } 2508cb0ac99SPaul Walmsley 2518cb0ac99SPaul Walmsley return c; 25277da2d91SJon Hunter } 25377da2d91SJon Hunter 25477da2d91SJon Hunter /* 25577da2d91SJon Hunter * PRCM Interrupt Handler 25677da2d91SJon Hunter * 25777da2d91SJon Hunter * The PRM_IRQSTATUS_MPU register indicates if there are any pending 25877da2d91SJon Hunter * interrupts from the PRCM for the MPU. These bits must be cleared in 25977da2d91SJon Hunter * order to clear the PRCM interrupt. The PRCM interrupt handler is 26077da2d91SJon Hunter * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear 26177da2d91SJon Hunter * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU 26277da2d91SJon Hunter * register indicates that a wake-up event is pending for the MPU and 26377da2d91SJon Hunter * this bit can only be cleared if the all the wake-up events latched 26477da2d91SJon Hunter * in the various PM_WKST_x registers have been cleared. The interrupt 26577da2d91SJon Hunter * handler is implemented using a do-while loop so that if a wake-up 26677da2d91SJon Hunter * event occurred during the processing of the prcm interrupt handler 26777da2d91SJon Hunter * (setting a bit in the corresponding PM_WKST_x register and thus 26877da2d91SJon Hunter * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register) 26977da2d91SJon Hunter * this would be handled. 27077da2d91SJon Hunter */ 2718bd22949SKevin Hilman static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) 2728bd22949SKevin Hilman { 273d6290a3eSKevin Hilman u32 irqenable_mpu, irqstatus_mpu; 2748cb0ac99SPaul Walmsley int c = 0; 2758bd22949SKevin Hilman 276d6290a3eSKevin Hilman irqenable_mpu = prm_read_mod_reg(OCP_MOD, 277d6290a3eSKevin Hilman OMAP3_PRM_IRQENABLE_MPU_OFFSET); 2788bd22949SKevin Hilman irqstatus_mpu = prm_read_mod_reg(OCP_MOD, 2798bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 280d6290a3eSKevin Hilman irqstatus_mpu &= irqenable_mpu; 2818cb0ac99SPaul Walmsley 282d6290a3eSKevin Hilman do { 2832bc4ef71SPaul Walmsley if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK | 2842bc4ef71SPaul Walmsley OMAP3430_IO_ST_MASK)) { 2858cb0ac99SPaul Walmsley c = _prcm_int_handle_wakeup(); 2868cb0ac99SPaul Walmsley 2878cb0ac99SPaul Walmsley /* 2888cb0ac99SPaul Walmsley * Is the MPU PRCM interrupt handler racing with the 2898cb0ac99SPaul Walmsley * IVA2 PRCM interrupt handler ? 2908cb0ac99SPaul Walmsley */ 2918cb0ac99SPaul Walmsley WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup " 2928cb0ac99SPaul Walmsley "but no wakeup sources are marked\n"); 2938cb0ac99SPaul Walmsley } else { 2948cb0ac99SPaul Walmsley /* XXX we need to expand our PRCM interrupt handler */ 2958cb0ac99SPaul Walmsley WARN(1, "prcm: WARNING: PRCM interrupt received, but " 2968cb0ac99SPaul Walmsley "no code to handle it (%08x)\n", irqstatus_mpu); 2978cb0ac99SPaul Walmsley } 2988cb0ac99SPaul Walmsley 2998bd22949SKevin Hilman prm_write_mod_reg(irqstatus_mpu, OCP_MOD, 3008bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 3018bd22949SKevin Hilman 302d6290a3eSKevin Hilman irqstatus_mpu = prm_read_mod_reg(OCP_MOD, 303d6290a3eSKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 304d6290a3eSKevin Hilman irqstatus_mpu &= irqenable_mpu; 305d6290a3eSKevin Hilman 306d6290a3eSKevin Hilman } while (irqstatus_mpu); 3078bd22949SKevin Hilman 3088bd22949SKevin Hilman return IRQ_HANDLED; 3098bd22949SKevin Hilman } 3108bd22949SKevin Hilman 31157f277b0SRajendra Nayak static void restore_control_register(u32 val) 31257f277b0SRajendra Nayak { 31357f277b0SRajendra Nayak __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val)); 31457f277b0SRajendra Nayak } 31557f277b0SRajendra Nayak 31657f277b0SRajendra Nayak /* Function to restore the table entry that was modified for enabling MMU */ 31757f277b0SRajendra Nayak static void restore_table_entry(void) 31857f277b0SRajendra Nayak { 31957f277b0SRajendra Nayak u32 *scratchpad_address; 32057f277b0SRajendra Nayak u32 previous_value, control_reg_value; 32157f277b0SRajendra Nayak u32 *address; 32257f277b0SRajendra Nayak 32357f277b0SRajendra Nayak scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD); 32457f277b0SRajendra Nayak 32557f277b0SRajendra Nayak /* Get address of entry that was modified */ 32657f277b0SRajendra Nayak address = (u32 *)__raw_readl(scratchpad_address + 32757f277b0SRajendra Nayak OMAP343X_TABLE_ADDRESS_OFFSET); 32857f277b0SRajendra Nayak /* Get the previous value which needs to be restored */ 32957f277b0SRajendra Nayak previous_value = __raw_readl(scratchpad_address + 33057f277b0SRajendra Nayak OMAP343X_TABLE_VALUE_OFFSET); 33157f277b0SRajendra Nayak address = __va(address); 33257f277b0SRajendra Nayak *address = previous_value; 33357f277b0SRajendra Nayak flush_tlb_all(); 33457f277b0SRajendra Nayak control_reg_value = __raw_readl(scratchpad_address 33557f277b0SRajendra Nayak + OMAP343X_CONTROL_REG_VALUE_OFFSET); 33657f277b0SRajendra Nayak /* This will enable caches and prediction */ 33757f277b0SRajendra Nayak restore_control_register(control_reg_value); 33857f277b0SRajendra Nayak } 33957f277b0SRajendra Nayak 34099e6a4d2SRajendra Nayak void omap_sram_idle(void) 3418bd22949SKevin Hilman { 3428bd22949SKevin Hilman /* Variable to tell what needs to be saved and restored 3438bd22949SKevin Hilman * in omap_sram_idle*/ 3448bd22949SKevin Hilman /* save_state = 0 => Nothing to save and restored */ 3458bd22949SKevin Hilman /* save_state = 1 => Only L1 and logic lost */ 3468bd22949SKevin Hilman /* save_state = 2 => Only L2 lost */ 3478bd22949SKevin Hilman /* save_state = 3 => L1, L2 and logic lost */ 348fa3c2a4fSRajendra Nayak int save_state = 0; 349fa3c2a4fSRajendra Nayak int mpu_next_state = PWRDM_POWER_ON; 350fa3c2a4fSRajendra Nayak int per_next_state = PWRDM_POWER_ON; 351fa3c2a4fSRajendra Nayak int core_next_state = PWRDM_POWER_ON; 3522f5939c3SRajendra Nayak int core_prev_state, per_prev_state; 35313a6fe0fSTero Kristo u32 sdrc_pwr = 0; 354ecf157d0STero Kristo int per_state_modified = 0; 3558bd22949SKevin Hilman 3568bd22949SKevin Hilman if (!_omap_sram_idle) 3578bd22949SKevin Hilman return; 3588bd22949SKevin Hilman 359fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(mpu_pwrdm); 360fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(neon_pwrdm); 361fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(core_pwrdm); 362fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(per_pwrdm); 363fa3c2a4fSRajendra Nayak 3648bd22949SKevin Hilman mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 3658bd22949SKevin Hilman switch (mpu_next_state) { 366fa3c2a4fSRajendra Nayak case PWRDM_POWER_ON: 3678bd22949SKevin Hilman case PWRDM_POWER_RET: 3688bd22949SKevin Hilman /* No need to save context */ 3698bd22949SKevin Hilman save_state = 0; 3708bd22949SKevin Hilman break; 37161255ab9SRajendra Nayak case PWRDM_POWER_OFF: 37261255ab9SRajendra Nayak save_state = 3; 37361255ab9SRajendra Nayak break; 3748bd22949SKevin Hilman default: 3758bd22949SKevin Hilman /* Invalid state */ 3768bd22949SKevin Hilman printk(KERN_ERR "Invalid mpu state in sram_idle\n"); 3778bd22949SKevin Hilman return; 3788bd22949SKevin Hilman } 379fe617af7SPeter 'p2' De Schrijver pwrdm_pre_transition(); 380fe617af7SPeter 'p2' De Schrijver 381fa3c2a4fSRajendra Nayak /* NEON control */ 382fa3c2a4fSRajendra Nayak if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) 3837139178eSJouni Hogander pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); 384fa3c2a4fSRajendra Nayak 38540742fa8SMike Chan /* Enable IO-PAD and IO-CHAIN wakeups */ 386fa3c2a4fSRajendra Nayak per_next_state = pwrdm_read_next_pwrst(per_pwrdm); 387ecf157d0STero Kristo core_next_state = pwrdm_read_next_pwrst(core_pwrdm); 388ad0c63f1Sstanley.miao if (omap3_has_io_wakeup() && \ 389ad0c63f1Sstanley.miao (per_next_state < PWRDM_POWER_ON || 390ad0c63f1Sstanley.miao core_next_state < PWRDM_POWER_ON)) { 3912bc4ef71SPaul Walmsley prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); 39240742fa8SMike Chan omap3_enable_io_chain(); 39340742fa8SMike Chan } 39440742fa8SMike Chan 39540742fa8SMike Chan /* PER */ 3962f5939c3SRajendra Nayak if (per_next_state < PWRDM_POWER_ON) { 3974af4016cSKevin Hilman omap_uart_prepare_idle(2); 39843ffcd9aSKevin Hilman omap2_gpio_prepare_for_idle(per_next_state); 399ecf157d0STero Kristo if (per_next_state == PWRDM_POWER_OFF) { 400ecf157d0STero Kristo if (core_next_state == PWRDM_POWER_ON) { 401ecf157d0STero Kristo per_next_state = PWRDM_POWER_RET; 402ecf157d0STero Kristo pwrdm_set_next_pwrst(per_pwrdm, per_next_state); 403ecf157d0STero Kristo per_state_modified = 1; 40443ffcd9aSKevin Hilman } else 4052f5939c3SRajendra Nayak omap3_per_save_context(); 4062f5939c3SRajendra Nayak } 407ecf157d0STero Kristo } 408658ce97eSKevin Hilman 409c16c3f67STero Kristo if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON) 410c16c3f67STero Kristo omap2_clkdm_deny_idle(mpu_pwrdm->pwrdm_clkdms[0]); 411c16c3f67STero Kristo 412658ce97eSKevin Hilman /* CORE */ 413658ce97eSKevin Hilman if (core_next_state < PWRDM_POWER_ON) { 414658ce97eSKevin Hilman omap_uart_prepare_idle(0); 415658ce97eSKevin Hilman omap_uart_prepare_idle(1); 4162f5939c3SRajendra Nayak if (core_next_state == PWRDM_POWER_OFF) { 4172f5939c3SRajendra Nayak omap3_core_save_context(); 4182f5939c3SRajendra Nayak omap3_prcm_save_context(); 4192f5939c3SRajendra Nayak } 420fa3c2a4fSRajendra Nayak } 42140742fa8SMike Chan 422f18cc2ffSTero Kristo omap3_intc_prepare_idle(); 4238bd22949SKevin Hilman 42461255ab9SRajendra Nayak /* 425f265dc4cSRajendra Nayak * On EMU/HS devices ROM code restores a SRDC value 426f265dc4cSRajendra Nayak * from scratchpad which has automatic self refresh on timeout 427f265dc4cSRajendra Nayak * of AUTO_CNT = 1 enabled. This takes care of errata 1.142. 428f265dc4cSRajendra Nayak * Hence store/restore the SDRC_POWER register here. 42913a6fe0fSTero Kristo */ 43013a6fe0fSTero Kristo if (omap_rev() >= OMAP3430_REV_ES3_0 && 43113a6fe0fSTero Kristo omap_type() != OMAP2_DEVICE_TYPE_GP && 432f265dc4cSRajendra Nayak core_next_state == PWRDM_POWER_OFF) 43313a6fe0fSTero Kristo sdrc_pwr = sdrc_read_reg(SDRC_POWER); 43413a6fe0fSTero Kristo 43513a6fe0fSTero Kristo /* 43661255ab9SRajendra Nayak * omap3_arm_context is the location where ARM registers 43761255ab9SRajendra Nayak * get saved. The restore path then reads from this 43861255ab9SRajendra Nayak * location and restores them back. 43961255ab9SRajendra Nayak */ 44061255ab9SRajendra Nayak _omap_sram_idle(omap3_arm_context, save_state); 4418bd22949SKevin Hilman cpu_init(); 4428bd22949SKevin Hilman 443f265dc4cSRajendra Nayak /* Restore normal SDRC POWER settings */ 44413a6fe0fSTero Kristo if (omap_rev() >= OMAP3430_REV_ES3_0 && 44513a6fe0fSTero Kristo omap_type() != OMAP2_DEVICE_TYPE_GP && 44613a6fe0fSTero Kristo core_next_state == PWRDM_POWER_OFF) 44713a6fe0fSTero Kristo sdrc_write_reg(sdrc_pwr, SDRC_POWER); 44813a6fe0fSTero Kristo 44957f277b0SRajendra Nayak /* Restore table entry modified during MMU restoration */ 45057f277b0SRajendra Nayak if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF) 45157f277b0SRajendra Nayak restore_table_entry(); 45257f277b0SRajendra Nayak 453658ce97eSKevin Hilman /* CORE */ 454fa3c2a4fSRajendra Nayak if (core_next_state < PWRDM_POWER_ON) { 4552f5939c3SRajendra Nayak core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); 4562f5939c3SRajendra Nayak if (core_prev_state == PWRDM_POWER_OFF) { 4572f5939c3SRajendra Nayak omap3_core_restore_context(); 4582f5939c3SRajendra Nayak omap3_prcm_restore_context(); 4592f5939c3SRajendra Nayak omap3_sram_restore_context(); 4608a917d2fSKalle Jokiniemi omap2_sms_restore_context(); 4612f5939c3SRajendra Nayak } 462658ce97eSKevin Hilman omap_uart_resume_idle(0); 463658ce97eSKevin Hilman omap_uart_resume_idle(1); 464658ce97eSKevin Hilman if (core_next_state == PWRDM_POWER_OFF) 4652bc4ef71SPaul Walmsley prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, 466658ce97eSKevin Hilman OMAP3430_GR_MOD, 467658ce97eSKevin Hilman OMAP3_PRM_VOLTCTRL_OFFSET); 468658ce97eSKevin Hilman } 469f18cc2ffSTero Kristo omap3_intc_resume_idle(); 470658ce97eSKevin Hilman 471658ce97eSKevin Hilman /* PER */ 4722f5939c3SRajendra Nayak if (per_next_state < PWRDM_POWER_ON) { 473658ce97eSKevin Hilman per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); 47443ffcd9aSKevin Hilman omap2_gpio_resume_after_idle(); 47543ffcd9aSKevin Hilman if (per_prev_state == PWRDM_POWER_OFF) 4762f5939c3SRajendra Nayak omap3_per_restore_context(); 477ecf157d0STero Kristo omap_uart_resume_idle(2); 478ecf157d0STero Kristo if (per_state_modified) 479ecf157d0STero Kristo pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF); 480fa3c2a4fSRajendra Nayak } 481fe617af7SPeter 'p2' De Schrijver 4823a7ec26bSKalle Jokiniemi /* Disable IO-PAD and IO-CHAIN wakeup */ 483ad0c63f1Sstanley.miao if (omap3_has_io_wakeup() && core_next_state < PWRDM_POWER_ON) { 4842bc4ef71SPaul Walmsley prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); 4853a7ec26bSKalle Jokiniemi omap3_disable_io_chain(); 4863a7ec26bSKalle Jokiniemi } 487658ce97eSKevin Hilman 488fe617af7SPeter 'p2' De Schrijver pwrdm_post_transition(); 489fe617af7SPeter 'p2' De Schrijver 490c16c3f67STero Kristo omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); 4918bd22949SKevin Hilman } 4928bd22949SKevin Hilman 49320b01669SRajendra Nayak int omap3_can_sleep(void) 4948bd22949SKevin Hilman { 495c40552bcSKevin Hilman if (!sleep_while_idle) 496c40552bcSKevin Hilman return 0; 4974af4016cSKevin Hilman if (!omap_uart_can_sleep()) 4984af4016cSKevin Hilman return 0; 4998bd22949SKevin Hilman return 1; 5008bd22949SKevin Hilman } 5018bd22949SKevin Hilman 5028bd22949SKevin Hilman /* This sets pwrdm state (other than mpu & core. Currently only ON & 5038bd22949SKevin Hilman * RET are supported. Function is assuming that clkdm doesn't have 5048bd22949SKevin Hilman * hw_sup mode enabled. */ 50520b01669SRajendra Nayak int set_pwrdm_state(struct powerdomain *pwrdm, u32 state) 5068bd22949SKevin Hilman { 5078bd22949SKevin Hilman u32 cur_state; 5088bd22949SKevin Hilman int sleep_switch = 0; 5098bd22949SKevin Hilman int ret = 0; 5108bd22949SKevin Hilman 5118bd22949SKevin Hilman if (pwrdm == NULL || IS_ERR(pwrdm)) 5128bd22949SKevin Hilman return -EINVAL; 5138bd22949SKevin Hilman 5148bd22949SKevin Hilman while (!(pwrdm->pwrsts & (1 << state))) { 5158bd22949SKevin Hilman if (state == PWRDM_POWER_OFF) 5168bd22949SKevin Hilman return ret; 5178bd22949SKevin Hilman state--; 5188bd22949SKevin Hilman } 5198bd22949SKevin Hilman 5208bd22949SKevin Hilman cur_state = pwrdm_read_next_pwrst(pwrdm); 5218bd22949SKevin Hilman if (cur_state == state) 5228bd22949SKevin Hilman return ret; 5238bd22949SKevin Hilman 5248bd22949SKevin Hilman if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) { 5258bd22949SKevin Hilman omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); 5268bd22949SKevin Hilman sleep_switch = 1; 5278bd22949SKevin Hilman pwrdm_wait_transition(pwrdm); 5288bd22949SKevin Hilman } 5298bd22949SKevin Hilman 5308bd22949SKevin Hilman ret = pwrdm_set_next_pwrst(pwrdm, state); 5318bd22949SKevin Hilman if (ret) { 5328bd22949SKevin Hilman printk(KERN_ERR "Unable to set state of powerdomain: %s\n", 5338bd22949SKevin Hilman pwrdm->name); 5348bd22949SKevin Hilman goto err; 5358bd22949SKevin Hilman } 5368bd22949SKevin Hilman 5378bd22949SKevin Hilman if (sleep_switch) { 5388bd22949SKevin Hilman omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); 5398bd22949SKevin Hilman pwrdm_wait_transition(pwrdm); 540fe617af7SPeter 'p2' De Schrijver pwrdm_state_switch(pwrdm); 5418bd22949SKevin Hilman } 5428bd22949SKevin Hilman 5438bd22949SKevin Hilman err: 5448bd22949SKevin Hilman return ret; 5458bd22949SKevin Hilman } 5468bd22949SKevin Hilman 5478bd22949SKevin Hilman static void omap3_pm_idle(void) 5488bd22949SKevin Hilman { 5498bd22949SKevin Hilman local_irq_disable(); 5508bd22949SKevin Hilman local_fiq_disable(); 5518bd22949SKevin Hilman 5528bd22949SKevin Hilman if (!omap3_can_sleep()) 5538bd22949SKevin Hilman goto out; 5548bd22949SKevin Hilman 555cf22854cSTero Kristo if (omap_irq_pending() || need_resched()) 5568bd22949SKevin Hilman goto out; 5578bd22949SKevin Hilman 5588bd22949SKevin Hilman omap_sram_idle(); 5598bd22949SKevin Hilman 5608bd22949SKevin Hilman out: 5618bd22949SKevin Hilman local_fiq_enable(); 5628bd22949SKevin Hilman local_irq_enable(); 5638bd22949SKevin Hilman } 5648bd22949SKevin Hilman 56510f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 5662466211eSTero Kristo static suspend_state_t suspend_state; 5672466211eSTero Kristo 5688e2efde9SAri Kauppi static void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds) 569d7814e4dSKevin Hilman { 570d7814e4dSKevin Hilman u32 tick_rate, cycles; 571d7814e4dSKevin Hilman 5728e2efde9SAri Kauppi if (!seconds && !milliseconds) 573d7814e4dSKevin Hilman return; 574d7814e4dSKevin Hilman 575d7814e4dSKevin Hilman tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup)); 5768e2efde9SAri Kauppi cycles = tick_rate * seconds + tick_rate * milliseconds / 1000; 577d7814e4dSKevin Hilman omap_dm_timer_stop(gptimer_wakeup); 578d7814e4dSKevin Hilman omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles); 579d7814e4dSKevin Hilman 5808e2efde9SAri Kauppi pr_info("PM: Resume timer in %u.%03u secs" 5818e2efde9SAri Kauppi " (%d ticks at %d ticks/sec.)\n", 5828e2efde9SAri Kauppi seconds, milliseconds, cycles, tick_rate); 583d7814e4dSKevin Hilman } 584d7814e4dSKevin Hilman 5858bd22949SKevin Hilman static int omap3_pm_prepare(void) 5868bd22949SKevin Hilman { 5878bd22949SKevin Hilman disable_hlt(); 5888bd22949SKevin Hilman return 0; 5898bd22949SKevin Hilman } 5908bd22949SKevin Hilman 5918bd22949SKevin Hilman static int omap3_pm_suspend(void) 5928bd22949SKevin Hilman { 5938bd22949SKevin Hilman struct power_state *pwrst; 5948bd22949SKevin Hilman int state, ret = 0; 5958bd22949SKevin Hilman 5968e2efde9SAri Kauppi if (wakeup_timer_seconds || wakeup_timer_milliseconds) 5978e2efde9SAri Kauppi omap2_pm_wakeup_on_timer(wakeup_timer_seconds, 5988e2efde9SAri Kauppi wakeup_timer_milliseconds); 599d7814e4dSKevin Hilman 6008bd22949SKevin Hilman /* Read current next_pwrsts */ 6018bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) 6028bd22949SKevin Hilman pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 6038bd22949SKevin Hilman /* Set ones wanted by suspend */ 6048bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 6058bd22949SKevin Hilman if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) 6068bd22949SKevin Hilman goto restore; 6078bd22949SKevin Hilman if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) 6088bd22949SKevin Hilman goto restore; 6098bd22949SKevin Hilman } 6108bd22949SKevin Hilman 6114af4016cSKevin Hilman omap_uart_prepare_suspend(); 6122bbe3af3STero Kristo omap3_intc_suspend(); 6132bbe3af3STero Kristo 6148bd22949SKevin Hilman omap_sram_idle(); 6158bd22949SKevin Hilman 6168bd22949SKevin Hilman restore: 6178bd22949SKevin Hilman /* Restore next_pwrsts */ 6188bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 6198bd22949SKevin Hilman state = pwrdm_read_prev_pwrst(pwrst->pwrdm); 6208bd22949SKevin Hilman if (state > pwrst->next_state) { 6218bd22949SKevin Hilman printk(KERN_INFO "Powerdomain (%s) didn't enter " 6228bd22949SKevin Hilman "target state %d\n", 6238bd22949SKevin Hilman pwrst->pwrdm->name, pwrst->next_state); 6248bd22949SKevin Hilman ret = -1; 6258bd22949SKevin Hilman } 6266c5f8039SJouni Hogander set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); 6278bd22949SKevin Hilman } 6288bd22949SKevin Hilman if (ret) 6298bd22949SKevin Hilman printk(KERN_ERR "Could not enter target state in pm_suspend\n"); 6308bd22949SKevin Hilman else 6318bd22949SKevin Hilman printk(KERN_INFO "Successfully put all powerdomains " 6328bd22949SKevin Hilman "to target state\n"); 6338bd22949SKevin Hilman 6348bd22949SKevin Hilman return ret; 6358bd22949SKevin Hilman } 6368bd22949SKevin Hilman 6372466211eSTero Kristo static int omap3_pm_enter(suspend_state_t unused) 6388bd22949SKevin Hilman { 6398bd22949SKevin Hilman int ret = 0; 6408bd22949SKevin Hilman 6412466211eSTero Kristo switch (suspend_state) { 6428bd22949SKevin Hilman case PM_SUSPEND_STANDBY: 6438bd22949SKevin Hilman case PM_SUSPEND_MEM: 6448bd22949SKevin Hilman ret = omap3_pm_suspend(); 6458bd22949SKevin Hilman break; 6468bd22949SKevin Hilman default: 6478bd22949SKevin Hilman ret = -EINVAL; 6488bd22949SKevin Hilman } 6498bd22949SKevin Hilman 6508bd22949SKevin Hilman return ret; 6518bd22949SKevin Hilman } 6528bd22949SKevin Hilman 6538bd22949SKevin Hilman static void omap3_pm_finish(void) 6548bd22949SKevin Hilman { 6558bd22949SKevin Hilman enable_hlt(); 6568bd22949SKevin Hilman } 6578bd22949SKevin Hilman 6582466211eSTero Kristo /* Hooks to enable / disable UART interrupts during suspend */ 6592466211eSTero Kristo static int omap3_pm_begin(suspend_state_t state) 6602466211eSTero Kristo { 6612466211eSTero Kristo suspend_state = state; 6622466211eSTero Kristo omap_uart_enable_irqs(0); 6632466211eSTero Kristo return 0; 6642466211eSTero Kristo } 6652466211eSTero Kristo 6662466211eSTero Kristo static void omap3_pm_end(void) 6672466211eSTero Kristo { 6682466211eSTero Kristo suspend_state = PM_SUSPEND_ON; 6692466211eSTero Kristo omap_uart_enable_irqs(1); 6702466211eSTero Kristo return; 6712466211eSTero Kristo } 6722466211eSTero Kristo 6738bd22949SKevin Hilman static struct platform_suspend_ops omap_pm_ops = { 6742466211eSTero Kristo .begin = omap3_pm_begin, 6752466211eSTero Kristo .end = omap3_pm_end, 6768bd22949SKevin Hilman .prepare = omap3_pm_prepare, 6778bd22949SKevin Hilman .enter = omap3_pm_enter, 6788bd22949SKevin Hilman .finish = omap3_pm_finish, 6798bd22949SKevin Hilman .valid = suspend_valid_only_mem, 6808bd22949SKevin Hilman }; 68110f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 6828bd22949SKevin Hilman 6831155e426SKevin Hilman 6841155e426SKevin Hilman /** 6851155e426SKevin Hilman * omap3_iva_idle(): ensure IVA is in idle so it can be put into 6861155e426SKevin Hilman * retention 6871155e426SKevin Hilman * 6881155e426SKevin Hilman * In cases where IVA2 is activated by bootcode, it may prevent 6891155e426SKevin Hilman * full-chip retention or off-mode because it is not idle. This 6901155e426SKevin Hilman * function forces the IVA2 into idle state so it can go 6911155e426SKevin Hilman * into retention/off and thus allow full-chip retention/off. 6921155e426SKevin Hilman * 6931155e426SKevin Hilman **/ 6941155e426SKevin Hilman static void __init omap3_iva_idle(void) 6951155e426SKevin Hilman { 6961155e426SKevin Hilman /* ensure IVA2 clock is disabled */ 6971155e426SKevin Hilman cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 6981155e426SKevin Hilman 6991155e426SKevin Hilman /* if no clock activity, nothing else to do */ 7001155e426SKevin Hilman if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & 7011155e426SKevin Hilman OMAP3430_CLKACTIVITY_IVA2_MASK)) 7021155e426SKevin Hilman return; 7031155e426SKevin Hilman 7041155e426SKevin Hilman /* Reset IVA2 */ 7052bc4ef71SPaul Walmsley prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | 7062bc4ef71SPaul Walmsley OMAP3430_RST2_IVA2_MASK | 7072bc4ef71SPaul Walmsley OMAP3430_RST3_IVA2_MASK, 70837903009SAbhijit Pagare OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 7091155e426SKevin Hilman 7101155e426SKevin Hilman /* Enable IVA2 clock */ 711dfa6d6f8SKevin Hilman cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, 7121155e426SKevin Hilman OMAP3430_IVA2_MOD, CM_FCLKEN); 7131155e426SKevin Hilman 7141155e426SKevin Hilman /* Set IVA2 boot mode to 'idle' */ 7151155e426SKevin Hilman omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, 7161155e426SKevin Hilman OMAP343X_CONTROL_IVA2_BOOTMOD); 7171155e426SKevin Hilman 7181155e426SKevin Hilman /* Un-reset IVA2 */ 71937903009SAbhijit Pagare prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 7201155e426SKevin Hilman 7211155e426SKevin Hilman /* Disable IVA2 clock */ 7221155e426SKevin Hilman cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 7231155e426SKevin Hilman 7241155e426SKevin Hilman /* Reset IVA2 */ 7252bc4ef71SPaul Walmsley prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | 7262bc4ef71SPaul Walmsley OMAP3430_RST2_IVA2_MASK | 7272bc4ef71SPaul Walmsley OMAP3430_RST3_IVA2_MASK, 72837903009SAbhijit Pagare OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 7291155e426SKevin Hilman } 7301155e426SKevin Hilman 7318111b221SKevin Hilman static void __init omap3_d2d_idle(void) 7328bd22949SKevin Hilman { 7338111b221SKevin Hilman u16 mask, padconf; 7348111b221SKevin Hilman 7358111b221SKevin Hilman /* In a stand alone OMAP3430 where there is not a stacked 7368111b221SKevin Hilman * modem for the D2D Idle Ack and D2D MStandby must be pulled 7378111b221SKevin Hilman * high. S CONTROL_PADCONF_SAD2D_IDLEACK and 7388111b221SKevin Hilman * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ 7398111b221SKevin Hilman mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ 7408111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); 7418111b221SKevin Hilman padconf |= mask; 7428111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); 7438111b221SKevin Hilman 7448111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); 7458111b221SKevin Hilman padconf |= mask; 7468111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 7478111b221SKevin Hilman 7488bd22949SKevin Hilman /* reset modem */ 7492bc4ef71SPaul Walmsley prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | 7502bc4ef71SPaul Walmsley OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, 75137903009SAbhijit Pagare CORE_MOD, OMAP2_RM_RSTCTRL); 75237903009SAbhijit Pagare prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); 7538111b221SKevin Hilman } 7548bd22949SKevin Hilman 7558111b221SKevin Hilman static void __init prcm_setup_regs(void) 7568111b221SKevin Hilman { 7578bd22949SKevin Hilman /* XXX Reset all wkdeps. This should be done when initializing 7588bd22949SKevin Hilman * powerdomains */ 7598bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); 7608bd22949SKevin Hilman prm_write_mod_reg(0, MPU_MOD, PM_WKDEP); 7618bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP); 7628bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP); 7638bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP); 7648bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP); 7658bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 7668bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP); 7678bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP); 7688bd22949SKevin Hilman } else 7698bd22949SKevin Hilman prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); 7708bd22949SKevin Hilman 7718bd22949SKevin Hilman /* 7728bd22949SKevin Hilman * Enable interface clock autoidle for all modules. 7738bd22949SKevin Hilman * Note that in the long run this should be done by clockfw 7748bd22949SKevin Hilman */ 7758bd22949SKevin Hilman cm_write_mod_reg( 7762bc4ef71SPaul Walmsley OMAP3430_AUTO_MODEM_MASK | 7772bc4ef71SPaul Walmsley OMAP3430ES2_AUTO_MMC3_MASK | 7782bc4ef71SPaul Walmsley OMAP3430ES2_AUTO_ICR_MASK | 7792bc4ef71SPaul Walmsley OMAP3430_AUTO_AES2_MASK | 7802bc4ef71SPaul Walmsley OMAP3430_AUTO_SHA12_MASK | 7812bc4ef71SPaul Walmsley OMAP3430_AUTO_DES2_MASK | 7822bc4ef71SPaul Walmsley OMAP3430_AUTO_MMC2_MASK | 7832bc4ef71SPaul Walmsley OMAP3430_AUTO_MMC1_MASK | 7842bc4ef71SPaul Walmsley OMAP3430_AUTO_MSPRO_MASK | 7852bc4ef71SPaul Walmsley OMAP3430_AUTO_HDQ_MASK | 7862bc4ef71SPaul Walmsley OMAP3430_AUTO_MCSPI4_MASK | 7872bc4ef71SPaul Walmsley OMAP3430_AUTO_MCSPI3_MASK | 7882bc4ef71SPaul Walmsley OMAP3430_AUTO_MCSPI2_MASK | 7892bc4ef71SPaul Walmsley OMAP3430_AUTO_MCSPI1_MASK | 7902bc4ef71SPaul Walmsley OMAP3430_AUTO_I2C3_MASK | 7912bc4ef71SPaul Walmsley OMAP3430_AUTO_I2C2_MASK | 7922bc4ef71SPaul Walmsley OMAP3430_AUTO_I2C1_MASK | 7932bc4ef71SPaul Walmsley OMAP3430_AUTO_UART2_MASK | 7942bc4ef71SPaul Walmsley OMAP3430_AUTO_UART1_MASK | 7952bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT11_MASK | 7962bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT10_MASK | 7972bc4ef71SPaul Walmsley OMAP3430_AUTO_MCBSP5_MASK | 7982bc4ef71SPaul Walmsley OMAP3430_AUTO_MCBSP1_MASK | 7992bc4ef71SPaul Walmsley OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */ 8002bc4ef71SPaul Walmsley OMAP3430_AUTO_MAILBOXES_MASK | 8012bc4ef71SPaul Walmsley OMAP3430_AUTO_OMAPCTRL_MASK | 8022bc4ef71SPaul Walmsley OMAP3430ES1_AUTO_FSHOSTUSB_MASK | 8032bc4ef71SPaul Walmsley OMAP3430_AUTO_HSOTGUSB_MASK | 8042bc4ef71SPaul Walmsley OMAP3430_AUTO_SAD2D_MASK | 8052bc4ef71SPaul Walmsley OMAP3430_AUTO_SSI_MASK, 8068bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE1); 8078bd22949SKevin Hilman 8088bd22949SKevin Hilman cm_write_mod_reg( 8092bc4ef71SPaul Walmsley OMAP3430_AUTO_PKA_MASK | 8102bc4ef71SPaul Walmsley OMAP3430_AUTO_AES1_MASK | 8112bc4ef71SPaul Walmsley OMAP3430_AUTO_RNG_MASK | 8122bc4ef71SPaul Walmsley OMAP3430_AUTO_SHA11_MASK | 8132bc4ef71SPaul Walmsley OMAP3430_AUTO_DES1_MASK, 8148bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE2); 8158bd22949SKevin Hilman 8168bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 8178bd22949SKevin Hilman cm_write_mod_reg( 8182bc4ef71SPaul Walmsley OMAP3430_AUTO_MAD2D_MASK | 8192bc4ef71SPaul Walmsley OMAP3430ES2_AUTO_USBTLL_MASK, 8208bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE3); 8218bd22949SKevin Hilman } 8228bd22949SKevin Hilman 8238bd22949SKevin Hilman cm_write_mod_reg( 8242bc4ef71SPaul Walmsley OMAP3430_AUTO_WDT2_MASK | 8252bc4ef71SPaul Walmsley OMAP3430_AUTO_WDT1_MASK | 8262bc4ef71SPaul Walmsley OMAP3430_AUTO_GPIO1_MASK | 8272bc4ef71SPaul Walmsley OMAP3430_AUTO_32KSYNC_MASK | 8282bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT12_MASK | 8292bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT1_MASK, 8308bd22949SKevin Hilman WKUP_MOD, CM_AUTOIDLE); 8318bd22949SKevin Hilman 8328bd22949SKevin Hilman cm_write_mod_reg( 8332bc4ef71SPaul Walmsley OMAP3430_AUTO_DSS_MASK, 8348bd22949SKevin Hilman OMAP3430_DSS_MOD, 8358bd22949SKevin Hilman CM_AUTOIDLE); 8368bd22949SKevin Hilman 8378bd22949SKevin Hilman cm_write_mod_reg( 8382bc4ef71SPaul Walmsley OMAP3430_AUTO_CAM_MASK, 8398bd22949SKevin Hilman OMAP3430_CAM_MOD, 8408bd22949SKevin Hilman CM_AUTOIDLE); 8418bd22949SKevin Hilman 8428bd22949SKevin Hilman cm_write_mod_reg( 8432bc4ef71SPaul Walmsley OMAP3430_AUTO_GPIO6_MASK | 8442bc4ef71SPaul Walmsley OMAP3430_AUTO_GPIO5_MASK | 8452bc4ef71SPaul Walmsley OMAP3430_AUTO_GPIO4_MASK | 8462bc4ef71SPaul Walmsley OMAP3430_AUTO_GPIO3_MASK | 8472bc4ef71SPaul Walmsley OMAP3430_AUTO_GPIO2_MASK | 8482bc4ef71SPaul Walmsley OMAP3430_AUTO_WDT3_MASK | 8492bc4ef71SPaul Walmsley OMAP3430_AUTO_UART3_MASK | 8502bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT9_MASK | 8512bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT8_MASK | 8522bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT7_MASK | 8532bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT6_MASK | 8542bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT5_MASK | 8552bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT4_MASK | 8562bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT3_MASK | 8572bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT2_MASK | 8582bc4ef71SPaul Walmsley OMAP3430_AUTO_MCBSP4_MASK | 8592bc4ef71SPaul Walmsley OMAP3430_AUTO_MCBSP3_MASK | 8602bc4ef71SPaul Walmsley OMAP3430_AUTO_MCBSP2_MASK, 8618bd22949SKevin Hilman OMAP3430_PER_MOD, 8628bd22949SKevin Hilman CM_AUTOIDLE); 8638bd22949SKevin Hilman 8648bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 8658bd22949SKevin Hilman cm_write_mod_reg( 8662bc4ef71SPaul Walmsley OMAP3430ES2_AUTO_USBHOST_MASK, 8678bd22949SKevin Hilman OMAP3430ES2_USBHOST_MOD, 8688bd22949SKevin Hilman CM_AUTOIDLE); 8698bd22949SKevin Hilman } 8708bd22949SKevin Hilman 8712fd0f75cSPaul Walmsley omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); 872b296c811STero Kristo 8738bd22949SKevin Hilman /* 8748bd22949SKevin Hilman * Set all plls to autoidle. This is needed until autoidle is 8758bd22949SKevin Hilman * enabled by clockfw 8768bd22949SKevin Hilman */ 8778bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, 8788bd22949SKevin Hilman OMAP3430_IVA2_MOD, CM_AUTOIDLE2); 8798bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT, 8808bd22949SKevin Hilman MPU_MOD, 8818bd22949SKevin Hilman CM_AUTOIDLE2); 8828bd22949SKevin Hilman cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | 8838bd22949SKevin Hilman (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT), 8848bd22949SKevin Hilman PLL_MOD, 8858bd22949SKevin Hilman CM_AUTOIDLE); 8868bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, 8878bd22949SKevin Hilman PLL_MOD, 8888bd22949SKevin Hilman CM_AUTOIDLE2); 8898bd22949SKevin Hilman 8908bd22949SKevin Hilman /* 8918bd22949SKevin Hilman * Enable control of expternal oscillator through 8928bd22949SKevin Hilman * sys_clkreq. In the long run clock framework should 8938bd22949SKevin Hilman * take care of this. 8948bd22949SKevin Hilman */ 8958bd22949SKevin Hilman prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 8968bd22949SKevin Hilman 1 << OMAP_AUTOEXTCLKMODE_SHIFT, 8978bd22949SKevin Hilman OMAP3430_GR_MOD, 8988bd22949SKevin Hilman OMAP3_PRM_CLKSRC_CTRL_OFFSET); 8998bd22949SKevin Hilman 9008bd22949SKevin Hilman /* setup wakup source */ 9012fd0f75cSPaul Walmsley prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | 9022fd0f75cSPaul Walmsley OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, 9038bd22949SKevin Hilman WKUP_MOD, PM_WKEN); 9048bd22949SKevin Hilman /* No need to write EN_IO, that is always enabled */ 905275f675cSPaul Walmsley prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | 906275f675cSPaul Walmsley OMAP3430_GRPSEL_GPT1_MASK | 907275f675cSPaul Walmsley OMAP3430_GRPSEL_GPT12_MASK, 9088bd22949SKevin Hilman WKUP_MOD, OMAP3430_PM_MPUGRPSEL); 9098bd22949SKevin Hilman /* For some reason IO doesn't generate wakeup event even if 9108bd22949SKevin Hilman * it is selected to mpu wakeup goup */ 9112bc4ef71SPaul Walmsley prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK, 9128bd22949SKevin Hilman OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); 9131155e426SKevin Hilman 914b92c5721SSubramani Venkatesh /* Enable PM_WKEN to support DSS LPR */ 9152bc4ef71SPaul Walmsley prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, 916b92c5721SSubramani Venkatesh OMAP3430_DSS_MOD, PM_WKEN); 917b92c5721SSubramani Venkatesh 918b427f92fSKevin Hilman /* Enable wakeups in PER */ 9192fd0f75cSPaul Walmsley prm_write_mod_reg(OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | 9202fd0f75cSPaul Walmsley OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | 9212fd0f75cSPaul Walmsley OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | 9222fd0f75cSPaul Walmsley OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK | 9232fd0f75cSPaul Walmsley OMAP3430_EN_MCBSP4_MASK, 924b427f92fSKevin Hilman OMAP3430_PER_MOD, PM_WKEN); 925eb350f74SKevin Hilman /* and allow them to wake up MPU */ 926275f675cSPaul Walmsley prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2_MASK | 927275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO3_MASK | 928275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO4_MASK | 929275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO5_MASK | 930275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO6_MASK | 931275f675cSPaul Walmsley OMAP3430_GRPSEL_UART3_MASK | 932275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP2_MASK | 933275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP3_MASK | 934275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP4_MASK, 935eb350f74SKevin Hilman OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); 936eb350f74SKevin Hilman 937d3fd3290SKevin Hilman /* Don't attach IVA interrupts */ 938d3fd3290SKevin Hilman prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 939d3fd3290SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 940d3fd3290SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 941d3fd3290SKevin Hilman prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); 942d3fd3290SKevin Hilman 943b1340d17SKevin Hilman /* Clear any pending 'reset' flags */ 94437903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); 94537903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); 94637903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); 94737903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); 94837903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); 94937903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); 95037903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); 951b1340d17SKevin Hilman 952014c46dbSKevin Hilman /* Clear any pending PRCM interrupts */ 953014c46dbSKevin Hilman prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 954014c46dbSKevin Hilman 9551155e426SKevin Hilman omap3_iva_idle(); 9568111b221SKevin Hilman omap3_d2d_idle(); 9578bd22949SKevin Hilman } 9588bd22949SKevin Hilman 959c40552bcSKevin Hilman void omap3_pm_off_mode_enable(int enable) 960c40552bcSKevin Hilman { 961c40552bcSKevin Hilman struct power_state *pwrst; 962c40552bcSKevin Hilman u32 state; 963c40552bcSKevin Hilman 964c40552bcSKevin Hilman if (enable) 965c40552bcSKevin Hilman state = PWRDM_POWER_OFF; 966c40552bcSKevin Hilman else 967c40552bcSKevin Hilman state = PWRDM_POWER_RET; 968c40552bcSKevin Hilman 9696af83b38SSanjeev Premi #ifdef CONFIG_CPU_IDLE 9706af83b38SSanjeev Premi omap3_cpuidle_update_states(); 9716af83b38SSanjeev Premi #endif 9726af83b38SSanjeev Premi 973c40552bcSKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 974c40552bcSKevin Hilman pwrst->next_state = state; 975c40552bcSKevin Hilman set_pwrdm_state(pwrst->pwrdm, state); 976c40552bcSKevin Hilman } 977c40552bcSKevin Hilman } 978c40552bcSKevin Hilman 97968d4778cSTero Kristo int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) 98068d4778cSTero Kristo { 98168d4778cSTero Kristo struct power_state *pwrst; 98268d4778cSTero Kristo 98368d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 98468d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) 98568d4778cSTero Kristo return pwrst->next_state; 98668d4778cSTero Kristo } 98768d4778cSTero Kristo return -EINVAL; 98868d4778cSTero Kristo } 98968d4778cSTero Kristo 99068d4778cSTero Kristo int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) 99168d4778cSTero Kristo { 99268d4778cSTero Kristo struct power_state *pwrst; 99368d4778cSTero Kristo 99468d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 99568d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) { 99668d4778cSTero Kristo pwrst->next_state = state; 99768d4778cSTero Kristo return 0; 99868d4778cSTero Kristo } 99968d4778cSTero Kristo } 100068d4778cSTero Kristo return -EINVAL; 100168d4778cSTero Kristo } 100268d4778cSTero Kristo 1003a23456e9SPeter 'p2' De Schrijver static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) 10048bd22949SKevin Hilman { 10058bd22949SKevin Hilman struct power_state *pwrst; 10068bd22949SKevin Hilman 10078bd22949SKevin Hilman if (!pwrdm->pwrsts) 10088bd22949SKevin Hilman return 0; 10098bd22949SKevin Hilman 1010d3d381c6SMing Lei pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); 10118bd22949SKevin Hilman if (!pwrst) 10128bd22949SKevin Hilman return -ENOMEM; 10138bd22949SKevin Hilman pwrst->pwrdm = pwrdm; 10148bd22949SKevin Hilman pwrst->next_state = PWRDM_POWER_RET; 10158bd22949SKevin Hilman list_add(&pwrst->node, &pwrst_list); 10168bd22949SKevin Hilman 10178bd22949SKevin Hilman if (pwrdm_has_hdwr_sar(pwrdm)) 10188bd22949SKevin Hilman pwrdm_enable_hdwr_sar(pwrdm); 10198bd22949SKevin Hilman 10208bd22949SKevin Hilman return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 10218bd22949SKevin Hilman } 10228bd22949SKevin Hilman 10238bd22949SKevin Hilman /* 10248bd22949SKevin Hilman * Enable hw supervised mode for all clockdomains if it's 10258bd22949SKevin Hilman * supported. Initiate sleep transition for other clockdomains, if 10268bd22949SKevin Hilman * they are not used 10278bd22949SKevin Hilman */ 1028a23456e9SPeter 'p2' De Schrijver static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) 10298bd22949SKevin Hilman { 1030369d5614SPaul Walmsley clkdm_clear_all_wkdeps(clkdm); 1031369d5614SPaul Walmsley clkdm_clear_all_sleepdeps(clkdm); 1032369d5614SPaul Walmsley 10338bd22949SKevin Hilman if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) 10348bd22949SKevin Hilman omap2_clkdm_allow_idle(clkdm); 10358bd22949SKevin Hilman else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && 10368bd22949SKevin Hilman atomic_read(&clkdm->usecount) == 0) 10378bd22949SKevin Hilman omap2_clkdm_sleep(clkdm); 10388bd22949SKevin Hilman return 0; 10398bd22949SKevin Hilman } 10408bd22949SKevin Hilman 10413231fc88SRajendra Nayak void omap_push_sram_idle(void) 10423231fc88SRajendra Nayak { 10433231fc88SRajendra Nayak _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend, 10443231fc88SRajendra Nayak omap34xx_cpu_suspend_sz); 104527d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) 104627d59a4aSTero Kristo _omap_save_secure_sram = omap_sram_push(save_secure_ram_context, 104727d59a4aSTero Kristo save_secure_ram_context_sz); 10483231fc88SRajendra Nayak } 10493231fc88SRajendra Nayak 10507cc515f7SKevin Hilman static int __init omap3_pm_init(void) 10518bd22949SKevin Hilman { 10528bd22949SKevin Hilman struct power_state *pwrst, *tmp; 105355ed9694SPaul Walmsley struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm; 10548bd22949SKevin Hilman int ret; 10558bd22949SKevin Hilman 10568bd22949SKevin Hilman if (!cpu_is_omap34xx()) 10578bd22949SKevin Hilman return -ENODEV; 10588bd22949SKevin Hilman 10598bd22949SKevin Hilman printk(KERN_ERR "Power Management for TI OMAP3.\n"); 10608bd22949SKevin Hilman 10618bd22949SKevin Hilman /* XXX prcm_setup_regs needs to be before enabling hw 10628bd22949SKevin Hilman * supervised mode for powerdomains */ 10638bd22949SKevin Hilman prcm_setup_regs(); 10648bd22949SKevin Hilman 10658bd22949SKevin Hilman ret = request_irq(INT_34XX_PRCM_MPU_IRQ, 10668bd22949SKevin Hilman (irq_handler_t)prcm_interrupt_handler, 10678bd22949SKevin Hilman IRQF_DISABLED, "prcm", NULL); 10688bd22949SKevin Hilman if (ret) { 10698bd22949SKevin Hilman printk(KERN_ERR "request_irq failed to register for 0x%x\n", 10708bd22949SKevin Hilman INT_34XX_PRCM_MPU_IRQ); 10718bd22949SKevin Hilman goto err1; 10728bd22949SKevin Hilman } 10738bd22949SKevin Hilman 1074a23456e9SPeter 'p2' De Schrijver ret = pwrdm_for_each(pwrdms_setup, NULL); 10758bd22949SKevin Hilman if (ret) { 10768bd22949SKevin Hilman printk(KERN_ERR "Failed to setup powerdomains\n"); 10778bd22949SKevin Hilman goto err2; 10788bd22949SKevin Hilman } 10798bd22949SKevin Hilman 1080a23456e9SPeter 'p2' De Schrijver (void) clkdm_for_each(clkdms_setup, NULL); 10818bd22949SKevin Hilman 10828bd22949SKevin Hilman mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); 10838bd22949SKevin Hilman if (mpu_pwrdm == NULL) { 10848bd22949SKevin Hilman printk(KERN_ERR "Failed to get mpu_pwrdm\n"); 10858bd22949SKevin Hilman goto err2; 10868bd22949SKevin Hilman } 10878bd22949SKevin Hilman 1088fa3c2a4fSRajendra Nayak neon_pwrdm = pwrdm_lookup("neon_pwrdm"); 1089fa3c2a4fSRajendra Nayak per_pwrdm = pwrdm_lookup("per_pwrdm"); 1090fa3c2a4fSRajendra Nayak core_pwrdm = pwrdm_lookup("core_pwrdm"); 1091c16c3f67STero Kristo cam_pwrdm = pwrdm_lookup("cam_pwrdm"); 1092fa3c2a4fSRajendra Nayak 109355ed9694SPaul Walmsley neon_clkdm = clkdm_lookup("neon_clkdm"); 109455ed9694SPaul Walmsley mpu_clkdm = clkdm_lookup("mpu_clkdm"); 109555ed9694SPaul Walmsley per_clkdm = clkdm_lookup("per_clkdm"); 109655ed9694SPaul Walmsley core_clkdm = clkdm_lookup("core_clkdm"); 109755ed9694SPaul Walmsley 10983231fc88SRajendra Nayak omap_push_sram_idle(); 109910f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 11008bd22949SKevin Hilman suspend_set_ops(&omap_pm_ops); 110110f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 11028bd22949SKevin Hilman 11038bd22949SKevin Hilman pm_idle = omap3_pm_idle; 11040343371eSKalle Jokiniemi omap3_idle_init(); 11058bd22949SKevin Hilman 110655ed9694SPaul Walmsley clkdm_add_wkdep(neon_clkdm, mpu_clkdm); 110727d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 110827d59a4aSTero Kristo omap3_secure_ram_storage = 110927d59a4aSTero Kristo kmalloc(0x803F, GFP_KERNEL); 111027d59a4aSTero Kristo if (!omap3_secure_ram_storage) 111127d59a4aSTero Kristo printk(KERN_ERR "Memory allocation failed when" 111227d59a4aSTero Kristo "allocating for secure sram context\n"); 111327d59a4aSTero Kristo 11149d97140bSTero Kristo local_irq_disable(); 11159d97140bSTero Kristo local_fiq_disable(); 11169d97140bSTero Kristo 11179d97140bSTero Kristo omap_dma_global_context_save(); 11189d97140bSTero Kristo omap3_save_secure_ram_context(PWRDM_POWER_ON); 11199d97140bSTero Kristo omap_dma_global_context_restore(); 11209d97140bSTero Kristo 11219d97140bSTero Kristo local_irq_enable(); 11229d97140bSTero Kristo local_fiq_enable(); 11239d97140bSTero Kristo } 11249d97140bSTero Kristo 11259d97140bSTero Kristo omap3_save_scratchpad_contents(); 11268bd22949SKevin Hilman err1: 11278bd22949SKevin Hilman return ret; 11288bd22949SKevin Hilman err2: 11298bd22949SKevin Hilman free_irq(INT_34XX_PRCM_MPU_IRQ, NULL); 11308bd22949SKevin Hilman list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { 11318bd22949SKevin Hilman list_del(&pwrst->node); 11328bd22949SKevin Hilman kfree(pwrst); 11338bd22949SKevin Hilman } 11348bd22949SKevin Hilman return ret; 11358bd22949SKevin Hilman } 11368bd22949SKevin Hilman 11378bd22949SKevin Hilman late_initcall(omap3_pm_init); 1138