18bd22949SKevin Hilman /* 28bd22949SKevin Hilman * OMAP3 Power Management Routines 38bd22949SKevin Hilman * 48bd22949SKevin Hilman * Copyright (C) 2006-2008 Nokia Corporation 58bd22949SKevin Hilman * Tony Lindgren <tony@atomide.com> 68bd22949SKevin Hilman * Jouni Hogander 78bd22949SKevin Hilman * 82f5939c3SRajendra Nayak * Copyright (C) 2007 Texas Instruments, Inc. 92f5939c3SRajendra Nayak * Rajendra Nayak <rnayak@ti.com> 102f5939c3SRajendra Nayak * 118bd22949SKevin Hilman * Copyright (C) 2005 Texas Instruments, Inc. 128bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 138bd22949SKevin Hilman * 148bd22949SKevin Hilman * Based on pm.c for omap1 158bd22949SKevin Hilman * 168bd22949SKevin Hilman * This program is free software; you can redistribute it and/or modify 178bd22949SKevin Hilman * it under the terms of the GNU General Public License version 2 as 188bd22949SKevin Hilman * published by the Free Software Foundation. 198bd22949SKevin Hilman */ 208bd22949SKevin Hilman 218bd22949SKevin Hilman #include <linux/pm.h> 228bd22949SKevin Hilman #include <linux/suspend.h> 238bd22949SKevin Hilman #include <linux/interrupt.h> 248bd22949SKevin Hilman #include <linux/module.h> 258bd22949SKevin Hilman #include <linux/list.h> 268bd22949SKevin Hilman #include <linux/err.h> 278bd22949SKevin Hilman #include <linux/gpio.h> 28c40552bcSKevin Hilman #include <linux/clk.h> 29dccaad89STero Kristo #include <linux/delay.h> 305a0e3ad6STejun Heo #include <linux/slab.h> 310d8e2d0dSPaul Walmsley #include <linux/console.h> 328bd22949SKevin Hilman 33ce491cf8STony Lindgren #include <plat/sram.h> 34ce491cf8STony Lindgren #include <plat/clockdomain.h> 35ce491cf8STony Lindgren #include <plat/powerdomain.h> 36ce491cf8STony Lindgren #include <plat/serial.h> 3761255ab9SRajendra Nayak #include <plat/sdrc.h> 382f5939c3SRajendra Nayak #include <plat/prcm.h> 392f5939c3SRajendra Nayak #include <plat/gpmc.h> 40f2d11858STero Kristo #include <plat/dma.h> 418bd22949SKevin Hilman 4257f277b0SRajendra Nayak #include <asm/tlbflush.h> 4357f277b0SRajendra Nayak 448bd22949SKevin Hilman #include "cm.h" 458bd22949SKevin Hilman #include "cm-regbits-34xx.h" 468bd22949SKevin Hilman #include "prm-regbits-34xx.h" 478bd22949SKevin Hilman 488bd22949SKevin Hilman #include "prm.h" 498bd22949SKevin Hilman #include "pm.h" 5013a6fe0fSTero Kristo #include "sdrc.h" 514814ced5SPaul Walmsley #include "control.h" 5213a6fe0fSTero Kristo 53e83df17fSKevin Hilman #ifdef CONFIG_SUSPEND 54e83df17fSKevin Hilman static suspend_state_t suspend_state = PM_SUSPEND_ON; 55e83df17fSKevin Hilman static inline bool is_suspending(void) 56e83df17fSKevin Hilman { 57e83df17fSKevin Hilman return (suspend_state != PM_SUSPEND_ON); 58e83df17fSKevin Hilman } 59e83df17fSKevin Hilman #else 60e83df17fSKevin Hilman static inline bool is_suspending(void) 61e83df17fSKevin Hilman { 62e83df17fSKevin Hilman return false; 63e83df17fSKevin Hilman } 64e83df17fSKevin Hilman #endif 65e83df17fSKevin Hilman 662f5939c3SRajendra Nayak /* Scratchpad offsets */ 67de658158SKevin Hilman #define OMAP343X_TABLE_ADDRESS_OFFSET 0xc4 68de658158SKevin Hilman #define OMAP343X_TABLE_VALUE_OFFSET 0xc0 69de658158SKevin Hilman #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8 702f5939c3SRajendra Nayak 718cdfd834SNishanth Menon /* pm34xx errata defined in pm.h */ 728cdfd834SNishanth Menon u16 pm34xx_errata; 738cdfd834SNishanth Menon 748bd22949SKevin Hilman struct power_state { 758bd22949SKevin Hilman struct powerdomain *pwrdm; 768bd22949SKevin Hilman u32 next_state; 7710f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 788bd22949SKevin Hilman u32 saved_state; 7910f90ed2SKevin Hilman #endif 808bd22949SKevin Hilman struct list_head node; 818bd22949SKevin Hilman }; 828bd22949SKevin Hilman 838bd22949SKevin Hilman static LIST_HEAD(pwrst_list); 848bd22949SKevin Hilman 858bd22949SKevin Hilman static void (*_omap_sram_idle)(u32 *addr, int save_state); 868bd22949SKevin Hilman 8727d59a4aSTero Kristo static int (*_omap_save_secure_sram)(u32 *addr); 8827d59a4aSTero Kristo 89fa3c2a4fSRajendra Nayak static struct powerdomain *mpu_pwrdm, *neon_pwrdm; 90fa3c2a4fSRajendra Nayak static struct powerdomain *core_pwrdm, *per_pwrdm; 91c16c3f67STero Kristo static struct powerdomain *cam_pwrdm; 92fa3c2a4fSRajendra Nayak 932f5939c3SRajendra Nayak static inline void omap3_per_save_context(void) 942f5939c3SRajendra Nayak { 952f5939c3SRajendra Nayak omap_gpio_save_context(); 962f5939c3SRajendra Nayak } 972f5939c3SRajendra Nayak 982f5939c3SRajendra Nayak static inline void omap3_per_restore_context(void) 992f5939c3SRajendra Nayak { 1002f5939c3SRajendra Nayak omap_gpio_restore_context(); 1012f5939c3SRajendra Nayak } 1022f5939c3SRajendra Nayak 1033a7ec26bSKalle Jokiniemi static void omap3_enable_io_chain(void) 1043a7ec26bSKalle Jokiniemi { 1053a7ec26bSKalle Jokiniemi int timeout = 0; 1063a7ec26bSKalle Jokiniemi 1073a7ec26bSKalle Jokiniemi if (omap_rev() >= OMAP3430_REV_ES3_1) { 1082bc4ef71SPaul Walmsley prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, 1092bc4ef71SPaul Walmsley PM_WKEN); 1103a7ec26bSKalle Jokiniemi /* Do a readback to assure write has been done */ 1113a7ec26bSKalle Jokiniemi prm_read_mod_reg(WKUP_MOD, PM_WKEN); 1123a7ec26bSKalle Jokiniemi 1130b96a3a3SKevin Hilman while (!(prm_read_mod_reg(WKUP_MOD, PM_WKEN) & 1142bc4ef71SPaul Walmsley OMAP3430_ST_IO_CHAIN_MASK)) { 1153a7ec26bSKalle Jokiniemi timeout++; 1163a7ec26bSKalle Jokiniemi if (timeout > 1000) { 1173a7ec26bSKalle Jokiniemi printk(KERN_ERR "Wake up daisy chain " 1183a7ec26bSKalle Jokiniemi "activation failed.\n"); 1193a7ec26bSKalle Jokiniemi return; 1203a7ec26bSKalle Jokiniemi } 1212bc4ef71SPaul Walmsley prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, 1220b96a3a3SKevin Hilman WKUP_MOD, PM_WKEN); 1233a7ec26bSKalle Jokiniemi } 1243a7ec26bSKalle Jokiniemi } 1253a7ec26bSKalle Jokiniemi } 1263a7ec26bSKalle Jokiniemi 1273a7ec26bSKalle Jokiniemi static void omap3_disable_io_chain(void) 1283a7ec26bSKalle Jokiniemi { 1293a7ec26bSKalle Jokiniemi if (omap_rev() >= OMAP3430_REV_ES3_1) 1302bc4ef71SPaul Walmsley prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, 1312bc4ef71SPaul Walmsley PM_WKEN); 1323a7ec26bSKalle Jokiniemi } 1333a7ec26bSKalle Jokiniemi 1342f5939c3SRajendra Nayak static void omap3_core_save_context(void) 1352f5939c3SRajendra Nayak { 1362f5939c3SRajendra Nayak u32 control_padconf_off; 1372f5939c3SRajendra Nayak 1382f5939c3SRajendra Nayak /* Save the padconf registers */ 1392f5939c3SRajendra Nayak control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF); 1402f5939c3SRajendra Nayak control_padconf_off |= START_PADCONF_SAVE; 1412f5939c3SRajendra Nayak omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF); 1422f5939c3SRajendra Nayak /* wait for the save to complete */ 1431b6e821fSRoel Kluin while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) 1441b6e821fSRoel Kluin & PADCONF_SAVE_DONE)) 145dccaad89STero Kristo udelay(1); 146dccaad89STero Kristo 147dccaad89STero Kristo /* 148dccaad89STero Kristo * Force write last pad into memory, as this can fail in some 14983521291SJean Pihet * cases according to errata 1.157, 1.185 150dccaad89STero Kristo */ 151dccaad89STero Kristo omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), 152dccaad89STero Kristo OMAP343X_CONTROL_MEM_WKUP + 0x2a0); 153dccaad89STero Kristo 1542f5939c3SRajendra Nayak /* Save the Interrupt controller context */ 1552f5939c3SRajendra Nayak omap_intc_save_context(); 1562f5939c3SRajendra Nayak /* Save the GPMC context */ 1572f5939c3SRajendra Nayak omap3_gpmc_save_context(); 1582f5939c3SRajendra Nayak /* Save the system control module context, padconf already save above*/ 1592f5939c3SRajendra Nayak omap3_control_save_context(); 160f2d11858STero Kristo omap_dma_global_context_save(); 1612f5939c3SRajendra Nayak } 1622f5939c3SRajendra Nayak 1632f5939c3SRajendra Nayak static void omap3_core_restore_context(void) 1642f5939c3SRajendra Nayak { 1652f5939c3SRajendra Nayak /* Restore the control module context, padconf restored by h/w */ 1662f5939c3SRajendra Nayak omap3_control_restore_context(); 1672f5939c3SRajendra Nayak /* Restore the GPMC context */ 1682f5939c3SRajendra Nayak omap3_gpmc_restore_context(); 1692f5939c3SRajendra Nayak /* Restore the interrupt controller context */ 1702f5939c3SRajendra Nayak omap_intc_restore_context(); 171f2d11858STero Kristo omap_dma_global_context_restore(); 1722f5939c3SRajendra Nayak } 1732f5939c3SRajendra Nayak 1749d97140bSTero Kristo /* 1759d97140bSTero Kristo * FIXME: This function should be called before entering off-mode after 1769d97140bSTero Kristo * OMAP3 secure services have been accessed. Currently it is only called 1779d97140bSTero Kristo * once during boot sequence, but this works as we are not using secure 1789d97140bSTero Kristo * services. 1799d97140bSTero Kristo */ 18027d59a4aSTero Kristo static void omap3_save_secure_ram_context(u32 target_mpu_state) 18127d59a4aSTero Kristo { 18227d59a4aSTero Kristo u32 ret; 18327d59a4aSTero Kristo 18427d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 18527d59a4aSTero Kristo /* 18627d59a4aSTero Kristo * MPU next state must be set to POWER_ON temporarily, 18727d59a4aSTero Kristo * otherwise the WFI executed inside the ROM code 18827d59a4aSTero Kristo * will hang the system. 18927d59a4aSTero Kristo */ 19027d59a4aSTero Kristo pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); 19127d59a4aSTero Kristo ret = _omap_save_secure_sram((u32 *) 19227d59a4aSTero Kristo __pa(omap3_secure_ram_storage)); 19327d59a4aSTero Kristo pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state); 19427d59a4aSTero Kristo /* Following is for error tracking, it should not happen */ 19527d59a4aSTero Kristo if (ret) { 19627d59a4aSTero Kristo printk(KERN_ERR "save_secure_sram() returns %08x\n", 19727d59a4aSTero Kristo ret); 19827d59a4aSTero Kristo while (1) 19927d59a4aSTero Kristo ; 20027d59a4aSTero Kristo } 20127d59a4aSTero Kristo } 20227d59a4aSTero Kristo } 20327d59a4aSTero Kristo 20477da2d91SJon Hunter /* 20577da2d91SJon Hunter * PRCM Interrupt Handler Helper Function 20677da2d91SJon Hunter * 20777da2d91SJon Hunter * The purpose of this function is to clear any wake-up events latched 20877da2d91SJon Hunter * in the PRCM PM_WKST_x registers. It is possible that a wake-up event 20977da2d91SJon Hunter * may occur whilst attempting to clear a PM_WKST_x register and thus 21077da2d91SJon Hunter * set another bit in this register. A while loop is used to ensure 21177da2d91SJon Hunter * that any peripheral wake-up events occurring while attempting to 21277da2d91SJon Hunter * clear the PM_WKST_x are detected and cleared. 21377da2d91SJon Hunter */ 2148cb0ac99SPaul Walmsley static int prcm_clear_mod_irqs(s16 module, u8 regs) 21577da2d91SJon Hunter { 21671a80775SVikram Pandita u32 wkst, fclk, iclk, clken; 21777da2d91SJon Hunter u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; 21877da2d91SJon Hunter u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; 21977da2d91SJon Hunter u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; 2205d805978SPaul Walmsley u16 grpsel_off = (regs == 3) ? 2215d805978SPaul Walmsley OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; 2228cb0ac99SPaul Walmsley int c = 0; 22377da2d91SJon Hunter 22477da2d91SJon Hunter wkst = prm_read_mod_reg(module, wkst_off); 2255d805978SPaul Walmsley wkst &= prm_read_mod_reg(module, grpsel_off); 22677da2d91SJon Hunter if (wkst) { 22777da2d91SJon Hunter iclk = cm_read_mod_reg(module, iclk_off); 22877da2d91SJon Hunter fclk = cm_read_mod_reg(module, fclk_off); 22977da2d91SJon Hunter while (wkst) { 23071a80775SVikram Pandita clken = wkst; 23171a80775SVikram Pandita cm_set_mod_reg_bits(clken, module, iclk_off); 23271a80775SVikram Pandita /* 23371a80775SVikram Pandita * For USBHOST, we don't know whether HOST1 or 23471a80775SVikram Pandita * HOST2 woke us up, so enable both f-clocks 23571a80775SVikram Pandita */ 23671a80775SVikram Pandita if (module == OMAP3430ES2_USBHOST_MOD) 23771a80775SVikram Pandita clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; 23871a80775SVikram Pandita cm_set_mod_reg_bits(clken, module, fclk_off); 23977da2d91SJon Hunter prm_write_mod_reg(wkst, module, wkst_off); 24077da2d91SJon Hunter wkst = prm_read_mod_reg(module, wkst_off); 2418cb0ac99SPaul Walmsley c++; 24277da2d91SJon Hunter } 24377da2d91SJon Hunter cm_write_mod_reg(iclk, module, iclk_off); 24477da2d91SJon Hunter cm_write_mod_reg(fclk, module, fclk_off); 24577da2d91SJon Hunter } 2468cb0ac99SPaul Walmsley 2478cb0ac99SPaul Walmsley return c; 2488cb0ac99SPaul Walmsley } 2498cb0ac99SPaul Walmsley 2508cb0ac99SPaul Walmsley static int _prcm_int_handle_wakeup(void) 2518cb0ac99SPaul Walmsley { 2528cb0ac99SPaul Walmsley int c; 2538cb0ac99SPaul Walmsley 2548cb0ac99SPaul Walmsley c = prcm_clear_mod_irqs(WKUP_MOD, 1); 2558cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(CORE_MOD, 1); 2568cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1); 2578cb0ac99SPaul Walmsley if (omap_rev() > OMAP3430_REV_ES1_0) { 2588cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(CORE_MOD, 3); 2598cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1); 2608cb0ac99SPaul Walmsley } 2618cb0ac99SPaul Walmsley 2628cb0ac99SPaul Walmsley return c; 26377da2d91SJon Hunter } 26477da2d91SJon Hunter 26577da2d91SJon Hunter /* 26677da2d91SJon Hunter * PRCM Interrupt Handler 26777da2d91SJon Hunter * 26877da2d91SJon Hunter * The PRM_IRQSTATUS_MPU register indicates if there are any pending 26977da2d91SJon Hunter * interrupts from the PRCM for the MPU. These bits must be cleared in 27077da2d91SJon Hunter * order to clear the PRCM interrupt. The PRCM interrupt handler is 27177da2d91SJon Hunter * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear 27277da2d91SJon Hunter * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU 27377da2d91SJon Hunter * register indicates that a wake-up event is pending for the MPU and 27477da2d91SJon Hunter * this bit can only be cleared if the all the wake-up events latched 27577da2d91SJon Hunter * in the various PM_WKST_x registers have been cleared. The interrupt 27677da2d91SJon Hunter * handler is implemented using a do-while loop so that if a wake-up 27777da2d91SJon Hunter * event occurred during the processing of the prcm interrupt handler 27877da2d91SJon Hunter * (setting a bit in the corresponding PM_WKST_x register and thus 27977da2d91SJon Hunter * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register) 28077da2d91SJon Hunter * this would be handled. 28177da2d91SJon Hunter */ 2828bd22949SKevin Hilman static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) 2838bd22949SKevin Hilman { 284d6290a3eSKevin Hilman u32 irqenable_mpu, irqstatus_mpu; 2858cb0ac99SPaul Walmsley int c = 0; 2868bd22949SKevin Hilman 287d6290a3eSKevin Hilman irqenable_mpu = prm_read_mod_reg(OCP_MOD, 288d6290a3eSKevin Hilman OMAP3_PRM_IRQENABLE_MPU_OFFSET); 2898bd22949SKevin Hilman irqstatus_mpu = prm_read_mod_reg(OCP_MOD, 2908bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 291d6290a3eSKevin Hilman irqstatus_mpu &= irqenable_mpu; 2928cb0ac99SPaul Walmsley 293d6290a3eSKevin Hilman do { 2942bc4ef71SPaul Walmsley if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK | 2952bc4ef71SPaul Walmsley OMAP3430_IO_ST_MASK)) { 2968cb0ac99SPaul Walmsley c = _prcm_int_handle_wakeup(); 2978cb0ac99SPaul Walmsley 2988cb0ac99SPaul Walmsley /* 2998cb0ac99SPaul Walmsley * Is the MPU PRCM interrupt handler racing with the 3008cb0ac99SPaul Walmsley * IVA2 PRCM interrupt handler ? 3018cb0ac99SPaul Walmsley */ 3028cb0ac99SPaul Walmsley WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup " 3038cb0ac99SPaul Walmsley "but no wakeup sources are marked\n"); 3048cb0ac99SPaul Walmsley } else { 3058cb0ac99SPaul Walmsley /* XXX we need to expand our PRCM interrupt handler */ 3068cb0ac99SPaul Walmsley WARN(1, "prcm: WARNING: PRCM interrupt received, but " 3078cb0ac99SPaul Walmsley "no code to handle it (%08x)\n", irqstatus_mpu); 3088cb0ac99SPaul Walmsley } 3098cb0ac99SPaul Walmsley 3108bd22949SKevin Hilman prm_write_mod_reg(irqstatus_mpu, OCP_MOD, 3118bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 3128bd22949SKevin Hilman 313d6290a3eSKevin Hilman irqstatus_mpu = prm_read_mod_reg(OCP_MOD, 314d6290a3eSKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 315d6290a3eSKevin Hilman irqstatus_mpu &= irqenable_mpu; 316d6290a3eSKevin Hilman 317d6290a3eSKevin Hilman } while (irqstatus_mpu); 3188bd22949SKevin Hilman 3198bd22949SKevin Hilman return IRQ_HANDLED; 3208bd22949SKevin Hilman } 3218bd22949SKevin Hilman 32257f277b0SRajendra Nayak static void restore_control_register(u32 val) 32357f277b0SRajendra Nayak { 32457f277b0SRajendra Nayak __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val)); 32557f277b0SRajendra Nayak } 32657f277b0SRajendra Nayak 32757f277b0SRajendra Nayak /* Function to restore the table entry that was modified for enabling MMU */ 32857f277b0SRajendra Nayak static void restore_table_entry(void) 32957f277b0SRajendra Nayak { 3304d63bc1dSManjunath Kondaiah G void __iomem *scratchpad_address; 33157f277b0SRajendra Nayak u32 previous_value, control_reg_value; 33257f277b0SRajendra Nayak u32 *address; 33357f277b0SRajendra Nayak 33457f277b0SRajendra Nayak scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD); 33557f277b0SRajendra Nayak 33657f277b0SRajendra Nayak /* Get address of entry that was modified */ 33757f277b0SRajendra Nayak address = (u32 *)__raw_readl(scratchpad_address + 33857f277b0SRajendra Nayak OMAP343X_TABLE_ADDRESS_OFFSET); 33957f277b0SRajendra Nayak /* Get the previous value which needs to be restored */ 34057f277b0SRajendra Nayak previous_value = __raw_readl(scratchpad_address + 34157f277b0SRajendra Nayak OMAP343X_TABLE_VALUE_OFFSET); 34257f277b0SRajendra Nayak address = __va(address); 34357f277b0SRajendra Nayak *address = previous_value; 34457f277b0SRajendra Nayak flush_tlb_all(); 34557f277b0SRajendra Nayak control_reg_value = __raw_readl(scratchpad_address 34657f277b0SRajendra Nayak + OMAP343X_CONTROL_REG_VALUE_OFFSET); 34757f277b0SRajendra Nayak /* This will enable caches and prediction */ 34857f277b0SRajendra Nayak restore_control_register(control_reg_value); 34957f277b0SRajendra Nayak } 35057f277b0SRajendra Nayak 35199e6a4d2SRajendra Nayak void omap_sram_idle(void) 3528bd22949SKevin Hilman { 3538bd22949SKevin Hilman /* Variable to tell what needs to be saved and restored 3548bd22949SKevin Hilman * in omap_sram_idle*/ 3558bd22949SKevin Hilman /* save_state = 0 => Nothing to save and restored */ 3568bd22949SKevin Hilman /* save_state = 1 => Only L1 and logic lost */ 3578bd22949SKevin Hilman /* save_state = 2 => Only L2 lost */ 3588bd22949SKevin Hilman /* save_state = 3 => L1, L2 and logic lost */ 359fa3c2a4fSRajendra Nayak int save_state = 0; 360fa3c2a4fSRajendra Nayak int mpu_next_state = PWRDM_POWER_ON; 361fa3c2a4fSRajendra Nayak int per_next_state = PWRDM_POWER_ON; 362fa3c2a4fSRajendra Nayak int core_next_state = PWRDM_POWER_ON; 3632f5939c3SRajendra Nayak int core_prev_state, per_prev_state; 36413a6fe0fSTero Kristo u32 sdrc_pwr = 0; 3658bd22949SKevin Hilman 3668bd22949SKevin Hilman if (!_omap_sram_idle) 3678bd22949SKevin Hilman return; 3688bd22949SKevin Hilman 369fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(mpu_pwrdm); 370fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(neon_pwrdm); 371fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(core_pwrdm); 372fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(per_pwrdm); 373fa3c2a4fSRajendra Nayak 3748bd22949SKevin Hilman mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 3758bd22949SKevin Hilman switch (mpu_next_state) { 376fa3c2a4fSRajendra Nayak case PWRDM_POWER_ON: 3778bd22949SKevin Hilman case PWRDM_POWER_RET: 3788bd22949SKevin Hilman /* No need to save context */ 3798bd22949SKevin Hilman save_state = 0; 3808bd22949SKevin Hilman break; 38161255ab9SRajendra Nayak case PWRDM_POWER_OFF: 38261255ab9SRajendra Nayak save_state = 3; 38361255ab9SRajendra Nayak break; 3848bd22949SKevin Hilman default: 3858bd22949SKevin Hilman /* Invalid state */ 3868bd22949SKevin Hilman printk(KERN_ERR "Invalid mpu state in sram_idle\n"); 3878bd22949SKevin Hilman return; 3888bd22949SKevin Hilman } 389fe617af7SPeter 'p2' De Schrijver pwrdm_pre_transition(); 390fe617af7SPeter 'p2' De Schrijver 391fa3c2a4fSRajendra Nayak /* NEON control */ 392fa3c2a4fSRajendra Nayak if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) 3937139178eSJouni Hogander pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); 394fa3c2a4fSRajendra Nayak 39540742fa8SMike Chan /* Enable IO-PAD and IO-CHAIN wakeups */ 396fa3c2a4fSRajendra Nayak per_next_state = pwrdm_read_next_pwrst(per_pwrdm); 397ecf157d0STero Kristo core_next_state = pwrdm_read_next_pwrst(core_pwrdm); 398d5c47d7eSKevin Hilman if (omap3_has_io_wakeup() && 399ad0c63f1Sstanley.miao (per_next_state < PWRDM_POWER_ON || 400ad0c63f1Sstanley.miao core_next_state < PWRDM_POWER_ON)) { 4012bc4ef71SPaul Walmsley prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); 40240742fa8SMike Chan omap3_enable_io_chain(); 40340742fa8SMike Chan } 40440742fa8SMike Chan 4050d8e2d0dSPaul Walmsley /* Block console output in case it is on one of the OMAP UARTs */ 406e83df17fSKevin Hilman if (!is_suspending()) 4070d8e2d0dSPaul Walmsley if (per_next_state < PWRDM_POWER_ON || 4080d8e2d0dSPaul Walmsley core_next_state < PWRDM_POWER_ON) 4090d8e2d0dSPaul Walmsley if (try_acquire_console_sem()) 4100d8e2d0dSPaul Walmsley goto console_still_active; 4110d8e2d0dSPaul Walmsley 41240742fa8SMike Chan /* PER */ 4132f5939c3SRajendra Nayak if (per_next_state < PWRDM_POWER_ON) { 4144af4016cSKevin Hilman omap_uart_prepare_idle(2); 415cd4f1faeSGovindraj.R omap_uart_prepare_idle(3); 41643ffcd9aSKevin Hilman omap2_gpio_prepare_for_idle(per_next_state); 417e7410cf7SKevin Hilman if (per_next_state == PWRDM_POWER_OFF) 4182f5939c3SRajendra Nayak omap3_per_save_context(); 4192f5939c3SRajendra Nayak } 420c16c3f67STero Kristo 421658ce97eSKevin Hilman /* CORE */ 422658ce97eSKevin Hilman if (core_next_state < PWRDM_POWER_ON) { 423658ce97eSKevin Hilman omap_uart_prepare_idle(0); 424658ce97eSKevin Hilman omap_uart_prepare_idle(1); 4252f5939c3SRajendra Nayak if (core_next_state == PWRDM_POWER_OFF) { 4262f5939c3SRajendra Nayak omap3_core_save_context(); 4272f5939c3SRajendra Nayak omap3_prcm_save_context(); 4282f5939c3SRajendra Nayak } 429fa3c2a4fSRajendra Nayak } 43040742fa8SMike Chan 431f18cc2ffSTero Kristo omap3_intc_prepare_idle(); 4328bd22949SKevin Hilman 43361255ab9SRajendra Nayak /* 434f265dc4cSRajendra Nayak * On EMU/HS devices ROM code restores a SRDC value 435f265dc4cSRajendra Nayak * from scratchpad which has automatic self refresh on timeout 43683521291SJean Pihet * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443. 437f265dc4cSRajendra Nayak * Hence store/restore the SDRC_POWER register here. 43813a6fe0fSTero Kristo */ 43913a6fe0fSTero Kristo if (omap_rev() >= OMAP3430_REV_ES3_0 && 44013a6fe0fSTero Kristo omap_type() != OMAP2_DEVICE_TYPE_GP && 441f265dc4cSRajendra Nayak core_next_state == PWRDM_POWER_OFF) 44213a6fe0fSTero Kristo sdrc_pwr = sdrc_read_reg(SDRC_POWER); 44313a6fe0fSTero Kristo 44413a6fe0fSTero Kristo /* 44561255ab9SRajendra Nayak * omap3_arm_context is the location where ARM registers 44661255ab9SRajendra Nayak * get saved. The restore path then reads from this 44761255ab9SRajendra Nayak * location and restores them back. 44861255ab9SRajendra Nayak */ 44961255ab9SRajendra Nayak _omap_sram_idle(omap3_arm_context, save_state); 4508bd22949SKevin Hilman cpu_init(); 4518bd22949SKevin Hilman 452f265dc4cSRajendra Nayak /* Restore normal SDRC POWER settings */ 45313a6fe0fSTero Kristo if (omap_rev() >= OMAP3430_REV_ES3_0 && 45413a6fe0fSTero Kristo omap_type() != OMAP2_DEVICE_TYPE_GP && 45513a6fe0fSTero Kristo core_next_state == PWRDM_POWER_OFF) 45613a6fe0fSTero Kristo sdrc_write_reg(sdrc_pwr, SDRC_POWER); 45713a6fe0fSTero Kristo 45857f277b0SRajendra Nayak /* Restore table entry modified during MMU restoration */ 45957f277b0SRajendra Nayak if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF) 46057f277b0SRajendra Nayak restore_table_entry(); 46157f277b0SRajendra Nayak 462658ce97eSKevin Hilman /* CORE */ 463fa3c2a4fSRajendra Nayak if (core_next_state < PWRDM_POWER_ON) { 4642f5939c3SRajendra Nayak core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); 4652f5939c3SRajendra Nayak if (core_prev_state == PWRDM_POWER_OFF) { 4662f5939c3SRajendra Nayak omap3_core_restore_context(); 4672f5939c3SRajendra Nayak omap3_prcm_restore_context(); 4682f5939c3SRajendra Nayak omap3_sram_restore_context(); 4698a917d2fSKalle Jokiniemi omap2_sms_restore_context(); 4702f5939c3SRajendra Nayak } 471658ce97eSKevin Hilman omap_uart_resume_idle(0); 472658ce97eSKevin Hilman omap_uart_resume_idle(1); 473658ce97eSKevin Hilman if (core_next_state == PWRDM_POWER_OFF) 4742bc4ef71SPaul Walmsley prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, 475658ce97eSKevin Hilman OMAP3430_GR_MOD, 476658ce97eSKevin Hilman OMAP3_PRM_VOLTCTRL_OFFSET); 477658ce97eSKevin Hilman } 478f18cc2ffSTero Kristo omap3_intc_resume_idle(); 479658ce97eSKevin Hilman 480658ce97eSKevin Hilman /* PER */ 4812f5939c3SRajendra Nayak if (per_next_state < PWRDM_POWER_ON) { 482658ce97eSKevin Hilman per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); 48343ffcd9aSKevin Hilman omap2_gpio_resume_after_idle(); 48443ffcd9aSKevin Hilman if (per_prev_state == PWRDM_POWER_OFF) 4852f5939c3SRajendra Nayak omap3_per_restore_context(); 486ecf157d0STero Kristo omap_uart_resume_idle(2); 487cd4f1faeSGovindraj.R omap_uart_resume_idle(3); 488fa3c2a4fSRajendra Nayak } 489fe617af7SPeter 'p2' De Schrijver 490e83df17fSKevin Hilman if (!is_suspending()) 4910d8e2d0dSPaul Walmsley release_console_sem(); 4920d8e2d0dSPaul Walmsley 4930d8e2d0dSPaul Walmsley console_still_active: 4943a7ec26bSKalle Jokiniemi /* Disable IO-PAD and IO-CHAIN wakeup */ 49558a5559eSKevin Hilman if (omap3_has_io_wakeup() && 49658a5559eSKevin Hilman (per_next_state < PWRDM_POWER_ON || 49758a5559eSKevin Hilman core_next_state < PWRDM_POWER_ON)) { 4982bc4ef71SPaul Walmsley prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); 4993a7ec26bSKalle Jokiniemi omap3_disable_io_chain(); 5003a7ec26bSKalle Jokiniemi } 501658ce97eSKevin Hilman 502fe617af7SPeter 'p2' De Schrijver pwrdm_post_transition(); 503fe617af7SPeter 'p2' De Schrijver 504c16c3f67STero Kristo omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); 5058bd22949SKevin Hilman } 5068bd22949SKevin Hilman 50720b01669SRajendra Nayak int omap3_can_sleep(void) 5088bd22949SKevin Hilman { 509c40552bcSKevin Hilman if (!sleep_while_idle) 510c40552bcSKevin Hilman return 0; 5114af4016cSKevin Hilman if (!omap_uart_can_sleep()) 5124af4016cSKevin Hilman return 0; 5138bd22949SKevin Hilman return 1; 5148bd22949SKevin Hilman } 5158bd22949SKevin Hilman 5168bd22949SKevin Hilman static void omap3_pm_idle(void) 5178bd22949SKevin Hilman { 5188bd22949SKevin Hilman local_irq_disable(); 5198bd22949SKevin Hilman local_fiq_disable(); 5208bd22949SKevin Hilman 5218bd22949SKevin Hilman if (!omap3_can_sleep()) 5228bd22949SKevin Hilman goto out; 5238bd22949SKevin Hilman 524cf22854cSTero Kristo if (omap_irq_pending() || need_resched()) 5258bd22949SKevin Hilman goto out; 5268bd22949SKevin Hilman 5278bd22949SKevin Hilman omap_sram_idle(); 5288bd22949SKevin Hilman 5298bd22949SKevin Hilman out: 5308bd22949SKevin Hilman local_fiq_enable(); 5318bd22949SKevin Hilman local_irq_enable(); 5328bd22949SKevin Hilman } 5338bd22949SKevin Hilman 53410f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 5358bd22949SKevin Hilman static int omap3_pm_suspend(void) 5368bd22949SKevin Hilman { 5378bd22949SKevin Hilman struct power_state *pwrst; 5388bd22949SKevin Hilman int state, ret = 0; 5398bd22949SKevin Hilman 5408e2efde9SAri Kauppi if (wakeup_timer_seconds || wakeup_timer_milliseconds) 5418e2efde9SAri Kauppi omap2_pm_wakeup_on_timer(wakeup_timer_seconds, 5428e2efde9SAri Kauppi wakeup_timer_milliseconds); 543d7814e4dSKevin Hilman 5448bd22949SKevin Hilman /* Read current next_pwrsts */ 5458bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) 5468bd22949SKevin Hilman pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 5478bd22949SKevin Hilman /* Set ones wanted by suspend */ 5488bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 549eb6a2c75SSantosh Shilimkar if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) 5508bd22949SKevin Hilman goto restore; 5518bd22949SKevin Hilman if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) 5528bd22949SKevin Hilman goto restore; 5538bd22949SKevin Hilman } 5548bd22949SKevin Hilman 5554af4016cSKevin Hilman omap_uart_prepare_suspend(); 5562bbe3af3STero Kristo omap3_intc_suspend(); 5572bbe3af3STero Kristo 5588bd22949SKevin Hilman omap_sram_idle(); 5598bd22949SKevin Hilman 5608bd22949SKevin Hilman restore: 5618bd22949SKevin Hilman /* Restore next_pwrsts */ 5628bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 5638bd22949SKevin Hilman state = pwrdm_read_prev_pwrst(pwrst->pwrdm); 5648bd22949SKevin Hilman if (state > pwrst->next_state) { 5658bd22949SKevin Hilman printk(KERN_INFO "Powerdomain (%s) didn't enter " 5668bd22949SKevin Hilman "target state %d\n", 5678bd22949SKevin Hilman pwrst->pwrdm->name, pwrst->next_state); 5688bd22949SKevin Hilman ret = -1; 5698bd22949SKevin Hilman } 570eb6a2c75SSantosh Shilimkar omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); 5718bd22949SKevin Hilman } 5728bd22949SKevin Hilman if (ret) 5738bd22949SKevin Hilman printk(KERN_ERR "Could not enter target state in pm_suspend\n"); 5748bd22949SKevin Hilman else 5758bd22949SKevin Hilman printk(KERN_INFO "Successfully put all powerdomains " 5768bd22949SKevin Hilman "to target state\n"); 5778bd22949SKevin Hilman 5788bd22949SKevin Hilman return ret; 5798bd22949SKevin Hilman } 5808bd22949SKevin Hilman 5812466211eSTero Kristo static int omap3_pm_enter(suspend_state_t unused) 5828bd22949SKevin Hilman { 5838bd22949SKevin Hilman int ret = 0; 5848bd22949SKevin Hilman 5852466211eSTero Kristo switch (suspend_state) { 5868bd22949SKevin Hilman case PM_SUSPEND_STANDBY: 5878bd22949SKevin Hilman case PM_SUSPEND_MEM: 5888bd22949SKevin Hilman ret = omap3_pm_suspend(); 5898bd22949SKevin Hilman break; 5908bd22949SKevin Hilman default: 5918bd22949SKevin Hilman ret = -EINVAL; 5928bd22949SKevin Hilman } 5938bd22949SKevin Hilman 5948bd22949SKevin Hilman return ret; 5958bd22949SKevin Hilman } 5968bd22949SKevin Hilman 5972466211eSTero Kristo /* Hooks to enable / disable UART interrupts during suspend */ 5982466211eSTero Kristo static int omap3_pm_begin(suspend_state_t state) 5992466211eSTero Kristo { 600c166381dSJean Pihet disable_hlt(); 6012466211eSTero Kristo suspend_state = state; 6022466211eSTero Kristo omap_uart_enable_irqs(0); 6032466211eSTero Kristo return 0; 6042466211eSTero Kristo } 6052466211eSTero Kristo 6062466211eSTero Kristo static void omap3_pm_end(void) 6072466211eSTero Kristo { 6082466211eSTero Kristo suspend_state = PM_SUSPEND_ON; 6092466211eSTero Kristo omap_uart_enable_irqs(1); 610c166381dSJean Pihet enable_hlt(); 6112466211eSTero Kristo return; 6122466211eSTero Kristo } 6132466211eSTero Kristo 6148bd22949SKevin Hilman static struct platform_suspend_ops omap_pm_ops = { 6152466211eSTero Kristo .begin = omap3_pm_begin, 6162466211eSTero Kristo .end = omap3_pm_end, 6178bd22949SKevin Hilman .enter = omap3_pm_enter, 6188bd22949SKevin Hilman .valid = suspend_valid_only_mem, 6198bd22949SKevin Hilman }; 62010f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 6218bd22949SKevin Hilman 6221155e426SKevin Hilman 6231155e426SKevin Hilman /** 6241155e426SKevin Hilman * omap3_iva_idle(): ensure IVA is in idle so it can be put into 6251155e426SKevin Hilman * retention 6261155e426SKevin Hilman * 6271155e426SKevin Hilman * In cases where IVA2 is activated by bootcode, it may prevent 6281155e426SKevin Hilman * full-chip retention or off-mode because it is not idle. This 6291155e426SKevin Hilman * function forces the IVA2 into idle state so it can go 6301155e426SKevin Hilman * into retention/off and thus allow full-chip retention/off. 6311155e426SKevin Hilman * 6321155e426SKevin Hilman **/ 6331155e426SKevin Hilman static void __init omap3_iva_idle(void) 6341155e426SKevin Hilman { 6351155e426SKevin Hilman /* ensure IVA2 clock is disabled */ 6361155e426SKevin Hilman cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 6371155e426SKevin Hilman 6381155e426SKevin Hilman /* if no clock activity, nothing else to do */ 6391155e426SKevin Hilman if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & 6401155e426SKevin Hilman OMAP3430_CLKACTIVITY_IVA2_MASK)) 6411155e426SKevin Hilman return; 6421155e426SKevin Hilman 6431155e426SKevin Hilman /* Reset IVA2 */ 6442bc4ef71SPaul Walmsley prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | 6452bc4ef71SPaul Walmsley OMAP3430_RST2_IVA2_MASK | 6462bc4ef71SPaul Walmsley OMAP3430_RST3_IVA2_MASK, 64737903009SAbhijit Pagare OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 6481155e426SKevin Hilman 6491155e426SKevin Hilman /* Enable IVA2 clock */ 650dfa6d6f8SKevin Hilman cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, 6511155e426SKevin Hilman OMAP3430_IVA2_MOD, CM_FCLKEN); 6521155e426SKevin Hilman 6531155e426SKevin Hilman /* Set IVA2 boot mode to 'idle' */ 6541155e426SKevin Hilman omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, 6551155e426SKevin Hilman OMAP343X_CONTROL_IVA2_BOOTMOD); 6561155e426SKevin Hilman 6571155e426SKevin Hilman /* Un-reset IVA2 */ 65837903009SAbhijit Pagare prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 6591155e426SKevin Hilman 6601155e426SKevin Hilman /* Disable IVA2 clock */ 6611155e426SKevin Hilman cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 6621155e426SKevin Hilman 6631155e426SKevin Hilman /* Reset IVA2 */ 6642bc4ef71SPaul Walmsley prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | 6652bc4ef71SPaul Walmsley OMAP3430_RST2_IVA2_MASK | 6662bc4ef71SPaul Walmsley OMAP3430_RST3_IVA2_MASK, 66737903009SAbhijit Pagare OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 6681155e426SKevin Hilman } 6691155e426SKevin Hilman 6708111b221SKevin Hilman static void __init omap3_d2d_idle(void) 6718bd22949SKevin Hilman { 6728111b221SKevin Hilman u16 mask, padconf; 6738111b221SKevin Hilman 6748111b221SKevin Hilman /* In a stand alone OMAP3430 where there is not a stacked 6758111b221SKevin Hilman * modem for the D2D Idle Ack and D2D MStandby must be pulled 6768111b221SKevin Hilman * high. S CONTROL_PADCONF_SAD2D_IDLEACK and 6778111b221SKevin Hilman * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ 6788111b221SKevin Hilman mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ 6798111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); 6808111b221SKevin Hilman padconf |= mask; 6818111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); 6828111b221SKevin Hilman 6838111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); 6848111b221SKevin Hilman padconf |= mask; 6858111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 6868111b221SKevin Hilman 6878bd22949SKevin Hilman /* reset modem */ 6882bc4ef71SPaul Walmsley prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | 6892bc4ef71SPaul Walmsley OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, 69037903009SAbhijit Pagare CORE_MOD, OMAP2_RM_RSTCTRL); 69137903009SAbhijit Pagare prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); 6928111b221SKevin Hilman } 6938bd22949SKevin Hilman 6948111b221SKevin Hilman static void __init prcm_setup_regs(void) 6958111b221SKevin Hilman { 696e5863689SGovindraj.R u32 omap3630_auto_uart4_mask = cpu_is_omap3630() ? 697e5863689SGovindraj.R OMAP3630_AUTO_UART4_MASK : 0; 698e5863689SGovindraj.R u32 omap3630_en_uart4_mask = cpu_is_omap3630() ? 699e5863689SGovindraj.R OMAP3630_EN_UART4_MASK : 0; 700e5863689SGovindraj.R u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ? 701e5863689SGovindraj.R OMAP3630_GRPSEL_UART4_MASK : 0; 702e5863689SGovindraj.R 703e5863689SGovindraj.R 7048bd22949SKevin Hilman /* XXX Reset all wkdeps. This should be done when initializing 7058bd22949SKevin Hilman * powerdomains */ 7068bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); 7078bd22949SKevin Hilman prm_write_mod_reg(0, MPU_MOD, PM_WKDEP); 7088bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP); 7098bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP); 7108bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP); 7118bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP); 7128bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 7138bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP); 7148bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP); 7158bd22949SKevin Hilman } else 7168bd22949SKevin Hilman prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); 7178bd22949SKevin Hilman 7188bd22949SKevin Hilman /* 7198bd22949SKevin Hilman * Enable interface clock autoidle for all modules. 7208bd22949SKevin Hilman * Note that in the long run this should be done by clockfw 7218bd22949SKevin Hilman */ 7228bd22949SKevin Hilman cm_write_mod_reg( 7232bc4ef71SPaul Walmsley OMAP3430_AUTO_MODEM_MASK | 7242bc4ef71SPaul Walmsley OMAP3430ES2_AUTO_MMC3_MASK | 7252bc4ef71SPaul Walmsley OMAP3430ES2_AUTO_ICR_MASK | 7262bc4ef71SPaul Walmsley OMAP3430_AUTO_AES2_MASK | 7272bc4ef71SPaul Walmsley OMAP3430_AUTO_SHA12_MASK | 7282bc4ef71SPaul Walmsley OMAP3430_AUTO_DES2_MASK | 7292bc4ef71SPaul Walmsley OMAP3430_AUTO_MMC2_MASK | 7302bc4ef71SPaul Walmsley OMAP3430_AUTO_MMC1_MASK | 7312bc4ef71SPaul Walmsley OMAP3430_AUTO_MSPRO_MASK | 7322bc4ef71SPaul Walmsley OMAP3430_AUTO_HDQ_MASK | 7332bc4ef71SPaul Walmsley OMAP3430_AUTO_MCSPI4_MASK | 7342bc4ef71SPaul Walmsley OMAP3430_AUTO_MCSPI3_MASK | 7352bc4ef71SPaul Walmsley OMAP3430_AUTO_MCSPI2_MASK | 7362bc4ef71SPaul Walmsley OMAP3430_AUTO_MCSPI1_MASK | 7372bc4ef71SPaul Walmsley OMAP3430_AUTO_I2C3_MASK | 7382bc4ef71SPaul Walmsley OMAP3430_AUTO_I2C2_MASK | 7392bc4ef71SPaul Walmsley OMAP3430_AUTO_I2C1_MASK | 7402bc4ef71SPaul Walmsley OMAP3430_AUTO_UART2_MASK | 7412bc4ef71SPaul Walmsley OMAP3430_AUTO_UART1_MASK | 7422bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT11_MASK | 7432bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT10_MASK | 7442bc4ef71SPaul Walmsley OMAP3430_AUTO_MCBSP5_MASK | 7452bc4ef71SPaul Walmsley OMAP3430_AUTO_MCBSP1_MASK | 7462bc4ef71SPaul Walmsley OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */ 7472bc4ef71SPaul Walmsley OMAP3430_AUTO_MAILBOXES_MASK | 7482bc4ef71SPaul Walmsley OMAP3430_AUTO_OMAPCTRL_MASK | 7492bc4ef71SPaul Walmsley OMAP3430ES1_AUTO_FSHOSTUSB_MASK | 7502bc4ef71SPaul Walmsley OMAP3430_AUTO_HSOTGUSB_MASK | 7512bc4ef71SPaul Walmsley OMAP3430_AUTO_SAD2D_MASK | 7522bc4ef71SPaul Walmsley OMAP3430_AUTO_SSI_MASK, 7538bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE1); 7548bd22949SKevin Hilman 7558bd22949SKevin Hilman cm_write_mod_reg( 7562bc4ef71SPaul Walmsley OMAP3430_AUTO_PKA_MASK | 7572bc4ef71SPaul Walmsley OMAP3430_AUTO_AES1_MASK | 7582bc4ef71SPaul Walmsley OMAP3430_AUTO_RNG_MASK | 7592bc4ef71SPaul Walmsley OMAP3430_AUTO_SHA11_MASK | 7602bc4ef71SPaul Walmsley OMAP3430_AUTO_DES1_MASK, 7618bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE2); 7628bd22949SKevin Hilman 7638bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 7648bd22949SKevin Hilman cm_write_mod_reg( 7652bc4ef71SPaul Walmsley OMAP3430_AUTO_MAD2D_MASK | 7662bc4ef71SPaul Walmsley OMAP3430ES2_AUTO_USBTLL_MASK, 7678bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE3); 7688bd22949SKevin Hilman } 7698bd22949SKevin Hilman 7708bd22949SKevin Hilman cm_write_mod_reg( 7712bc4ef71SPaul Walmsley OMAP3430_AUTO_WDT2_MASK | 7722bc4ef71SPaul Walmsley OMAP3430_AUTO_WDT1_MASK | 7732bc4ef71SPaul Walmsley OMAP3430_AUTO_GPIO1_MASK | 7742bc4ef71SPaul Walmsley OMAP3430_AUTO_32KSYNC_MASK | 7752bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT12_MASK | 7762bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT1_MASK, 7778bd22949SKevin Hilman WKUP_MOD, CM_AUTOIDLE); 7788bd22949SKevin Hilman 7798bd22949SKevin Hilman cm_write_mod_reg( 7802bc4ef71SPaul Walmsley OMAP3430_AUTO_DSS_MASK, 7818bd22949SKevin Hilman OMAP3430_DSS_MOD, 7828bd22949SKevin Hilman CM_AUTOIDLE); 7838bd22949SKevin Hilman 7848bd22949SKevin Hilman cm_write_mod_reg( 7852bc4ef71SPaul Walmsley OMAP3430_AUTO_CAM_MASK, 7868bd22949SKevin Hilman OMAP3430_CAM_MOD, 7878bd22949SKevin Hilman CM_AUTOIDLE); 7888bd22949SKevin Hilman 7898bd22949SKevin Hilman cm_write_mod_reg( 790e5863689SGovindraj.R omap3630_auto_uart4_mask | 7912bc4ef71SPaul Walmsley OMAP3430_AUTO_GPIO6_MASK | 7922bc4ef71SPaul Walmsley OMAP3430_AUTO_GPIO5_MASK | 7932bc4ef71SPaul Walmsley OMAP3430_AUTO_GPIO4_MASK | 7942bc4ef71SPaul Walmsley OMAP3430_AUTO_GPIO3_MASK | 7952bc4ef71SPaul Walmsley OMAP3430_AUTO_GPIO2_MASK | 7962bc4ef71SPaul Walmsley OMAP3430_AUTO_WDT3_MASK | 7972bc4ef71SPaul Walmsley OMAP3430_AUTO_UART3_MASK | 7982bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT9_MASK | 7992bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT8_MASK | 8002bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT7_MASK | 8012bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT6_MASK | 8022bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT5_MASK | 8032bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT4_MASK | 8042bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT3_MASK | 8052bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT2_MASK | 8062bc4ef71SPaul Walmsley OMAP3430_AUTO_MCBSP4_MASK | 8072bc4ef71SPaul Walmsley OMAP3430_AUTO_MCBSP3_MASK | 8082bc4ef71SPaul Walmsley OMAP3430_AUTO_MCBSP2_MASK, 8098bd22949SKevin Hilman OMAP3430_PER_MOD, 8108bd22949SKevin Hilman CM_AUTOIDLE); 8118bd22949SKevin Hilman 8128bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 8138bd22949SKevin Hilman cm_write_mod_reg( 8142bc4ef71SPaul Walmsley OMAP3430ES2_AUTO_USBHOST_MASK, 8158bd22949SKevin Hilman OMAP3430ES2_USBHOST_MOD, 8168bd22949SKevin Hilman CM_AUTOIDLE); 8178bd22949SKevin Hilman } 8188bd22949SKevin Hilman 8192fd0f75cSPaul Walmsley omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); 820b296c811STero Kristo 8218bd22949SKevin Hilman /* 8228bd22949SKevin Hilman * Set all plls to autoidle. This is needed until autoidle is 8238bd22949SKevin Hilman * enabled by clockfw 8248bd22949SKevin Hilman */ 8258bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, 8268bd22949SKevin Hilman OMAP3430_IVA2_MOD, CM_AUTOIDLE2); 8278bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT, 8288bd22949SKevin Hilman MPU_MOD, 8298bd22949SKevin Hilman CM_AUTOIDLE2); 8308bd22949SKevin Hilman cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | 8318bd22949SKevin Hilman (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT), 8328bd22949SKevin Hilman PLL_MOD, 8338bd22949SKevin Hilman CM_AUTOIDLE); 8348bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, 8358bd22949SKevin Hilman PLL_MOD, 8368bd22949SKevin Hilman CM_AUTOIDLE2); 8378bd22949SKevin Hilman 8388bd22949SKevin Hilman /* 8398bd22949SKevin Hilman * Enable control of expternal oscillator through 8408bd22949SKevin Hilman * sys_clkreq. In the long run clock framework should 8418bd22949SKevin Hilman * take care of this. 8428bd22949SKevin Hilman */ 8438bd22949SKevin Hilman prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 8448bd22949SKevin Hilman 1 << OMAP_AUTOEXTCLKMODE_SHIFT, 8458bd22949SKevin Hilman OMAP3430_GR_MOD, 8468bd22949SKevin Hilman OMAP3_PRM_CLKSRC_CTRL_OFFSET); 8478bd22949SKevin Hilman 8488bd22949SKevin Hilman /* setup wakup source */ 8492fd0f75cSPaul Walmsley prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | 8502fd0f75cSPaul Walmsley OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, 8518bd22949SKevin Hilman WKUP_MOD, PM_WKEN); 8528bd22949SKevin Hilman /* No need to write EN_IO, that is always enabled */ 853275f675cSPaul Walmsley prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | 854275f675cSPaul Walmsley OMAP3430_GRPSEL_GPT1_MASK | 855275f675cSPaul Walmsley OMAP3430_GRPSEL_GPT12_MASK, 8568bd22949SKevin Hilman WKUP_MOD, OMAP3430_PM_MPUGRPSEL); 8578bd22949SKevin Hilman /* For some reason IO doesn't generate wakeup event even if 8588bd22949SKevin Hilman * it is selected to mpu wakeup goup */ 8592bc4ef71SPaul Walmsley prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK, 8608bd22949SKevin Hilman OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); 8611155e426SKevin Hilman 862b92c5721SSubramani Venkatesh /* Enable PM_WKEN to support DSS LPR */ 8632bc4ef71SPaul Walmsley prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, 864b92c5721SSubramani Venkatesh OMAP3430_DSS_MOD, PM_WKEN); 865b92c5721SSubramani Venkatesh 866b427f92fSKevin Hilman /* Enable wakeups in PER */ 867e5863689SGovindraj.R prm_write_mod_reg(omap3630_en_uart4_mask | 868e5863689SGovindraj.R OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | 8692fd0f75cSPaul Walmsley OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | 8702fd0f75cSPaul Walmsley OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | 8712fd0f75cSPaul Walmsley OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK | 8722fd0f75cSPaul Walmsley OMAP3430_EN_MCBSP4_MASK, 873b427f92fSKevin Hilman OMAP3430_PER_MOD, PM_WKEN); 874eb350f74SKevin Hilman /* and allow them to wake up MPU */ 875e5863689SGovindraj.R prm_write_mod_reg(omap3630_grpsel_uart4_mask | 876e5863689SGovindraj.R OMAP3430_GRPSEL_GPIO2_MASK | 877275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO3_MASK | 878275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO4_MASK | 879275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO5_MASK | 880275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO6_MASK | 881275f675cSPaul Walmsley OMAP3430_GRPSEL_UART3_MASK | 882275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP2_MASK | 883275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP3_MASK | 884275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP4_MASK, 885eb350f74SKevin Hilman OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); 886eb350f74SKevin Hilman 887d3fd3290SKevin Hilman /* Don't attach IVA interrupts */ 888d3fd3290SKevin Hilman prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 889d3fd3290SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 890d3fd3290SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 891d3fd3290SKevin Hilman prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); 892d3fd3290SKevin Hilman 893b1340d17SKevin Hilman /* Clear any pending 'reset' flags */ 89437903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); 89537903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); 89637903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); 89737903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); 89837903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); 89937903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); 90037903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); 901b1340d17SKevin Hilman 902014c46dbSKevin Hilman /* Clear any pending PRCM interrupts */ 903014c46dbSKevin Hilman prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 904014c46dbSKevin Hilman 9051155e426SKevin Hilman omap3_iva_idle(); 9068111b221SKevin Hilman omap3_d2d_idle(); 9078bd22949SKevin Hilman } 9088bd22949SKevin Hilman 909c40552bcSKevin Hilman void omap3_pm_off_mode_enable(int enable) 910c40552bcSKevin Hilman { 911c40552bcSKevin Hilman struct power_state *pwrst; 912c40552bcSKevin Hilman u32 state; 913c40552bcSKevin Hilman 914c40552bcSKevin Hilman if (enable) 915c40552bcSKevin Hilman state = PWRDM_POWER_OFF; 916c40552bcSKevin Hilman else 917c40552bcSKevin Hilman state = PWRDM_POWER_RET; 918c40552bcSKevin Hilman 9196af83b38SSanjeev Premi #ifdef CONFIG_CPU_IDLE 920cc1b6028SEduardo Valentin /* 921cc1b6028SEduardo Valentin * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot 922cc1b6028SEduardo Valentin * enable OFF mode in a stable form for previous revisions, restrict 923cc1b6028SEduardo Valentin * instead to RET 924cc1b6028SEduardo Valentin */ 925cc1b6028SEduardo Valentin if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) 926cc1b6028SEduardo Valentin omap3_cpuidle_update_states(state, PWRDM_POWER_RET); 927cc1b6028SEduardo Valentin else 92880723c3fSNishanth Menon omap3_cpuidle_update_states(state, state); 9296af83b38SSanjeev Premi #endif 9306af83b38SSanjeev Premi 931c40552bcSKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 932cc1b6028SEduardo Valentin if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) && 933cc1b6028SEduardo Valentin pwrst->pwrdm == core_pwrdm && 934cc1b6028SEduardo Valentin state == PWRDM_POWER_OFF) { 935cc1b6028SEduardo Valentin pwrst->next_state = PWRDM_POWER_RET; 936cc1b6028SEduardo Valentin WARN_ONCE(1, 937cc1b6028SEduardo Valentin "%s: Core OFF disabled due to errata i583\n", 938cc1b6028SEduardo Valentin __func__); 939cc1b6028SEduardo Valentin } else { 940c40552bcSKevin Hilman pwrst->next_state = state; 941cc1b6028SEduardo Valentin } 942cc1b6028SEduardo Valentin omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 943c40552bcSKevin Hilman } 944c40552bcSKevin Hilman } 945c40552bcSKevin Hilman 94668d4778cSTero Kristo int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) 94768d4778cSTero Kristo { 94868d4778cSTero Kristo struct power_state *pwrst; 94968d4778cSTero Kristo 95068d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 95168d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) 95268d4778cSTero Kristo return pwrst->next_state; 95368d4778cSTero Kristo } 95468d4778cSTero Kristo return -EINVAL; 95568d4778cSTero Kristo } 95668d4778cSTero Kristo 95768d4778cSTero Kristo int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) 95868d4778cSTero Kristo { 95968d4778cSTero Kristo struct power_state *pwrst; 96068d4778cSTero Kristo 96168d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 96268d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) { 96368d4778cSTero Kristo pwrst->next_state = state; 96468d4778cSTero Kristo return 0; 96568d4778cSTero Kristo } 96668d4778cSTero Kristo } 96768d4778cSTero Kristo return -EINVAL; 96868d4778cSTero Kristo } 96968d4778cSTero Kristo 970a23456e9SPeter 'p2' De Schrijver static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) 9718bd22949SKevin Hilman { 9728bd22949SKevin Hilman struct power_state *pwrst; 9738bd22949SKevin Hilman 9748bd22949SKevin Hilman if (!pwrdm->pwrsts) 9758bd22949SKevin Hilman return 0; 9768bd22949SKevin Hilman 977d3d381c6SMing Lei pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); 9788bd22949SKevin Hilman if (!pwrst) 9798bd22949SKevin Hilman return -ENOMEM; 9808bd22949SKevin Hilman pwrst->pwrdm = pwrdm; 9818bd22949SKevin Hilman pwrst->next_state = PWRDM_POWER_RET; 9828bd22949SKevin Hilman list_add(&pwrst->node, &pwrst_list); 9838bd22949SKevin Hilman 9848bd22949SKevin Hilman if (pwrdm_has_hdwr_sar(pwrdm)) 9858bd22949SKevin Hilman pwrdm_enable_hdwr_sar(pwrdm); 9868bd22949SKevin Hilman 987eb6a2c75SSantosh Shilimkar return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 9888bd22949SKevin Hilman } 9898bd22949SKevin Hilman 9908bd22949SKevin Hilman /* 9918bd22949SKevin Hilman * Enable hw supervised mode for all clockdomains if it's 9928bd22949SKevin Hilman * supported. Initiate sleep transition for other clockdomains, if 9938bd22949SKevin Hilman * they are not used 9948bd22949SKevin Hilman */ 995a23456e9SPeter 'p2' De Schrijver static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) 9968bd22949SKevin Hilman { 9978bd22949SKevin Hilman if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) 9988bd22949SKevin Hilman omap2_clkdm_allow_idle(clkdm); 9998bd22949SKevin Hilman else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && 10008bd22949SKevin Hilman atomic_read(&clkdm->usecount) == 0) 10018bd22949SKevin Hilman omap2_clkdm_sleep(clkdm); 10028bd22949SKevin Hilman return 0; 10038bd22949SKevin Hilman } 10048bd22949SKevin Hilman 10053231fc88SRajendra Nayak void omap_push_sram_idle(void) 10063231fc88SRajendra Nayak { 10073231fc88SRajendra Nayak _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend, 10083231fc88SRajendra Nayak omap34xx_cpu_suspend_sz); 100927d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) 101027d59a4aSTero Kristo _omap_save_secure_sram = omap_sram_push(save_secure_ram_context, 101127d59a4aSTero Kristo save_secure_ram_context_sz); 10123231fc88SRajendra Nayak } 10133231fc88SRajendra Nayak 10148cdfd834SNishanth Menon static void __init pm_errata_configure(void) 10158cdfd834SNishanth Menon { 1016c4236d2eSPeter 'p2' De Schrijver if (cpu_is_omap3630()) { 1017458e999eSNishanth Menon pm34xx_errata |= PM_RTA_ERRATUM_i608; 1018c4236d2eSPeter 'p2' De Schrijver /* Enable the l2 cache toggling in sleep logic */ 1019c4236d2eSPeter 'p2' De Schrijver enable_omap3630_toggle_l2_on_restore(); 1020cc1b6028SEduardo Valentin if (omap_rev() < OMAP3630_REV_ES1_2) 1021cc1b6028SEduardo Valentin pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583; 1022c4236d2eSPeter 'p2' De Schrijver } 10238cdfd834SNishanth Menon } 10248cdfd834SNishanth Menon 10257cc515f7SKevin Hilman static int __init omap3_pm_init(void) 10268bd22949SKevin Hilman { 10278bd22949SKevin Hilman struct power_state *pwrst, *tmp; 102855ed9694SPaul Walmsley struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm; 10298bd22949SKevin Hilman int ret; 10308bd22949SKevin Hilman 10318bd22949SKevin Hilman if (!cpu_is_omap34xx()) 10328bd22949SKevin Hilman return -ENODEV; 10338bd22949SKevin Hilman 10348cdfd834SNishanth Menon pm_errata_configure(); 10358cdfd834SNishanth Menon 10368bd22949SKevin Hilman printk(KERN_ERR "Power Management for TI OMAP3.\n"); 10378bd22949SKevin Hilman 10388bd22949SKevin Hilman /* XXX prcm_setup_regs needs to be before enabling hw 10398bd22949SKevin Hilman * supervised mode for powerdomains */ 10408bd22949SKevin Hilman prcm_setup_regs(); 10418bd22949SKevin Hilman 10428bd22949SKevin Hilman ret = request_irq(INT_34XX_PRCM_MPU_IRQ, 10438bd22949SKevin Hilman (irq_handler_t)prcm_interrupt_handler, 10448bd22949SKevin Hilman IRQF_DISABLED, "prcm", NULL); 10458bd22949SKevin Hilman if (ret) { 10468bd22949SKevin Hilman printk(KERN_ERR "request_irq failed to register for 0x%x\n", 10478bd22949SKevin Hilman INT_34XX_PRCM_MPU_IRQ); 10488bd22949SKevin Hilman goto err1; 10498bd22949SKevin Hilman } 10508bd22949SKevin Hilman 1051a23456e9SPeter 'p2' De Schrijver ret = pwrdm_for_each(pwrdms_setup, NULL); 10528bd22949SKevin Hilman if (ret) { 10538bd22949SKevin Hilman printk(KERN_ERR "Failed to setup powerdomains\n"); 10548bd22949SKevin Hilman goto err2; 10558bd22949SKevin Hilman } 10568bd22949SKevin Hilman 1057a23456e9SPeter 'p2' De Schrijver (void) clkdm_for_each(clkdms_setup, NULL); 10588bd22949SKevin Hilman 10598bd22949SKevin Hilman mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); 10608bd22949SKevin Hilman if (mpu_pwrdm == NULL) { 10618bd22949SKevin Hilman printk(KERN_ERR "Failed to get mpu_pwrdm\n"); 10628bd22949SKevin Hilman goto err2; 10638bd22949SKevin Hilman } 10648bd22949SKevin Hilman 1065fa3c2a4fSRajendra Nayak neon_pwrdm = pwrdm_lookup("neon_pwrdm"); 1066fa3c2a4fSRajendra Nayak per_pwrdm = pwrdm_lookup("per_pwrdm"); 1067fa3c2a4fSRajendra Nayak core_pwrdm = pwrdm_lookup("core_pwrdm"); 1068c16c3f67STero Kristo cam_pwrdm = pwrdm_lookup("cam_pwrdm"); 1069fa3c2a4fSRajendra Nayak 107055ed9694SPaul Walmsley neon_clkdm = clkdm_lookup("neon_clkdm"); 107155ed9694SPaul Walmsley mpu_clkdm = clkdm_lookup("mpu_clkdm"); 107255ed9694SPaul Walmsley per_clkdm = clkdm_lookup("per_clkdm"); 107355ed9694SPaul Walmsley core_clkdm = clkdm_lookup("core_clkdm"); 107455ed9694SPaul Walmsley 10753231fc88SRajendra Nayak omap_push_sram_idle(); 107610f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 10778bd22949SKevin Hilman suspend_set_ops(&omap_pm_ops); 107810f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 10798bd22949SKevin Hilman 10808bd22949SKevin Hilman pm_idle = omap3_pm_idle; 10810343371eSKalle Jokiniemi omap3_idle_init(); 10828bd22949SKevin Hilman 1083458e999eSNishanth Menon /* 1084458e999eSNishanth Menon * RTA is disabled during initialization as per erratum i608 1085458e999eSNishanth Menon * it is safer to disable RTA by the bootloader, but we would like 1086458e999eSNishanth Menon * to be doubly sure here and prevent any mishaps. 1087458e999eSNishanth Menon */ 1088458e999eSNishanth Menon if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608)) 1089458e999eSNishanth Menon omap3630_ctrl_disable_rta(); 1090458e999eSNishanth Menon 109155ed9694SPaul Walmsley clkdm_add_wkdep(neon_clkdm, mpu_clkdm); 109227d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 109327d59a4aSTero Kristo omap3_secure_ram_storage = 109427d59a4aSTero Kristo kmalloc(0x803F, GFP_KERNEL); 109527d59a4aSTero Kristo if (!omap3_secure_ram_storage) 109627d59a4aSTero Kristo printk(KERN_ERR "Memory allocation failed when" 109727d59a4aSTero Kristo "allocating for secure sram context\n"); 109827d59a4aSTero Kristo 10999d97140bSTero Kristo local_irq_disable(); 11009d97140bSTero Kristo local_fiq_disable(); 11019d97140bSTero Kristo 11029d97140bSTero Kristo omap_dma_global_context_save(); 11039d97140bSTero Kristo omap3_save_secure_ram_context(PWRDM_POWER_ON); 11049d97140bSTero Kristo omap_dma_global_context_restore(); 11059d97140bSTero Kristo 11069d97140bSTero Kristo local_irq_enable(); 11079d97140bSTero Kristo local_fiq_enable(); 11089d97140bSTero Kristo } 11099d97140bSTero Kristo 11109d97140bSTero Kristo omap3_save_scratchpad_contents(); 11118bd22949SKevin Hilman err1: 11128bd22949SKevin Hilman return ret; 11138bd22949SKevin Hilman err2: 11148bd22949SKevin Hilman free_irq(INT_34XX_PRCM_MPU_IRQ, NULL); 11158bd22949SKevin Hilman list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { 11168bd22949SKevin Hilman list_del(&pwrst->node); 11178bd22949SKevin Hilman kfree(pwrst); 11188bd22949SKevin Hilman } 11198bd22949SKevin Hilman return ret; 11208bd22949SKevin Hilman } 11218bd22949SKevin Hilman 11228bd22949SKevin Hilman late_initcall(omap3_pm_init); 1123