18bd22949SKevin Hilman /* 28bd22949SKevin Hilman * OMAP3 Power Management Routines 38bd22949SKevin Hilman * 48bd22949SKevin Hilman * Copyright (C) 2006-2008 Nokia Corporation 58bd22949SKevin Hilman * Tony Lindgren <tony@atomide.com> 68bd22949SKevin Hilman * Jouni Hogander 78bd22949SKevin Hilman * 82f5939c3SRajendra Nayak * Copyright (C) 2007 Texas Instruments, Inc. 92f5939c3SRajendra Nayak * Rajendra Nayak <rnayak@ti.com> 102f5939c3SRajendra Nayak * 118bd22949SKevin Hilman * Copyright (C) 2005 Texas Instruments, Inc. 128bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 138bd22949SKevin Hilman * 148bd22949SKevin Hilman * Based on pm.c for omap1 158bd22949SKevin Hilman * 168bd22949SKevin Hilman * This program is free software; you can redistribute it and/or modify 178bd22949SKevin Hilman * it under the terms of the GNU General Public License version 2 as 188bd22949SKevin Hilman * published by the Free Software Foundation. 198bd22949SKevin Hilman */ 208bd22949SKevin Hilman 218bd22949SKevin Hilman #include <linux/pm.h> 228bd22949SKevin Hilman #include <linux/suspend.h> 238bd22949SKevin Hilman #include <linux/interrupt.h> 248bd22949SKevin Hilman #include <linux/module.h> 258bd22949SKevin Hilman #include <linux/list.h> 268bd22949SKevin Hilman #include <linux/err.h> 278bd22949SKevin Hilman #include <linux/gpio.h> 28c40552bcSKevin Hilman #include <linux/clk.h> 29dccaad89STero Kristo #include <linux/delay.h> 305a0e3ad6STejun Heo #include <linux/slab.h> 3145c3eb7dSTony Lindgren #include <linux/omap-dma.h> 32e639cd5bSTony Lindgren #include <linux/omap-gpmc.h> 334b25408fSTony Lindgren #include <linux/platform_data/gpio-omap.h> 344b25408fSTony Lindgren 355e7c58dcSJean Pihet #include <trace/events/power.h> 368bd22949SKevin Hilman 37bf027ca1STony Lindgren #include <asm/fncpy.h> 382c74a0ceSRussell King #include <asm/suspend.h> 399f97da78SDavid Howells #include <asm/system_misc.h> 402c74a0ceSRussell King 411540f214SPaul Walmsley #include "clockdomain.h" 4272e06d08SPaul Walmsley #include "powerdomain.h" 43e4c060dbSTony Lindgren #include "soc.h" 444e65331cSTony Lindgren #include "common.h" 45ff4ae5d9SPaul Walmsley #include "cm3xxx.h" 468bd22949SKevin Hilman #include "cm-regbits-34xx.h" 478bd22949SKevin Hilman #include "prm-regbits-34xx.h" 48139563adSPaul Walmsley #include "prm3xxx.h" 498bd22949SKevin Hilman #include "pm.h" 5013a6fe0fSTero Kristo #include "sdrc.h" 51bf027ca1STony Lindgren #include "sram.h" 524814ced5SPaul Walmsley #include "control.h" 533b8c4ebbSTony Lindgren #include "vc.h" 5413a6fe0fSTero Kristo 558cdfd834SNishanth Menon /* pm34xx errata defined in pm.h */ 568cdfd834SNishanth Menon u16 pm34xx_errata; 578cdfd834SNishanth Menon 588bd22949SKevin Hilman struct power_state { 598bd22949SKevin Hilman struct powerdomain *pwrdm; 608bd22949SKevin Hilman u32 next_state; 6110f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 628bd22949SKevin Hilman u32 saved_state; 6310f90ed2SKevin Hilman #endif 648bd22949SKevin Hilman struct list_head node; 658bd22949SKevin Hilman }; 668bd22949SKevin Hilman 678bd22949SKevin Hilman static LIST_HEAD(pwrst_list); 688bd22949SKevin Hilman 6927d59a4aSTero Kristo static int (*_omap_save_secure_sram)(u32 *addr); 7046e130d2SJean Pihet void (*omap3_do_wfi_sram)(void); 7127d59a4aSTero Kristo 72fa3c2a4fSRajendra Nayak static struct powerdomain *mpu_pwrdm, *neon_pwrdm; 73fa3c2a4fSRajendra Nayak static struct powerdomain *core_pwrdm, *per_pwrdm; 743a7ec26bSKalle Jokiniemi 752f5939c3SRajendra Nayak static void omap3_core_save_context(void) 762f5939c3SRajendra Nayak { 77596efe47SPaul Walmsley omap3_ctrl_save_padconf(); 78dccaad89STero Kristo 79dccaad89STero Kristo /* 80dccaad89STero Kristo * Force write last pad into memory, as this can fail in some 8183521291SJean Pihet * cases according to errata 1.157, 1.185 82dccaad89STero Kristo */ 83dccaad89STero Kristo omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), 84dccaad89STero Kristo OMAP343X_CONTROL_MEM_WKUP + 0x2a0); 85dccaad89STero Kristo 862f5939c3SRajendra Nayak /* Save the Interrupt controller context */ 872f5939c3SRajendra Nayak omap_intc_save_context(); 882f5939c3SRajendra Nayak /* Save the GPMC context */ 892f5939c3SRajendra Nayak omap3_gpmc_save_context(); 902f5939c3SRajendra Nayak /* Save the system control module context, padconf already save above*/ 912f5939c3SRajendra Nayak omap3_control_save_context(); 92f2d11858STero Kristo omap_dma_global_context_save(); 932f5939c3SRajendra Nayak } 942f5939c3SRajendra Nayak 952f5939c3SRajendra Nayak static void omap3_core_restore_context(void) 962f5939c3SRajendra Nayak { 972f5939c3SRajendra Nayak /* Restore the control module context, padconf restored by h/w */ 982f5939c3SRajendra Nayak omap3_control_restore_context(); 992f5939c3SRajendra Nayak /* Restore the GPMC context */ 1002f5939c3SRajendra Nayak omap3_gpmc_restore_context(); 1012f5939c3SRajendra Nayak /* Restore the interrupt controller context */ 1022f5939c3SRajendra Nayak omap_intc_restore_context(); 103f2d11858STero Kristo omap_dma_global_context_restore(); 1042f5939c3SRajendra Nayak } 1052f5939c3SRajendra Nayak 1069d97140bSTero Kristo /* 1079d97140bSTero Kristo * FIXME: This function should be called before entering off-mode after 1089d97140bSTero Kristo * OMAP3 secure services have been accessed. Currently it is only called 1099d97140bSTero Kristo * once during boot sequence, but this works as we are not using secure 1109d97140bSTero Kristo * services. 1119d97140bSTero Kristo */ 112617fcc98SKevin Hilman static void omap3_save_secure_ram_context(void) 11327d59a4aSTero Kristo { 11427d59a4aSTero Kristo u32 ret; 115617fcc98SKevin Hilman int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 11627d59a4aSTero Kristo 11727d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 11827d59a4aSTero Kristo /* 11927d59a4aSTero Kristo * MPU next state must be set to POWER_ON temporarily, 12027d59a4aSTero Kristo * otherwise the WFI executed inside the ROM code 12127d59a4aSTero Kristo * will hang the system. 12227d59a4aSTero Kristo */ 12327d59a4aSTero Kristo pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); 1246dd1e357SOlof Johansson ret = _omap_save_secure_sram((u32 *)(unsigned long) 12527d59a4aSTero Kristo __pa(omap3_secure_ram_storage)); 126617fcc98SKevin Hilman pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state); 12727d59a4aSTero Kristo /* Following is for error tracking, it should not happen */ 12827d59a4aSTero Kristo if (ret) { 12998179856SMark A. Greer pr_err("save_secure_sram() returns %08x\n", ret); 13027d59a4aSTero Kristo while (1) 13127d59a4aSTero Kristo ; 13227d59a4aSTero Kristo } 13327d59a4aSTero Kristo } 13427d59a4aSTero Kristo } 13527d59a4aSTero Kristo 13622f51371STero Kristo static irqreturn_t _prcm_int_handle_io(int irq, void *unused) 1378cb0ac99SPaul Walmsley { 1388cb0ac99SPaul Walmsley int c; 1398cb0ac99SPaul Walmsley 1409cb6d363STero Kristo c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, OMAP3430_ST_IO_MASK | 141f0caa527STero Kristo OMAP3430_ST_IO_CHAIN_MASK); 14222f51371STero Kristo 14322f51371STero Kristo return c ? IRQ_HANDLED : IRQ_NONE; 1448cb0ac99SPaul Walmsley } 1458cb0ac99SPaul Walmsley 14622f51371STero Kristo static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused) 1478bd22949SKevin Hilman { 14822f51371STero Kristo int c; 1498cb0ac99SPaul Walmsley 1508cb0ac99SPaul Walmsley /* 15122f51371STero Kristo * Clear all except ST_IO and ST_IO_CHAIN for wkup module, 15222f51371STero Kristo * these are handled in a separate handler to avoid acking 15322f51371STero Kristo * IO events before parsing in mux code 1548cb0ac99SPaul Walmsley */ 1559cb6d363STero Kristo c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, ~(OMAP3430_ST_IO_MASK | 156f0caa527STero Kristo OMAP3430_ST_IO_CHAIN_MASK)); 1579cb6d363STero Kristo c += omap_prm_clear_mod_irqs(CORE_MOD, 1, ~0); 1589cb6d363STero Kristo c += omap_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, ~0); 15922f51371STero Kristo if (omap_rev() > OMAP3430_REV_ES1_0) { 1609cb6d363STero Kristo c += omap_prm_clear_mod_irqs(CORE_MOD, 3, ~0); 1619cb6d363STero Kristo c += omap_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, ~0); 1628cb0ac99SPaul Walmsley } 1638cb0ac99SPaul Walmsley 16422f51371STero Kristo return c ? IRQ_HANDLED : IRQ_NONE; 1658bd22949SKevin Hilman } 1668bd22949SKevin Hilman 167cbe26349SRussell King static void omap34xx_save_context(u32 *save) 168cbe26349SRussell King { 169cbe26349SRussell King u32 val; 170cbe26349SRussell King 171cbe26349SRussell King /* Read Auxiliary Control Register */ 172cbe26349SRussell King asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val)); 173cbe26349SRussell King *save++ = 1; 174cbe26349SRussell King *save++ = val; 175cbe26349SRussell King 176cbe26349SRussell King /* Read L2 AUX ctrl register */ 177cbe26349SRussell King asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); 178cbe26349SRussell King *save++ = 1; 179cbe26349SRussell King *save++ = val; 180cbe26349SRussell King } 181cbe26349SRussell King 18229cb3cd2SRussell King static int omap34xx_do_sram_idle(unsigned long save_state) 18357f277b0SRajendra Nayak { 184cbe26349SRussell King omap34xx_cpu_suspend(save_state); 18529cb3cd2SRussell King return 0; 18657f277b0SRajendra Nayak } 18757f277b0SRajendra Nayak 18899e6a4d2SRajendra Nayak void omap_sram_idle(void) 1898bd22949SKevin Hilman { 1908bd22949SKevin Hilman /* Variable to tell what needs to be saved and restored 1918bd22949SKevin Hilman * in omap_sram_idle*/ 1928bd22949SKevin Hilman /* save_state = 0 => Nothing to save and restored */ 1938bd22949SKevin Hilman /* save_state = 1 => Only L1 and logic lost */ 1948bd22949SKevin Hilman /* save_state = 2 => Only L2 lost */ 1958bd22949SKevin Hilman /* save_state = 3 => L1, L2 and logic lost */ 196fa3c2a4fSRajendra Nayak int save_state = 0; 197fa3c2a4fSRajendra Nayak int mpu_next_state = PWRDM_POWER_ON; 198fa3c2a4fSRajendra Nayak int per_next_state = PWRDM_POWER_ON; 199fa3c2a4fSRajendra Nayak int core_next_state = PWRDM_POWER_ON; 20072e06d08SPaul Walmsley int per_going_off; 201eeb3711bSPaul Walmsley int core_prev_state; 20213a6fe0fSTero Kristo u32 sdrc_pwr = 0; 2038bd22949SKevin Hilman 2048bd22949SKevin Hilman mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 2058bd22949SKevin Hilman switch (mpu_next_state) { 206fa3c2a4fSRajendra Nayak case PWRDM_POWER_ON: 2078bd22949SKevin Hilman case PWRDM_POWER_RET: 2088bd22949SKevin Hilman /* No need to save context */ 2098bd22949SKevin Hilman save_state = 0; 2108bd22949SKevin Hilman break; 21161255ab9SRajendra Nayak case PWRDM_POWER_OFF: 21261255ab9SRajendra Nayak save_state = 3; 21361255ab9SRajendra Nayak break; 2148bd22949SKevin Hilman default: 2158bd22949SKevin Hilman /* Invalid state */ 21698179856SMark A. Greer pr_err("Invalid mpu state in sram_idle\n"); 2178bd22949SKevin Hilman return; 2188bd22949SKevin Hilman } 219fe617af7SPeter 'p2' De Schrijver 220fa3c2a4fSRajendra Nayak /* NEON control */ 221fa3c2a4fSRajendra Nayak if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) 2227139178eSJouni Hogander pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); 223fa3c2a4fSRajendra Nayak 22440742fa8SMike Chan /* Enable IO-PAD and IO-CHAIN wakeups */ 225fa3c2a4fSRajendra Nayak per_next_state = pwrdm_read_next_pwrst(per_pwrdm); 226ecf157d0STero Kristo core_next_state = pwrdm_read_next_pwrst(core_pwrdm); 22740742fa8SMike Chan 228e0e29fd7SKevin Hilman pwrdm_pre_transition(NULL); 229ff2f8e5fSCharulatha V 23040742fa8SMike Chan /* PER */ 2312f5939c3SRajendra Nayak if (per_next_state < PWRDM_POWER_ON) { 23272e06d08SPaul Walmsley per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0; 23372e06d08SPaul Walmsley omap2_gpio_prepare_for_idle(per_going_off); 2342f5939c3SRajendra Nayak } 235c16c3f67STero Kristo 236658ce97eSKevin Hilman /* CORE */ 237658ce97eSKevin Hilman if (core_next_state < PWRDM_POWER_ON) { 2382f5939c3SRajendra Nayak if (core_next_state == PWRDM_POWER_OFF) { 2392f5939c3SRajendra Nayak omap3_core_save_context(); 240f0611a5cSPaul Walmsley omap3_cm_save_context(); 2412f5939c3SRajendra Nayak } 242fa3c2a4fSRajendra Nayak } 24340742fa8SMike Chan 2443b8c4ebbSTony Lindgren /* Configure PMIC signaling for I2C4 or sys_off_mode */ 2453b8c4ebbSTony Lindgren omap3_vc_set_pmic_signaling(core_next_state); 2463b8c4ebbSTony Lindgren 247f18cc2ffSTero Kristo omap3_intc_prepare_idle(); 2488bd22949SKevin Hilman 24961255ab9SRajendra Nayak /* 250f265dc4cSRajendra Nayak * On EMU/HS devices ROM code restores a SRDC value 251f265dc4cSRajendra Nayak * from scratchpad which has automatic self refresh on timeout 25283521291SJean Pihet * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443. 253f265dc4cSRajendra Nayak * Hence store/restore the SDRC_POWER register here. 25413a6fe0fSTero Kristo */ 25530474544SPaul Walmsley if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && 25630474544SPaul Walmsley (omap_type() == OMAP2_DEVICE_TYPE_EMU || 25730474544SPaul Walmsley omap_type() == OMAP2_DEVICE_TYPE_SEC) && 258f265dc4cSRajendra Nayak core_next_state == PWRDM_POWER_OFF) 25913a6fe0fSTero Kristo sdrc_pwr = sdrc_read_reg(SDRC_POWER); 26013a6fe0fSTero Kristo 26113a6fe0fSTero Kristo /* 262076f2cc4SRussell King * omap3_arm_context is the location where some ARM context 263076f2cc4SRussell King * get saved. The rest is placed on the stack, and restored 264076f2cc4SRussell King * from there before resuming. 26561255ab9SRajendra Nayak */ 266cbe26349SRussell King if (save_state) 267cbe26349SRussell King omap34xx_save_context(omap3_arm_context); 268076f2cc4SRussell King if (save_state == 1 || save_state == 3) 2692c74a0ceSRussell King cpu_suspend(save_state, omap34xx_do_sram_idle); 270076f2cc4SRussell King else 271076f2cc4SRussell King omap34xx_do_sram_idle(save_state); 2728bd22949SKevin Hilman 273f265dc4cSRajendra Nayak /* Restore normal SDRC POWER settings */ 27430474544SPaul Walmsley if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && 27530474544SPaul Walmsley (omap_type() == OMAP2_DEVICE_TYPE_EMU || 27630474544SPaul Walmsley omap_type() == OMAP2_DEVICE_TYPE_SEC) && 27713a6fe0fSTero Kristo core_next_state == PWRDM_POWER_OFF) 27813a6fe0fSTero Kristo sdrc_write_reg(sdrc_pwr, SDRC_POWER); 27913a6fe0fSTero Kristo 280658ce97eSKevin Hilman /* CORE */ 281fa3c2a4fSRajendra Nayak if (core_next_state < PWRDM_POWER_ON) { 2822f5939c3SRajendra Nayak core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); 2832f5939c3SRajendra Nayak if (core_prev_state == PWRDM_POWER_OFF) { 2842f5939c3SRajendra Nayak omap3_core_restore_context(); 285f0611a5cSPaul Walmsley omap3_cm_restore_context(); 2862f5939c3SRajendra Nayak omap3_sram_restore_context(); 2878a917d2fSKalle Jokiniemi omap2_sms_restore_context(); 2882f5939c3SRajendra Nayak } 289658ce97eSKevin Hilman } 290f18cc2ffSTero Kristo omap3_intc_resume_idle(); 291658ce97eSKevin Hilman 292e0e29fd7SKevin Hilman pwrdm_post_transition(NULL); 293658ce97eSKevin Hilman 294e0e29fd7SKevin Hilman /* PER */ 295e0e29fd7SKevin Hilman if (per_next_state < PWRDM_POWER_ON) 296e0e29fd7SKevin Hilman omap2_gpio_resume_after_idle(); 2978bd22949SKevin Hilman } 2988bd22949SKevin Hilman 2998bd22949SKevin Hilman static void omap3_pm_idle(void) 3008bd22949SKevin Hilman { 3010bcd24b0SNicolas Pitre if (omap_irq_pending()) 3026b85638bSSantosh Shilimkar return; 3038bd22949SKevin Hilman 3046ca22700SJisheng Zhang trace_cpu_idle_rcuidle(1, smp_processor_id()); 3055e7c58dcSJean Pihet 3068bd22949SKevin Hilman omap_sram_idle(); 3078bd22949SKevin Hilman 3086ca22700SJisheng Zhang trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); 3098bd22949SKevin Hilman } 3108bd22949SKevin Hilman 31110f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 3128bd22949SKevin Hilman static int omap3_pm_suspend(void) 3138bd22949SKevin Hilman { 3148bd22949SKevin Hilman struct power_state *pwrst; 3158bd22949SKevin Hilman int state, ret = 0; 3168bd22949SKevin Hilman 3178bd22949SKevin Hilman /* Read current next_pwrsts */ 3188bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) 3198bd22949SKevin Hilman pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 3208bd22949SKevin Hilman /* Set ones wanted by suspend */ 3218bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 322eb6a2c75SSantosh Shilimkar if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) 3238bd22949SKevin Hilman goto restore; 3248bd22949SKevin Hilman if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) 3258bd22949SKevin Hilman goto restore; 3268bd22949SKevin Hilman } 3278bd22949SKevin Hilman 3282bbe3af3STero Kristo omap3_intc_suspend(); 3292bbe3af3STero Kristo 3308bd22949SKevin Hilman omap_sram_idle(); 3318bd22949SKevin Hilman 3328bd22949SKevin Hilman restore: 3338bd22949SKevin Hilman /* Restore next_pwrsts */ 3348bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 3358bd22949SKevin Hilman state = pwrdm_read_prev_pwrst(pwrst->pwrdm); 3368bd22949SKevin Hilman if (state > pwrst->next_state) { 3377852ec05SPaul Walmsley pr_info("Powerdomain (%s) didn't enter target state %d\n", 3388bd22949SKevin Hilman pwrst->pwrdm->name, pwrst->next_state); 3398bd22949SKevin Hilman ret = -1; 3408bd22949SKevin Hilman } 341eb6a2c75SSantosh Shilimkar omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); 3428bd22949SKevin Hilman } 3438bd22949SKevin Hilman if (ret) 34498179856SMark A. Greer pr_err("Could not enter target state in pm_suspend\n"); 3458bd22949SKevin Hilman else 34698179856SMark A. Greer pr_info("Successfully put all powerdomains to target state\n"); 3478bd22949SKevin Hilman 3488bd22949SKevin Hilman return ret; 3498bd22949SKevin Hilman } 3502e4b62dcSDave Gerlach #else 3512e4b62dcSDave Gerlach #define omap3_pm_suspend NULL 35210f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 3538bd22949SKevin Hilman 3548111b221SKevin Hilman static void __init prcm_setup_regs(void) 3558111b221SKevin Hilman { 356ba12c242STero Kristo omap3_ctrl_init(); 357b296c811STero Kristo 358c5180a2bSTero Kristo omap3_prm_init_pm(cpu_is_omap3630(), omap3_has_iva()); 3598bd22949SKevin Hilman } 3608bd22949SKevin Hilman 361c40552bcSKevin Hilman void omap3_pm_off_mode_enable(int enable) 362c40552bcSKevin Hilman { 363c40552bcSKevin Hilman struct power_state *pwrst; 364c40552bcSKevin Hilman u32 state; 365c40552bcSKevin Hilman 366c40552bcSKevin Hilman if (enable) 367c40552bcSKevin Hilman state = PWRDM_POWER_OFF; 368c40552bcSKevin Hilman else 369c40552bcSKevin Hilman state = PWRDM_POWER_RET; 370c40552bcSKevin Hilman 371c40552bcSKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 372cc1b6028SEduardo Valentin if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) && 373cc1b6028SEduardo Valentin pwrst->pwrdm == core_pwrdm && 374cc1b6028SEduardo Valentin state == PWRDM_POWER_OFF) { 375cc1b6028SEduardo Valentin pwrst->next_state = PWRDM_POWER_RET; 376e16b41bfSRicardo Salveti de Araujo pr_warn("%s: Core OFF disabled due to errata i583\n", 377cc1b6028SEduardo Valentin __func__); 378cc1b6028SEduardo Valentin } else { 379c40552bcSKevin Hilman pwrst->next_state = state; 380cc1b6028SEduardo Valentin } 381cc1b6028SEduardo Valentin omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 382c40552bcSKevin Hilman } 383c40552bcSKevin Hilman } 384c40552bcSKevin Hilman 38568d4778cSTero Kristo int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) 38668d4778cSTero Kristo { 38768d4778cSTero Kristo struct power_state *pwrst; 38868d4778cSTero Kristo 38968d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 39068d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) 39168d4778cSTero Kristo return pwrst->next_state; 39268d4778cSTero Kristo } 39368d4778cSTero Kristo return -EINVAL; 39468d4778cSTero Kristo } 39568d4778cSTero Kristo 39668d4778cSTero Kristo int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) 39768d4778cSTero Kristo { 39868d4778cSTero Kristo struct power_state *pwrst; 39968d4778cSTero Kristo 40068d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 40168d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) { 40268d4778cSTero Kristo pwrst->next_state = state; 40368d4778cSTero Kristo return 0; 40468d4778cSTero Kristo } 40568d4778cSTero Kristo } 40668d4778cSTero Kristo return -EINVAL; 40768d4778cSTero Kristo } 40868d4778cSTero Kristo 409a23456e9SPeter 'p2' De Schrijver static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) 4108bd22949SKevin Hilman { 4118bd22949SKevin Hilman struct power_state *pwrst; 4128bd22949SKevin Hilman 4138bd22949SKevin Hilman if (!pwrdm->pwrsts) 4148bd22949SKevin Hilman return 0; 4158bd22949SKevin Hilman 416d3d381c6SMing Lei pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); 4178bd22949SKevin Hilman if (!pwrst) 4188bd22949SKevin Hilman return -ENOMEM; 4198bd22949SKevin Hilman pwrst->pwrdm = pwrdm; 4208bd22949SKevin Hilman pwrst->next_state = PWRDM_POWER_RET; 4218bd22949SKevin Hilman list_add(&pwrst->node, &pwrst_list); 4228bd22949SKevin Hilman 4238bd22949SKevin Hilman if (pwrdm_has_hdwr_sar(pwrdm)) 4248bd22949SKevin Hilman pwrdm_enable_hdwr_sar(pwrdm); 4258bd22949SKevin Hilman 426eb6a2c75SSantosh Shilimkar return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 4278bd22949SKevin Hilman } 4288bd22949SKevin Hilman 4298bd22949SKevin Hilman /* 43046e130d2SJean Pihet * Push functions to SRAM 43146e130d2SJean Pihet * 43246e130d2SJean Pihet * The minimum set of functions is pushed to SRAM for execution: 43346e130d2SJean Pihet * - omap3_do_wfi for erratum i581 WA, 43446e130d2SJean Pihet * - save_secure_ram_context for security extensions. 43546e130d2SJean Pihet */ 4363231fc88SRajendra Nayak void omap_push_sram_idle(void) 4373231fc88SRajendra Nayak { 43846e130d2SJean Pihet omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz); 43946e130d2SJean Pihet 44027d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) 44127d59a4aSTero Kristo _omap_save_secure_sram = omap_sram_push(save_secure_ram_context, 44227d59a4aSTero Kristo save_secure_ram_context_sz); 4433231fc88SRajendra Nayak } 4443231fc88SRajendra Nayak 4458cdfd834SNishanth Menon static void __init pm_errata_configure(void) 4468cdfd834SNishanth Menon { 447c4236d2eSPeter 'p2' De Schrijver if (cpu_is_omap3630()) { 448458e999eSNishanth Menon pm34xx_errata |= PM_RTA_ERRATUM_i608; 449c4236d2eSPeter 'p2' De Schrijver /* Enable the l2 cache toggling in sleep logic */ 450c4236d2eSPeter 'p2' De Schrijver enable_omap3630_toggle_l2_on_restore(); 451cc1b6028SEduardo Valentin if (omap_rev() < OMAP3630_REV_ES1_2) 452856c3c5bSPaul Walmsley pm34xx_errata |= (PM_SDRC_WAKEUP_ERRATUM_i583 | 453856c3c5bSPaul Walmsley PM_PER_MEMORIES_ERRATUM_i582); 454856c3c5bSPaul Walmsley } else if (cpu_is_omap34xx()) { 455856c3c5bSPaul Walmsley pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582; 456c4236d2eSPeter 'p2' De Schrijver } 4578cdfd834SNishanth Menon } 4588cdfd834SNishanth Menon 459bbd707acSShawn Guo int __init omap3_pm_init(void) 4608bd22949SKevin Hilman { 4618bd22949SKevin Hilman struct power_state *pwrst, *tmp; 462856c3c5bSPaul Walmsley struct clockdomain *neon_clkdm, *mpu_clkdm, *per_clkdm, *wkup_clkdm; 4638bd22949SKevin Hilman int ret; 4648bd22949SKevin Hilman 465b02b9172SPaul Walmsley if (!omap3_has_io_chain_ctrl()) 4663d0cb73eSJoe Perches pr_warn("PM: no software I/O chain control; some wakeups may be lost\n"); 467b02b9172SPaul Walmsley 4688cdfd834SNishanth Menon pm_errata_configure(); 4698cdfd834SNishanth Menon 4708bd22949SKevin Hilman /* XXX prcm_setup_regs needs to be before enabling hw 4718bd22949SKevin Hilman * supervised mode for powerdomains */ 4728bd22949SKevin Hilman prcm_setup_regs(); 4738bd22949SKevin Hilman 47422f51371STero Kristo ret = request_irq(omap_prcm_event_to_irq("wkup"), 47522f51371STero Kristo _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL); 47622f51371STero Kristo 4778bd22949SKevin Hilman if (ret) { 47822f51371STero Kristo pr_err("pm: Failed to request pm_wkup irq\n"); 47922f51371STero Kristo goto err1; 48022f51371STero Kristo } 48122f51371STero Kristo 48222f51371STero Kristo /* IO interrupt is shared with mux code */ 48322f51371STero Kristo ret = request_irq(omap_prcm_event_to_irq("io"), 48422f51371STero Kristo _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io", 48522f51371STero Kristo omap3_pm_init); 48699b59df0SKevin Hilman enable_irq(omap_prcm_event_to_irq("io")); 48722f51371STero Kristo 48822f51371STero Kristo if (ret) { 48922f51371STero Kristo pr_err("pm: Failed to request pm_io irq\n"); 490ce229c5dSMark A. Greer goto err2; 4918bd22949SKevin Hilman } 4928bd22949SKevin Hilman 493a23456e9SPeter 'p2' De Schrijver ret = pwrdm_for_each(pwrdms_setup, NULL); 4948bd22949SKevin Hilman if (ret) { 49598179856SMark A. Greer pr_err("Failed to setup powerdomains\n"); 496ce229c5dSMark A. Greer goto err3; 4978bd22949SKevin Hilman } 4988bd22949SKevin Hilman 49992206fd2SPaul Walmsley (void) clkdm_for_each(omap_pm_clkdms_setup, NULL); 5008bd22949SKevin Hilman 5018bd22949SKevin Hilman mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); 5028bd22949SKevin Hilman if (mpu_pwrdm == NULL) { 50398179856SMark A. Greer pr_err("Failed to get mpu_pwrdm\n"); 504ce229c5dSMark A. Greer ret = -EINVAL; 505ce229c5dSMark A. Greer goto err3; 5068bd22949SKevin Hilman } 5078bd22949SKevin Hilman 508fa3c2a4fSRajendra Nayak neon_pwrdm = pwrdm_lookup("neon_pwrdm"); 509fa3c2a4fSRajendra Nayak per_pwrdm = pwrdm_lookup("per_pwrdm"); 510fa3c2a4fSRajendra Nayak core_pwrdm = pwrdm_lookup("core_pwrdm"); 511fa3c2a4fSRajendra Nayak 51255ed9694SPaul Walmsley neon_clkdm = clkdm_lookup("neon_clkdm"); 51355ed9694SPaul Walmsley mpu_clkdm = clkdm_lookup("mpu_clkdm"); 514856c3c5bSPaul Walmsley per_clkdm = clkdm_lookup("per_clkdm"); 515856c3c5bSPaul Walmsley wkup_clkdm = clkdm_lookup("wkup_clkdm"); 51655ed9694SPaul Walmsley 5172e4b62dcSDave Gerlach omap_common_suspend_init(omap3_pm_suspend); 5188bd22949SKevin Hilman 5190bcd24b0SNicolas Pitre arm_pm_idle = omap3_pm_idle; 5200343371eSKalle Jokiniemi omap3_idle_init(); 5218bd22949SKevin Hilman 522458e999eSNishanth Menon /* 523458e999eSNishanth Menon * RTA is disabled during initialization as per erratum i608 524458e999eSNishanth Menon * it is safer to disable RTA by the bootloader, but we would like 525458e999eSNishanth Menon * to be doubly sure here and prevent any mishaps. 526458e999eSNishanth Menon */ 527458e999eSNishanth Menon if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608)) 528458e999eSNishanth Menon omap3630_ctrl_disable_rta(); 529458e999eSNishanth Menon 530856c3c5bSPaul Walmsley /* 531856c3c5bSPaul Walmsley * The UART3/4 FIFO and the sidetone memory in McBSP2/3 are 532856c3c5bSPaul Walmsley * not correctly reset when the PER powerdomain comes back 533856c3c5bSPaul Walmsley * from OFF or OSWR when the CORE powerdomain is kept active. 534856c3c5bSPaul Walmsley * See OMAP36xx Erratum i582 "PER Domain reset issue after 535856c3c5bSPaul Walmsley * Domain-OFF/OSWR Wakeup". This wakeup dependency is not a 536856c3c5bSPaul Walmsley * complete workaround. The kernel must also prevent the PER 537856c3c5bSPaul Walmsley * powerdomain from going to OSWR/OFF while the CORE 538856c3c5bSPaul Walmsley * powerdomain is not going to OSWR/OFF. And if PER last 539856c3c5bSPaul Walmsley * power state was off while CORE last power state was ON, the 540856c3c5bSPaul Walmsley * UART3/4 and McBSP2/3 SIDETONE devices need to run a 541856c3c5bSPaul Walmsley * self-test using their loopback tests; if that fails, those 542856c3c5bSPaul Walmsley * devices are unusable until the PER/CORE can complete a transition 543856c3c5bSPaul Walmsley * from ON to OSWR/OFF and then back to ON. 544856c3c5bSPaul Walmsley * 545856c3c5bSPaul Walmsley * XXX Technically this workaround is only needed if off-mode 546856c3c5bSPaul Walmsley * or OSWR is enabled. 547856c3c5bSPaul Walmsley */ 548856c3c5bSPaul Walmsley if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582)) 549856c3c5bSPaul Walmsley clkdm_add_wkdep(per_clkdm, wkup_clkdm); 550856c3c5bSPaul Walmsley 55155ed9694SPaul Walmsley clkdm_add_wkdep(neon_clkdm, mpu_clkdm); 55227d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 55327d59a4aSTero Kristo omap3_secure_ram_storage = 55427d59a4aSTero Kristo kmalloc(0x803F, GFP_KERNEL); 55527d59a4aSTero Kristo if (!omap3_secure_ram_storage) 5567852ec05SPaul Walmsley pr_err("Memory allocation failed when allocating for secure sram context\n"); 55727d59a4aSTero Kristo 5589d97140bSTero Kristo local_irq_disable(); 5599d97140bSTero Kristo 5609d97140bSTero Kristo omap_dma_global_context_save(); 561617fcc98SKevin Hilman omap3_save_secure_ram_context(); 5629d97140bSTero Kristo omap_dma_global_context_restore(); 5639d97140bSTero Kristo 5649d97140bSTero Kristo local_irq_enable(); 5659d97140bSTero Kristo } 5669d97140bSTero Kristo 5679d97140bSTero Kristo omap3_save_scratchpad_contents(); 5688bd22949SKevin Hilman return ret; 569ce229c5dSMark A. Greer 570ce229c5dSMark A. Greer err3: 5718bd22949SKevin Hilman list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { 5728bd22949SKevin Hilman list_del(&pwrst->node); 5738bd22949SKevin Hilman kfree(pwrst); 5748bd22949SKevin Hilman } 575ce229c5dSMark A. Greer free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init); 576ce229c5dSMark A. Greer err2: 577ce229c5dSMark A. Greer free_irq(omap_prcm_event_to_irq("wkup"), NULL); 578ce229c5dSMark A. Greer err1: 5798bd22949SKevin Hilman return ret; 5808bd22949SKevin Hilman } 581