18bd22949SKevin Hilman /* 28bd22949SKevin Hilman * OMAP3 Power Management Routines 38bd22949SKevin Hilman * 48bd22949SKevin Hilman * Copyright (C) 2006-2008 Nokia Corporation 58bd22949SKevin Hilman * Tony Lindgren <tony@atomide.com> 68bd22949SKevin Hilman * Jouni Hogander 78bd22949SKevin Hilman * 82f5939c3SRajendra Nayak * Copyright (C) 2007 Texas Instruments, Inc. 92f5939c3SRajendra Nayak * Rajendra Nayak <rnayak@ti.com> 102f5939c3SRajendra Nayak * 118bd22949SKevin Hilman * Copyright (C) 2005 Texas Instruments, Inc. 128bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 138bd22949SKevin Hilman * 148bd22949SKevin Hilman * Based on pm.c for omap1 158bd22949SKevin Hilman * 168bd22949SKevin Hilman * This program is free software; you can redistribute it and/or modify 178bd22949SKevin Hilman * it under the terms of the GNU General Public License version 2 as 188bd22949SKevin Hilman * published by the Free Software Foundation. 198bd22949SKevin Hilman */ 208bd22949SKevin Hilman 218bd22949SKevin Hilman #include <linux/pm.h> 228bd22949SKevin Hilman #include <linux/suspend.h> 238bd22949SKevin Hilman #include <linux/interrupt.h> 248bd22949SKevin Hilman #include <linux/module.h> 258bd22949SKevin Hilman #include <linux/list.h> 268bd22949SKevin Hilman #include <linux/err.h> 278bd22949SKevin Hilman #include <linux/gpio.h> 28c40552bcSKevin Hilman #include <linux/clk.h> 29dccaad89STero Kristo #include <linux/delay.h> 305a0e3ad6STejun Heo #include <linux/slab.h> 310d8e2d0dSPaul Walmsley #include <linux/console.h> 328bd22949SKevin Hilman 33ce491cf8STony Lindgren #include <plat/sram.h> 341540f214SPaul Walmsley #include "clockdomain.h" 3572e06d08SPaul Walmsley #include "powerdomain.h" 36ce491cf8STony Lindgren #include <plat/serial.h> 3761255ab9SRajendra Nayak #include <plat/sdrc.h> 382f5939c3SRajendra Nayak #include <plat/prcm.h> 392f5939c3SRajendra Nayak #include <plat/gpmc.h> 40f2d11858STero Kristo #include <plat/dma.h> 418bd22949SKevin Hilman 4257f277b0SRajendra Nayak #include <asm/tlbflush.h> 4357f277b0SRajendra Nayak 4459fb659bSPaul Walmsley #include "cm2xxx_3xxx.h" 458bd22949SKevin Hilman #include "cm-regbits-34xx.h" 468bd22949SKevin Hilman #include "prm-regbits-34xx.h" 478bd22949SKevin Hilman 4859fb659bSPaul Walmsley #include "prm2xxx_3xxx.h" 498bd22949SKevin Hilman #include "pm.h" 5013a6fe0fSTero Kristo #include "sdrc.h" 514814ced5SPaul Walmsley #include "control.h" 5213a6fe0fSTero Kristo 53e83df17fSKevin Hilman #ifdef CONFIG_SUSPEND 54e83df17fSKevin Hilman static suspend_state_t suspend_state = PM_SUSPEND_ON; 55e83df17fSKevin Hilman static inline bool is_suspending(void) 56e83df17fSKevin Hilman { 57e83df17fSKevin Hilman return (suspend_state != PM_SUSPEND_ON); 58e83df17fSKevin Hilman } 59e83df17fSKevin Hilman #else 60e83df17fSKevin Hilman static inline bool is_suspending(void) 61e83df17fSKevin Hilman { 62e83df17fSKevin Hilman return false; 63e83df17fSKevin Hilman } 64e83df17fSKevin Hilman #endif 65e83df17fSKevin Hilman 662f5939c3SRajendra Nayak /* Scratchpad offsets */ 67de658158SKevin Hilman #define OMAP343X_TABLE_ADDRESS_OFFSET 0xc4 68de658158SKevin Hilman #define OMAP343X_TABLE_VALUE_OFFSET 0xc0 69de658158SKevin Hilman #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8 702f5939c3SRajendra Nayak 718cdfd834SNishanth Menon /* pm34xx errata defined in pm.h */ 728cdfd834SNishanth Menon u16 pm34xx_errata; 738cdfd834SNishanth Menon 748bd22949SKevin Hilman struct power_state { 758bd22949SKevin Hilman struct powerdomain *pwrdm; 768bd22949SKevin Hilman u32 next_state; 7710f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 788bd22949SKevin Hilman u32 saved_state; 7910f90ed2SKevin Hilman #endif 808bd22949SKevin Hilman struct list_head node; 818bd22949SKevin Hilman }; 828bd22949SKevin Hilman 838bd22949SKevin Hilman static LIST_HEAD(pwrst_list); 848bd22949SKevin Hilman 858bd22949SKevin Hilman static void (*_omap_sram_idle)(u32 *addr, int save_state); 868bd22949SKevin Hilman 8727d59a4aSTero Kristo static int (*_omap_save_secure_sram)(u32 *addr); 8827d59a4aSTero Kristo 89fa3c2a4fSRajendra Nayak static struct powerdomain *mpu_pwrdm, *neon_pwrdm; 90fa3c2a4fSRajendra Nayak static struct powerdomain *core_pwrdm, *per_pwrdm; 91c16c3f67STero Kristo static struct powerdomain *cam_pwrdm; 92fa3c2a4fSRajendra Nayak 932f5939c3SRajendra Nayak static inline void omap3_per_save_context(void) 942f5939c3SRajendra Nayak { 952f5939c3SRajendra Nayak omap_gpio_save_context(); 962f5939c3SRajendra Nayak } 972f5939c3SRajendra Nayak 982f5939c3SRajendra Nayak static inline void omap3_per_restore_context(void) 992f5939c3SRajendra Nayak { 1002f5939c3SRajendra Nayak omap_gpio_restore_context(); 1012f5939c3SRajendra Nayak } 1022f5939c3SRajendra Nayak 1033a7ec26bSKalle Jokiniemi static void omap3_enable_io_chain(void) 1043a7ec26bSKalle Jokiniemi { 1053a7ec26bSKalle Jokiniemi int timeout = 0; 1063a7ec26bSKalle Jokiniemi 1073a7ec26bSKalle Jokiniemi if (omap_rev() >= OMAP3430_REV_ES3_1) { 108c4d7e58fSPaul Walmsley omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, 1092bc4ef71SPaul Walmsley PM_WKEN); 1103a7ec26bSKalle Jokiniemi /* Do a readback to assure write has been done */ 111c4d7e58fSPaul Walmsley omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN); 1123a7ec26bSKalle Jokiniemi 113c4d7e58fSPaul Walmsley while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) & 1142bc4ef71SPaul Walmsley OMAP3430_ST_IO_CHAIN_MASK)) { 1153a7ec26bSKalle Jokiniemi timeout++; 1163a7ec26bSKalle Jokiniemi if (timeout > 1000) { 1173a7ec26bSKalle Jokiniemi printk(KERN_ERR "Wake up daisy chain " 1183a7ec26bSKalle Jokiniemi "activation failed.\n"); 1193a7ec26bSKalle Jokiniemi return; 1203a7ec26bSKalle Jokiniemi } 121c4d7e58fSPaul Walmsley omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, 1220b96a3a3SKevin Hilman WKUP_MOD, PM_WKEN); 1233a7ec26bSKalle Jokiniemi } 1243a7ec26bSKalle Jokiniemi } 1253a7ec26bSKalle Jokiniemi } 1263a7ec26bSKalle Jokiniemi 1273a7ec26bSKalle Jokiniemi static void omap3_disable_io_chain(void) 1283a7ec26bSKalle Jokiniemi { 1293a7ec26bSKalle Jokiniemi if (omap_rev() >= OMAP3430_REV_ES3_1) 130c4d7e58fSPaul Walmsley omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, 1312bc4ef71SPaul Walmsley PM_WKEN); 1323a7ec26bSKalle Jokiniemi } 1333a7ec26bSKalle Jokiniemi 1342f5939c3SRajendra Nayak static void omap3_core_save_context(void) 1352f5939c3SRajendra Nayak { 136596efe47SPaul Walmsley omap3_ctrl_save_padconf(); 137dccaad89STero Kristo 138dccaad89STero Kristo /* 139dccaad89STero Kristo * Force write last pad into memory, as this can fail in some 14083521291SJean Pihet * cases according to errata 1.157, 1.185 141dccaad89STero Kristo */ 142dccaad89STero Kristo omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), 143dccaad89STero Kristo OMAP343X_CONTROL_MEM_WKUP + 0x2a0); 144dccaad89STero Kristo 1452f5939c3SRajendra Nayak /* Save the Interrupt controller context */ 1462f5939c3SRajendra Nayak omap_intc_save_context(); 1472f5939c3SRajendra Nayak /* Save the GPMC context */ 1482f5939c3SRajendra Nayak omap3_gpmc_save_context(); 1492f5939c3SRajendra Nayak /* Save the system control module context, padconf already save above*/ 1502f5939c3SRajendra Nayak omap3_control_save_context(); 151f2d11858STero Kristo omap_dma_global_context_save(); 1522f5939c3SRajendra Nayak } 1532f5939c3SRajendra Nayak 1542f5939c3SRajendra Nayak static void omap3_core_restore_context(void) 1552f5939c3SRajendra Nayak { 1562f5939c3SRajendra Nayak /* Restore the control module context, padconf restored by h/w */ 1572f5939c3SRajendra Nayak omap3_control_restore_context(); 1582f5939c3SRajendra Nayak /* Restore the GPMC context */ 1592f5939c3SRajendra Nayak omap3_gpmc_restore_context(); 1602f5939c3SRajendra Nayak /* Restore the interrupt controller context */ 1612f5939c3SRajendra Nayak omap_intc_restore_context(); 162f2d11858STero Kristo omap_dma_global_context_restore(); 1632f5939c3SRajendra Nayak } 1642f5939c3SRajendra Nayak 1659d97140bSTero Kristo /* 1669d97140bSTero Kristo * FIXME: This function should be called before entering off-mode after 1679d97140bSTero Kristo * OMAP3 secure services have been accessed. Currently it is only called 1689d97140bSTero Kristo * once during boot sequence, but this works as we are not using secure 1699d97140bSTero Kristo * services. 1709d97140bSTero Kristo */ 171617fcc98SKevin Hilman static void omap3_save_secure_ram_context(void) 17227d59a4aSTero Kristo { 17327d59a4aSTero Kristo u32 ret; 174617fcc98SKevin Hilman int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 17527d59a4aSTero Kristo 17627d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 17727d59a4aSTero Kristo /* 17827d59a4aSTero Kristo * MPU next state must be set to POWER_ON temporarily, 17927d59a4aSTero Kristo * otherwise the WFI executed inside the ROM code 18027d59a4aSTero Kristo * will hang the system. 18127d59a4aSTero Kristo */ 18227d59a4aSTero Kristo pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); 18327d59a4aSTero Kristo ret = _omap_save_secure_sram((u32 *) 18427d59a4aSTero Kristo __pa(omap3_secure_ram_storage)); 185617fcc98SKevin Hilman pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state); 18627d59a4aSTero Kristo /* Following is for error tracking, it should not happen */ 18727d59a4aSTero Kristo if (ret) { 18827d59a4aSTero Kristo printk(KERN_ERR "save_secure_sram() returns %08x\n", 18927d59a4aSTero Kristo ret); 19027d59a4aSTero Kristo while (1) 19127d59a4aSTero Kristo ; 19227d59a4aSTero Kristo } 19327d59a4aSTero Kristo } 19427d59a4aSTero Kristo } 19527d59a4aSTero Kristo 19677da2d91SJon Hunter /* 19777da2d91SJon Hunter * PRCM Interrupt Handler Helper Function 19877da2d91SJon Hunter * 19977da2d91SJon Hunter * The purpose of this function is to clear any wake-up events latched 20077da2d91SJon Hunter * in the PRCM PM_WKST_x registers. It is possible that a wake-up event 20177da2d91SJon Hunter * may occur whilst attempting to clear a PM_WKST_x register and thus 20277da2d91SJon Hunter * set another bit in this register. A while loop is used to ensure 20377da2d91SJon Hunter * that any peripheral wake-up events occurring while attempting to 20477da2d91SJon Hunter * clear the PM_WKST_x are detected and cleared. 20577da2d91SJon Hunter */ 2068cb0ac99SPaul Walmsley static int prcm_clear_mod_irqs(s16 module, u8 regs) 20777da2d91SJon Hunter { 20871a80775SVikram Pandita u32 wkst, fclk, iclk, clken; 20977da2d91SJon Hunter u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; 21077da2d91SJon Hunter u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; 21177da2d91SJon Hunter u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; 2125d805978SPaul Walmsley u16 grpsel_off = (regs == 3) ? 2135d805978SPaul Walmsley OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; 2148cb0ac99SPaul Walmsley int c = 0; 21577da2d91SJon Hunter 216c4d7e58fSPaul Walmsley wkst = omap2_prm_read_mod_reg(module, wkst_off); 217c4d7e58fSPaul Walmsley wkst &= omap2_prm_read_mod_reg(module, grpsel_off); 21877da2d91SJon Hunter if (wkst) { 219c4d7e58fSPaul Walmsley iclk = omap2_cm_read_mod_reg(module, iclk_off); 220c4d7e58fSPaul Walmsley fclk = omap2_cm_read_mod_reg(module, fclk_off); 22177da2d91SJon Hunter while (wkst) { 22271a80775SVikram Pandita clken = wkst; 223c4d7e58fSPaul Walmsley omap2_cm_set_mod_reg_bits(clken, module, iclk_off); 22471a80775SVikram Pandita /* 22571a80775SVikram Pandita * For USBHOST, we don't know whether HOST1 or 22671a80775SVikram Pandita * HOST2 woke us up, so enable both f-clocks 22771a80775SVikram Pandita */ 22871a80775SVikram Pandita if (module == OMAP3430ES2_USBHOST_MOD) 22971a80775SVikram Pandita clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; 230c4d7e58fSPaul Walmsley omap2_cm_set_mod_reg_bits(clken, module, fclk_off); 231c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(wkst, module, wkst_off); 232c4d7e58fSPaul Walmsley wkst = omap2_prm_read_mod_reg(module, wkst_off); 2338cb0ac99SPaul Walmsley c++; 23477da2d91SJon Hunter } 235c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(iclk, module, iclk_off); 236c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(fclk, module, fclk_off); 23777da2d91SJon Hunter } 2388cb0ac99SPaul Walmsley 2398cb0ac99SPaul Walmsley return c; 2408cb0ac99SPaul Walmsley } 2418cb0ac99SPaul Walmsley 2428cb0ac99SPaul Walmsley static int _prcm_int_handle_wakeup(void) 2438cb0ac99SPaul Walmsley { 2448cb0ac99SPaul Walmsley int c; 2458cb0ac99SPaul Walmsley 2468cb0ac99SPaul Walmsley c = prcm_clear_mod_irqs(WKUP_MOD, 1); 2478cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(CORE_MOD, 1); 2488cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1); 2498cb0ac99SPaul Walmsley if (omap_rev() > OMAP3430_REV_ES1_0) { 2508cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(CORE_MOD, 3); 2518cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1); 2528cb0ac99SPaul Walmsley } 2538cb0ac99SPaul Walmsley 2548cb0ac99SPaul Walmsley return c; 25577da2d91SJon Hunter } 25677da2d91SJon Hunter 25777da2d91SJon Hunter /* 25877da2d91SJon Hunter * PRCM Interrupt Handler 25977da2d91SJon Hunter * 26077da2d91SJon Hunter * The PRM_IRQSTATUS_MPU register indicates if there are any pending 26177da2d91SJon Hunter * interrupts from the PRCM for the MPU. These bits must be cleared in 26277da2d91SJon Hunter * order to clear the PRCM interrupt. The PRCM interrupt handler is 26377da2d91SJon Hunter * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear 26477da2d91SJon Hunter * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU 26577da2d91SJon Hunter * register indicates that a wake-up event is pending for the MPU and 26677da2d91SJon Hunter * this bit can only be cleared if the all the wake-up events latched 26777da2d91SJon Hunter * in the various PM_WKST_x registers have been cleared. The interrupt 26877da2d91SJon Hunter * handler is implemented using a do-while loop so that if a wake-up 26977da2d91SJon Hunter * event occurred during the processing of the prcm interrupt handler 27077da2d91SJon Hunter * (setting a bit in the corresponding PM_WKST_x register and thus 27177da2d91SJon Hunter * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register) 27277da2d91SJon Hunter * this would be handled. 27377da2d91SJon Hunter */ 2748bd22949SKevin Hilman static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) 2758bd22949SKevin Hilman { 276d6290a3eSKevin Hilman u32 irqenable_mpu, irqstatus_mpu; 2778cb0ac99SPaul Walmsley int c = 0; 2788bd22949SKevin Hilman 279c4d7e58fSPaul Walmsley irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD, 280d6290a3eSKevin Hilman OMAP3_PRM_IRQENABLE_MPU_OFFSET); 281c4d7e58fSPaul Walmsley irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD, 2828bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 283d6290a3eSKevin Hilman irqstatus_mpu &= irqenable_mpu; 2848cb0ac99SPaul Walmsley 285d6290a3eSKevin Hilman do { 2862bc4ef71SPaul Walmsley if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK | 2872bc4ef71SPaul Walmsley OMAP3430_IO_ST_MASK)) { 2888cb0ac99SPaul Walmsley c = _prcm_int_handle_wakeup(); 2898cb0ac99SPaul Walmsley 2908cb0ac99SPaul Walmsley /* 2918cb0ac99SPaul Walmsley * Is the MPU PRCM interrupt handler racing with the 2928cb0ac99SPaul Walmsley * IVA2 PRCM interrupt handler ? 2938cb0ac99SPaul Walmsley */ 2948cb0ac99SPaul Walmsley WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup " 2958cb0ac99SPaul Walmsley "but no wakeup sources are marked\n"); 2968cb0ac99SPaul Walmsley } else { 2978cb0ac99SPaul Walmsley /* XXX we need to expand our PRCM interrupt handler */ 2988cb0ac99SPaul Walmsley WARN(1, "prcm: WARNING: PRCM interrupt received, but " 2998cb0ac99SPaul Walmsley "no code to handle it (%08x)\n", irqstatus_mpu); 3008cb0ac99SPaul Walmsley } 3018cb0ac99SPaul Walmsley 302c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD, 3038bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 3048bd22949SKevin Hilman 305c4d7e58fSPaul Walmsley irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD, 306d6290a3eSKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 307d6290a3eSKevin Hilman irqstatus_mpu &= irqenable_mpu; 308d6290a3eSKevin Hilman 309d6290a3eSKevin Hilman } while (irqstatus_mpu); 3108bd22949SKevin Hilman 3118bd22949SKevin Hilman return IRQ_HANDLED; 3128bd22949SKevin Hilman } 3138bd22949SKevin Hilman 31457f277b0SRajendra Nayak static void restore_control_register(u32 val) 31557f277b0SRajendra Nayak { 31657f277b0SRajendra Nayak __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val)); 31757f277b0SRajendra Nayak } 31857f277b0SRajendra Nayak 31957f277b0SRajendra Nayak /* Function to restore the table entry that was modified for enabling MMU */ 32057f277b0SRajendra Nayak static void restore_table_entry(void) 32157f277b0SRajendra Nayak { 3224d63bc1dSManjunath Kondaiah G void __iomem *scratchpad_address; 32357f277b0SRajendra Nayak u32 previous_value, control_reg_value; 32457f277b0SRajendra Nayak u32 *address; 32557f277b0SRajendra Nayak 32657f277b0SRajendra Nayak scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD); 32757f277b0SRajendra Nayak 32857f277b0SRajendra Nayak /* Get address of entry that was modified */ 32957f277b0SRajendra Nayak address = (u32 *)__raw_readl(scratchpad_address + 33057f277b0SRajendra Nayak OMAP343X_TABLE_ADDRESS_OFFSET); 33157f277b0SRajendra Nayak /* Get the previous value which needs to be restored */ 33257f277b0SRajendra Nayak previous_value = __raw_readl(scratchpad_address + 33357f277b0SRajendra Nayak OMAP343X_TABLE_VALUE_OFFSET); 33457f277b0SRajendra Nayak address = __va(address); 33557f277b0SRajendra Nayak *address = previous_value; 33657f277b0SRajendra Nayak flush_tlb_all(); 33757f277b0SRajendra Nayak control_reg_value = __raw_readl(scratchpad_address 33857f277b0SRajendra Nayak + OMAP343X_CONTROL_REG_VALUE_OFFSET); 33957f277b0SRajendra Nayak /* This will enable caches and prediction */ 34057f277b0SRajendra Nayak restore_control_register(control_reg_value); 34157f277b0SRajendra Nayak } 34257f277b0SRajendra Nayak 34399e6a4d2SRajendra Nayak void omap_sram_idle(void) 3448bd22949SKevin Hilman { 3458bd22949SKevin Hilman /* Variable to tell what needs to be saved and restored 3468bd22949SKevin Hilman * in omap_sram_idle*/ 3478bd22949SKevin Hilman /* save_state = 0 => Nothing to save and restored */ 3488bd22949SKevin Hilman /* save_state = 1 => Only L1 and logic lost */ 3498bd22949SKevin Hilman /* save_state = 2 => Only L2 lost */ 3508bd22949SKevin Hilman /* save_state = 3 => L1, L2 and logic lost */ 351fa3c2a4fSRajendra Nayak int save_state = 0; 352fa3c2a4fSRajendra Nayak int mpu_next_state = PWRDM_POWER_ON; 353fa3c2a4fSRajendra Nayak int per_next_state = PWRDM_POWER_ON; 354fa3c2a4fSRajendra Nayak int core_next_state = PWRDM_POWER_ON; 35572e06d08SPaul Walmsley int per_going_off; 3562f5939c3SRajendra Nayak int core_prev_state, per_prev_state; 35713a6fe0fSTero Kristo u32 sdrc_pwr = 0; 3588bd22949SKevin Hilman 3598bd22949SKevin Hilman if (!_omap_sram_idle) 3608bd22949SKevin Hilman return; 3618bd22949SKevin Hilman 362fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(mpu_pwrdm); 363fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(neon_pwrdm); 364fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(core_pwrdm); 365fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(per_pwrdm); 366fa3c2a4fSRajendra Nayak 3678bd22949SKevin Hilman mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 3688bd22949SKevin Hilman switch (mpu_next_state) { 369fa3c2a4fSRajendra Nayak case PWRDM_POWER_ON: 3708bd22949SKevin Hilman case PWRDM_POWER_RET: 3718bd22949SKevin Hilman /* No need to save context */ 3728bd22949SKevin Hilman save_state = 0; 3738bd22949SKevin Hilman break; 37461255ab9SRajendra Nayak case PWRDM_POWER_OFF: 37561255ab9SRajendra Nayak save_state = 3; 37661255ab9SRajendra Nayak break; 3778bd22949SKevin Hilman default: 3788bd22949SKevin Hilman /* Invalid state */ 3798bd22949SKevin Hilman printk(KERN_ERR "Invalid mpu state in sram_idle\n"); 3808bd22949SKevin Hilman return; 3818bd22949SKevin Hilman } 382fe617af7SPeter 'p2' De Schrijver pwrdm_pre_transition(); 383fe617af7SPeter 'p2' De Schrijver 384fa3c2a4fSRajendra Nayak /* NEON control */ 385fa3c2a4fSRajendra Nayak if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) 3867139178eSJouni Hogander pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); 387fa3c2a4fSRajendra Nayak 38840742fa8SMike Chan /* Enable IO-PAD and IO-CHAIN wakeups */ 389fa3c2a4fSRajendra Nayak per_next_state = pwrdm_read_next_pwrst(per_pwrdm); 390ecf157d0STero Kristo core_next_state = pwrdm_read_next_pwrst(core_pwrdm); 391d5c47d7eSKevin Hilman if (omap3_has_io_wakeup() && 392ad0c63f1Sstanley.miao (per_next_state < PWRDM_POWER_ON || 393ad0c63f1Sstanley.miao core_next_state < PWRDM_POWER_ON)) { 394c4d7e58fSPaul Walmsley omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); 39540742fa8SMike Chan omap3_enable_io_chain(); 39640742fa8SMike Chan } 39740742fa8SMike Chan 3980d8e2d0dSPaul Walmsley /* Block console output in case it is on one of the OMAP UARTs */ 399e83df17fSKevin Hilman if (!is_suspending()) 4000d8e2d0dSPaul Walmsley if (per_next_state < PWRDM_POWER_ON || 4010d8e2d0dSPaul Walmsley core_next_state < PWRDM_POWER_ON) 4020d8e2d0dSPaul Walmsley if (try_acquire_console_sem()) 4030d8e2d0dSPaul Walmsley goto console_still_active; 4040d8e2d0dSPaul Walmsley 40540742fa8SMike Chan /* PER */ 4062f5939c3SRajendra Nayak if (per_next_state < PWRDM_POWER_ON) { 40772e06d08SPaul Walmsley per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0; 4084af4016cSKevin Hilman omap_uart_prepare_idle(2); 409cd4f1faeSGovindraj.R omap_uart_prepare_idle(3); 41072e06d08SPaul Walmsley omap2_gpio_prepare_for_idle(per_going_off); 411e7410cf7SKevin Hilman if (per_next_state == PWRDM_POWER_OFF) 4122f5939c3SRajendra Nayak omap3_per_save_context(); 4132f5939c3SRajendra Nayak } 414c16c3f67STero Kristo 415658ce97eSKevin Hilman /* CORE */ 416658ce97eSKevin Hilman if (core_next_state < PWRDM_POWER_ON) { 417658ce97eSKevin Hilman omap_uart_prepare_idle(0); 418658ce97eSKevin Hilman omap_uart_prepare_idle(1); 4192f5939c3SRajendra Nayak if (core_next_state == PWRDM_POWER_OFF) { 4202f5939c3SRajendra Nayak omap3_core_save_context(); 421f0611a5cSPaul Walmsley omap3_cm_save_context(); 4222f5939c3SRajendra Nayak } 423fa3c2a4fSRajendra Nayak } 42440742fa8SMike Chan 425f18cc2ffSTero Kristo omap3_intc_prepare_idle(); 4268bd22949SKevin Hilman 42761255ab9SRajendra Nayak /* 428f265dc4cSRajendra Nayak * On EMU/HS devices ROM code restores a SRDC value 429f265dc4cSRajendra Nayak * from scratchpad which has automatic self refresh on timeout 43083521291SJean Pihet * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443. 431f265dc4cSRajendra Nayak * Hence store/restore the SDRC_POWER register here. 43213a6fe0fSTero Kristo */ 43313a6fe0fSTero Kristo if (omap_rev() >= OMAP3430_REV_ES3_0 && 43413a6fe0fSTero Kristo omap_type() != OMAP2_DEVICE_TYPE_GP && 435f265dc4cSRajendra Nayak core_next_state == PWRDM_POWER_OFF) 43613a6fe0fSTero Kristo sdrc_pwr = sdrc_read_reg(SDRC_POWER); 43713a6fe0fSTero Kristo 43813a6fe0fSTero Kristo /* 43961255ab9SRajendra Nayak * omap3_arm_context is the location where ARM registers 44061255ab9SRajendra Nayak * get saved. The restore path then reads from this 44161255ab9SRajendra Nayak * location and restores them back. 44261255ab9SRajendra Nayak */ 44361255ab9SRajendra Nayak _omap_sram_idle(omap3_arm_context, save_state); 4448bd22949SKevin Hilman cpu_init(); 4458bd22949SKevin Hilman 446f265dc4cSRajendra Nayak /* Restore normal SDRC POWER settings */ 44713a6fe0fSTero Kristo if (omap_rev() >= OMAP3430_REV_ES3_0 && 44813a6fe0fSTero Kristo omap_type() != OMAP2_DEVICE_TYPE_GP && 44913a6fe0fSTero Kristo core_next_state == PWRDM_POWER_OFF) 45013a6fe0fSTero Kristo sdrc_write_reg(sdrc_pwr, SDRC_POWER); 45113a6fe0fSTero Kristo 45257f277b0SRajendra Nayak /* Restore table entry modified during MMU restoration */ 45357f277b0SRajendra Nayak if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF) 45457f277b0SRajendra Nayak restore_table_entry(); 45557f277b0SRajendra Nayak 456658ce97eSKevin Hilman /* CORE */ 457fa3c2a4fSRajendra Nayak if (core_next_state < PWRDM_POWER_ON) { 4582f5939c3SRajendra Nayak core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); 4592f5939c3SRajendra Nayak if (core_prev_state == PWRDM_POWER_OFF) { 4602f5939c3SRajendra Nayak omap3_core_restore_context(); 461f0611a5cSPaul Walmsley omap3_cm_restore_context(); 4622f5939c3SRajendra Nayak omap3_sram_restore_context(); 4638a917d2fSKalle Jokiniemi omap2_sms_restore_context(); 4642f5939c3SRajendra Nayak } 465658ce97eSKevin Hilman omap_uart_resume_idle(0); 466658ce97eSKevin Hilman omap_uart_resume_idle(1); 467658ce97eSKevin Hilman if (core_next_state == PWRDM_POWER_OFF) 468c4d7e58fSPaul Walmsley omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, 469658ce97eSKevin Hilman OMAP3430_GR_MOD, 470658ce97eSKevin Hilman OMAP3_PRM_VOLTCTRL_OFFSET); 471658ce97eSKevin Hilman } 472f18cc2ffSTero Kristo omap3_intc_resume_idle(); 473658ce97eSKevin Hilman 474658ce97eSKevin Hilman /* PER */ 4752f5939c3SRajendra Nayak if (per_next_state < PWRDM_POWER_ON) { 476658ce97eSKevin Hilman per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); 47743ffcd9aSKevin Hilman omap2_gpio_resume_after_idle(); 47843ffcd9aSKevin Hilman if (per_prev_state == PWRDM_POWER_OFF) 4792f5939c3SRajendra Nayak omap3_per_restore_context(); 480ecf157d0STero Kristo omap_uart_resume_idle(2); 481cd4f1faeSGovindraj.R omap_uart_resume_idle(3); 482fa3c2a4fSRajendra Nayak } 483fe617af7SPeter 'p2' De Schrijver 484e83df17fSKevin Hilman if (!is_suspending()) 4850d8e2d0dSPaul Walmsley release_console_sem(); 4860d8e2d0dSPaul Walmsley 4870d8e2d0dSPaul Walmsley console_still_active: 4883a7ec26bSKalle Jokiniemi /* Disable IO-PAD and IO-CHAIN wakeup */ 48958a5559eSKevin Hilman if (omap3_has_io_wakeup() && 49058a5559eSKevin Hilman (per_next_state < PWRDM_POWER_ON || 49158a5559eSKevin Hilman core_next_state < PWRDM_POWER_ON)) { 492c4d7e58fSPaul Walmsley omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, 493c4d7e58fSPaul Walmsley PM_WKEN); 4943a7ec26bSKalle Jokiniemi omap3_disable_io_chain(); 4953a7ec26bSKalle Jokiniemi } 496658ce97eSKevin Hilman 497fe617af7SPeter 'p2' De Schrijver pwrdm_post_transition(); 498fe617af7SPeter 'p2' De Schrijver 499c16c3f67STero Kristo omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); 5008bd22949SKevin Hilman } 5018bd22949SKevin Hilman 50220b01669SRajendra Nayak int omap3_can_sleep(void) 5038bd22949SKevin Hilman { 504c40552bcSKevin Hilman if (!sleep_while_idle) 505c40552bcSKevin Hilman return 0; 5064af4016cSKevin Hilman if (!omap_uart_can_sleep()) 5074af4016cSKevin Hilman return 0; 5088bd22949SKevin Hilman return 1; 5098bd22949SKevin Hilman } 5108bd22949SKevin Hilman 5118bd22949SKevin Hilman static void omap3_pm_idle(void) 5128bd22949SKevin Hilman { 5138bd22949SKevin Hilman local_irq_disable(); 5148bd22949SKevin Hilman local_fiq_disable(); 5158bd22949SKevin Hilman 5168bd22949SKevin Hilman if (!omap3_can_sleep()) 5178bd22949SKevin Hilman goto out; 5188bd22949SKevin Hilman 519cf22854cSTero Kristo if (omap_irq_pending() || need_resched()) 5208bd22949SKevin Hilman goto out; 5218bd22949SKevin Hilman 5228bd22949SKevin Hilman omap_sram_idle(); 5238bd22949SKevin Hilman 5248bd22949SKevin Hilman out: 5258bd22949SKevin Hilman local_fiq_enable(); 5268bd22949SKevin Hilman local_irq_enable(); 5278bd22949SKevin Hilman } 5288bd22949SKevin Hilman 52910f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 5308bd22949SKevin Hilman static int omap3_pm_suspend(void) 5318bd22949SKevin Hilman { 5328bd22949SKevin Hilman struct power_state *pwrst; 5338bd22949SKevin Hilman int state, ret = 0; 5348bd22949SKevin Hilman 5358e2efde9SAri Kauppi if (wakeup_timer_seconds || wakeup_timer_milliseconds) 5368e2efde9SAri Kauppi omap2_pm_wakeup_on_timer(wakeup_timer_seconds, 5378e2efde9SAri Kauppi wakeup_timer_milliseconds); 538d7814e4dSKevin Hilman 5398bd22949SKevin Hilman /* Read current next_pwrsts */ 5408bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) 5418bd22949SKevin Hilman pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 5428bd22949SKevin Hilman /* Set ones wanted by suspend */ 5438bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 544eb6a2c75SSantosh Shilimkar if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) 5458bd22949SKevin Hilman goto restore; 5468bd22949SKevin Hilman if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) 5478bd22949SKevin Hilman goto restore; 5488bd22949SKevin Hilman } 5498bd22949SKevin Hilman 5504af4016cSKevin Hilman omap_uart_prepare_suspend(); 5512bbe3af3STero Kristo omap3_intc_suspend(); 5522bbe3af3STero Kristo 5538bd22949SKevin Hilman omap_sram_idle(); 5548bd22949SKevin Hilman 5558bd22949SKevin Hilman restore: 5568bd22949SKevin Hilman /* Restore next_pwrsts */ 5578bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 5588bd22949SKevin Hilman state = pwrdm_read_prev_pwrst(pwrst->pwrdm); 5598bd22949SKevin Hilman if (state > pwrst->next_state) { 5608bd22949SKevin Hilman printk(KERN_INFO "Powerdomain (%s) didn't enter " 5618bd22949SKevin Hilman "target state %d\n", 5628bd22949SKevin Hilman pwrst->pwrdm->name, pwrst->next_state); 5638bd22949SKevin Hilman ret = -1; 5648bd22949SKevin Hilman } 565eb6a2c75SSantosh Shilimkar omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); 5668bd22949SKevin Hilman } 5678bd22949SKevin Hilman if (ret) 5688bd22949SKevin Hilman printk(KERN_ERR "Could not enter target state in pm_suspend\n"); 5698bd22949SKevin Hilman else 5708bd22949SKevin Hilman printk(KERN_INFO "Successfully put all powerdomains " 5718bd22949SKevin Hilman "to target state\n"); 5728bd22949SKevin Hilman 5738bd22949SKevin Hilman return ret; 5748bd22949SKevin Hilman } 5758bd22949SKevin Hilman 5762466211eSTero Kristo static int omap3_pm_enter(suspend_state_t unused) 5778bd22949SKevin Hilman { 5788bd22949SKevin Hilman int ret = 0; 5798bd22949SKevin Hilman 5802466211eSTero Kristo switch (suspend_state) { 5818bd22949SKevin Hilman case PM_SUSPEND_STANDBY: 5828bd22949SKevin Hilman case PM_SUSPEND_MEM: 5838bd22949SKevin Hilman ret = omap3_pm_suspend(); 5848bd22949SKevin Hilman break; 5858bd22949SKevin Hilman default: 5868bd22949SKevin Hilman ret = -EINVAL; 5878bd22949SKevin Hilman } 5888bd22949SKevin Hilman 5898bd22949SKevin Hilman return ret; 5908bd22949SKevin Hilman } 5918bd22949SKevin Hilman 5922466211eSTero Kristo /* Hooks to enable / disable UART interrupts during suspend */ 5932466211eSTero Kristo static int omap3_pm_begin(suspend_state_t state) 5942466211eSTero Kristo { 595c166381dSJean Pihet disable_hlt(); 5962466211eSTero Kristo suspend_state = state; 5972466211eSTero Kristo omap_uart_enable_irqs(0); 5982466211eSTero Kristo return 0; 5992466211eSTero Kristo } 6002466211eSTero Kristo 6012466211eSTero Kristo static void omap3_pm_end(void) 6022466211eSTero Kristo { 6032466211eSTero Kristo suspend_state = PM_SUSPEND_ON; 6042466211eSTero Kristo omap_uart_enable_irqs(1); 605c166381dSJean Pihet enable_hlt(); 6062466211eSTero Kristo return; 6072466211eSTero Kristo } 6082466211eSTero Kristo 6092f55ac07SLionel Debroux static const struct platform_suspend_ops omap_pm_ops = { 6102466211eSTero Kristo .begin = omap3_pm_begin, 6112466211eSTero Kristo .end = omap3_pm_end, 6128bd22949SKevin Hilman .enter = omap3_pm_enter, 6138bd22949SKevin Hilman .valid = suspend_valid_only_mem, 6148bd22949SKevin Hilman }; 61510f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 6168bd22949SKevin Hilman 6171155e426SKevin Hilman 6181155e426SKevin Hilman /** 6191155e426SKevin Hilman * omap3_iva_idle(): ensure IVA is in idle so it can be put into 6201155e426SKevin Hilman * retention 6211155e426SKevin Hilman * 6221155e426SKevin Hilman * In cases where IVA2 is activated by bootcode, it may prevent 6231155e426SKevin Hilman * full-chip retention or off-mode because it is not idle. This 6241155e426SKevin Hilman * function forces the IVA2 into idle state so it can go 6251155e426SKevin Hilman * into retention/off and thus allow full-chip retention/off. 6261155e426SKevin Hilman * 6271155e426SKevin Hilman **/ 6281155e426SKevin Hilman static void __init omap3_iva_idle(void) 6291155e426SKevin Hilman { 6301155e426SKevin Hilman /* ensure IVA2 clock is disabled */ 631c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 6321155e426SKevin Hilman 6331155e426SKevin Hilman /* if no clock activity, nothing else to do */ 634c4d7e58fSPaul Walmsley if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & 6351155e426SKevin Hilman OMAP3430_CLKACTIVITY_IVA2_MASK)) 6361155e426SKevin Hilman return; 6371155e426SKevin Hilman 6381155e426SKevin Hilman /* Reset IVA2 */ 639c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | 6402bc4ef71SPaul Walmsley OMAP3430_RST2_IVA2_MASK | 6412bc4ef71SPaul Walmsley OMAP3430_RST3_IVA2_MASK, 64237903009SAbhijit Pagare OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 6431155e426SKevin Hilman 6441155e426SKevin Hilman /* Enable IVA2 clock */ 645c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, 6461155e426SKevin Hilman OMAP3430_IVA2_MOD, CM_FCLKEN); 6471155e426SKevin Hilman 6481155e426SKevin Hilman /* Set IVA2 boot mode to 'idle' */ 6491155e426SKevin Hilman omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, 6501155e426SKevin Hilman OMAP343X_CONTROL_IVA2_BOOTMOD); 6511155e426SKevin Hilman 6521155e426SKevin Hilman /* Un-reset IVA2 */ 653c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 6541155e426SKevin Hilman 6551155e426SKevin Hilman /* Disable IVA2 clock */ 656c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 6571155e426SKevin Hilman 6581155e426SKevin Hilman /* Reset IVA2 */ 659c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | 6602bc4ef71SPaul Walmsley OMAP3430_RST2_IVA2_MASK | 6612bc4ef71SPaul Walmsley OMAP3430_RST3_IVA2_MASK, 66237903009SAbhijit Pagare OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 6631155e426SKevin Hilman } 6641155e426SKevin Hilman 6658111b221SKevin Hilman static void __init omap3_d2d_idle(void) 6668bd22949SKevin Hilman { 6678111b221SKevin Hilman u16 mask, padconf; 6688111b221SKevin Hilman 6698111b221SKevin Hilman /* In a stand alone OMAP3430 where there is not a stacked 6708111b221SKevin Hilman * modem for the D2D Idle Ack and D2D MStandby must be pulled 6718111b221SKevin Hilman * high. S CONTROL_PADCONF_SAD2D_IDLEACK and 6728111b221SKevin Hilman * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ 6738111b221SKevin Hilman mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ 6748111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); 6758111b221SKevin Hilman padconf |= mask; 6768111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); 6778111b221SKevin Hilman 6788111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); 6798111b221SKevin Hilman padconf |= mask; 6808111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 6818111b221SKevin Hilman 6828bd22949SKevin Hilman /* reset modem */ 683c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | 6842bc4ef71SPaul Walmsley OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, 68537903009SAbhijit Pagare CORE_MOD, OMAP2_RM_RSTCTRL); 686c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); 6878111b221SKevin Hilman } 6888bd22949SKevin Hilman 6898111b221SKevin Hilman static void __init prcm_setup_regs(void) 6908111b221SKevin Hilman { 691e5863689SGovindraj.R u32 omap3630_auto_uart4_mask = cpu_is_omap3630() ? 692e5863689SGovindraj.R OMAP3630_AUTO_UART4_MASK : 0; 693e5863689SGovindraj.R u32 omap3630_en_uart4_mask = cpu_is_omap3630() ? 694e5863689SGovindraj.R OMAP3630_EN_UART4_MASK : 0; 695e5863689SGovindraj.R u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ? 696e5863689SGovindraj.R OMAP3630_GRPSEL_UART4_MASK : 0; 697e5863689SGovindraj.R 698e5863689SGovindraj.R 6998bd22949SKevin Hilman /* XXX Reset all wkdeps. This should be done when initializing 7008bd22949SKevin Hilman * powerdomains */ 701c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); 702c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, MPU_MOD, PM_WKDEP); 703c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP); 704c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP); 705c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP); 706c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP); 7078bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 708c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP); 709c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP); 7108bd22949SKevin Hilman } else 711c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); 7128bd22949SKevin Hilman 7138bd22949SKevin Hilman /* 7148bd22949SKevin Hilman * Enable interface clock autoidle for all modules. 7158bd22949SKevin Hilman * Note that in the long run this should be done by clockfw 7168bd22949SKevin Hilman */ 717c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg( 7182bc4ef71SPaul Walmsley OMAP3430_AUTO_MODEM_MASK | 7192bc4ef71SPaul Walmsley OMAP3430ES2_AUTO_MMC3_MASK | 7202bc4ef71SPaul Walmsley OMAP3430ES2_AUTO_ICR_MASK | 7212bc4ef71SPaul Walmsley OMAP3430_AUTO_AES2_MASK | 7222bc4ef71SPaul Walmsley OMAP3430_AUTO_SHA12_MASK | 7232bc4ef71SPaul Walmsley OMAP3430_AUTO_DES2_MASK | 7242bc4ef71SPaul Walmsley OMAP3430_AUTO_MMC2_MASK | 7252bc4ef71SPaul Walmsley OMAP3430_AUTO_MMC1_MASK | 7262bc4ef71SPaul Walmsley OMAP3430_AUTO_MSPRO_MASK | 7272bc4ef71SPaul Walmsley OMAP3430_AUTO_HDQ_MASK | 7282bc4ef71SPaul Walmsley OMAP3430_AUTO_MCSPI4_MASK | 7292bc4ef71SPaul Walmsley OMAP3430_AUTO_MCSPI3_MASK | 7302bc4ef71SPaul Walmsley OMAP3430_AUTO_MCSPI2_MASK | 7312bc4ef71SPaul Walmsley OMAP3430_AUTO_MCSPI1_MASK | 7322bc4ef71SPaul Walmsley OMAP3430_AUTO_I2C3_MASK | 7332bc4ef71SPaul Walmsley OMAP3430_AUTO_I2C2_MASK | 7342bc4ef71SPaul Walmsley OMAP3430_AUTO_I2C1_MASK | 7352bc4ef71SPaul Walmsley OMAP3430_AUTO_UART2_MASK | 7362bc4ef71SPaul Walmsley OMAP3430_AUTO_UART1_MASK | 7372bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT11_MASK | 7382bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT10_MASK | 7392bc4ef71SPaul Walmsley OMAP3430_AUTO_MCBSP5_MASK | 7402bc4ef71SPaul Walmsley OMAP3430_AUTO_MCBSP1_MASK | 7412bc4ef71SPaul Walmsley OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */ 7422bc4ef71SPaul Walmsley OMAP3430_AUTO_MAILBOXES_MASK | 7432bc4ef71SPaul Walmsley OMAP3430_AUTO_OMAPCTRL_MASK | 7442bc4ef71SPaul Walmsley OMAP3430ES1_AUTO_FSHOSTUSB_MASK | 7452bc4ef71SPaul Walmsley OMAP3430_AUTO_HSOTGUSB_MASK | 7462bc4ef71SPaul Walmsley OMAP3430_AUTO_SAD2D_MASK | 7472bc4ef71SPaul Walmsley OMAP3430_AUTO_SSI_MASK, 7488bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE1); 7498bd22949SKevin Hilman 750c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg( 7512bc4ef71SPaul Walmsley OMAP3430_AUTO_PKA_MASK | 7522bc4ef71SPaul Walmsley OMAP3430_AUTO_AES1_MASK | 7532bc4ef71SPaul Walmsley OMAP3430_AUTO_RNG_MASK | 7542bc4ef71SPaul Walmsley OMAP3430_AUTO_SHA11_MASK | 7552bc4ef71SPaul Walmsley OMAP3430_AUTO_DES1_MASK, 7568bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE2); 7578bd22949SKevin Hilman 7588bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 759c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg( 7602bc4ef71SPaul Walmsley OMAP3430_AUTO_MAD2D_MASK | 7612bc4ef71SPaul Walmsley OMAP3430ES2_AUTO_USBTLL_MASK, 7628bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE3); 7638bd22949SKevin Hilman } 7648bd22949SKevin Hilman 765c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg( 7662bc4ef71SPaul Walmsley OMAP3430_AUTO_WDT2_MASK | 7672bc4ef71SPaul Walmsley OMAP3430_AUTO_WDT1_MASK | 7682bc4ef71SPaul Walmsley OMAP3430_AUTO_GPIO1_MASK | 7692bc4ef71SPaul Walmsley OMAP3430_AUTO_32KSYNC_MASK | 7702bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT12_MASK | 7712bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT1_MASK, 7728bd22949SKevin Hilman WKUP_MOD, CM_AUTOIDLE); 7738bd22949SKevin Hilman 774c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg( 7752bc4ef71SPaul Walmsley OMAP3430_AUTO_DSS_MASK, 7768bd22949SKevin Hilman OMAP3430_DSS_MOD, 7778bd22949SKevin Hilman CM_AUTOIDLE); 7788bd22949SKevin Hilman 779c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg( 7802bc4ef71SPaul Walmsley OMAP3430_AUTO_CAM_MASK, 7818bd22949SKevin Hilman OMAP3430_CAM_MOD, 7828bd22949SKevin Hilman CM_AUTOIDLE); 7838bd22949SKevin Hilman 784c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg( 785e5863689SGovindraj.R omap3630_auto_uart4_mask | 7862bc4ef71SPaul Walmsley OMAP3430_AUTO_GPIO6_MASK | 7872bc4ef71SPaul Walmsley OMAP3430_AUTO_GPIO5_MASK | 7882bc4ef71SPaul Walmsley OMAP3430_AUTO_GPIO4_MASK | 7892bc4ef71SPaul Walmsley OMAP3430_AUTO_GPIO3_MASK | 7902bc4ef71SPaul Walmsley OMAP3430_AUTO_GPIO2_MASK | 7912bc4ef71SPaul Walmsley OMAP3430_AUTO_WDT3_MASK | 7922bc4ef71SPaul Walmsley OMAP3430_AUTO_UART3_MASK | 7932bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT9_MASK | 7942bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT8_MASK | 7952bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT7_MASK | 7962bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT6_MASK | 7972bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT5_MASK | 7982bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT4_MASK | 7992bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT3_MASK | 8002bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT2_MASK | 8012bc4ef71SPaul Walmsley OMAP3430_AUTO_MCBSP4_MASK | 8022bc4ef71SPaul Walmsley OMAP3430_AUTO_MCBSP3_MASK | 8032bc4ef71SPaul Walmsley OMAP3430_AUTO_MCBSP2_MASK, 8048bd22949SKevin Hilman OMAP3430_PER_MOD, 8058bd22949SKevin Hilman CM_AUTOIDLE); 8068bd22949SKevin Hilman 8078bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 808c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg( 8092bc4ef71SPaul Walmsley OMAP3430ES2_AUTO_USBHOST_MASK, 8108bd22949SKevin Hilman OMAP3430ES2_USBHOST_MOD, 8118bd22949SKevin Hilman CM_AUTOIDLE); 8128bd22949SKevin Hilman } 8138bd22949SKevin Hilman 8142fd0f75cSPaul Walmsley omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); 815b296c811STero Kristo 8168bd22949SKevin Hilman /* 8178bd22949SKevin Hilman * Set all plls to autoidle. This is needed until autoidle is 8188bd22949SKevin Hilman * enabled by clockfw 8198bd22949SKevin Hilman */ 820c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, 8218bd22949SKevin Hilman OMAP3430_IVA2_MOD, CM_AUTOIDLE2); 822c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT, 8238bd22949SKevin Hilman MPU_MOD, 8248bd22949SKevin Hilman CM_AUTOIDLE2); 825c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | 8268bd22949SKevin Hilman (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT), 8278bd22949SKevin Hilman PLL_MOD, 8288bd22949SKevin Hilman CM_AUTOIDLE); 829c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, 8308bd22949SKevin Hilman PLL_MOD, 8318bd22949SKevin Hilman CM_AUTOIDLE2); 8328bd22949SKevin Hilman 8338bd22949SKevin Hilman /* 8348bd22949SKevin Hilman * Enable control of expternal oscillator through 8358bd22949SKevin Hilman * sys_clkreq. In the long run clock framework should 8368bd22949SKevin Hilman * take care of this. 8378bd22949SKevin Hilman */ 838c4d7e58fSPaul Walmsley omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 8398bd22949SKevin Hilman 1 << OMAP_AUTOEXTCLKMODE_SHIFT, 8408bd22949SKevin Hilman OMAP3430_GR_MOD, 8418bd22949SKevin Hilman OMAP3_PRM_CLKSRC_CTRL_OFFSET); 8428bd22949SKevin Hilman 8438bd22949SKevin Hilman /* setup wakup source */ 844c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | 8452fd0f75cSPaul Walmsley OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, 8468bd22949SKevin Hilman WKUP_MOD, PM_WKEN); 8478bd22949SKevin Hilman /* No need to write EN_IO, that is always enabled */ 848c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | 849275f675cSPaul Walmsley OMAP3430_GRPSEL_GPT1_MASK | 850275f675cSPaul Walmsley OMAP3430_GRPSEL_GPT12_MASK, 8518bd22949SKevin Hilman WKUP_MOD, OMAP3430_PM_MPUGRPSEL); 8528bd22949SKevin Hilman /* For some reason IO doesn't generate wakeup event even if 8538bd22949SKevin Hilman * it is selected to mpu wakeup goup */ 854c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK, 8558bd22949SKevin Hilman OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); 8561155e426SKevin Hilman 857b92c5721SSubramani Venkatesh /* Enable PM_WKEN to support DSS LPR */ 858c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, 859b92c5721SSubramani Venkatesh OMAP3430_DSS_MOD, PM_WKEN); 860b92c5721SSubramani Venkatesh 861b427f92fSKevin Hilman /* Enable wakeups in PER */ 862c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(omap3630_en_uart4_mask | 863e5863689SGovindraj.R OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | 8642fd0f75cSPaul Walmsley OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | 8652fd0f75cSPaul Walmsley OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | 8662fd0f75cSPaul Walmsley OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK | 8672fd0f75cSPaul Walmsley OMAP3430_EN_MCBSP4_MASK, 868b427f92fSKevin Hilman OMAP3430_PER_MOD, PM_WKEN); 869eb350f74SKevin Hilman /* and allow them to wake up MPU */ 870c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask | 871e5863689SGovindraj.R OMAP3430_GRPSEL_GPIO2_MASK | 872275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO3_MASK | 873275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO4_MASK | 874275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO5_MASK | 875275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO6_MASK | 876275f675cSPaul Walmsley OMAP3430_GRPSEL_UART3_MASK | 877275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP2_MASK | 878275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP3_MASK | 879275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP4_MASK, 880eb350f74SKevin Hilman OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); 881eb350f74SKevin Hilman 882d3fd3290SKevin Hilman /* Don't attach IVA interrupts */ 883c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 884c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 885c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 886c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); 887d3fd3290SKevin Hilman 888b1340d17SKevin Hilman /* Clear any pending 'reset' flags */ 889c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); 890c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); 891c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); 892c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); 893c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); 894c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); 895c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); 896b1340d17SKevin Hilman 897014c46dbSKevin Hilman /* Clear any pending PRCM interrupts */ 898c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 899014c46dbSKevin Hilman 9001155e426SKevin Hilman omap3_iva_idle(); 9018111b221SKevin Hilman omap3_d2d_idle(); 9028bd22949SKevin Hilman } 9038bd22949SKevin Hilman 904c40552bcSKevin Hilman void omap3_pm_off_mode_enable(int enable) 905c40552bcSKevin Hilman { 906c40552bcSKevin Hilman struct power_state *pwrst; 907c40552bcSKevin Hilman u32 state; 908c40552bcSKevin Hilman 909c40552bcSKevin Hilman if (enable) 910c40552bcSKevin Hilman state = PWRDM_POWER_OFF; 911c40552bcSKevin Hilman else 912c40552bcSKevin Hilman state = PWRDM_POWER_RET; 913c40552bcSKevin Hilman 9146af83b38SSanjeev Premi #ifdef CONFIG_CPU_IDLE 915cc1b6028SEduardo Valentin /* 916cc1b6028SEduardo Valentin * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot 917cc1b6028SEduardo Valentin * enable OFF mode in a stable form for previous revisions, restrict 918cc1b6028SEduardo Valentin * instead to RET 919cc1b6028SEduardo Valentin */ 920cc1b6028SEduardo Valentin if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) 921cc1b6028SEduardo Valentin omap3_cpuidle_update_states(state, PWRDM_POWER_RET); 922cc1b6028SEduardo Valentin else 92380723c3fSNishanth Menon omap3_cpuidle_update_states(state, state); 9246af83b38SSanjeev Premi #endif 9256af83b38SSanjeev Premi 926c40552bcSKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 927cc1b6028SEduardo Valentin if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) && 928cc1b6028SEduardo Valentin pwrst->pwrdm == core_pwrdm && 929cc1b6028SEduardo Valentin state == PWRDM_POWER_OFF) { 930cc1b6028SEduardo Valentin pwrst->next_state = PWRDM_POWER_RET; 931cc1b6028SEduardo Valentin WARN_ONCE(1, 932cc1b6028SEduardo Valentin "%s: Core OFF disabled due to errata i583\n", 933cc1b6028SEduardo Valentin __func__); 934cc1b6028SEduardo Valentin } else { 935c40552bcSKevin Hilman pwrst->next_state = state; 936cc1b6028SEduardo Valentin } 937cc1b6028SEduardo Valentin omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 938c40552bcSKevin Hilman } 939c40552bcSKevin Hilman } 940c40552bcSKevin Hilman 94168d4778cSTero Kristo int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) 94268d4778cSTero Kristo { 94368d4778cSTero Kristo struct power_state *pwrst; 94468d4778cSTero Kristo 94568d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 94668d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) 94768d4778cSTero Kristo return pwrst->next_state; 94868d4778cSTero Kristo } 94968d4778cSTero Kristo return -EINVAL; 95068d4778cSTero Kristo } 95168d4778cSTero Kristo 95268d4778cSTero Kristo int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) 95368d4778cSTero Kristo { 95468d4778cSTero Kristo struct power_state *pwrst; 95568d4778cSTero Kristo 95668d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 95768d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) { 95868d4778cSTero Kristo pwrst->next_state = state; 95968d4778cSTero Kristo return 0; 96068d4778cSTero Kristo } 96168d4778cSTero Kristo } 96268d4778cSTero Kristo return -EINVAL; 96368d4778cSTero Kristo } 96468d4778cSTero Kristo 965a23456e9SPeter 'p2' De Schrijver static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) 9668bd22949SKevin Hilman { 9678bd22949SKevin Hilman struct power_state *pwrst; 9688bd22949SKevin Hilman 9698bd22949SKevin Hilman if (!pwrdm->pwrsts) 9708bd22949SKevin Hilman return 0; 9718bd22949SKevin Hilman 972d3d381c6SMing Lei pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); 9738bd22949SKevin Hilman if (!pwrst) 9748bd22949SKevin Hilman return -ENOMEM; 9758bd22949SKevin Hilman pwrst->pwrdm = pwrdm; 9768bd22949SKevin Hilman pwrst->next_state = PWRDM_POWER_RET; 9778bd22949SKevin Hilman list_add(&pwrst->node, &pwrst_list); 9788bd22949SKevin Hilman 9798bd22949SKevin Hilman if (pwrdm_has_hdwr_sar(pwrdm)) 9808bd22949SKevin Hilman pwrdm_enable_hdwr_sar(pwrdm); 9818bd22949SKevin Hilman 982eb6a2c75SSantosh Shilimkar return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 9838bd22949SKevin Hilman } 9848bd22949SKevin Hilman 9858bd22949SKevin Hilman /* 9868bd22949SKevin Hilman * Enable hw supervised mode for all clockdomains if it's 9878bd22949SKevin Hilman * supported. Initiate sleep transition for other clockdomains, if 9888bd22949SKevin Hilman * they are not used 9898bd22949SKevin Hilman */ 990a23456e9SPeter 'p2' De Schrijver static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) 9918bd22949SKevin Hilman { 9928bd22949SKevin Hilman if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) 9938bd22949SKevin Hilman omap2_clkdm_allow_idle(clkdm); 9948bd22949SKevin Hilman else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && 9958bd22949SKevin Hilman atomic_read(&clkdm->usecount) == 0) 9968bd22949SKevin Hilman omap2_clkdm_sleep(clkdm); 9978bd22949SKevin Hilman return 0; 9988bd22949SKevin Hilman } 9998bd22949SKevin Hilman 10003231fc88SRajendra Nayak void omap_push_sram_idle(void) 10013231fc88SRajendra Nayak { 10023231fc88SRajendra Nayak _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend, 10033231fc88SRajendra Nayak omap34xx_cpu_suspend_sz); 100427d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) 100527d59a4aSTero Kristo _omap_save_secure_sram = omap_sram_push(save_secure_ram_context, 100627d59a4aSTero Kristo save_secure_ram_context_sz); 10073231fc88SRajendra Nayak } 10083231fc88SRajendra Nayak 10098cdfd834SNishanth Menon static void __init pm_errata_configure(void) 10108cdfd834SNishanth Menon { 1011c4236d2eSPeter 'p2' De Schrijver if (cpu_is_omap3630()) { 1012458e999eSNishanth Menon pm34xx_errata |= PM_RTA_ERRATUM_i608; 1013c4236d2eSPeter 'p2' De Schrijver /* Enable the l2 cache toggling in sleep logic */ 1014c4236d2eSPeter 'p2' De Schrijver enable_omap3630_toggle_l2_on_restore(); 1015cc1b6028SEduardo Valentin if (omap_rev() < OMAP3630_REV_ES1_2) 1016cc1b6028SEduardo Valentin pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583; 1017c4236d2eSPeter 'p2' De Schrijver } 10188cdfd834SNishanth Menon } 10198cdfd834SNishanth Menon 10207cc515f7SKevin Hilman static int __init omap3_pm_init(void) 10218bd22949SKevin Hilman { 10228bd22949SKevin Hilman struct power_state *pwrst, *tmp; 102355ed9694SPaul Walmsley struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm; 10248bd22949SKevin Hilman int ret; 10258bd22949SKevin Hilman 10268bd22949SKevin Hilman if (!cpu_is_omap34xx()) 10278bd22949SKevin Hilman return -ENODEV; 10288bd22949SKevin Hilman 10298cdfd834SNishanth Menon pm_errata_configure(); 10308cdfd834SNishanth Menon 10318bd22949SKevin Hilman printk(KERN_ERR "Power Management for TI OMAP3.\n"); 10328bd22949SKevin Hilman 10338bd22949SKevin Hilman /* XXX prcm_setup_regs needs to be before enabling hw 10348bd22949SKevin Hilman * supervised mode for powerdomains */ 10358bd22949SKevin Hilman prcm_setup_regs(); 10368bd22949SKevin Hilman 10378bd22949SKevin Hilman ret = request_irq(INT_34XX_PRCM_MPU_IRQ, 10388bd22949SKevin Hilman (irq_handler_t)prcm_interrupt_handler, 10398bd22949SKevin Hilman IRQF_DISABLED, "prcm", NULL); 10408bd22949SKevin Hilman if (ret) { 10418bd22949SKevin Hilman printk(KERN_ERR "request_irq failed to register for 0x%x\n", 10428bd22949SKevin Hilman INT_34XX_PRCM_MPU_IRQ); 10438bd22949SKevin Hilman goto err1; 10448bd22949SKevin Hilman } 10458bd22949SKevin Hilman 1046a23456e9SPeter 'p2' De Schrijver ret = pwrdm_for_each(pwrdms_setup, NULL); 10478bd22949SKevin Hilman if (ret) { 10488bd22949SKevin Hilman printk(KERN_ERR "Failed to setup powerdomains\n"); 10498bd22949SKevin Hilman goto err2; 10508bd22949SKevin Hilman } 10518bd22949SKevin Hilman 1052a23456e9SPeter 'p2' De Schrijver (void) clkdm_for_each(clkdms_setup, NULL); 10538bd22949SKevin Hilman 10548bd22949SKevin Hilman mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); 10558bd22949SKevin Hilman if (mpu_pwrdm == NULL) { 10568bd22949SKevin Hilman printk(KERN_ERR "Failed to get mpu_pwrdm\n"); 10578bd22949SKevin Hilman goto err2; 10588bd22949SKevin Hilman } 10598bd22949SKevin Hilman 1060fa3c2a4fSRajendra Nayak neon_pwrdm = pwrdm_lookup("neon_pwrdm"); 1061fa3c2a4fSRajendra Nayak per_pwrdm = pwrdm_lookup("per_pwrdm"); 1062fa3c2a4fSRajendra Nayak core_pwrdm = pwrdm_lookup("core_pwrdm"); 1063c16c3f67STero Kristo cam_pwrdm = pwrdm_lookup("cam_pwrdm"); 1064fa3c2a4fSRajendra Nayak 106555ed9694SPaul Walmsley neon_clkdm = clkdm_lookup("neon_clkdm"); 106655ed9694SPaul Walmsley mpu_clkdm = clkdm_lookup("mpu_clkdm"); 106755ed9694SPaul Walmsley per_clkdm = clkdm_lookup("per_clkdm"); 106855ed9694SPaul Walmsley core_clkdm = clkdm_lookup("core_clkdm"); 106955ed9694SPaul Walmsley 10703231fc88SRajendra Nayak omap_push_sram_idle(); 107110f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 10728bd22949SKevin Hilman suspend_set_ops(&omap_pm_ops); 107310f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 10748bd22949SKevin Hilman 10758bd22949SKevin Hilman pm_idle = omap3_pm_idle; 10760343371eSKalle Jokiniemi omap3_idle_init(); 10778bd22949SKevin Hilman 1078458e999eSNishanth Menon /* 1079458e999eSNishanth Menon * RTA is disabled during initialization as per erratum i608 1080458e999eSNishanth Menon * it is safer to disable RTA by the bootloader, but we would like 1081458e999eSNishanth Menon * to be doubly sure here and prevent any mishaps. 1082458e999eSNishanth Menon */ 1083458e999eSNishanth Menon if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608)) 1084458e999eSNishanth Menon omap3630_ctrl_disable_rta(); 1085458e999eSNishanth Menon 108655ed9694SPaul Walmsley clkdm_add_wkdep(neon_clkdm, mpu_clkdm); 108727d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 108827d59a4aSTero Kristo omap3_secure_ram_storage = 108927d59a4aSTero Kristo kmalloc(0x803F, GFP_KERNEL); 109027d59a4aSTero Kristo if (!omap3_secure_ram_storage) 109127d59a4aSTero Kristo printk(KERN_ERR "Memory allocation failed when" 109227d59a4aSTero Kristo "allocating for secure sram context\n"); 109327d59a4aSTero Kristo 10949d97140bSTero Kristo local_irq_disable(); 10959d97140bSTero Kristo local_fiq_disable(); 10969d97140bSTero Kristo 10979d97140bSTero Kristo omap_dma_global_context_save(); 1098617fcc98SKevin Hilman omap3_save_secure_ram_context(); 10999d97140bSTero Kristo omap_dma_global_context_restore(); 11009d97140bSTero Kristo 11019d97140bSTero Kristo local_irq_enable(); 11029d97140bSTero Kristo local_fiq_enable(); 11039d97140bSTero Kristo } 11049d97140bSTero Kristo 11059d97140bSTero Kristo omap3_save_scratchpad_contents(); 11068bd22949SKevin Hilman err1: 11078bd22949SKevin Hilman return ret; 11088bd22949SKevin Hilman err2: 11098bd22949SKevin Hilman free_irq(INT_34XX_PRCM_MPU_IRQ, NULL); 11108bd22949SKevin Hilman list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { 11118bd22949SKevin Hilman list_del(&pwrst->node); 11128bd22949SKevin Hilman kfree(pwrst); 11138bd22949SKevin Hilman } 11148bd22949SKevin Hilman return ret; 11158bd22949SKevin Hilman } 11168bd22949SKevin Hilman 11178bd22949SKevin Hilman late_initcall(omap3_pm_init); 1118