18bd22949SKevin Hilman /* 28bd22949SKevin Hilman * OMAP3 Power Management Routines 38bd22949SKevin Hilman * 48bd22949SKevin Hilman * Copyright (C) 2006-2008 Nokia Corporation 58bd22949SKevin Hilman * Tony Lindgren <tony@atomide.com> 68bd22949SKevin Hilman * Jouni Hogander 78bd22949SKevin Hilman * 82f5939c3SRajendra Nayak * Copyright (C) 2007 Texas Instruments, Inc. 92f5939c3SRajendra Nayak * Rajendra Nayak <rnayak@ti.com> 102f5939c3SRajendra Nayak * 118bd22949SKevin Hilman * Copyright (C) 2005 Texas Instruments, Inc. 128bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 138bd22949SKevin Hilman * 148bd22949SKevin Hilman * Based on pm.c for omap1 158bd22949SKevin Hilman * 168bd22949SKevin Hilman * This program is free software; you can redistribute it and/or modify 178bd22949SKevin Hilman * it under the terms of the GNU General Public License version 2 as 188bd22949SKevin Hilman * published by the Free Software Foundation. 198bd22949SKevin Hilman */ 208bd22949SKevin Hilman 218bd22949SKevin Hilman #include <linux/pm.h> 228bd22949SKevin Hilman #include <linux/suspend.h> 238bd22949SKevin Hilman #include <linux/interrupt.h> 248bd22949SKevin Hilman #include <linux/module.h> 258bd22949SKevin Hilman #include <linux/list.h> 268bd22949SKevin Hilman #include <linux/err.h> 278bd22949SKevin Hilman #include <linux/gpio.h> 28c40552bcSKevin Hilman #include <linux/clk.h> 29dccaad89STero Kristo #include <linux/delay.h> 305a0e3ad6STejun Heo #include <linux/slab.h> 310d8e2d0dSPaul Walmsley #include <linux/console.h> 325e7c58dcSJean Pihet #include <trace/events/power.h> 338bd22949SKevin Hilman 34ce491cf8STony Lindgren #include <plat/sram.h> 351540f214SPaul Walmsley #include "clockdomain.h" 3672e06d08SPaul Walmsley #include "powerdomain.h" 37ce491cf8STony Lindgren #include <plat/serial.h> 3861255ab9SRajendra Nayak #include <plat/sdrc.h> 392f5939c3SRajendra Nayak #include <plat/prcm.h> 402f5939c3SRajendra Nayak #include <plat/gpmc.h> 41f2d11858STero Kristo #include <plat/dma.h> 428bd22949SKevin Hilman 4357f277b0SRajendra Nayak #include <asm/tlbflush.h> 4457f277b0SRajendra Nayak 4559fb659bSPaul Walmsley #include "cm2xxx_3xxx.h" 468bd22949SKevin Hilman #include "cm-regbits-34xx.h" 478bd22949SKevin Hilman #include "prm-regbits-34xx.h" 488bd22949SKevin Hilman 4959fb659bSPaul Walmsley #include "prm2xxx_3xxx.h" 508bd22949SKevin Hilman #include "pm.h" 5113a6fe0fSTero Kristo #include "sdrc.h" 524814ced5SPaul Walmsley #include "control.h" 5313a6fe0fSTero Kristo 54e83df17fSKevin Hilman #ifdef CONFIG_SUSPEND 55e83df17fSKevin Hilman static suspend_state_t suspend_state = PM_SUSPEND_ON; 56e83df17fSKevin Hilman static inline bool is_suspending(void) 57e83df17fSKevin Hilman { 58e83df17fSKevin Hilman return (suspend_state != PM_SUSPEND_ON); 59e83df17fSKevin Hilman } 60e83df17fSKevin Hilman #else 61e83df17fSKevin Hilman static inline bool is_suspending(void) 62e83df17fSKevin Hilman { 63e83df17fSKevin Hilman return false; 64e83df17fSKevin Hilman } 65e83df17fSKevin Hilman #endif 66e83df17fSKevin Hilman 672f5939c3SRajendra Nayak /* Scratchpad offsets */ 68de658158SKevin Hilman #define OMAP343X_TABLE_ADDRESS_OFFSET 0xc4 69de658158SKevin Hilman #define OMAP343X_TABLE_VALUE_OFFSET 0xc0 70de658158SKevin Hilman #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8 712f5939c3SRajendra Nayak 728cdfd834SNishanth Menon /* pm34xx errata defined in pm.h */ 738cdfd834SNishanth Menon u16 pm34xx_errata; 748cdfd834SNishanth Menon 758bd22949SKevin Hilman struct power_state { 768bd22949SKevin Hilman struct powerdomain *pwrdm; 778bd22949SKevin Hilman u32 next_state; 7810f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 798bd22949SKevin Hilman u32 saved_state; 8010f90ed2SKevin Hilman #endif 818bd22949SKevin Hilman struct list_head node; 828bd22949SKevin Hilman }; 838bd22949SKevin Hilman 848bd22949SKevin Hilman static LIST_HEAD(pwrst_list); 858bd22949SKevin Hilman 868bd22949SKevin Hilman static void (*_omap_sram_idle)(u32 *addr, int save_state); 878bd22949SKevin Hilman 8827d59a4aSTero Kristo static int (*_omap_save_secure_sram)(u32 *addr); 8927d59a4aSTero Kristo 90fa3c2a4fSRajendra Nayak static struct powerdomain *mpu_pwrdm, *neon_pwrdm; 91fa3c2a4fSRajendra Nayak static struct powerdomain *core_pwrdm, *per_pwrdm; 92c16c3f67STero Kristo static struct powerdomain *cam_pwrdm; 93fa3c2a4fSRajendra Nayak 942f5939c3SRajendra Nayak static inline void omap3_per_save_context(void) 952f5939c3SRajendra Nayak { 962f5939c3SRajendra Nayak omap_gpio_save_context(); 972f5939c3SRajendra Nayak } 982f5939c3SRajendra Nayak 992f5939c3SRajendra Nayak static inline void omap3_per_restore_context(void) 1002f5939c3SRajendra Nayak { 1012f5939c3SRajendra Nayak omap_gpio_restore_context(); 1022f5939c3SRajendra Nayak } 1032f5939c3SRajendra Nayak 1043a7ec26bSKalle Jokiniemi static void omap3_enable_io_chain(void) 1053a7ec26bSKalle Jokiniemi { 1063a7ec26bSKalle Jokiniemi int timeout = 0; 1073a7ec26bSKalle Jokiniemi 1083a7ec26bSKalle Jokiniemi if (omap_rev() >= OMAP3430_REV_ES3_1) { 109c4d7e58fSPaul Walmsley omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, 1102bc4ef71SPaul Walmsley PM_WKEN); 1113a7ec26bSKalle Jokiniemi /* Do a readback to assure write has been done */ 112c4d7e58fSPaul Walmsley omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN); 1133a7ec26bSKalle Jokiniemi 114c4d7e58fSPaul Walmsley while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) & 1152bc4ef71SPaul Walmsley OMAP3430_ST_IO_CHAIN_MASK)) { 1163a7ec26bSKalle Jokiniemi timeout++; 1173a7ec26bSKalle Jokiniemi if (timeout > 1000) { 1183a7ec26bSKalle Jokiniemi printk(KERN_ERR "Wake up daisy chain " 1193a7ec26bSKalle Jokiniemi "activation failed.\n"); 1203a7ec26bSKalle Jokiniemi return; 1213a7ec26bSKalle Jokiniemi } 122c4d7e58fSPaul Walmsley omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, 1230b96a3a3SKevin Hilman WKUP_MOD, PM_WKEN); 1243a7ec26bSKalle Jokiniemi } 1253a7ec26bSKalle Jokiniemi } 1263a7ec26bSKalle Jokiniemi } 1273a7ec26bSKalle Jokiniemi 1283a7ec26bSKalle Jokiniemi static void omap3_disable_io_chain(void) 1293a7ec26bSKalle Jokiniemi { 1303a7ec26bSKalle Jokiniemi if (omap_rev() >= OMAP3430_REV_ES3_1) 131c4d7e58fSPaul Walmsley omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, 1322bc4ef71SPaul Walmsley PM_WKEN); 1333a7ec26bSKalle Jokiniemi } 1343a7ec26bSKalle Jokiniemi 1352f5939c3SRajendra Nayak static void omap3_core_save_context(void) 1362f5939c3SRajendra Nayak { 137596efe47SPaul Walmsley omap3_ctrl_save_padconf(); 138dccaad89STero Kristo 139dccaad89STero Kristo /* 140dccaad89STero Kristo * Force write last pad into memory, as this can fail in some 14183521291SJean Pihet * cases according to errata 1.157, 1.185 142dccaad89STero Kristo */ 143dccaad89STero Kristo omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), 144dccaad89STero Kristo OMAP343X_CONTROL_MEM_WKUP + 0x2a0); 145dccaad89STero Kristo 1462f5939c3SRajendra Nayak /* Save the Interrupt controller context */ 1472f5939c3SRajendra Nayak omap_intc_save_context(); 1482f5939c3SRajendra Nayak /* Save the GPMC context */ 1492f5939c3SRajendra Nayak omap3_gpmc_save_context(); 1502f5939c3SRajendra Nayak /* Save the system control module context, padconf already save above*/ 1512f5939c3SRajendra Nayak omap3_control_save_context(); 152f2d11858STero Kristo omap_dma_global_context_save(); 1532f5939c3SRajendra Nayak } 1542f5939c3SRajendra Nayak 1552f5939c3SRajendra Nayak static void omap3_core_restore_context(void) 1562f5939c3SRajendra Nayak { 1572f5939c3SRajendra Nayak /* Restore the control module context, padconf restored by h/w */ 1582f5939c3SRajendra Nayak omap3_control_restore_context(); 1592f5939c3SRajendra Nayak /* Restore the GPMC context */ 1602f5939c3SRajendra Nayak omap3_gpmc_restore_context(); 1612f5939c3SRajendra Nayak /* Restore the interrupt controller context */ 1622f5939c3SRajendra Nayak omap_intc_restore_context(); 163f2d11858STero Kristo omap_dma_global_context_restore(); 1642f5939c3SRajendra Nayak } 1652f5939c3SRajendra Nayak 1669d97140bSTero Kristo /* 1679d97140bSTero Kristo * FIXME: This function should be called before entering off-mode after 1689d97140bSTero Kristo * OMAP3 secure services have been accessed. Currently it is only called 1699d97140bSTero Kristo * once during boot sequence, but this works as we are not using secure 1709d97140bSTero Kristo * services. 1719d97140bSTero Kristo */ 172617fcc98SKevin Hilman static void omap3_save_secure_ram_context(void) 17327d59a4aSTero Kristo { 17427d59a4aSTero Kristo u32 ret; 175617fcc98SKevin Hilman int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 17627d59a4aSTero Kristo 17727d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 17827d59a4aSTero Kristo /* 17927d59a4aSTero Kristo * MPU next state must be set to POWER_ON temporarily, 18027d59a4aSTero Kristo * otherwise the WFI executed inside the ROM code 18127d59a4aSTero Kristo * will hang the system. 18227d59a4aSTero Kristo */ 18327d59a4aSTero Kristo pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); 18427d59a4aSTero Kristo ret = _omap_save_secure_sram((u32 *) 18527d59a4aSTero Kristo __pa(omap3_secure_ram_storage)); 186617fcc98SKevin Hilman pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state); 18727d59a4aSTero Kristo /* Following is for error tracking, it should not happen */ 18827d59a4aSTero Kristo if (ret) { 18927d59a4aSTero Kristo printk(KERN_ERR "save_secure_sram() returns %08x\n", 19027d59a4aSTero Kristo ret); 19127d59a4aSTero Kristo while (1) 19227d59a4aSTero Kristo ; 19327d59a4aSTero Kristo } 19427d59a4aSTero Kristo } 19527d59a4aSTero Kristo } 19627d59a4aSTero Kristo 19777da2d91SJon Hunter /* 19877da2d91SJon Hunter * PRCM Interrupt Handler Helper Function 19977da2d91SJon Hunter * 20077da2d91SJon Hunter * The purpose of this function is to clear any wake-up events latched 20177da2d91SJon Hunter * in the PRCM PM_WKST_x registers. It is possible that a wake-up event 20277da2d91SJon Hunter * may occur whilst attempting to clear a PM_WKST_x register and thus 20377da2d91SJon Hunter * set another bit in this register. A while loop is used to ensure 20477da2d91SJon Hunter * that any peripheral wake-up events occurring while attempting to 20577da2d91SJon Hunter * clear the PM_WKST_x are detected and cleared. 20677da2d91SJon Hunter */ 2078cb0ac99SPaul Walmsley static int prcm_clear_mod_irqs(s16 module, u8 regs) 20877da2d91SJon Hunter { 20971a80775SVikram Pandita u32 wkst, fclk, iclk, clken; 21077da2d91SJon Hunter u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; 21177da2d91SJon Hunter u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; 21277da2d91SJon Hunter u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; 2135d805978SPaul Walmsley u16 grpsel_off = (regs == 3) ? 2145d805978SPaul Walmsley OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; 2158cb0ac99SPaul Walmsley int c = 0; 21677da2d91SJon Hunter 217c4d7e58fSPaul Walmsley wkst = omap2_prm_read_mod_reg(module, wkst_off); 218c4d7e58fSPaul Walmsley wkst &= omap2_prm_read_mod_reg(module, grpsel_off); 21977da2d91SJon Hunter if (wkst) { 220c4d7e58fSPaul Walmsley iclk = omap2_cm_read_mod_reg(module, iclk_off); 221c4d7e58fSPaul Walmsley fclk = omap2_cm_read_mod_reg(module, fclk_off); 22277da2d91SJon Hunter while (wkst) { 22371a80775SVikram Pandita clken = wkst; 224c4d7e58fSPaul Walmsley omap2_cm_set_mod_reg_bits(clken, module, iclk_off); 22571a80775SVikram Pandita /* 22671a80775SVikram Pandita * For USBHOST, we don't know whether HOST1 or 22771a80775SVikram Pandita * HOST2 woke us up, so enable both f-clocks 22871a80775SVikram Pandita */ 22971a80775SVikram Pandita if (module == OMAP3430ES2_USBHOST_MOD) 23071a80775SVikram Pandita clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; 231c4d7e58fSPaul Walmsley omap2_cm_set_mod_reg_bits(clken, module, fclk_off); 232c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(wkst, module, wkst_off); 233c4d7e58fSPaul Walmsley wkst = omap2_prm_read_mod_reg(module, wkst_off); 2348cb0ac99SPaul Walmsley c++; 23577da2d91SJon Hunter } 236c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(iclk, module, iclk_off); 237c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(fclk, module, fclk_off); 23877da2d91SJon Hunter } 2398cb0ac99SPaul Walmsley 2408cb0ac99SPaul Walmsley return c; 2418cb0ac99SPaul Walmsley } 2428cb0ac99SPaul Walmsley 2438cb0ac99SPaul Walmsley static int _prcm_int_handle_wakeup(void) 2448cb0ac99SPaul Walmsley { 2458cb0ac99SPaul Walmsley int c; 2468cb0ac99SPaul Walmsley 2478cb0ac99SPaul Walmsley c = prcm_clear_mod_irqs(WKUP_MOD, 1); 2488cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(CORE_MOD, 1); 2498cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1); 2508cb0ac99SPaul Walmsley if (omap_rev() > OMAP3430_REV_ES1_0) { 2518cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(CORE_MOD, 3); 2528cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1); 2538cb0ac99SPaul Walmsley } 2548cb0ac99SPaul Walmsley 2558cb0ac99SPaul Walmsley return c; 25677da2d91SJon Hunter } 25777da2d91SJon Hunter 25877da2d91SJon Hunter /* 25977da2d91SJon Hunter * PRCM Interrupt Handler 26077da2d91SJon Hunter * 26177da2d91SJon Hunter * The PRM_IRQSTATUS_MPU register indicates if there are any pending 26277da2d91SJon Hunter * interrupts from the PRCM for the MPU. These bits must be cleared in 26377da2d91SJon Hunter * order to clear the PRCM interrupt. The PRCM interrupt handler is 26477da2d91SJon Hunter * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear 26577da2d91SJon Hunter * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU 26677da2d91SJon Hunter * register indicates that a wake-up event is pending for the MPU and 26777da2d91SJon Hunter * this bit can only be cleared if the all the wake-up events latched 26877da2d91SJon Hunter * in the various PM_WKST_x registers have been cleared. The interrupt 26977da2d91SJon Hunter * handler is implemented using a do-while loop so that if a wake-up 27077da2d91SJon Hunter * event occurred during the processing of the prcm interrupt handler 27177da2d91SJon Hunter * (setting a bit in the corresponding PM_WKST_x register and thus 27277da2d91SJon Hunter * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register) 27377da2d91SJon Hunter * this would be handled. 27477da2d91SJon Hunter */ 2758bd22949SKevin Hilman static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) 2768bd22949SKevin Hilman { 277d6290a3eSKevin Hilman u32 irqenable_mpu, irqstatus_mpu; 2788cb0ac99SPaul Walmsley int c = 0; 2798bd22949SKevin Hilman 280c4d7e58fSPaul Walmsley irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD, 281d6290a3eSKevin Hilman OMAP3_PRM_IRQENABLE_MPU_OFFSET); 282c4d7e58fSPaul Walmsley irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD, 2838bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 284d6290a3eSKevin Hilman irqstatus_mpu &= irqenable_mpu; 2858cb0ac99SPaul Walmsley 286d6290a3eSKevin Hilman do { 2872bc4ef71SPaul Walmsley if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK | 2882bc4ef71SPaul Walmsley OMAP3430_IO_ST_MASK)) { 2898cb0ac99SPaul Walmsley c = _prcm_int_handle_wakeup(); 2908cb0ac99SPaul Walmsley 2918cb0ac99SPaul Walmsley /* 2928cb0ac99SPaul Walmsley * Is the MPU PRCM interrupt handler racing with the 2938cb0ac99SPaul Walmsley * IVA2 PRCM interrupt handler ? 2948cb0ac99SPaul Walmsley */ 2958cb0ac99SPaul Walmsley WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup " 2968cb0ac99SPaul Walmsley "but no wakeup sources are marked\n"); 2978cb0ac99SPaul Walmsley } else { 2988cb0ac99SPaul Walmsley /* XXX we need to expand our PRCM interrupt handler */ 2998cb0ac99SPaul Walmsley WARN(1, "prcm: WARNING: PRCM interrupt received, but " 3008cb0ac99SPaul Walmsley "no code to handle it (%08x)\n", irqstatus_mpu); 3018cb0ac99SPaul Walmsley } 3028cb0ac99SPaul Walmsley 303c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD, 3048bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 3058bd22949SKevin Hilman 306c4d7e58fSPaul Walmsley irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD, 307d6290a3eSKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 308d6290a3eSKevin Hilman irqstatus_mpu &= irqenable_mpu; 309d6290a3eSKevin Hilman 310d6290a3eSKevin Hilman } while (irqstatus_mpu); 3118bd22949SKevin Hilman 3128bd22949SKevin Hilman return IRQ_HANDLED; 3138bd22949SKevin Hilman } 3148bd22949SKevin Hilman 31557f277b0SRajendra Nayak static void restore_control_register(u32 val) 31657f277b0SRajendra Nayak { 31757f277b0SRajendra Nayak __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val)); 31857f277b0SRajendra Nayak } 31957f277b0SRajendra Nayak 32057f277b0SRajendra Nayak /* Function to restore the table entry that was modified for enabling MMU */ 32157f277b0SRajendra Nayak static void restore_table_entry(void) 32257f277b0SRajendra Nayak { 3234d63bc1dSManjunath Kondaiah G void __iomem *scratchpad_address; 32457f277b0SRajendra Nayak u32 previous_value, control_reg_value; 32557f277b0SRajendra Nayak u32 *address; 32657f277b0SRajendra Nayak 32757f277b0SRajendra Nayak scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD); 32857f277b0SRajendra Nayak 32957f277b0SRajendra Nayak /* Get address of entry that was modified */ 33057f277b0SRajendra Nayak address = (u32 *)__raw_readl(scratchpad_address + 33157f277b0SRajendra Nayak OMAP343X_TABLE_ADDRESS_OFFSET); 33257f277b0SRajendra Nayak /* Get the previous value which needs to be restored */ 33357f277b0SRajendra Nayak previous_value = __raw_readl(scratchpad_address + 33457f277b0SRajendra Nayak OMAP343X_TABLE_VALUE_OFFSET); 33557f277b0SRajendra Nayak address = __va(address); 33657f277b0SRajendra Nayak *address = previous_value; 33757f277b0SRajendra Nayak flush_tlb_all(); 33857f277b0SRajendra Nayak control_reg_value = __raw_readl(scratchpad_address 33957f277b0SRajendra Nayak + OMAP343X_CONTROL_REG_VALUE_OFFSET); 34057f277b0SRajendra Nayak /* This will enable caches and prediction */ 34157f277b0SRajendra Nayak restore_control_register(control_reg_value); 34257f277b0SRajendra Nayak } 34357f277b0SRajendra Nayak 34499e6a4d2SRajendra Nayak void omap_sram_idle(void) 3458bd22949SKevin Hilman { 3468bd22949SKevin Hilman /* Variable to tell what needs to be saved and restored 3478bd22949SKevin Hilman * in omap_sram_idle*/ 3488bd22949SKevin Hilman /* save_state = 0 => Nothing to save and restored */ 3498bd22949SKevin Hilman /* save_state = 1 => Only L1 and logic lost */ 3508bd22949SKevin Hilman /* save_state = 2 => Only L2 lost */ 3518bd22949SKevin Hilman /* save_state = 3 => L1, L2 and logic lost */ 352fa3c2a4fSRajendra Nayak int save_state = 0; 353fa3c2a4fSRajendra Nayak int mpu_next_state = PWRDM_POWER_ON; 354fa3c2a4fSRajendra Nayak int per_next_state = PWRDM_POWER_ON; 355fa3c2a4fSRajendra Nayak int core_next_state = PWRDM_POWER_ON; 35672e06d08SPaul Walmsley int per_going_off; 3572f5939c3SRajendra Nayak int core_prev_state, per_prev_state; 35813a6fe0fSTero Kristo u32 sdrc_pwr = 0; 3598bd22949SKevin Hilman 3608bd22949SKevin Hilman if (!_omap_sram_idle) 3618bd22949SKevin Hilman return; 3628bd22949SKevin Hilman 363fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(mpu_pwrdm); 364fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(neon_pwrdm); 365fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(core_pwrdm); 366fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(per_pwrdm); 367fa3c2a4fSRajendra Nayak 3688bd22949SKevin Hilman mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 3698bd22949SKevin Hilman switch (mpu_next_state) { 370fa3c2a4fSRajendra Nayak case PWRDM_POWER_ON: 3718bd22949SKevin Hilman case PWRDM_POWER_RET: 3728bd22949SKevin Hilman /* No need to save context */ 3738bd22949SKevin Hilman save_state = 0; 3748bd22949SKevin Hilman break; 37561255ab9SRajendra Nayak case PWRDM_POWER_OFF: 37661255ab9SRajendra Nayak save_state = 3; 37761255ab9SRajendra Nayak break; 3788bd22949SKevin Hilman default: 3798bd22949SKevin Hilman /* Invalid state */ 3808bd22949SKevin Hilman printk(KERN_ERR "Invalid mpu state in sram_idle\n"); 3818bd22949SKevin Hilman return; 3828bd22949SKevin Hilman } 383fe617af7SPeter 'p2' De Schrijver pwrdm_pre_transition(); 384fe617af7SPeter 'p2' De Schrijver 385fa3c2a4fSRajendra Nayak /* NEON control */ 386fa3c2a4fSRajendra Nayak if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) 3877139178eSJouni Hogander pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); 388fa3c2a4fSRajendra Nayak 38940742fa8SMike Chan /* Enable IO-PAD and IO-CHAIN wakeups */ 390fa3c2a4fSRajendra Nayak per_next_state = pwrdm_read_next_pwrst(per_pwrdm); 391ecf157d0STero Kristo core_next_state = pwrdm_read_next_pwrst(core_pwrdm); 392d5c47d7eSKevin Hilman if (omap3_has_io_wakeup() && 393ad0c63f1Sstanley.miao (per_next_state < PWRDM_POWER_ON || 394ad0c63f1Sstanley.miao core_next_state < PWRDM_POWER_ON)) { 395c4d7e58fSPaul Walmsley omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); 39640742fa8SMike Chan omap3_enable_io_chain(); 39740742fa8SMike Chan } 39840742fa8SMike Chan 3990d8e2d0dSPaul Walmsley /* Block console output in case it is on one of the OMAP UARTs */ 400e83df17fSKevin Hilman if (!is_suspending()) 4010d8e2d0dSPaul Walmsley if (per_next_state < PWRDM_POWER_ON || 4020d8e2d0dSPaul Walmsley core_next_state < PWRDM_POWER_ON) 403ac751efaSTorben Hohn if (!console_trylock()) 4040d8e2d0dSPaul Walmsley goto console_still_active; 4050d8e2d0dSPaul Walmsley 40640742fa8SMike Chan /* PER */ 4072f5939c3SRajendra Nayak if (per_next_state < PWRDM_POWER_ON) { 40872e06d08SPaul Walmsley per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0; 4094af4016cSKevin Hilman omap_uart_prepare_idle(2); 410cd4f1faeSGovindraj.R omap_uart_prepare_idle(3); 41172e06d08SPaul Walmsley omap2_gpio_prepare_for_idle(per_going_off); 412e7410cf7SKevin Hilman if (per_next_state == PWRDM_POWER_OFF) 4132f5939c3SRajendra Nayak omap3_per_save_context(); 4142f5939c3SRajendra Nayak } 415c16c3f67STero Kristo 416658ce97eSKevin Hilman /* CORE */ 417658ce97eSKevin Hilman if (core_next_state < PWRDM_POWER_ON) { 418658ce97eSKevin Hilman omap_uart_prepare_idle(0); 419658ce97eSKevin Hilman omap_uart_prepare_idle(1); 4202f5939c3SRajendra Nayak if (core_next_state == PWRDM_POWER_OFF) { 4212f5939c3SRajendra Nayak omap3_core_save_context(); 422f0611a5cSPaul Walmsley omap3_cm_save_context(); 4232f5939c3SRajendra Nayak } 424fa3c2a4fSRajendra Nayak } 42540742fa8SMike Chan 426f18cc2ffSTero Kristo omap3_intc_prepare_idle(); 4278bd22949SKevin Hilman 42861255ab9SRajendra Nayak /* 429f265dc4cSRajendra Nayak * On EMU/HS devices ROM code restores a SRDC value 430f265dc4cSRajendra Nayak * from scratchpad which has automatic self refresh on timeout 43183521291SJean Pihet * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443. 432f265dc4cSRajendra Nayak * Hence store/restore the SDRC_POWER register here. 43313a6fe0fSTero Kristo */ 43413a6fe0fSTero Kristo if (omap_rev() >= OMAP3430_REV_ES3_0 && 43513a6fe0fSTero Kristo omap_type() != OMAP2_DEVICE_TYPE_GP && 436f265dc4cSRajendra Nayak core_next_state == PWRDM_POWER_OFF) 43713a6fe0fSTero Kristo sdrc_pwr = sdrc_read_reg(SDRC_POWER); 43813a6fe0fSTero Kristo 43913a6fe0fSTero Kristo /* 44061255ab9SRajendra Nayak * omap3_arm_context is the location where ARM registers 44161255ab9SRajendra Nayak * get saved. The restore path then reads from this 44261255ab9SRajendra Nayak * location and restores them back. 44361255ab9SRajendra Nayak */ 44461255ab9SRajendra Nayak _omap_sram_idle(omap3_arm_context, save_state); 4458bd22949SKevin Hilman cpu_init(); 4468bd22949SKevin Hilman 447f265dc4cSRajendra Nayak /* Restore normal SDRC POWER settings */ 44813a6fe0fSTero Kristo if (omap_rev() >= OMAP3430_REV_ES3_0 && 44913a6fe0fSTero Kristo omap_type() != OMAP2_DEVICE_TYPE_GP && 45013a6fe0fSTero Kristo core_next_state == PWRDM_POWER_OFF) 45113a6fe0fSTero Kristo sdrc_write_reg(sdrc_pwr, SDRC_POWER); 45213a6fe0fSTero Kristo 45357f277b0SRajendra Nayak /* Restore table entry modified during MMU restoration */ 45457f277b0SRajendra Nayak if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF) 45557f277b0SRajendra Nayak restore_table_entry(); 45657f277b0SRajendra Nayak 457658ce97eSKevin Hilman /* CORE */ 458fa3c2a4fSRajendra Nayak if (core_next_state < PWRDM_POWER_ON) { 4592f5939c3SRajendra Nayak core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); 4602f5939c3SRajendra Nayak if (core_prev_state == PWRDM_POWER_OFF) { 4612f5939c3SRajendra Nayak omap3_core_restore_context(); 462f0611a5cSPaul Walmsley omap3_cm_restore_context(); 4632f5939c3SRajendra Nayak omap3_sram_restore_context(); 4648a917d2fSKalle Jokiniemi omap2_sms_restore_context(); 4652f5939c3SRajendra Nayak } 466658ce97eSKevin Hilman omap_uart_resume_idle(0); 467658ce97eSKevin Hilman omap_uart_resume_idle(1); 468658ce97eSKevin Hilman if (core_next_state == PWRDM_POWER_OFF) 469c4d7e58fSPaul Walmsley omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, 470658ce97eSKevin Hilman OMAP3430_GR_MOD, 471658ce97eSKevin Hilman OMAP3_PRM_VOLTCTRL_OFFSET); 472658ce97eSKevin Hilman } 473f18cc2ffSTero Kristo omap3_intc_resume_idle(); 474658ce97eSKevin Hilman 475658ce97eSKevin Hilman /* PER */ 4762f5939c3SRajendra Nayak if (per_next_state < PWRDM_POWER_ON) { 477658ce97eSKevin Hilman per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); 47843ffcd9aSKevin Hilman omap2_gpio_resume_after_idle(); 47943ffcd9aSKevin Hilman if (per_prev_state == PWRDM_POWER_OFF) 4802f5939c3SRajendra Nayak omap3_per_restore_context(); 481ecf157d0STero Kristo omap_uart_resume_idle(2); 482cd4f1faeSGovindraj.R omap_uart_resume_idle(3); 483fa3c2a4fSRajendra Nayak } 484fe617af7SPeter 'p2' De Schrijver 485e83df17fSKevin Hilman if (!is_suspending()) 486ac751efaSTorben Hohn console_unlock(); 4870d8e2d0dSPaul Walmsley 4880d8e2d0dSPaul Walmsley console_still_active: 4893a7ec26bSKalle Jokiniemi /* Disable IO-PAD and IO-CHAIN wakeup */ 49058a5559eSKevin Hilman if (omap3_has_io_wakeup() && 49158a5559eSKevin Hilman (per_next_state < PWRDM_POWER_ON || 49258a5559eSKevin Hilman core_next_state < PWRDM_POWER_ON)) { 493c4d7e58fSPaul Walmsley omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, 494c4d7e58fSPaul Walmsley PM_WKEN); 4953a7ec26bSKalle Jokiniemi omap3_disable_io_chain(); 4963a7ec26bSKalle Jokiniemi } 497658ce97eSKevin Hilman 498fe617af7SPeter 'p2' De Schrijver pwrdm_post_transition(); 499fe617af7SPeter 'p2' De Schrijver 5005cd1937bSRajendra Nayak clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); 5018bd22949SKevin Hilman } 5028bd22949SKevin Hilman 50320b01669SRajendra Nayak int omap3_can_sleep(void) 5048bd22949SKevin Hilman { 505c40552bcSKevin Hilman if (!sleep_while_idle) 506c40552bcSKevin Hilman return 0; 5074af4016cSKevin Hilman if (!omap_uart_can_sleep()) 5084af4016cSKevin Hilman return 0; 5098bd22949SKevin Hilman return 1; 5108bd22949SKevin Hilman } 5118bd22949SKevin Hilman 5128bd22949SKevin Hilman static void omap3_pm_idle(void) 5138bd22949SKevin Hilman { 5148bd22949SKevin Hilman local_irq_disable(); 5158bd22949SKevin Hilman local_fiq_disable(); 5168bd22949SKevin Hilman 5178bd22949SKevin Hilman if (!omap3_can_sleep()) 5188bd22949SKevin Hilman goto out; 5198bd22949SKevin Hilman 520cf22854cSTero Kristo if (omap_irq_pending() || need_resched()) 5218bd22949SKevin Hilman goto out; 5228bd22949SKevin Hilman 5235e7c58dcSJean Pihet trace_power_start(POWER_CSTATE, 1, smp_processor_id()); 5245e7c58dcSJean Pihet trace_cpu_idle(1, smp_processor_id()); 5255e7c58dcSJean Pihet 5268bd22949SKevin Hilman omap_sram_idle(); 5278bd22949SKevin Hilman 5285e7c58dcSJean Pihet trace_power_end(smp_processor_id()); 5295e7c58dcSJean Pihet trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); 5305e7c58dcSJean Pihet 5318bd22949SKevin Hilman out: 5328bd22949SKevin Hilman local_fiq_enable(); 5338bd22949SKevin Hilman local_irq_enable(); 5348bd22949SKevin Hilman } 5358bd22949SKevin Hilman 53610f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 5378bd22949SKevin Hilman static int omap3_pm_suspend(void) 5388bd22949SKevin Hilman { 5398bd22949SKevin Hilman struct power_state *pwrst; 5408bd22949SKevin Hilman int state, ret = 0; 5418bd22949SKevin Hilman 5428e2efde9SAri Kauppi if (wakeup_timer_seconds || wakeup_timer_milliseconds) 5438e2efde9SAri Kauppi omap2_pm_wakeup_on_timer(wakeup_timer_seconds, 5448e2efde9SAri Kauppi wakeup_timer_milliseconds); 545d7814e4dSKevin Hilman 5468bd22949SKevin Hilman /* Read current next_pwrsts */ 5478bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) 5488bd22949SKevin Hilman pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 5498bd22949SKevin Hilman /* Set ones wanted by suspend */ 5508bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 551eb6a2c75SSantosh Shilimkar if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) 5528bd22949SKevin Hilman goto restore; 5538bd22949SKevin Hilman if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) 5548bd22949SKevin Hilman goto restore; 5558bd22949SKevin Hilman } 5568bd22949SKevin Hilman 5574af4016cSKevin Hilman omap_uart_prepare_suspend(); 5582bbe3af3STero Kristo omap3_intc_suspend(); 5592bbe3af3STero Kristo 5608bd22949SKevin Hilman omap_sram_idle(); 5618bd22949SKevin Hilman 5628bd22949SKevin Hilman restore: 5638bd22949SKevin Hilman /* Restore next_pwrsts */ 5648bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 5658bd22949SKevin Hilman state = pwrdm_read_prev_pwrst(pwrst->pwrdm); 5668bd22949SKevin Hilman if (state > pwrst->next_state) { 5678bd22949SKevin Hilman printk(KERN_INFO "Powerdomain (%s) didn't enter " 5688bd22949SKevin Hilman "target state %d\n", 5698bd22949SKevin Hilman pwrst->pwrdm->name, pwrst->next_state); 5708bd22949SKevin Hilman ret = -1; 5718bd22949SKevin Hilman } 572eb6a2c75SSantosh Shilimkar omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); 5738bd22949SKevin Hilman } 5748bd22949SKevin Hilman if (ret) 5758bd22949SKevin Hilman printk(KERN_ERR "Could not enter target state in pm_suspend\n"); 5768bd22949SKevin Hilman else 5778bd22949SKevin Hilman printk(KERN_INFO "Successfully put all powerdomains " 5788bd22949SKevin Hilman "to target state\n"); 5798bd22949SKevin Hilman 5808bd22949SKevin Hilman return ret; 5818bd22949SKevin Hilman } 5828bd22949SKevin Hilman 5832466211eSTero Kristo static int omap3_pm_enter(suspend_state_t unused) 5848bd22949SKevin Hilman { 5858bd22949SKevin Hilman int ret = 0; 5868bd22949SKevin Hilman 5872466211eSTero Kristo switch (suspend_state) { 5888bd22949SKevin Hilman case PM_SUSPEND_STANDBY: 5898bd22949SKevin Hilman case PM_SUSPEND_MEM: 5908bd22949SKevin Hilman ret = omap3_pm_suspend(); 5918bd22949SKevin Hilman break; 5928bd22949SKevin Hilman default: 5938bd22949SKevin Hilman ret = -EINVAL; 5948bd22949SKevin Hilman } 5958bd22949SKevin Hilman 5968bd22949SKevin Hilman return ret; 5978bd22949SKevin Hilman } 5988bd22949SKevin Hilman 5992466211eSTero Kristo /* Hooks to enable / disable UART interrupts during suspend */ 6002466211eSTero Kristo static int omap3_pm_begin(suspend_state_t state) 6012466211eSTero Kristo { 602c166381dSJean Pihet disable_hlt(); 6032466211eSTero Kristo suspend_state = state; 6042466211eSTero Kristo omap_uart_enable_irqs(0); 6052466211eSTero Kristo return 0; 6062466211eSTero Kristo } 6072466211eSTero Kristo 6082466211eSTero Kristo static void omap3_pm_end(void) 6092466211eSTero Kristo { 6102466211eSTero Kristo suspend_state = PM_SUSPEND_ON; 6112466211eSTero Kristo omap_uart_enable_irqs(1); 612c166381dSJean Pihet enable_hlt(); 6132466211eSTero Kristo return; 6142466211eSTero Kristo } 6152466211eSTero Kristo 6162f55ac07SLionel Debroux static const struct platform_suspend_ops omap_pm_ops = { 6172466211eSTero Kristo .begin = omap3_pm_begin, 6182466211eSTero Kristo .end = omap3_pm_end, 6198bd22949SKevin Hilman .enter = omap3_pm_enter, 6208bd22949SKevin Hilman .valid = suspend_valid_only_mem, 6218bd22949SKevin Hilman }; 62210f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 6238bd22949SKevin Hilman 6241155e426SKevin Hilman 6251155e426SKevin Hilman /** 6261155e426SKevin Hilman * omap3_iva_idle(): ensure IVA is in idle so it can be put into 6271155e426SKevin Hilman * retention 6281155e426SKevin Hilman * 6291155e426SKevin Hilman * In cases where IVA2 is activated by bootcode, it may prevent 6301155e426SKevin Hilman * full-chip retention or off-mode because it is not idle. This 6311155e426SKevin Hilman * function forces the IVA2 into idle state so it can go 6321155e426SKevin Hilman * into retention/off and thus allow full-chip retention/off. 6331155e426SKevin Hilman * 6341155e426SKevin Hilman **/ 6351155e426SKevin Hilman static void __init omap3_iva_idle(void) 6361155e426SKevin Hilman { 6371155e426SKevin Hilman /* ensure IVA2 clock is disabled */ 638c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 6391155e426SKevin Hilman 6401155e426SKevin Hilman /* if no clock activity, nothing else to do */ 641c4d7e58fSPaul Walmsley if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & 6421155e426SKevin Hilman OMAP3430_CLKACTIVITY_IVA2_MASK)) 6431155e426SKevin Hilman return; 6441155e426SKevin Hilman 6451155e426SKevin Hilman /* Reset IVA2 */ 646c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | 6472bc4ef71SPaul Walmsley OMAP3430_RST2_IVA2_MASK | 6482bc4ef71SPaul Walmsley OMAP3430_RST3_IVA2_MASK, 64937903009SAbhijit Pagare OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 6501155e426SKevin Hilman 6511155e426SKevin Hilman /* Enable IVA2 clock */ 652c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, 6531155e426SKevin Hilman OMAP3430_IVA2_MOD, CM_FCLKEN); 6541155e426SKevin Hilman 6551155e426SKevin Hilman /* Set IVA2 boot mode to 'idle' */ 6561155e426SKevin Hilman omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, 6571155e426SKevin Hilman OMAP343X_CONTROL_IVA2_BOOTMOD); 6581155e426SKevin Hilman 6591155e426SKevin Hilman /* Un-reset IVA2 */ 660c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 6611155e426SKevin Hilman 6621155e426SKevin Hilman /* Disable IVA2 clock */ 663c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 6641155e426SKevin Hilman 6651155e426SKevin Hilman /* Reset IVA2 */ 666c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | 6672bc4ef71SPaul Walmsley OMAP3430_RST2_IVA2_MASK | 6682bc4ef71SPaul Walmsley OMAP3430_RST3_IVA2_MASK, 66937903009SAbhijit Pagare OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 6701155e426SKevin Hilman } 6711155e426SKevin Hilman 6728111b221SKevin Hilman static void __init omap3_d2d_idle(void) 6738bd22949SKevin Hilman { 6748111b221SKevin Hilman u16 mask, padconf; 6758111b221SKevin Hilman 6768111b221SKevin Hilman /* In a stand alone OMAP3430 where there is not a stacked 6778111b221SKevin Hilman * modem for the D2D Idle Ack and D2D MStandby must be pulled 6788111b221SKevin Hilman * high. S CONTROL_PADCONF_SAD2D_IDLEACK and 6798111b221SKevin Hilman * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ 6808111b221SKevin Hilman mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ 6818111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); 6828111b221SKevin Hilman padconf |= mask; 6838111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); 6848111b221SKevin Hilman 6858111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); 6868111b221SKevin Hilman padconf |= mask; 6878111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 6888111b221SKevin Hilman 6898bd22949SKevin Hilman /* reset modem */ 690c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | 6912bc4ef71SPaul Walmsley OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, 69237903009SAbhijit Pagare CORE_MOD, OMAP2_RM_RSTCTRL); 693c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); 6948111b221SKevin Hilman } 6958bd22949SKevin Hilman 6968111b221SKevin Hilman static void __init prcm_setup_regs(void) 6978111b221SKevin Hilman { 698e5863689SGovindraj.R u32 omap3630_en_uart4_mask = cpu_is_omap3630() ? 699e5863689SGovindraj.R OMAP3630_EN_UART4_MASK : 0; 700e5863689SGovindraj.R u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ? 701e5863689SGovindraj.R OMAP3630_GRPSEL_UART4_MASK : 0; 702e5863689SGovindraj.R 7038bd22949SKevin Hilman /* XXX Reset all wkdeps. This should be done when initializing 7048bd22949SKevin Hilman * powerdomains */ 705c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); 706c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, MPU_MOD, PM_WKDEP); 707c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP); 708c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP); 709c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP); 710c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP); 7118bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 712c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP); 713c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP); 7148bd22949SKevin Hilman } else 715c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); 7168bd22949SKevin Hilman 7174ef70c06SPaul Walmsley /* XXX This should be handled by hwmod code or SCM init code */ 7182fd0f75cSPaul Walmsley omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); 719b296c811STero Kristo 7208bd22949SKevin Hilman /* 7218bd22949SKevin Hilman * Enable control of expternal oscillator through 7228bd22949SKevin Hilman * sys_clkreq. In the long run clock framework should 7238bd22949SKevin Hilman * take care of this. 7248bd22949SKevin Hilman */ 725c4d7e58fSPaul Walmsley omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 7268bd22949SKevin Hilman 1 << OMAP_AUTOEXTCLKMODE_SHIFT, 7278bd22949SKevin Hilman OMAP3430_GR_MOD, 7288bd22949SKevin Hilman OMAP3_PRM_CLKSRC_CTRL_OFFSET); 7298bd22949SKevin Hilman 7308bd22949SKevin Hilman /* setup wakup source */ 731c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | 7322fd0f75cSPaul Walmsley OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, 7338bd22949SKevin Hilman WKUP_MOD, PM_WKEN); 7348bd22949SKevin Hilman /* No need to write EN_IO, that is always enabled */ 735c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | 736275f675cSPaul Walmsley OMAP3430_GRPSEL_GPT1_MASK | 737275f675cSPaul Walmsley OMAP3430_GRPSEL_GPT12_MASK, 7388bd22949SKevin Hilman WKUP_MOD, OMAP3430_PM_MPUGRPSEL); 7398bd22949SKevin Hilman /* For some reason IO doesn't generate wakeup event even if 7408bd22949SKevin Hilman * it is selected to mpu wakeup goup */ 741c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK, 7428bd22949SKevin Hilman OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); 7431155e426SKevin Hilman 744b92c5721SSubramani Venkatesh /* Enable PM_WKEN to support DSS LPR */ 745c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, 746b92c5721SSubramani Venkatesh OMAP3430_DSS_MOD, PM_WKEN); 747b92c5721SSubramani Venkatesh 748b427f92fSKevin Hilman /* Enable wakeups in PER */ 749c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(omap3630_en_uart4_mask | 750e5863689SGovindraj.R OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | 7512fd0f75cSPaul Walmsley OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | 7522fd0f75cSPaul Walmsley OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | 7532fd0f75cSPaul Walmsley OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK | 7542fd0f75cSPaul Walmsley OMAP3430_EN_MCBSP4_MASK, 755b427f92fSKevin Hilman OMAP3430_PER_MOD, PM_WKEN); 756eb350f74SKevin Hilman /* and allow them to wake up MPU */ 757c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask | 758e5863689SGovindraj.R OMAP3430_GRPSEL_GPIO2_MASK | 759275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO3_MASK | 760275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO4_MASK | 761275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO5_MASK | 762275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO6_MASK | 763275f675cSPaul Walmsley OMAP3430_GRPSEL_UART3_MASK | 764275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP2_MASK | 765275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP3_MASK | 766275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP4_MASK, 767eb350f74SKevin Hilman OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); 768eb350f74SKevin Hilman 769d3fd3290SKevin Hilman /* Don't attach IVA interrupts */ 770c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 771c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 772c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 773c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); 774d3fd3290SKevin Hilman 775b1340d17SKevin Hilman /* Clear any pending 'reset' flags */ 776c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); 777c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); 778c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); 779c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); 780c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); 781c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); 782c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); 783b1340d17SKevin Hilman 784014c46dbSKevin Hilman /* Clear any pending PRCM interrupts */ 785c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 786014c46dbSKevin Hilman 7871155e426SKevin Hilman omap3_iva_idle(); 7888111b221SKevin Hilman omap3_d2d_idle(); 7898bd22949SKevin Hilman } 7908bd22949SKevin Hilman 791c40552bcSKevin Hilman void omap3_pm_off_mode_enable(int enable) 792c40552bcSKevin Hilman { 793c40552bcSKevin Hilman struct power_state *pwrst; 794c40552bcSKevin Hilman u32 state; 795c40552bcSKevin Hilman 796c40552bcSKevin Hilman if (enable) 797c40552bcSKevin Hilman state = PWRDM_POWER_OFF; 798c40552bcSKevin Hilman else 799c40552bcSKevin Hilman state = PWRDM_POWER_RET; 800c40552bcSKevin Hilman 8016af83b38SSanjeev Premi #ifdef CONFIG_CPU_IDLE 802cc1b6028SEduardo Valentin /* 803cc1b6028SEduardo Valentin * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot 804cc1b6028SEduardo Valentin * enable OFF mode in a stable form for previous revisions, restrict 805cc1b6028SEduardo Valentin * instead to RET 806cc1b6028SEduardo Valentin */ 807cc1b6028SEduardo Valentin if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) 808cc1b6028SEduardo Valentin omap3_cpuidle_update_states(state, PWRDM_POWER_RET); 809cc1b6028SEduardo Valentin else 81080723c3fSNishanth Menon omap3_cpuidle_update_states(state, state); 8116af83b38SSanjeev Premi #endif 8126af83b38SSanjeev Premi 813c40552bcSKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 814cc1b6028SEduardo Valentin if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) && 815cc1b6028SEduardo Valentin pwrst->pwrdm == core_pwrdm && 816cc1b6028SEduardo Valentin state == PWRDM_POWER_OFF) { 817cc1b6028SEduardo Valentin pwrst->next_state = PWRDM_POWER_RET; 818cc1b6028SEduardo Valentin WARN_ONCE(1, 819cc1b6028SEduardo Valentin "%s: Core OFF disabled due to errata i583\n", 820cc1b6028SEduardo Valentin __func__); 821cc1b6028SEduardo Valentin } else { 822c40552bcSKevin Hilman pwrst->next_state = state; 823cc1b6028SEduardo Valentin } 824cc1b6028SEduardo Valentin omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 825c40552bcSKevin Hilman } 826c40552bcSKevin Hilman } 827c40552bcSKevin Hilman 82868d4778cSTero Kristo int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) 82968d4778cSTero Kristo { 83068d4778cSTero Kristo struct power_state *pwrst; 83168d4778cSTero Kristo 83268d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 83368d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) 83468d4778cSTero Kristo return pwrst->next_state; 83568d4778cSTero Kristo } 83668d4778cSTero Kristo return -EINVAL; 83768d4778cSTero Kristo } 83868d4778cSTero Kristo 83968d4778cSTero Kristo int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) 84068d4778cSTero Kristo { 84168d4778cSTero Kristo struct power_state *pwrst; 84268d4778cSTero Kristo 84368d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 84468d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) { 84568d4778cSTero Kristo pwrst->next_state = state; 84668d4778cSTero Kristo return 0; 84768d4778cSTero Kristo } 84868d4778cSTero Kristo } 84968d4778cSTero Kristo return -EINVAL; 85068d4778cSTero Kristo } 85168d4778cSTero Kristo 852a23456e9SPeter 'p2' De Schrijver static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) 8538bd22949SKevin Hilman { 8548bd22949SKevin Hilman struct power_state *pwrst; 8558bd22949SKevin Hilman 8568bd22949SKevin Hilman if (!pwrdm->pwrsts) 8578bd22949SKevin Hilman return 0; 8588bd22949SKevin Hilman 859d3d381c6SMing Lei pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); 8608bd22949SKevin Hilman if (!pwrst) 8618bd22949SKevin Hilman return -ENOMEM; 8628bd22949SKevin Hilman pwrst->pwrdm = pwrdm; 8638bd22949SKevin Hilman pwrst->next_state = PWRDM_POWER_RET; 8648bd22949SKevin Hilman list_add(&pwrst->node, &pwrst_list); 8658bd22949SKevin Hilman 8668bd22949SKevin Hilman if (pwrdm_has_hdwr_sar(pwrdm)) 8678bd22949SKevin Hilman pwrdm_enable_hdwr_sar(pwrdm); 8688bd22949SKevin Hilman 869eb6a2c75SSantosh Shilimkar return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 8708bd22949SKevin Hilman } 8718bd22949SKevin Hilman 8728bd22949SKevin Hilman /* 8738bd22949SKevin Hilman * Enable hw supervised mode for all clockdomains if it's 8748bd22949SKevin Hilman * supported. Initiate sleep transition for other clockdomains, if 8758bd22949SKevin Hilman * they are not used 8768bd22949SKevin Hilman */ 877a23456e9SPeter 'p2' De Schrijver static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) 8788bd22949SKevin Hilman { 8798bd22949SKevin Hilman if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) 8805cd1937bSRajendra Nayak clkdm_allow_idle(clkdm); 8818bd22949SKevin Hilman else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && 8828bd22949SKevin Hilman atomic_read(&clkdm->usecount) == 0) 88368b921adSRajendra Nayak clkdm_sleep(clkdm); 8848bd22949SKevin Hilman return 0; 8858bd22949SKevin Hilman } 8868bd22949SKevin Hilman 8873231fc88SRajendra Nayak void omap_push_sram_idle(void) 8883231fc88SRajendra Nayak { 8893231fc88SRajendra Nayak _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend, 8903231fc88SRajendra Nayak omap34xx_cpu_suspend_sz); 89127d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) 89227d59a4aSTero Kristo _omap_save_secure_sram = omap_sram_push(save_secure_ram_context, 89327d59a4aSTero Kristo save_secure_ram_context_sz); 8943231fc88SRajendra Nayak } 8953231fc88SRajendra Nayak 8968cdfd834SNishanth Menon static void __init pm_errata_configure(void) 8978cdfd834SNishanth Menon { 898c4236d2eSPeter 'p2' De Schrijver if (cpu_is_omap3630()) { 899458e999eSNishanth Menon pm34xx_errata |= PM_RTA_ERRATUM_i608; 900c4236d2eSPeter 'p2' De Schrijver /* Enable the l2 cache toggling in sleep logic */ 901c4236d2eSPeter 'p2' De Schrijver enable_omap3630_toggle_l2_on_restore(); 902cc1b6028SEduardo Valentin if (omap_rev() < OMAP3630_REV_ES1_2) 903cc1b6028SEduardo Valentin pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583; 904c4236d2eSPeter 'p2' De Schrijver } 9058cdfd834SNishanth Menon } 9068cdfd834SNishanth Menon 9077cc515f7SKevin Hilman static int __init omap3_pm_init(void) 9088bd22949SKevin Hilman { 9098bd22949SKevin Hilman struct power_state *pwrst, *tmp; 91055ed9694SPaul Walmsley struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm; 9118bd22949SKevin Hilman int ret; 9128bd22949SKevin Hilman 9138bd22949SKevin Hilman if (!cpu_is_omap34xx()) 9148bd22949SKevin Hilman return -ENODEV; 9158bd22949SKevin Hilman 9168cdfd834SNishanth Menon pm_errata_configure(); 9178cdfd834SNishanth Menon 9188bd22949SKevin Hilman printk(KERN_ERR "Power Management for TI OMAP3.\n"); 9198bd22949SKevin Hilman 9208bd22949SKevin Hilman /* XXX prcm_setup_regs needs to be before enabling hw 9218bd22949SKevin Hilman * supervised mode for powerdomains */ 9228bd22949SKevin Hilman prcm_setup_regs(); 9238bd22949SKevin Hilman 9248bd22949SKevin Hilman ret = request_irq(INT_34XX_PRCM_MPU_IRQ, 9258bd22949SKevin Hilman (irq_handler_t)prcm_interrupt_handler, 9268bd22949SKevin Hilman IRQF_DISABLED, "prcm", NULL); 9278bd22949SKevin Hilman if (ret) { 9288bd22949SKevin Hilman printk(KERN_ERR "request_irq failed to register for 0x%x\n", 9298bd22949SKevin Hilman INT_34XX_PRCM_MPU_IRQ); 9308bd22949SKevin Hilman goto err1; 9318bd22949SKevin Hilman } 9328bd22949SKevin Hilman 933a23456e9SPeter 'p2' De Schrijver ret = pwrdm_for_each(pwrdms_setup, NULL); 9348bd22949SKevin Hilman if (ret) { 9358bd22949SKevin Hilman printk(KERN_ERR "Failed to setup powerdomains\n"); 9368bd22949SKevin Hilman goto err2; 9378bd22949SKevin Hilman } 9388bd22949SKevin Hilman 939a23456e9SPeter 'p2' De Schrijver (void) clkdm_for_each(clkdms_setup, NULL); 9408bd22949SKevin Hilman 9418bd22949SKevin Hilman mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); 9428bd22949SKevin Hilman if (mpu_pwrdm == NULL) { 9438bd22949SKevin Hilman printk(KERN_ERR "Failed to get mpu_pwrdm\n"); 9448bd22949SKevin Hilman goto err2; 9458bd22949SKevin Hilman } 9468bd22949SKevin Hilman 947fa3c2a4fSRajendra Nayak neon_pwrdm = pwrdm_lookup("neon_pwrdm"); 948fa3c2a4fSRajendra Nayak per_pwrdm = pwrdm_lookup("per_pwrdm"); 949fa3c2a4fSRajendra Nayak core_pwrdm = pwrdm_lookup("core_pwrdm"); 950c16c3f67STero Kristo cam_pwrdm = pwrdm_lookup("cam_pwrdm"); 951fa3c2a4fSRajendra Nayak 95255ed9694SPaul Walmsley neon_clkdm = clkdm_lookup("neon_clkdm"); 95355ed9694SPaul Walmsley mpu_clkdm = clkdm_lookup("mpu_clkdm"); 95455ed9694SPaul Walmsley per_clkdm = clkdm_lookup("per_clkdm"); 95555ed9694SPaul Walmsley core_clkdm = clkdm_lookup("core_clkdm"); 95655ed9694SPaul Walmsley 9573231fc88SRajendra Nayak omap_push_sram_idle(); 95810f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 9598bd22949SKevin Hilman suspend_set_ops(&omap_pm_ops); 96010f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 9618bd22949SKevin Hilman 9628bd22949SKevin Hilman pm_idle = omap3_pm_idle; 9630343371eSKalle Jokiniemi omap3_idle_init(); 9648bd22949SKevin Hilman 965458e999eSNishanth Menon /* 966458e999eSNishanth Menon * RTA is disabled during initialization as per erratum i608 967458e999eSNishanth Menon * it is safer to disable RTA by the bootloader, but we would like 968458e999eSNishanth Menon * to be doubly sure here and prevent any mishaps. 969458e999eSNishanth Menon */ 970458e999eSNishanth Menon if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608)) 971458e999eSNishanth Menon omap3630_ctrl_disable_rta(); 972458e999eSNishanth Menon 97355ed9694SPaul Walmsley clkdm_add_wkdep(neon_clkdm, mpu_clkdm); 97427d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 97527d59a4aSTero Kristo omap3_secure_ram_storage = 97627d59a4aSTero Kristo kmalloc(0x803F, GFP_KERNEL); 97727d59a4aSTero Kristo if (!omap3_secure_ram_storage) 97827d59a4aSTero Kristo printk(KERN_ERR "Memory allocation failed when" 97927d59a4aSTero Kristo "allocating for secure sram context\n"); 98027d59a4aSTero Kristo 9819d97140bSTero Kristo local_irq_disable(); 9829d97140bSTero Kristo local_fiq_disable(); 9839d97140bSTero Kristo 9849d97140bSTero Kristo omap_dma_global_context_save(); 985617fcc98SKevin Hilman omap3_save_secure_ram_context(); 9869d97140bSTero Kristo omap_dma_global_context_restore(); 9879d97140bSTero Kristo 9889d97140bSTero Kristo local_irq_enable(); 9899d97140bSTero Kristo local_fiq_enable(); 9909d97140bSTero Kristo } 9919d97140bSTero Kristo 9929d97140bSTero Kristo omap3_save_scratchpad_contents(); 9938bd22949SKevin Hilman err1: 9948bd22949SKevin Hilman return ret; 9958bd22949SKevin Hilman err2: 9968bd22949SKevin Hilman free_irq(INT_34XX_PRCM_MPU_IRQ, NULL); 9978bd22949SKevin Hilman list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { 9988bd22949SKevin Hilman list_del(&pwrst->node); 9998bd22949SKevin Hilman kfree(pwrst); 10008bd22949SKevin Hilman } 10018bd22949SKevin Hilman return ret; 10028bd22949SKevin Hilman } 10038bd22949SKevin Hilman 10048bd22949SKevin Hilman late_initcall(omap3_pm_init); 1005