18bd22949SKevin Hilman /* 28bd22949SKevin Hilman * OMAP3 Power Management Routines 38bd22949SKevin Hilman * 48bd22949SKevin Hilman * Copyright (C) 2006-2008 Nokia Corporation 58bd22949SKevin Hilman * Tony Lindgren <tony@atomide.com> 68bd22949SKevin Hilman * Jouni Hogander 78bd22949SKevin Hilman * 88bd22949SKevin Hilman * Copyright (C) 2005 Texas Instruments, Inc. 98bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 108bd22949SKevin Hilman * 118bd22949SKevin Hilman * Based on pm.c for omap1 128bd22949SKevin Hilman * 138bd22949SKevin Hilman * This program is free software; you can redistribute it and/or modify 148bd22949SKevin Hilman * it under the terms of the GNU General Public License version 2 as 158bd22949SKevin Hilman * published by the Free Software Foundation. 168bd22949SKevin Hilman */ 178bd22949SKevin Hilman 188bd22949SKevin Hilman #include <linux/pm.h> 198bd22949SKevin Hilman #include <linux/suspend.h> 208bd22949SKevin Hilman #include <linux/interrupt.h> 218bd22949SKevin Hilman #include <linux/module.h> 228bd22949SKevin Hilman #include <linux/list.h> 238bd22949SKevin Hilman #include <linux/err.h> 248bd22949SKevin Hilman #include <linux/gpio.h> 258bd22949SKevin Hilman 268bd22949SKevin Hilman #include <mach/sram.h> 278bd22949SKevin Hilman #include <mach/clockdomain.h> 288bd22949SKevin Hilman #include <mach/powerdomain.h> 298bd22949SKevin Hilman #include <mach/control.h> 304af4016cSKevin Hilman #include <mach/serial.h> 318bd22949SKevin Hilman 328bd22949SKevin Hilman #include "cm.h" 338bd22949SKevin Hilman #include "cm-regbits-34xx.h" 348bd22949SKevin Hilman #include "prm-regbits-34xx.h" 358bd22949SKevin Hilman 368bd22949SKevin Hilman #include "prm.h" 378bd22949SKevin Hilman #include "pm.h" 388bd22949SKevin Hilman 398bd22949SKevin Hilman struct power_state { 408bd22949SKevin Hilman struct powerdomain *pwrdm; 418bd22949SKevin Hilman u32 next_state; 4210f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 438bd22949SKevin Hilman u32 saved_state; 4410f90ed2SKevin Hilman #endif 458bd22949SKevin Hilman struct list_head node; 468bd22949SKevin Hilman }; 478bd22949SKevin Hilman 488bd22949SKevin Hilman static LIST_HEAD(pwrst_list); 498bd22949SKevin Hilman 508bd22949SKevin Hilman static void (*_omap_sram_idle)(u32 *addr, int save_state); 518bd22949SKevin Hilman 528bd22949SKevin Hilman static struct powerdomain *mpu_pwrdm; 538bd22949SKevin Hilman 5477da2d91SJon Hunter /* 5577da2d91SJon Hunter * PRCM Interrupt Handler Helper Function 5677da2d91SJon Hunter * 5777da2d91SJon Hunter * The purpose of this function is to clear any wake-up events latched 5877da2d91SJon Hunter * in the PRCM PM_WKST_x registers. It is possible that a wake-up event 5977da2d91SJon Hunter * may occur whilst attempting to clear a PM_WKST_x register and thus 6077da2d91SJon Hunter * set another bit in this register. A while loop is used to ensure 6177da2d91SJon Hunter * that any peripheral wake-up events occurring while attempting to 6277da2d91SJon Hunter * clear the PM_WKST_x are detected and cleared. 6377da2d91SJon Hunter */ 6477da2d91SJon Hunter static void prcm_clear_mod_irqs(s16 module, u8 regs) 6577da2d91SJon Hunter { 6677da2d91SJon Hunter u32 wkst, fclk, iclk; 6777da2d91SJon Hunter u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; 6877da2d91SJon Hunter u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; 6977da2d91SJon Hunter u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; 705d805978SPaul Walmsley u16 grpsel_off = (regs == 3) ? 715d805978SPaul Walmsley OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; 7277da2d91SJon Hunter 7377da2d91SJon Hunter wkst = prm_read_mod_reg(module, wkst_off); 745d805978SPaul Walmsley wkst &= prm_read_mod_reg(module, grpsel_off); 7577da2d91SJon Hunter if (wkst) { 7677da2d91SJon Hunter iclk = cm_read_mod_reg(module, iclk_off); 7777da2d91SJon Hunter fclk = cm_read_mod_reg(module, fclk_off); 7877da2d91SJon Hunter while (wkst) { 7977da2d91SJon Hunter cm_set_mod_reg_bits(wkst, module, iclk_off); 8077da2d91SJon Hunter cm_set_mod_reg_bits(wkst, module, fclk_off); 8177da2d91SJon Hunter prm_write_mod_reg(wkst, module, wkst_off); 8277da2d91SJon Hunter wkst = prm_read_mod_reg(module, wkst_off); 8377da2d91SJon Hunter } 8477da2d91SJon Hunter cm_write_mod_reg(iclk, module, iclk_off); 8577da2d91SJon Hunter cm_write_mod_reg(fclk, module, fclk_off); 8677da2d91SJon Hunter } 8777da2d91SJon Hunter } 8877da2d91SJon Hunter 8977da2d91SJon Hunter /* 9077da2d91SJon Hunter * PRCM Interrupt Handler 9177da2d91SJon Hunter * 9277da2d91SJon Hunter * The PRM_IRQSTATUS_MPU register indicates if there are any pending 9377da2d91SJon Hunter * interrupts from the PRCM for the MPU. These bits must be cleared in 9477da2d91SJon Hunter * order to clear the PRCM interrupt. The PRCM interrupt handler is 9577da2d91SJon Hunter * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear 9677da2d91SJon Hunter * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU 9777da2d91SJon Hunter * register indicates that a wake-up event is pending for the MPU and 9877da2d91SJon Hunter * this bit can only be cleared if the all the wake-up events latched 9977da2d91SJon Hunter * in the various PM_WKST_x registers have been cleared. The interrupt 10077da2d91SJon Hunter * handler is implemented using a do-while loop so that if a wake-up 10177da2d91SJon Hunter * event occurred during the processing of the prcm interrupt handler 10277da2d91SJon Hunter * (setting a bit in the corresponding PM_WKST_x register and thus 10377da2d91SJon Hunter * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register) 10477da2d91SJon Hunter * this would be handled. 10577da2d91SJon Hunter */ 1068bd22949SKevin Hilman static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) 1078bd22949SKevin Hilman { 10877da2d91SJon Hunter u32 irqstatus_mpu; 1098bd22949SKevin Hilman 11077da2d91SJon Hunter do { 11177da2d91SJon Hunter prcm_clear_mod_irqs(WKUP_MOD, 1); 11277da2d91SJon Hunter prcm_clear_mod_irqs(CORE_MOD, 1); 11377da2d91SJon Hunter prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1); 1148bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 11577da2d91SJon Hunter prcm_clear_mod_irqs(CORE_MOD, 3); 11677da2d91SJon Hunter prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1); 1178bd22949SKevin Hilman } 1188bd22949SKevin Hilman 1198bd22949SKevin Hilman irqstatus_mpu = prm_read_mod_reg(OCP_MOD, 1208bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 1218bd22949SKevin Hilman prm_write_mod_reg(irqstatus_mpu, OCP_MOD, 1228bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 1238bd22949SKevin Hilman 12477da2d91SJon Hunter } while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET)); 1258bd22949SKevin Hilman 1268bd22949SKevin Hilman return IRQ_HANDLED; 1278bd22949SKevin Hilman } 1288bd22949SKevin Hilman 1298bd22949SKevin Hilman static void omap_sram_idle(void) 1308bd22949SKevin Hilman { 1318bd22949SKevin Hilman /* Variable to tell what needs to be saved and restored 1328bd22949SKevin Hilman * in omap_sram_idle*/ 1338bd22949SKevin Hilman /* save_state = 0 => Nothing to save and restored */ 1348bd22949SKevin Hilman /* save_state = 1 => Only L1 and logic lost */ 1358bd22949SKevin Hilman /* save_state = 2 => Only L2 lost */ 1368bd22949SKevin Hilman /* save_state = 3 => L1, L2 and logic lost */ 1378bd22949SKevin Hilman int save_state = 0, mpu_next_state; 1388bd22949SKevin Hilman 1398bd22949SKevin Hilman if (!_omap_sram_idle) 1408bd22949SKevin Hilman return; 1418bd22949SKevin Hilman 1428bd22949SKevin Hilman mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 1438bd22949SKevin Hilman switch (mpu_next_state) { 1448bd22949SKevin Hilman case PWRDM_POWER_RET: 1458bd22949SKevin Hilman /* No need to save context */ 1468bd22949SKevin Hilman save_state = 0; 1478bd22949SKevin Hilman break; 1488bd22949SKevin Hilman default: 1498bd22949SKevin Hilman /* Invalid state */ 1508bd22949SKevin Hilman printk(KERN_ERR "Invalid mpu state in sram_idle\n"); 1518bd22949SKevin Hilman return; 1528bd22949SKevin Hilman } 153fe617af7SPeter 'p2' De Schrijver pwrdm_pre_transition(); 154fe617af7SPeter 'p2' De Schrijver 1558bd22949SKevin Hilman omap2_gpio_prepare_for_retention(); 1564af4016cSKevin Hilman omap_uart_prepare_idle(0); 1574af4016cSKevin Hilman omap_uart_prepare_idle(1); 1584af4016cSKevin Hilman omap_uart_prepare_idle(2); 1598bd22949SKevin Hilman 1608bd22949SKevin Hilman _omap_sram_idle(NULL, save_state); 1618bd22949SKevin Hilman cpu_init(); 1628bd22949SKevin Hilman 1634af4016cSKevin Hilman omap_uart_resume_idle(2); 1644af4016cSKevin Hilman omap_uart_resume_idle(1); 1654af4016cSKevin Hilman omap_uart_resume_idle(0); 1668bd22949SKevin Hilman omap2_gpio_resume_after_retention(); 167fe617af7SPeter 'p2' De Schrijver 168fe617af7SPeter 'p2' De Schrijver pwrdm_post_transition(); 169fe617af7SPeter 'p2' De Schrijver 1708bd22949SKevin Hilman } 1718bd22949SKevin Hilman 1728bd22949SKevin Hilman /* 1738bd22949SKevin Hilman * Check if functional clocks are enabled before entering 1748bd22949SKevin Hilman * sleep. This function could be behind CONFIG_PM_DEBUG 1758bd22949SKevin Hilman * when all drivers are configuring their sysconfig registers 1768bd22949SKevin Hilman * properly and using their clocks properly. 1778bd22949SKevin Hilman */ 1788bd22949SKevin Hilman static int omap3_fclks_active(void) 1798bd22949SKevin Hilman { 1808bd22949SKevin Hilman u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0, 1818bd22949SKevin Hilman fck_cam = 0, fck_per = 0, fck_usbhost = 0; 1828bd22949SKevin Hilman 1838bd22949SKevin Hilman fck_core1 = cm_read_mod_reg(CORE_MOD, 1848bd22949SKevin Hilman CM_FCLKEN1); 1858bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 1868bd22949SKevin Hilman fck_core3 = cm_read_mod_reg(CORE_MOD, 1878bd22949SKevin Hilman OMAP3430ES2_CM_FCLKEN3); 1888bd22949SKevin Hilman fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD, 1898bd22949SKevin Hilman CM_FCLKEN); 1908bd22949SKevin Hilman fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, 1918bd22949SKevin Hilman CM_FCLKEN); 1928bd22949SKevin Hilman } else 1938bd22949SKevin Hilman fck_sgx = cm_read_mod_reg(GFX_MOD, 1948bd22949SKevin Hilman OMAP3430ES2_CM_FCLKEN3); 1958bd22949SKevin Hilman fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD, 1968bd22949SKevin Hilman CM_FCLKEN); 1978bd22949SKevin Hilman fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD, 1988bd22949SKevin Hilman CM_FCLKEN); 1998bd22949SKevin Hilman fck_per = cm_read_mod_reg(OMAP3430_PER_MOD, 2008bd22949SKevin Hilman CM_FCLKEN); 2014af4016cSKevin Hilman 2024af4016cSKevin Hilman /* Ignore UART clocks. These are handled by UART core (serial.c) */ 2034af4016cSKevin Hilman fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2); 2044af4016cSKevin Hilman fck_per &= ~OMAP3430_EN_UART3; 2054af4016cSKevin Hilman 2068bd22949SKevin Hilman if (fck_core1 | fck_core3 | fck_sgx | fck_dss | 2078bd22949SKevin Hilman fck_cam | fck_per | fck_usbhost) 2088bd22949SKevin Hilman return 1; 2098bd22949SKevin Hilman return 0; 2108bd22949SKevin Hilman } 2118bd22949SKevin Hilman 2128bd22949SKevin Hilman static int omap3_can_sleep(void) 2138bd22949SKevin Hilman { 2144af4016cSKevin Hilman if (!omap_uart_can_sleep()) 2154af4016cSKevin Hilman return 0; 2168bd22949SKevin Hilman if (omap3_fclks_active()) 2178bd22949SKevin Hilman return 0; 2188bd22949SKevin Hilman return 1; 2198bd22949SKevin Hilman } 2208bd22949SKevin Hilman 2218bd22949SKevin Hilman /* This sets pwrdm state (other than mpu & core. Currently only ON & 2228bd22949SKevin Hilman * RET are supported. Function is assuming that clkdm doesn't have 2238bd22949SKevin Hilman * hw_sup mode enabled. */ 2248bd22949SKevin Hilman static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state) 2258bd22949SKevin Hilman { 2268bd22949SKevin Hilman u32 cur_state; 2278bd22949SKevin Hilman int sleep_switch = 0; 2288bd22949SKevin Hilman int ret = 0; 2298bd22949SKevin Hilman 2308bd22949SKevin Hilman if (pwrdm == NULL || IS_ERR(pwrdm)) 2318bd22949SKevin Hilman return -EINVAL; 2328bd22949SKevin Hilman 2338bd22949SKevin Hilman while (!(pwrdm->pwrsts & (1 << state))) { 2348bd22949SKevin Hilman if (state == PWRDM_POWER_OFF) 2358bd22949SKevin Hilman return ret; 2368bd22949SKevin Hilman state--; 2378bd22949SKevin Hilman } 2388bd22949SKevin Hilman 2398bd22949SKevin Hilman cur_state = pwrdm_read_next_pwrst(pwrdm); 2408bd22949SKevin Hilman if (cur_state == state) 2418bd22949SKevin Hilman return ret; 2428bd22949SKevin Hilman 2438bd22949SKevin Hilman if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) { 2448bd22949SKevin Hilman omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); 2458bd22949SKevin Hilman sleep_switch = 1; 2468bd22949SKevin Hilman pwrdm_wait_transition(pwrdm); 2478bd22949SKevin Hilman } 2488bd22949SKevin Hilman 2498bd22949SKevin Hilman ret = pwrdm_set_next_pwrst(pwrdm, state); 2508bd22949SKevin Hilman if (ret) { 2518bd22949SKevin Hilman printk(KERN_ERR "Unable to set state of powerdomain: %s\n", 2528bd22949SKevin Hilman pwrdm->name); 2538bd22949SKevin Hilman goto err; 2548bd22949SKevin Hilman } 2558bd22949SKevin Hilman 2568bd22949SKevin Hilman if (sleep_switch) { 2578bd22949SKevin Hilman omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); 2588bd22949SKevin Hilman pwrdm_wait_transition(pwrdm); 259fe617af7SPeter 'p2' De Schrijver pwrdm_state_switch(pwrdm); 2608bd22949SKevin Hilman } 2618bd22949SKevin Hilman 2628bd22949SKevin Hilman err: 2638bd22949SKevin Hilman return ret; 2648bd22949SKevin Hilman } 2658bd22949SKevin Hilman 2668bd22949SKevin Hilman static void omap3_pm_idle(void) 2678bd22949SKevin Hilman { 2688bd22949SKevin Hilman local_irq_disable(); 2698bd22949SKevin Hilman local_fiq_disable(); 2708bd22949SKevin Hilman 2718bd22949SKevin Hilman if (!omap3_can_sleep()) 2728bd22949SKevin Hilman goto out; 2738bd22949SKevin Hilman 2748bd22949SKevin Hilman if (omap_irq_pending()) 2758bd22949SKevin Hilman goto out; 2768bd22949SKevin Hilman 2778bd22949SKevin Hilman omap_sram_idle(); 2788bd22949SKevin Hilman 2798bd22949SKevin Hilman out: 2808bd22949SKevin Hilman local_fiq_enable(); 2818bd22949SKevin Hilman local_irq_enable(); 2828bd22949SKevin Hilman } 2838bd22949SKevin Hilman 28410f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 2852466211eSTero Kristo static suspend_state_t suspend_state; 2862466211eSTero Kristo 2878bd22949SKevin Hilman static int omap3_pm_prepare(void) 2888bd22949SKevin Hilman { 2898bd22949SKevin Hilman disable_hlt(); 2908bd22949SKevin Hilman return 0; 2918bd22949SKevin Hilman } 2928bd22949SKevin Hilman 2938bd22949SKevin Hilman static int omap3_pm_suspend(void) 2948bd22949SKevin Hilman { 2958bd22949SKevin Hilman struct power_state *pwrst; 2968bd22949SKevin Hilman int state, ret = 0; 2978bd22949SKevin Hilman 2988bd22949SKevin Hilman /* Read current next_pwrsts */ 2998bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) 3008bd22949SKevin Hilman pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 3018bd22949SKevin Hilman /* Set ones wanted by suspend */ 3028bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 3038bd22949SKevin Hilman if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) 3048bd22949SKevin Hilman goto restore; 3058bd22949SKevin Hilman if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) 3068bd22949SKevin Hilman goto restore; 3078bd22949SKevin Hilman } 3088bd22949SKevin Hilman 3094af4016cSKevin Hilman omap_uart_prepare_suspend(); 3108bd22949SKevin Hilman omap_sram_idle(); 3118bd22949SKevin Hilman 3128bd22949SKevin Hilman restore: 3138bd22949SKevin Hilman /* Restore next_pwrsts */ 3148bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 3158bd22949SKevin Hilman state = pwrdm_read_prev_pwrst(pwrst->pwrdm); 3168bd22949SKevin Hilman if (state > pwrst->next_state) { 3178bd22949SKevin Hilman printk(KERN_INFO "Powerdomain (%s) didn't enter " 3188bd22949SKevin Hilman "target state %d\n", 3198bd22949SKevin Hilman pwrst->pwrdm->name, pwrst->next_state); 3208bd22949SKevin Hilman ret = -1; 3218bd22949SKevin Hilman } 3226c5f8039SJouni Hogander set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); 3238bd22949SKevin Hilman } 3248bd22949SKevin Hilman if (ret) 3258bd22949SKevin Hilman printk(KERN_ERR "Could not enter target state in pm_suspend\n"); 3268bd22949SKevin Hilman else 3278bd22949SKevin Hilman printk(KERN_INFO "Successfully put all powerdomains " 3288bd22949SKevin Hilman "to target state\n"); 3298bd22949SKevin Hilman 3308bd22949SKevin Hilman return ret; 3318bd22949SKevin Hilman } 3328bd22949SKevin Hilman 3332466211eSTero Kristo static int omap3_pm_enter(suspend_state_t unused) 3348bd22949SKevin Hilman { 3358bd22949SKevin Hilman int ret = 0; 3368bd22949SKevin Hilman 3372466211eSTero Kristo switch (suspend_state) { 3388bd22949SKevin Hilman case PM_SUSPEND_STANDBY: 3398bd22949SKevin Hilman case PM_SUSPEND_MEM: 3408bd22949SKevin Hilman ret = omap3_pm_suspend(); 3418bd22949SKevin Hilman break; 3428bd22949SKevin Hilman default: 3438bd22949SKevin Hilman ret = -EINVAL; 3448bd22949SKevin Hilman } 3458bd22949SKevin Hilman 3468bd22949SKevin Hilman return ret; 3478bd22949SKevin Hilman } 3488bd22949SKevin Hilman 3498bd22949SKevin Hilman static void omap3_pm_finish(void) 3508bd22949SKevin Hilman { 3518bd22949SKevin Hilman enable_hlt(); 3528bd22949SKevin Hilman } 3538bd22949SKevin Hilman 3542466211eSTero Kristo /* Hooks to enable / disable UART interrupts during suspend */ 3552466211eSTero Kristo static int omap3_pm_begin(suspend_state_t state) 3562466211eSTero Kristo { 3572466211eSTero Kristo suspend_state = state; 3582466211eSTero Kristo omap_uart_enable_irqs(0); 3592466211eSTero Kristo return 0; 3602466211eSTero Kristo } 3612466211eSTero Kristo 3622466211eSTero Kristo static void omap3_pm_end(void) 3632466211eSTero Kristo { 3642466211eSTero Kristo suspend_state = PM_SUSPEND_ON; 3652466211eSTero Kristo omap_uart_enable_irqs(1); 3662466211eSTero Kristo return; 3672466211eSTero Kristo } 3682466211eSTero Kristo 3698bd22949SKevin Hilman static struct platform_suspend_ops omap_pm_ops = { 3702466211eSTero Kristo .begin = omap3_pm_begin, 3712466211eSTero Kristo .end = omap3_pm_end, 3728bd22949SKevin Hilman .prepare = omap3_pm_prepare, 3738bd22949SKevin Hilman .enter = omap3_pm_enter, 3748bd22949SKevin Hilman .finish = omap3_pm_finish, 3758bd22949SKevin Hilman .valid = suspend_valid_only_mem, 3768bd22949SKevin Hilman }; 37710f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 3788bd22949SKevin Hilman 3791155e426SKevin Hilman 3801155e426SKevin Hilman /** 3811155e426SKevin Hilman * omap3_iva_idle(): ensure IVA is in idle so it can be put into 3821155e426SKevin Hilman * retention 3831155e426SKevin Hilman * 3841155e426SKevin Hilman * In cases where IVA2 is activated by bootcode, it may prevent 3851155e426SKevin Hilman * full-chip retention or off-mode because it is not idle. This 3861155e426SKevin Hilman * function forces the IVA2 into idle state so it can go 3871155e426SKevin Hilman * into retention/off and thus allow full-chip retention/off. 3881155e426SKevin Hilman * 3891155e426SKevin Hilman **/ 3901155e426SKevin Hilman static void __init omap3_iva_idle(void) 3911155e426SKevin Hilman { 3921155e426SKevin Hilman /* ensure IVA2 clock is disabled */ 3931155e426SKevin Hilman cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 3941155e426SKevin Hilman 3951155e426SKevin Hilman /* if no clock activity, nothing else to do */ 3961155e426SKevin Hilman if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & 3971155e426SKevin Hilman OMAP3430_CLKACTIVITY_IVA2_MASK)) 3981155e426SKevin Hilman return; 3991155e426SKevin Hilman 4001155e426SKevin Hilman /* Reset IVA2 */ 4011155e426SKevin Hilman prm_write_mod_reg(OMAP3430_RST1_IVA2 | 4021155e426SKevin Hilman OMAP3430_RST2_IVA2 | 4031155e426SKevin Hilman OMAP3430_RST3_IVA2, 4041155e426SKevin Hilman OMAP3430_IVA2_MOD, RM_RSTCTRL); 4051155e426SKevin Hilman 4061155e426SKevin Hilman /* Enable IVA2 clock */ 4071155e426SKevin Hilman cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2, 4081155e426SKevin Hilman OMAP3430_IVA2_MOD, CM_FCLKEN); 4091155e426SKevin Hilman 4101155e426SKevin Hilman /* Set IVA2 boot mode to 'idle' */ 4111155e426SKevin Hilman omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, 4121155e426SKevin Hilman OMAP343X_CONTROL_IVA2_BOOTMOD); 4131155e426SKevin Hilman 4141155e426SKevin Hilman /* Un-reset IVA2 */ 4151155e426SKevin Hilman prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL); 4161155e426SKevin Hilman 4171155e426SKevin Hilman /* Disable IVA2 clock */ 4181155e426SKevin Hilman cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 4191155e426SKevin Hilman 4201155e426SKevin Hilman /* Reset IVA2 */ 4211155e426SKevin Hilman prm_write_mod_reg(OMAP3430_RST1_IVA2 | 4221155e426SKevin Hilman OMAP3430_RST2_IVA2 | 4231155e426SKevin Hilman OMAP3430_RST3_IVA2, 4241155e426SKevin Hilman OMAP3430_IVA2_MOD, RM_RSTCTRL); 4251155e426SKevin Hilman } 4261155e426SKevin Hilman 4278111b221SKevin Hilman static void __init omap3_d2d_idle(void) 4288bd22949SKevin Hilman { 4298111b221SKevin Hilman u16 mask, padconf; 4308111b221SKevin Hilman 4318111b221SKevin Hilman /* In a stand alone OMAP3430 where there is not a stacked 4328111b221SKevin Hilman * modem for the D2D Idle Ack and D2D MStandby must be pulled 4338111b221SKevin Hilman * high. S CONTROL_PADCONF_SAD2D_IDLEACK and 4348111b221SKevin Hilman * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ 4358111b221SKevin Hilman mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ 4368111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); 4378111b221SKevin Hilman padconf |= mask; 4388111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); 4398111b221SKevin Hilman 4408111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); 4418111b221SKevin Hilman padconf |= mask; 4428111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 4438111b221SKevin Hilman 4448bd22949SKevin Hilman /* reset modem */ 4458bd22949SKevin Hilman prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON | 4468bd22949SKevin Hilman OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST, 4478bd22949SKevin Hilman CORE_MOD, RM_RSTCTRL); 4488bd22949SKevin Hilman prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL); 4498111b221SKevin Hilman } 4508bd22949SKevin Hilman 4518111b221SKevin Hilman static void __init prcm_setup_regs(void) 4528111b221SKevin Hilman { 4538bd22949SKevin Hilman /* XXX Reset all wkdeps. This should be done when initializing 4548bd22949SKevin Hilman * powerdomains */ 4558bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); 4568bd22949SKevin Hilman prm_write_mod_reg(0, MPU_MOD, PM_WKDEP); 4578bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP); 4588bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP); 4598bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP); 4608bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP); 4618bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 4628bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP); 4638bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP); 4648bd22949SKevin Hilman } else 4658bd22949SKevin Hilman prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); 4668bd22949SKevin Hilman 4678bd22949SKevin Hilman /* 4688bd22949SKevin Hilman * Enable interface clock autoidle for all modules. 4698bd22949SKevin Hilman * Note that in the long run this should be done by clockfw 4708bd22949SKevin Hilman */ 4718bd22949SKevin Hilman cm_write_mod_reg( 4728111b221SKevin Hilman OMAP3430_AUTO_MODEM | 4738bd22949SKevin Hilman OMAP3430ES2_AUTO_MMC3 | 4748bd22949SKevin Hilman OMAP3430ES2_AUTO_ICR | 4758bd22949SKevin Hilman OMAP3430_AUTO_AES2 | 4768bd22949SKevin Hilman OMAP3430_AUTO_SHA12 | 4778bd22949SKevin Hilman OMAP3430_AUTO_DES2 | 4788bd22949SKevin Hilman OMAP3430_AUTO_MMC2 | 4798bd22949SKevin Hilman OMAP3430_AUTO_MMC1 | 4808bd22949SKevin Hilman OMAP3430_AUTO_MSPRO | 4818bd22949SKevin Hilman OMAP3430_AUTO_HDQ | 4828bd22949SKevin Hilman OMAP3430_AUTO_MCSPI4 | 4838bd22949SKevin Hilman OMAP3430_AUTO_MCSPI3 | 4848bd22949SKevin Hilman OMAP3430_AUTO_MCSPI2 | 4858bd22949SKevin Hilman OMAP3430_AUTO_MCSPI1 | 4868bd22949SKevin Hilman OMAP3430_AUTO_I2C3 | 4878bd22949SKevin Hilman OMAP3430_AUTO_I2C2 | 4888bd22949SKevin Hilman OMAP3430_AUTO_I2C1 | 4898bd22949SKevin Hilman OMAP3430_AUTO_UART2 | 4908bd22949SKevin Hilman OMAP3430_AUTO_UART1 | 4918bd22949SKevin Hilman OMAP3430_AUTO_GPT11 | 4928bd22949SKevin Hilman OMAP3430_AUTO_GPT10 | 4938bd22949SKevin Hilman OMAP3430_AUTO_MCBSP5 | 4948bd22949SKevin Hilman OMAP3430_AUTO_MCBSP1 | 4958bd22949SKevin Hilman OMAP3430ES1_AUTO_FAC | /* This is es1 only */ 4968bd22949SKevin Hilman OMAP3430_AUTO_MAILBOXES | 4978bd22949SKevin Hilman OMAP3430_AUTO_OMAPCTRL | 4988bd22949SKevin Hilman OMAP3430ES1_AUTO_FSHOSTUSB | 4998bd22949SKevin Hilman OMAP3430_AUTO_HSOTGUSB | 5008111b221SKevin Hilman OMAP3430_AUTO_SAD2D | 5018bd22949SKevin Hilman OMAP3430_AUTO_SSI, 5028bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE1); 5038bd22949SKevin Hilman 5048bd22949SKevin Hilman cm_write_mod_reg( 5058bd22949SKevin Hilman OMAP3430_AUTO_PKA | 5068bd22949SKevin Hilman OMAP3430_AUTO_AES1 | 5078bd22949SKevin Hilman OMAP3430_AUTO_RNG | 5088bd22949SKevin Hilman OMAP3430_AUTO_SHA11 | 5098bd22949SKevin Hilman OMAP3430_AUTO_DES1, 5108bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE2); 5118bd22949SKevin Hilman 5128bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 5138bd22949SKevin Hilman cm_write_mod_reg( 5148111b221SKevin Hilman OMAP3430_AUTO_MAD2D | 5158bd22949SKevin Hilman OMAP3430ES2_AUTO_USBTLL, 5168bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE3); 5178bd22949SKevin Hilman } 5188bd22949SKevin Hilman 5198bd22949SKevin Hilman cm_write_mod_reg( 5208bd22949SKevin Hilman OMAP3430_AUTO_WDT2 | 5218bd22949SKevin Hilman OMAP3430_AUTO_WDT1 | 5228bd22949SKevin Hilman OMAP3430_AUTO_GPIO1 | 5238bd22949SKevin Hilman OMAP3430_AUTO_32KSYNC | 5248bd22949SKevin Hilman OMAP3430_AUTO_GPT12 | 5258bd22949SKevin Hilman OMAP3430_AUTO_GPT1 , 5268bd22949SKevin Hilman WKUP_MOD, CM_AUTOIDLE); 5278bd22949SKevin Hilman 5288bd22949SKevin Hilman cm_write_mod_reg( 5298bd22949SKevin Hilman OMAP3430_AUTO_DSS, 5308bd22949SKevin Hilman OMAP3430_DSS_MOD, 5318bd22949SKevin Hilman CM_AUTOIDLE); 5328bd22949SKevin Hilman 5338bd22949SKevin Hilman cm_write_mod_reg( 5348bd22949SKevin Hilman OMAP3430_AUTO_CAM, 5358bd22949SKevin Hilman OMAP3430_CAM_MOD, 5368bd22949SKevin Hilman CM_AUTOIDLE); 5378bd22949SKevin Hilman 5388bd22949SKevin Hilman cm_write_mod_reg( 5398bd22949SKevin Hilman OMAP3430_AUTO_GPIO6 | 5408bd22949SKevin Hilman OMAP3430_AUTO_GPIO5 | 5418bd22949SKevin Hilman OMAP3430_AUTO_GPIO4 | 5428bd22949SKevin Hilman OMAP3430_AUTO_GPIO3 | 5438bd22949SKevin Hilman OMAP3430_AUTO_GPIO2 | 5448bd22949SKevin Hilman OMAP3430_AUTO_WDT3 | 5458bd22949SKevin Hilman OMAP3430_AUTO_UART3 | 5468bd22949SKevin Hilman OMAP3430_AUTO_GPT9 | 5478bd22949SKevin Hilman OMAP3430_AUTO_GPT8 | 5488bd22949SKevin Hilman OMAP3430_AUTO_GPT7 | 5498bd22949SKevin Hilman OMAP3430_AUTO_GPT6 | 5508bd22949SKevin Hilman OMAP3430_AUTO_GPT5 | 5518bd22949SKevin Hilman OMAP3430_AUTO_GPT4 | 5528bd22949SKevin Hilman OMAP3430_AUTO_GPT3 | 5538bd22949SKevin Hilman OMAP3430_AUTO_GPT2 | 5548bd22949SKevin Hilman OMAP3430_AUTO_MCBSP4 | 5558bd22949SKevin Hilman OMAP3430_AUTO_MCBSP3 | 5568bd22949SKevin Hilman OMAP3430_AUTO_MCBSP2, 5578bd22949SKevin Hilman OMAP3430_PER_MOD, 5588bd22949SKevin Hilman CM_AUTOIDLE); 5598bd22949SKevin Hilman 5608bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 5618bd22949SKevin Hilman cm_write_mod_reg( 5628bd22949SKevin Hilman OMAP3430ES2_AUTO_USBHOST, 5638bd22949SKevin Hilman OMAP3430ES2_USBHOST_MOD, 5648bd22949SKevin Hilman CM_AUTOIDLE); 5658bd22949SKevin Hilman } 5668bd22949SKevin Hilman 5678bd22949SKevin Hilman /* 5688bd22949SKevin Hilman * Set all plls to autoidle. This is needed until autoidle is 5698bd22949SKevin Hilman * enabled by clockfw 5708bd22949SKevin Hilman */ 5718bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, 5728bd22949SKevin Hilman OMAP3430_IVA2_MOD, CM_AUTOIDLE2); 5738bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT, 5748bd22949SKevin Hilman MPU_MOD, 5758bd22949SKevin Hilman CM_AUTOIDLE2); 5768bd22949SKevin Hilman cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | 5778bd22949SKevin Hilman (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT), 5788bd22949SKevin Hilman PLL_MOD, 5798bd22949SKevin Hilman CM_AUTOIDLE); 5808bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, 5818bd22949SKevin Hilman PLL_MOD, 5828bd22949SKevin Hilman CM_AUTOIDLE2); 5838bd22949SKevin Hilman 5848bd22949SKevin Hilman /* 5858bd22949SKevin Hilman * Enable control of expternal oscillator through 5868bd22949SKevin Hilman * sys_clkreq. In the long run clock framework should 5878bd22949SKevin Hilman * take care of this. 5888bd22949SKevin Hilman */ 5898bd22949SKevin Hilman prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 5908bd22949SKevin Hilman 1 << OMAP_AUTOEXTCLKMODE_SHIFT, 5918bd22949SKevin Hilman OMAP3430_GR_MOD, 5928bd22949SKevin Hilman OMAP3_PRM_CLKSRC_CTRL_OFFSET); 5938bd22949SKevin Hilman 5948bd22949SKevin Hilman /* setup wakup source */ 5958bd22949SKevin Hilman prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 | 5968bd22949SKevin Hilman OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12, 5978bd22949SKevin Hilman WKUP_MOD, PM_WKEN); 5988bd22949SKevin Hilman /* No need to write EN_IO, that is always enabled */ 5998bd22949SKevin Hilman prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 | 6008bd22949SKevin Hilman OMAP3430_EN_GPT12, 6018bd22949SKevin Hilman WKUP_MOD, OMAP3430_PM_MPUGRPSEL); 6028bd22949SKevin Hilman /* For some reason IO doesn't generate wakeup event even if 6038bd22949SKevin Hilman * it is selected to mpu wakeup goup */ 6048bd22949SKevin Hilman prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN, 6058bd22949SKevin Hilman OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); 6061155e426SKevin Hilman 607d3fd3290SKevin Hilman /* Don't attach IVA interrupts */ 608d3fd3290SKevin Hilman prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 609d3fd3290SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 610d3fd3290SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 611d3fd3290SKevin Hilman prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); 612d3fd3290SKevin Hilman 613b1340d17SKevin Hilman /* Clear any pending 'reset' flags */ 614b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST); 615b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST); 616b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST); 617b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST); 618b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST); 619b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST); 620b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST); 621b1340d17SKevin Hilman 622014c46dbSKevin Hilman /* Clear any pending PRCM interrupts */ 623014c46dbSKevin Hilman prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 624014c46dbSKevin Hilman 625040fed05SKevin Hilman /* Don't attach IVA interrupts */ 626040fed05SKevin Hilman prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 627040fed05SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 628040fed05SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 629040fed05SKevin Hilman prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); 630040fed05SKevin Hilman 6313a07ae30SKevin Hilman /* Clear any pending 'reset' flags */ 6323a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST); 6333a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST); 6343a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST); 6353a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST); 6363a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST); 6373a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST); 6383a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST); 6393a07ae30SKevin Hilman 6403a6667acSKevin Hilman /* Clear any pending PRCM interrupts */ 6413a6667acSKevin Hilman prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 6423a6667acSKevin Hilman 6431155e426SKevin Hilman omap3_iva_idle(); 6448111b221SKevin Hilman omap3_d2d_idle(); 6458bd22949SKevin Hilman } 6468bd22949SKevin Hilman 64768d4778cSTero Kristo int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) 64868d4778cSTero Kristo { 64968d4778cSTero Kristo struct power_state *pwrst; 65068d4778cSTero Kristo 65168d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 65268d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) 65368d4778cSTero Kristo return pwrst->next_state; 65468d4778cSTero Kristo } 65568d4778cSTero Kristo return -EINVAL; 65668d4778cSTero Kristo } 65768d4778cSTero Kristo 65868d4778cSTero Kristo int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) 65968d4778cSTero Kristo { 66068d4778cSTero Kristo struct power_state *pwrst; 66168d4778cSTero Kristo 66268d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 66368d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) { 66468d4778cSTero Kristo pwrst->next_state = state; 66568d4778cSTero Kristo return 0; 66668d4778cSTero Kristo } 66768d4778cSTero Kristo } 66868d4778cSTero Kristo return -EINVAL; 66968d4778cSTero Kristo } 67068d4778cSTero Kristo 671a23456e9SPeter 'p2' De Schrijver static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) 6728bd22949SKevin Hilman { 6738bd22949SKevin Hilman struct power_state *pwrst; 6748bd22949SKevin Hilman 6758bd22949SKevin Hilman if (!pwrdm->pwrsts) 6768bd22949SKevin Hilman return 0; 6778bd22949SKevin Hilman 678d3d381c6SMing Lei pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); 6798bd22949SKevin Hilman if (!pwrst) 6808bd22949SKevin Hilman return -ENOMEM; 6818bd22949SKevin Hilman pwrst->pwrdm = pwrdm; 6828bd22949SKevin Hilman pwrst->next_state = PWRDM_POWER_RET; 6838bd22949SKevin Hilman list_add(&pwrst->node, &pwrst_list); 6848bd22949SKevin Hilman 6858bd22949SKevin Hilman if (pwrdm_has_hdwr_sar(pwrdm)) 6868bd22949SKevin Hilman pwrdm_enable_hdwr_sar(pwrdm); 6878bd22949SKevin Hilman 6888bd22949SKevin Hilman return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 6898bd22949SKevin Hilman } 6908bd22949SKevin Hilman 6918bd22949SKevin Hilman /* 6928bd22949SKevin Hilman * Enable hw supervised mode for all clockdomains if it's 6938bd22949SKevin Hilman * supported. Initiate sleep transition for other clockdomains, if 6948bd22949SKevin Hilman * they are not used 6958bd22949SKevin Hilman */ 696a23456e9SPeter 'p2' De Schrijver static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) 6978bd22949SKevin Hilman { 6988bd22949SKevin Hilman if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) 6998bd22949SKevin Hilman omap2_clkdm_allow_idle(clkdm); 7008bd22949SKevin Hilman else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && 7018bd22949SKevin Hilman atomic_read(&clkdm->usecount) == 0) 7028bd22949SKevin Hilman omap2_clkdm_sleep(clkdm); 7038bd22949SKevin Hilman return 0; 7048bd22949SKevin Hilman } 7058bd22949SKevin Hilman 7067cc515f7SKevin Hilman static int __init omap3_pm_init(void) 7078bd22949SKevin Hilman { 7088bd22949SKevin Hilman struct power_state *pwrst, *tmp; 7098bd22949SKevin Hilman int ret; 7108bd22949SKevin Hilman 7118bd22949SKevin Hilman if (!cpu_is_omap34xx()) 7128bd22949SKevin Hilman return -ENODEV; 7138bd22949SKevin Hilman 7148bd22949SKevin Hilman printk(KERN_ERR "Power Management for TI OMAP3.\n"); 7158bd22949SKevin Hilman 7168bd22949SKevin Hilman /* XXX prcm_setup_regs needs to be before enabling hw 7178bd22949SKevin Hilman * supervised mode for powerdomains */ 7188bd22949SKevin Hilman prcm_setup_regs(); 7198bd22949SKevin Hilman 7208bd22949SKevin Hilman ret = request_irq(INT_34XX_PRCM_MPU_IRQ, 7218bd22949SKevin Hilman (irq_handler_t)prcm_interrupt_handler, 7228bd22949SKevin Hilman IRQF_DISABLED, "prcm", NULL); 7238bd22949SKevin Hilman if (ret) { 7248bd22949SKevin Hilman printk(KERN_ERR "request_irq failed to register for 0x%x\n", 7258bd22949SKevin Hilman INT_34XX_PRCM_MPU_IRQ); 7268bd22949SKevin Hilman goto err1; 7278bd22949SKevin Hilman } 7288bd22949SKevin Hilman 729a23456e9SPeter 'p2' De Schrijver ret = pwrdm_for_each(pwrdms_setup, NULL); 7308bd22949SKevin Hilman if (ret) { 7318bd22949SKevin Hilman printk(KERN_ERR "Failed to setup powerdomains\n"); 7328bd22949SKevin Hilman goto err2; 7338bd22949SKevin Hilman } 7348bd22949SKevin Hilman 735a23456e9SPeter 'p2' De Schrijver (void) clkdm_for_each(clkdms_setup, NULL); 7368bd22949SKevin Hilman 7378bd22949SKevin Hilman mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); 7388bd22949SKevin Hilman if (mpu_pwrdm == NULL) { 7398bd22949SKevin Hilman printk(KERN_ERR "Failed to get mpu_pwrdm\n"); 7408bd22949SKevin Hilman goto err2; 7418bd22949SKevin Hilman } 7428bd22949SKevin Hilman 7438bd22949SKevin Hilman _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend, 7448bd22949SKevin Hilman omap34xx_cpu_suspend_sz); 7458bd22949SKevin Hilman 74610f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 7478bd22949SKevin Hilman suspend_set_ops(&omap_pm_ops); 74810f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 7498bd22949SKevin Hilman 7508bd22949SKevin Hilman pm_idle = omap3_pm_idle; 7518bd22949SKevin Hilman 7528bd22949SKevin Hilman err1: 7538bd22949SKevin Hilman return ret; 7548bd22949SKevin Hilman err2: 7558bd22949SKevin Hilman free_irq(INT_34XX_PRCM_MPU_IRQ, NULL); 7568bd22949SKevin Hilman list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { 7578bd22949SKevin Hilman list_del(&pwrst->node); 7588bd22949SKevin Hilman kfree(pwrst); 7598bd22949SKevin Hilman } 7608bd22949SKevin Hilman return ret; 7618bd22949SKevin Hilman } 7628bd22949SKevin Hilman 7638bd22949SKevin Hilman late_initcall(omap3_pm_init); 764