18bd22949SKevin Hilman /* 28bd22949SKevin Hilman * OMAP3 Power Management Routines 38bd22949SKevin Hilman * 48bd22949SKevin Hilman * Copyright (C) 2006-2008 Nokia Corporation 58bd22949SKevin Hilman * Tony Lindgren <tony@atomide.com> 68bd22949SKevin Hilman * Jouni Hogander 78bd22949SKevin Hilman * 82f5939c3SRajendra Nayak * Copyright (C) 2007 Texas Instruments, Inc. 92f5939c3SRajendra Nayak * Rajendra Nayak <rnayak@ti.com> 102f5939c3SRajendra Nayak * 118bd22949SKevin Hilman * Copyright (C) 2005 Texas Instruments, Inc. 128bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 138bd22949SKevin Hilman * 148bd22949SKevin Hilman * Based on pm.c for omap1 158bd22949SKevin Hilman * 168bd22949SKevin Hilman * This program is free software; you can redistribute it and/or modify 178bd22949SKevin Hilman * it under the terms of the GNU General Public License version 2 as 188bd22949SKevin Hilman * published by the Free Software Foundation. 198bd22949SKevin Hilman */ 208bd22949SKevin Hilman 218bd22949SKevin Hilman #include <linux/pm.h> 228bd22949SKevin Hilman #include <linux/suspend.h> 238bd22949SKevin Hilman #include <linux/interrupt.h> 248bd22949SKevin Hilman #include <linux/module.h> 258bd22949SKevin Hilman #include <linux/list.h> 268bd22949SKevin Hilman #include <linux/err.h> 278bd22949SKevin Hilman #include <linux/gpio.h> 28c40552bcSKevin Hilman #include <linux/clk.h> 29dccaad89STero Kristo #include <linux/delay.h> 305a0e3ad6STejun Heo #include <linux/slab.h> 310d8e2d0dSPaul Walmsley #include <linux/console.h> 325e7c58dcSJean Pihet #include <trace/events/power.h> 338bd22949SKevin Hilman 342c74a0ceSRussell King #include <asm/suspend.h> 352c74a0ceSRussell King 36ce491cf8STony Lindgren #include <plat/sram.h> 371540f214SPaul Walmsley #include "clockdomain.h" 3872e06d08SPaul Walmsley #include "powerdomain.h" 39ce491cf8STony Lindgren #include <plat/serial.h> 4061255ab9SRajendra Nayak #include <plat/sdrc.h> 412f5939c3SRajendra Nayak #include <plat/prcm.h> 422f5939c3SRajendra Nayak #include <plat/gpmc.h> 43f2d11858STero Kristo #include <plat/dma.h> 448bd22949SKevin Hilman 454e65331cSTony Lindgren #include "common.h" 4659fb659bSPaul Walmsley #include "cm2xxx_3xxx.h" 478bd22949SKevin Hilman #include "cm-regbits-34xx.h" 488bd22949SKevin Hilman #include "prm-regbits-34xx.h" 498bd22949SKevin Hilman 5059fb659bSPaul Walmsley #include "prm2xxx_3xxx.h" 518bd22949SKevin Hilman #include "pm.h" 5213a6fe0fSTero Kristo #include "sdrc.h" 534814ced5SPaul Walmsley #include "control.h" 5413a6fe0fSTero Kristo 55e83df17fSKevin Hilman #ifdef CONFIG_SUSPEND 56e83df17fSKevin Hilman static suspend_state_t suspend_state = PM_SUSPEND_ON; 57e83df17fSKevin Hilman static inline bool is_suspending(void) 58e83df17fSKevin Hilman { 59dca2d0ebSKevin Hilman return (suspend_state != PM_SUSPEND_ON) && console_suspend_enabled; 60e83df17fSKevin Hilman } 61e83df17fSKevin Hilman #else 62e83df17fSKevin Hilman static inline bool is_suspending(void) 63e83df17fSKevin Hilman { 64e83df17fSKevin Hilman return false; 65e83df17fSKevin Hilman } 66e83df17fSKevin Hilman #endif 67e83df17fSKevin Hilman 688cdfd834SNishanth Menon /* pm34xx errata defined in pm.h */ 698cdfd834SNishanth Menon u16 pm34xx_errata; 708cdfd834SNishanth Menon 718bd22949SKevin Hilman struct power_state { 728bd22949SKevin Hilman struct powerdomain *pwrdm; 738bd22949SKevin Hilman u32 next_state; 7410f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 758bd22949SKevin Hilman u32 saved_state; 7610f90ed2SKevin Hilman #endif 778bd22949SKevin Hilman struct list_head node; 788bd22949SKevin Hilman }; 798bd22949SKevin Hilman 808bd22949SKevin Hilman static LIST_HEAD(pwrst_list); 818bd22949SKevin Hilman 8227d59a4aSTero Kristo static int (*_omap_save_secure_sram)(u32 *addr); 8346e130d2SJean Pihet void (*omap3_do_wfi_sram)(void); 8427d59a4aSTero Kristo 85fa3c2a4fSRajendra Nayak static struct powerdomain *mpu_pwrdm, *neon_pwrdm; 86fa3c2a4fSRajendra Nayak static struct powerdomain *core_pwrdm, *per_pwrdm; 87c16c3f67STero Kristo static struct powerdomain *cam_pwrdm; 88fa3c2a4fSRajendra Nayak 892f5939c3SRajendra Nayak static inline void omap3_per_save_context(void) 902f5939c3SRajendra Nayak { 912f5939c3SRajendra Nayak omap_gpio_save_context(); 922f5939c3SRajendra Nayak } 932f5939c3SRajendra Nayak 942f5939c3SRajendra Nayak static inline void omap3_per_restore_context(void) 952f5939c3SRajendra Nayak { 962f5939c3SRajendra Nayak omap_gpio_restore_context(); 972f5939c3SRajendra Nayak } 982f5939c3SRajendra Nayak 993a7ec26bSKalle Jokiniemi static void omap3_enable_io_chain(void) 1003a7ec26bSKalle Jokiniemi { 1013a7ec26bSKalle Jokiniemi int timeout = 0; 1023a7ec26bSKalle Jokiniemi 103c4d7e58fSPaul Walmsley omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, 1042bc4ef71SPaul Walmsley PM_WKEN); 1053a7ec26bSKalle Jokiniemi /* Do a readback to assure write has been done */ 106c4d7e58fSPaul Walmsley omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN); 1073a7ec26bSKalle Jokiniemi 108c4d7e58fSPaul Walmsley while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) & 1092bc4ef71SPaul Walmsley OMAP3430_ST_IO_CHAIN_MASK)) { 1103a7ec26bSKalle Jokiniemi timeout++; 1113a7ec26bSKalle Jokiniemi if (timeout > 1000) { 112b02b9172SPaul Walmsley pr_err("Wake up daisy chain activation failed.\n"); 1133a7ec26bSKalle Jokiniemi return; 1143a7ec26bSKalle Jokiniemi } 115c4d7e58fSPaul Walmsley omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, 1160b96a3a3SKevin Hilman WKUP_MOD, PM_WKEN); 1173a7ec26bSKalle Jokiniemi } 1183a7ec26bSKalle Jokiniemi } 1193a7ec26bSKalle Jokiniemi 1203a7ec26bSKalle Jokiniemi static void omap3_disable_io_chain(void) 1213a7ec26bSKalle Jokiniemi { 122c4d7e58fSPaul Walmsley omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, 1232bc4ef71SPaul Walmsley PM_WKEN); 1243a7ec26bSKalle Jokiniemi } 1253a7ec26bSKalle Jokiniemi 1262f5939c3SRajendra Nayak static void omap3_core_save_context(void) 1272f5939c3SRajendra Nayak { 128596efe47SPaul Walmsley omap3_ctrl_save_padconf(); 129dccaad89STero Kristo 130dccaad89STero Kristo /* 131dccaad89STero Kristo * Force write last pad into memory, as this can fail in some 13283521291SJean Pihet * cases according to errata 1.157, 1.185 133dccaad89STero Kristo */ 134dccaad89STero Kristo omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), 135dccaad89STero Kristo OMAP343X_CONTROL_MEM_WKUP + 0x2a0); 136dccaad89STero Kristo 1372f5939c3SRajendra Nayak /* Save the Interrupt controller context */ 1382f5939c3SRajendra Nayak omap_intc_save_context(); 1392f5939c3SRajendra Nayak /* Save the GPMC context */ 1402f5939c3SRajendra Nayak omap3_gpmc_save_context(); 1412f5939c3SRajendra Nayak /* Save the system control module context, padconf already save above*/ 1422f5939c3SRajendra Nayak omap3_control_save_context(); 143f2d11858STero Kristo omap_dma_global_context_save(); 1442f5939c3SRajendra Nayak } 1452f5939c3SRajendra Nayak 1462f5939c3SRajendra Nayak static void omap3_core_restore_context(void) 1472f5939c3SRajendra Nayak { 1482f5939c3SRajendra Nayak /* Restore the control module context, padconf restored by h/w */ 1492f5939c3SRajendra Nayak omap3_control_restore_context(); 1502f5939c3SRajendra Nayak /* Restore the GPMC context */ 1512f5939c3SRajendra Nayak omap3_gpmc_restore_context(); 1522f5939c3SRajendra Nayak /* Restore the interrupt controller context */ 1532f5939c3SRajendra Nayak omap_intc_restore_context(); 154f2d11858STero Kristo omap_dma_global_context_restore(); 1552f5939c3SRajendra Nayak } 1562f5939c3SRajendra Nayak 1579d97140bSTero Kristo /* 1589d97140bSTero Kristo * FIXME: This function should be called before entering off-mode after 1599d97140bSTero Kristo * OMAP3 secure services have been accessed. Currently it is only called 1609d97140bSTero Kristo * once during boot sequence, but this works as we are not using secure 1619d97140bSTero Kristo * services. 1629d97140bSTero Kristo */ 163617fcc98SKevin Hilman static void omap3_save_secure_ram_context(void) 16427d59a4aSTero Kristo { 16527d59a4aSTero Kristo u32 ret; 166617fcc98SKevin Hilman int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 16727d59a4aSTero Kristo 16827d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 16927d59a4aSTero Kristo /* 17027d59a4aSTero Kristo * MPU next state must be set to POWER_ON temporarily, 17127d59a4aSTero Kristo * otherwise the WFI executed inside the ROM code 17227d59a4aSTero Kristo * will hang the system. 17327d59a4aSTero Kristo */ 17427d59a4aSTero Kristo pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); 17527d59a4aSTero Kristo ret = _omap_save_secure_sram((u32 *) 17627d59a4aSTero Kristo __pa(omap3_secure_ram_storage)); 177617fcc98SKevin Hilman pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state); 17827d59a4aSTero Kristo /* Following is for error tracking, it should not happen */ 17927d59a4aSTero Kristo if (ret) { 18027d59a4aSTero Kristo printk(KERN_ERR "save_secure_sram() returns %08x\n", 18127d59a4aSTero Kristo ret); 18227d59a4aSTero Kristo while (1) 18327d59a4aSTero Kristo ; 18427d59a4aSTero Kristo } 18527d59a4aSTero Kristo } 18627d59a4aSTero Kristo } 18727d59a4aSTero Kristo 18877da2d91SJon Hunter /* 18977da2d91SJon Hunter * PRCM Interrupt Handler Helper Function 19077da2d91SJon Hunter * 19177da2d91SJon Hunter * The purpose of this function is to clear any wake-up events latched 19277da2d91SJon Hunter * in the PRCM PM_WKST_x registers. It is possible that a wake-up event 19377da2d91SJon Hunter * may occur whilst attempting to clear a PM_WKST_x register and thus 19477da2d91SJon Hunter * set another bit in this register. A while loop is used to ensure 19577da2d91SJon Hunter * that any peripheral wake-up events occurring while attempting to 19677da2d91SJon Hunter * clear the PM_WKST_x are detected and cleared. 19777da2d91SJon Hunter */ 1988cb0ac99SPaul Walmsley static int prcm_clear_mod_irqs(s16 module, u8 regs) 19977da2d91SJon Hunter { 20071a80775SVikram Pandita u32 wkst, fclk, iclk, clken; 20177da2d91SJon Hunter u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; 20277da2d91SJon Hunter u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; 20377da2d91SJon Hunter u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; 2045d805978SPaul Walmsley u16 grpsel_off = (regs == 3) ? 2055d805978SPaul Walmsley OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; 2068cb0ac99SPaul Walmsley int c = 0; 20777da2d91SJon Hunter 208c4d7e58fSPaul Walmsley wkst = omap2_prm_read_mod_reg(module, wkst_off); 209c4d7e58fSPaul Walmsley wkst &= omap2_prm_read_mod_reg(module, grpsel_off); 21077da2d91SJon Hunter if (wkst) { 211c4d7e58fSPaul Walmsley iclk = omap2_cm_read_mod_reg(module, iclk_off); 212c4d7e58fSPaul Walmsley fclk = omap2_cm_read_mod_reg(module, fclk_off); 21377da2d91SJon Hunter while (wkst) { 21471a80775SVikram Pandita clken = wkst; 215c4d7e58fSPaul Walmsley omap2_cm_set_mod_reg_bits(clken, module, iclk_off); 21671a80775SVikram Pandita /* 21771a80775SVikram Pandita * For USBHOST, we don't know whether HOST1 or 21871a80775SVikram Pandita * HOST2 woke us up, so enable both f-clocks 21971a80775SVikram Pandita */ 22071a80775SVikram Pandita if (module == OMAP3430ES2_USBHOST_MOD) 22171a80775SVikram Pandita clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; 222c4d7e58fSPaul Walmsley omap2_cm_set_mod_reg_bits(clken, module, fclk_off); 223c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(wkst, module, wkst_off); 224c4d7e58fSPaul Walmsley wkst = omap2_prm_read_mod_reg(module, wkst_off); 2258cb0ac99SPaul Walmsley c++; 22677da2d91SJon Hunter } 227c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(iclk, module, iclk_off); 228c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(fclk, module, fclk_off); 22977da2d91SJon Hunter } 2308cb0ac99SPaul Walmsley 2318cb0ac99SPaul Walmsley return c; 2328cb0ac99SPaul Walmsley } 2338cb0ac99SPaul Walmsley 2348cb0ac99SPaul Walmsley static int _prcm_int_handle_wakeup(void) 2358cb0ac99SPaul Walmsley { 2368cb0ac99SPaul Walmsley int c; 2378cb0ac99SPaul Walmsley 2388cb0ac99SPaul Walmsley c = prcm_clear_mod_irqs(WKUP_MOD, 1); 2398cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(CORE_MOD, 1); 2408cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1); 2418cb0ac99SPaul Walmsley if (omap_rev() > OMAP3430_REV_ES1_0) { 2428cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(CORE_MOD, 3); 2438cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1); 2448cb0ac99SPaul Walmsley } 2458cb0ac99SPaul Walmsley 2468cb0ac99SPaul Walmsley return c; 24777da2d91SJon Hunter } 24877da2d91SJon Hunter 24977da2d91SJon Hunter /* 25077da2d91SJon Hunter * PRCM Interrupt Handler 25177da2d91SJon Hunter * 25277da2d91SJon Hunter * The PRM_IRQSTATUS_MPU register indicates if there are any pending 25377da2d91SJon Hunter * interrupts from the PRCM for the MPU. These bits must be cleared in 25477da2d91SJon Hunter * order to clear the PRCM interrupt. The PRCM interrupt handler is 25577da2d91SJon Hunter * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear 25677da2d91SJon Hunter * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU 25777da2d91SJon Hunter * register indicates that a wake-up event is pending for the MPU and 25877da2d91SJon Hunter * this bit can only be cleared if the all the wake-up events latched 25977da2d91SJon Hunter * in the various PM_WKST_x registers have been cleared. The interrupt 26077da2d91SJon Hunter * handler is implemented using a do-while loop so that if a wake-up 26177da2d91SJon Hunter * event occurred during the processing of the prcm interrupt handler 26277da2d91SJon Hunter * (setting a bit in the corresponding PM_WKST_x register and thus 26377da2d91SJon Hunter * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register) 26477da2d91SJon Hunter * this would be handled. 26577da2d91SJon Hunter */ 2668bd22949SKevin Hilman static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) 2678bd22949SKevin Hilman { 268d6290a3eSKevin Hilman u32 irqenable_mpu, irqstatus_mpu; 2698cb0ac99SPaul Walmsley int c = 0; 2708bd22949SKevin Hilman 271c4d7e58fSPaul Walmsley irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD, 272d6290a3eSKevin Hilman OMAP3_PRM_IRQENABLE_MPU_OFFSET); 273c4d7e58fSPaul Walmsley irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD, 2748bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 275d6290a3eSKevin Hilman irqstatus_mpu &= irqenable_mpu; 2768cb0ac99SPaul Walmsley 277d6290a3eSKevin Hilman do { 2782bc4ef71SPaul Walmsley if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK | 2792bc4ef71SPaul Walmsley OMAP3430_IO_ST_MASK)) { 2808cb0ac99SPaul Walmsley c = _prcm_int_handle_wakeup(); 2818cb0ac99SPaul Walmsley 2828cb0ac99SPaul Walmsley /* 2838cb0ac99SPaul Walmsley * Is the MPU PRCM interrupt handler racing with the 2848cb0ac99SPaul Walmsley * IVA2 PRCM interrupt handler ? 2858cb0ac99SPaul Walmsley */ 2868cb0ac99SPaul Walmsley WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup " 2878cb0ac99SPaul Walmsley "but no wakeup sources are marked\n"); 2888cb0ac99SPaul Walmsley } else { 2898cb0ac99SPaul Walmsley /* XXX we need to expand our PRCM interrupt handler */ 2908cb0ac99SPaul Walmsley WARN(1, "prcm: WARNING: PRCM interrupt received, but " 2918cb0ac99SPaul Walmsley "no code to handle it (%08x)\n", irqstatus_mpu); 2928cb0ac99SPaul Walmsley } 2938cb0ac99SPaul Walmsley 294c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD, 2958bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 2968bd22949SKevin Hilman 297c4d7e58fSPaul Walmsley irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD, 298d6290a3eSKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 299d6290a3eSKevin Hilman irqstatus_mpu &= irqenable_mpu; 300d6290a3eSKevin Hilman 301d6290a3eSKevin Hilman } while (irqstatus_mpu); 3028bd22949SKevin Hilman 3038bd22949SKevin Hilman return IRQ_HANDLED; 3048bd22949SKevin Hilman } 3058bd22949SKevin Hilman 306cbe26349SRussell King static void omap34xx_save_context(u32 *save) 307cbe26349SRussell King { 308cbe26349SRussell King u32 val; 309cbe26349SRussell King 310cbe26349SRussell King /* Read Auxiliary Control Register */ 311cbe26349SRussell King asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val)); 312cbe26349SRussell King *save++ = 1; 313cbe26349SRussell King *save++ = val; 314cbe26349SRussell King 315cbe26349SRussell King /* Read L2 AUX ctrl register */ 316cbe26349SRussell King asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); 317cbe26349SRussell King *save++ = 1; 318cbe26349SRussell King *save++ = val; 319cbe26349SRussell King } 320cbe26349SRussell King 32129cb3cd2SRussell King static int omap34xx_do_sram_idle(unsigned long save_state) 32257f277b0SRajendra Nayak { 323cbe26349SRussell King omap34xx_cpu_suspend(save_state); 32429cb3cd2SRussell King return 0; 32557f277b0SRajendra Nayak } 32657f277b0SRajendra Nayak 32799e6a4d2SRajendra Nayak void omap_sram_idle(void) 3288bd22949SKevin Hilman { 3298bd22949SKevin Hilman /* Variable to tell what needs to be saved and restored 3308bd22949SKevin Hilman * in omap_sram_idle*/ 3318bd22949SKevin Hilman /* save_state = 0 => Nothing to save and restored */ 3328bd22949SKevin Hilman /* save_state = 1 => Only L1 and logic lost */ 3338bd22949SKevin Hilman /* save_state = 2 => Only L2 lost */ 3348bd22949SKevin Hilman /* save_state = 3 => L1, L2 and logic lost */ 335fa3c2a4fSRajendra Nayak int save_state = 0; 336fa3c2a4fSRajendra Nayak int mpu_next_state = PWRDM_POWER_ON; 337fa3c2a4fSRajendra Nayak int per_next_state = PWRDM_POWER_ON; 338fa3c2a4fSRajendra Nayak int core_next_state = PWRDM_POWER_ON; 33972e06d08SPaul Walmsley int per_going_off; 3402f5939c3SRajendra Nayak int core_prev_state, per_prev_state; 34113a6fe0fSTero Kristo u32 sdrc_pwr = 0; 3428bd22949SKevin Hilman 343fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(mpu_pwrdm); 344fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(neon_pwrdm); 345fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(core_pwrdm); 346fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(per_pwrdm); 347fa3c2a4fSRajendra Nayak 3488bd22949SKevin Hilman mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 3498bd22949SKevin Hilman switch (mpu_next_state) { 350fa3c2a4fSRajendra Nayak case PWRDM_POWER_ON: 3518bd22949SKevin Hilman case PWRDM_POWER_RET: 3528bd22949SKevin Hilman /* No need to save context */ 3538bd22949SKevin Hilman save_state = 0; 3548bd22949SKevin Hilman break; 35561255ab9SRajendra Nayak case PWRDM_POWER_OFF: 35661255ab9SRajendra Nayak save_state = 3; 35761255ab9SRajendra Nayak break; 3588bd22949SKevin Hilman default: 3598bd22949SKevin Hilman /* Invalid state */ 3608bd22949SKevin Hilman printk(KERN_ERR "Invalid mpu state in sram_idle\n"); 3618bd22949SKevin Hilman return; 3628bd22949SKevin Hilman } 363fe617af7SPeter 'p2' De Schrijver 364fa3c2a4fSRajendra Nayak /* NEON control */ 365fa3c2a4fSRajendra Nayak if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) 3667139178eSJouni Hogander pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); 367fa3c2a4fSRajendra Nayak 36840742fa8SMike Chan /* Enable IO-PAD and IO-CHAIN wakeups */ 369fa3c2a4fSRajendra Nayak per_next_state = pwrdm_read_next_pwrst(per_pwrdm); 370ecf157d0STero Kristo core_next_state = pwrdm_read_next_pwrst(core_pwrdm); 371d5c47d7eSKevin Hilman if (omap3_has_io_wakeup() && 372ad0c63f1Sstanley.miao (per_next_state < PWRDM_POWER_ON || 373ad0c63f1Sstanley.miao core_next_state < PWRDM_POWER_ON)) { 374c4d7e58fSPaul Walmsley omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); 375b02b9172SPaul Walmsley if (omap3_has_io_chain_ctrl()) 37640742fa8SMike Chan omap3_enable_io_chain(); 37740742fa8SMike Chan } 37840742fa8SMike Chan 3790d8e2d0dSPaul Walmsley /* Block console output in case it is on one of the OMAP UARTs */ 380e83df17fSKevin Hilman if (!is_suspending()) 3810d8e2d0dSPaul Walmsley if (per_next_state < PWRDM_POWER_ON || 3820d8e2d0dSPaul Walmsley core_next_state < PWRDM_POWER_ON) 383ac751efaSTorben Hohn if (!console_trylock()) 3840d8e2d0dSPaul Walmsley goto console_still_active; 3850d8e2d0dSPaul Walmsley 386ff2f8e5fSCharulatha V pwrdm_pre_transition(); 387ff2f8e5fSCharulatha V 38840742fa8SMike Chan /* PER */ 3892f5939c3SRajendra Nayak if (per_next_state < PWRDM_POWER_ON) { 39072e06d08SPaul Walmsley per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0; 3914af4016cSKevin Hilman omap_uart_prepare_idle(2); 392cd4f1faeSGovindraj.R omap_uart_prepare_idle(3); 39372e06d08SPaul Walmsley omap2_gpio_prepare_for_idle(per_going_off); 394e7410cf7SKevin Hilman if (per_next_state == PWRDM_POWER_OFF) 3952f5939c3SRajendra Nayak omap3_per_save_context(); 3962f5939c3SRajendra Nayak } 397c16c3f67STero Kristo 398658ce97eSKevin Hilman /* CORE */ 399658ce97eSKevin Hilman if (core_next_state < PWRDM_POWER_ON) { 400658ce97eSKevin Hilman omap_uart_prepare_idle(0); 401658ce97eSKevin Hilman omap_uart_prepare_idle(1); 4022f5939c3SRajendra Nayak if (core_next_state == PWRDM_POWER_OFF) { 4032f5939c3SRajendra Nayak omap3_core_save_context(); 404f0611a5cSPaul Walmsley omap3_cm_save_context(); 4052f5939c3SRajendra Nayak } 406fa3c2a4fSRajendra Nayak } 40740742fa8SMike Chan 408f18cc2ffSTero Kristo omap3_intc_prepare_idle(); 4098bd22949SKevin Hilman 41061255ab9SRajendra Nayak /* 411f265dc4cSRajendra Nayak * On EMU/HS devices ROM code restores a SRDC value 412f265dc4cSRajendra Nayak * from scratchpad which has automatic self refresh on timeout 41383521291SJean Pihet * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443. 414f265dc4cSRajendra Nayak * Hence store/restore the SDRC_POWER register here. 41513a6fe0fSTero Kristo */ 41630474544SPaul Walmsley if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && 41730474544SPaul Walmsley (omap_type() == OMAP2_DEVICE_TYPE_EMU || 41830474544SPaul Walmsley omap_type() == OMAP2_DEVICE_TYPE_SEC) && 419f265dc4cSRajendra Nayak core_next_state == PWRDM_POWER_OFF) 42013a6fe0fSTero Kristo sdrc_pwr = sdrc_read_reg(SDRC_POWER); 42113a6fe0fSTero Kristo 42213a6fe0fSTero Kristo /* 423076f2cc4SRussell King * omap3_arm_context is the location where some ARM context 424076f2cc4SRussell King * get saved. The rest is placed on the stack, and restored 425076f2cc4SRussell King * from there before resuming. 42661255ab9SRajendra Nayak */ 427cbe26349SRussell King if (save_state) 428cbe26349SRussell King omap34xx_save_context(omap3_arm_context); 429076f2cc4SRussell King if (save_state == 1 || save_state == 3) 4302c74a0ceSRussell King cpu_suspend(save_state, omap34xx_do_sram_idle); 431076f2cc4SRussell King else 432076f2cc4SRussell King omap34xx_do_sram_idle(save_state); 4338bd22949SKevin Hilman 434f265dc4cSRajendra Nayak /* Restore normal SDRC POWER settings */ 43530474544SPaul Walmsley if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && 43630474544SPaul Walmsley (omap_type() == OMAP2_DEVICE_TYPE_EMU || 43730474544SPaul Walmsley omap_type() == OMAP2_DEVICE_TYPE_SEC) && 43813a6fe0fSTero Kristo core_next_state == PWRDM_POWER_OFF) 43913a6fe0fSTero Kristo sdrc_write_reg(sdrc_pwr, SDRC_POWER); 44013a6fe0fSTero Kristo 441658ce97eSKevin Hilman /* CORE */ 442fa3c2a4fSRajendra Nayak if (core_next_state < PWRDM_POWER_ON) { 4432f5939c3SRajendra Nayak core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); 4442f5939c3SRajendra Nayak if (core_prev_state == PWRDM_POWER_OFF) { 4452f5939c3SRajendra Nayak omap3_core_restore_context(); 446f0611a5cSPaul Walmsley omap3_cm_restore_context(); 4472f5939c3SRajendra Nayak omap3_sram_restore_context(); 4488a917d2fSKalle Jokiniemi omap2_sms_restore_context(); 4492f5939c3SRajendra Nayak } 450658ce97eSKevin Hilman omap_uart_resume_idle(0); 451658ce97eSKevin Hilman omap_uart_resume_idle(1); 452658ce97eSKevin Hilman if (core_next_state == PWRDM_POWER_OFF) 453c4d7e58fSPaul Walmsley omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, 454658ce97eSKevin Hilman OMAP3430_GR_MOD, 455658ce97eSKevin Hilman OMAP3_PRM_VOLTCTRL_OFFSET); 456658ce97eSKevin Hilman } 457f18cc2ffSTero Kristo omap3_intc_resume_idle(); 458658ce97eSKevin Hilman 459ff2f8e5fSCharulatha V pwrdm_post_transition(); 460ff2f8e5fSCharulatha V 461658ce97eSKevin Hilman /* PER */ 4622f5939c3SRajendra Nayak if (per_next_state < PWRDM_POWER_ON) { 463658ce97eSKevin Hilman per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); 46443ffcd9aSKevin Hilman omap2_gpio_resume_after_idle(); 46543ffcd9aSKevin Hilman if (per_prev_state == PWRDM_POWER_OFF) 4662f5939c3SRajendra Nayak omap3_per_restore_context(); 467ecf157d0STero Kristo omap_uart_resume_idle(2); 468cd4f1faeSGovindraj.R omap_uart_resume_idle(3); 469fa3c2a4fSRajendra Nayak } 470fe617af7SPeter 'p2' De Schrijver 471e83df17fSKevin Hilman if (!is_suspending()) 472ac751efaSTorben Hohn console_unlock(); 4730d8e2d0dSPaul Walmsley 4740d8e2d0dSPaul Walmsley console_still_active: 4753a7ec26bSKalle Jokiniemi /* Disable IO-PAD and IO-CHAIN wakeup */ 47658a5559eSKevin Hilman if (omap3_has_io_wakeup() && 47758a5559eSKevin Hilman (per_next_state < PWRDM_POWER_ON || 47858a5559eSKevin Hilman core_next_state < PWRDM_POWER_ON)) { 479c4d7e58fSPaul Walmsley omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, 480c4d7e58fSPaul Walmsley PM_WKEN); 481b02b9172SPaul Walmsley if (omap3_has_io_chain_ctrl()) 4823a7ec26bSKalle Jokiniemi omap3_disable_io_chain(); 4833a7ec26bSKalle Jokiniemi } 484658ce97eSKevin Hilman 4855cd1937bSRajendra Nayak clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); 4868bd22949SKevin Hilman } 4878bd22949SKevin Hilman 48820b01669SRajendra Nayak int omap3_can_sleep(void) 4898bd22949SKevin Hilman { 4904af4016cSKevin Hilman if (!omap_uart_can_sleep()) 4914af4016cSKevin Hilman return 0; 4928bd22949SKevin Hilman return 1; 4938bd22949SKevin Hilman } 4948bd22949SKevin Hilman 4958bd22949SKevin Hilman static void omap3_pm_idle(void) 4968bd22949SKevin Hilman { 4978bd22949SKevin Hilman local_irq_disable(); 4988bd22949SKevin Hilman local_fiq_disable(); 4998bd22949SKevin Hilman 5008bd22949SKevin Hilman if (!omap3_can_sleep()) 5018bd22949SKevin Hilman goto out; 5028bd22949SKevin Hilman 503cf22854cSTero Kristo if (omap_irq_pending() || need_resched()) 5048bd22949SKevin Hilman goto out; 5058bd22949SKevin Hilman 5065e7c58dcSJean Pihet trace_power_start(POWER_CSTATE, 1, smp_processor_id()); 5075e7c58dcSJean Pihet trace_cpu_idle(1, smp_processor_id()); 5085e7c58dcSJean Pihet 5098bd22949SKevin Hilman omap_sram_idle(); 5108bd22949SKevin Hilman 5115e7c58dcSJean Pihet trace_power_end(smp_processor_id()); 5125e7c58dcSJean Pihet trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); 5135e7c58dcSJean Pihet 5148bd22949SKevin Hilman out: 5158bd22949SKevin Hilman local_fiq_enable(); 5168bd22949SKevin Hilman local_irq_enable(); 5178bd22949SKevin Hilman } 5188bd22949SKevin Hilman 51910f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 5208bd22949SKevin Hilman static int omap3_pm_suspend(void) 5218bd22949SKevin Hilman { 5228bd22949SKevin Hilman struct power_state *pwrst; 5238bd22949SKevin Hilman int state, ret = 0; 5248bd22949SKevin Hilman 5258bd22949SKevin Hilman /* Read current next_pwrsts */ 5268bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) 5278bd22949SKevin Hilman pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 5288bd22949SKevin Hilman /* Set ones wanted by suspend */ 5298bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 530eb6a2c75SSantosh Shilimkar if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) 5318bd22949SKevin Hilman goto restore; 5328bd22949SKevin Hilman if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) 5338bd22949SKevin Hilman goto restore; 5348bd22949SKevin Hilman } 5358bd22949SKevin Hilman 5364af4016cSKevin Hilman omap_uart_prepare_suspend(); 5372bbe3af3STero Kristo omap3_intc_suspend(); 5382bbe3af3STero Kristo 5398bd22949SKevin Hilman omap_sram_idle(); 5408bd22949SKevin Hilman 5418bd22949SKevin Hilman restore: 5428bd22949SKevin Hilman /* Restore next_pwrsts */ 5438bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 5448bd22949SKevin Hilman state = pwrdm_read_prev_pwrst(pwrst->pwrdm); 5458bd22949SKevin Hilman if (state > pwrst->next_state) { 5468bd22949SKevin Hilman printk(KERN_INFO "Powerdomain (%s) didn't enter " 5478bd22949SKevin Hilman "target state %d\n", 5488bd22949SKevin Hilman pwrst->pwrdm->name, pwrst->next_state); 5498bd22949SKevin Hilman ret = -1; 5508bd22949SKevin Hilman } 551eb6a2c75SSantosh Shilimkar omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); 5528bd22949SKevin Hilman } 5538bd22949SKevin Hilman if (ret) 5548bd22949SKevin Hilman printk(KERN_ERR "Could not enter target state in pm_suspend\n"); 5558bd22949SKevin Hilman else 5568bd22949SKevin Hilman printk(KERN_INFO "Successfully put all powerdomains " 5578bd22949SKevin Hilman "to target state\n"); 5588bd22949SKevin Hilman 5598bd22949SKevin Hilman return ret; 5608bd22949SKevin Hilman } 5618bd22949SKevin Hilman 5622466211eSTero Kristo static int omap3_pm_enter(suspend_state_t unused) 5638bd22949SKevin Hilman { 5648bd22949SKevin Hilman int ret = 0; 5658bd22949SKevin Hilman 5662466211eSTero Kristo switch (suspend_state) { 5678bd22949SKevin Hilman case PM_SUSPEND_STANDBY: 5688bd22949SKevin Hilman case PM_SUSPEND_MEM: 5698bd22949SKevin Hilman ret = omap3_pm_suspend(); 5708bd22949SKevin Hilman break; 5718bd22949SKevin Hilman default: 5728bd22949SKevin Hilman ret = -EINVAL; 5738bd22949SKevin Hilman } 5748bd22949SKevin Hilman 5758bd22949SKevin Hilman return ret; 5768bd22949SKevin Hilman } 5778bd22949SKevin Hilman 5782466211eSTero Kristo /* Hooks to enable / disable UART interrupts during suspend */ 5792466211eSTero Kristo static int omap3_pm_begin(suspend_state_t state) 5802466211eSTero Kristo { 581c166381dSJean Pihet disable_hlt(); 5822466211eSTero Kristo suspend_state = state; 5832466211eSTero Kristo omap_uart_enable_irqs(0); 5842466211eSTero Kristo return 0; 5852466211eSTero Kristo } 5862466211eSTero Kristo 5872466211eSTero Kristo static void omap3_pm_end(void) 5882466211eSTero Kristo { 5892466211eSTero Kristo suspend_state = PM_SUSPEND_ON; 5902466211eSTero Kristo omap_uart_enable_irqs(1); 591c166381dSJean Pihet enable_hlt(); 5922466211eSTero Kristo return; 5932466211eSTero Kristo } 5942466211eSTero Kristo 5952f55ac07SLionel Debroux static const struct platform_suspend_ops omap_pm_ops = { 5962466211eSTero Kristo .begin = omap3_pm_begin, 5972466211eSTero Kristo .end = omap3_pm_end, 5988bd22949SKevin Hilman .enter = omap3_pm_enter, 5998bd22949SKevin Hilman .valid = suspend_valid_only_mem, 6008bd22949SKevin Hilman }; 60110f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 6028bd22949SKevin Hilman 6031155e426SKevin Hilman 6041155e426SKevin Hilman /** 6051155e426SKevin Hilman * omap3_iva_idle(): ensure IVA is in idle so it can be put into 6061155e426SKevin Hilman * retention 6071155e426SKevin Hilman * 6081155e426SKevin Hilman * In cases where IVA2 is activated by bootcode, it may prevent 6091155e426SKevin Hilman * full-chip retention or off-mode because it is not idle. This 6101155e426SKevin Hilman * function forces the IVA2 into idle state so it can go 6111155e426SKevin Hilman * into retention/off and thus allow full-chip retention/off. 6121155e426SKevin Hilman * 6131155e426SKevin Hilman **/ 6141155e426SKevin Hilman static void __init omap3_iva_idle(void) 6151155e426SKevin Hilman { 6161155e426SKevin Hilman /* ensure IVA2 clock is disabled */ 617c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 6181155e426SKevin Hilman 6191155e426SKevin Hilman /* if no clock activity, nothing else to do */ 620c4d7e58fSPaul Walmsley if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & 6211155e426SKevin Hilman OMAP3430_CLKACTIVITY_IVA2_MASK)) 6221155e426SKevin Hilman return; 6231155e426SKevin Hilman 6241155e426SKevin Hilman /* Reset IVA2 */ 625c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | 6262bc4ef71SPaul Walmsley OMAP3430_RST2_IVA2_MASK | 6272bc4ef71SPaul Walmsley OMAP3430_RST3_IVA2_MASK, 62837903009SAbhijit Pagare OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 6291155e426SKevin Hilman 6301155e426SKevin Hilman /* Enable IVA2 clock */ 631c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, 6321155e426SKevin Hilman OMAP3430_IVA2_MOD, CM_FCLKEN); 6331155e426SKevin Hilman 6341155e426SKevin Hilman /* Set IVA2 boot mode to 'idle' */ 6351155e426SKevin Hilman omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, 6361155e426SKevin Hilman OMAP343X_CONTROL_IVA2_BOOTMOD); 6371155e426SKevin Hilman 6381155e426SKevin Hilman /* Un-reset IVA2 */ 639c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 6401155e426SKevin Hilman 6411155e426SKevin Hilman /* Disable IVA2 clock */ 642c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 6431155e426SKevin Hilman 6441155e426SKevin Hilman /* Reset IVA2 */ 645c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | 6462bc4ef71SPaul Walmsley OMAP3430_RST2_IVA2_MASK | 6472bc4ef71SPaul Walmsley OMAP3430_RST3_IVA2_MASK, 64837903009SAbhijit Pagare OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 6491155e426SKevin Hilman } 6501155e426SKevin Hilman 6518111b221SKevin Hilman static void __init omap3_d2d_idle(void) 6528bd22949SKevin Hilman { 6538111b221SKevin Hilman u16 mask, padconf; 6548111b221SKevin Hilman 6558111b221SKevin Hilman /* In a stand alone OMAP3430 where there is not a stacked 6568111b221SKevin Hilman * modem for the D2D Idle Ack and D2D MStandby must be pulled 6578111b221SKevin Hilman * high. S CONTROL_PADCONF_SAD2D_IDLEACK and 6588111b221SKevin Hilman * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ 6598111b221SKevin Hilman mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ 6608111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); 6618111b221SKevin Hilman padconf |= mask; 6628111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); 6638111b221SKevin Hilman 6648111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); 6658111b221SKevin Hilman padconf |= mask; 6668111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 6678111b221SKevin Hilman 6688bd22949SKevin Hilman /* reset modem */ 669c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | 6702bc4ef71SPaul Walmsley OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, 67137903009SAbhijit Pagare CORE_MOD, OMAP2_RM_RSTCTRL); 672c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); 6738111b221SKevin Hilman } 6748bd22949SKevin Hilman 6758111b221SKevin Hilman static void __init prcm_setup_regs(void) 6768111b221SKevin Hilman { 677e5863689SGovindraj.R u32 omap3630_en_uart4_mask = cpu_is_omap3630() ? 678e5863689SGovindraj.R OMAP3630_EN_UART4_MASK : 0; 679e5863689SGovindraj.R u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ? 680e5863689SGovindraj.R OMAP3630_GRPSEL_UART4_MASK : 0; 681e5863689SGovindraj.R 6824ef70c06SPaul Walmsley /* XXX This should be handled by hwmod code or SCM init code */ 6832fd0f75cSPaul Walmsley omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); 684b296c811STero Kristo 6858bd22949SKevin Hilman /* 6868bd22949SKevin Hilman * Enable control of expternal oscillator through 6878bd22949SKevin Hilman * sys_clkreq. In the long run clock framework should 6888bd22949SKevin Hilman * take care of this. 6898bd22949SKevin Hilman */ 690c4d7e58fSPaul Walmsley omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 6918bd22949SKevin Hilman 1 << OMAP_AUTOEXTCLKMODE_SHIFT, 6928bd22949SKevin Hilman OMAP3430_GR_MOD, 6938bd22949SKevin Hilman OMAP3_PRM_CLKSRC_CTRL_OFFSET); 6948bd22949SKevin Hilman 6958bd22949SKevin Hilman /* setup wakup source */ 696c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | 6972fd0f75cSPaul Walmsley OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, 6988bd22949SKevin Hilman WKUP_MOD, PM_WKEN); 6998bd22949SKevin Hilman /* No need to write EN_IO, that is always enabled */ 700c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | 701275f675cSPaul Walmsley OMAP3430_GRPSEL_GPT1_MASK | 702275f675cSPaul Walmsley OMAP3430_GRPSEL_GPT12_MASK, 7038bd22949SKevin Hilman WKUP_MOD, OMAP3430_PM_MPUGRPSEL); 7048bd22949SKevin Hilman /* For some reason IO doesn't generate wakeup event even if 7058bd22949SKevin Hilman * it is selected to mpu wakeup goup */ 706c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK, 7078bd22949SKevin Hilman OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); 7081155e426SKevin Hilman 709b92c5721SSubramani Venkatesh /* Enable PM_WKEN to support DSS LPR */ 710c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, 711b92c5721SSubramani Venkatesh OMAP3430_DSS_MOD, PM_WKEN); 712b92c5721SSubramani Venkatesh 713b427f92fSKevin Hilman /* Enable wakeups in PER */ 714c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(omap3630_en_uart4_mask | 715e5863689SGovindraj.R OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | 7162fd0f75cSPaul Walmsley OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | 7172fd0f75cSPaul Walmsley OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | 7182fd0f75cSPaul Walmsley OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK | 7192fd0f75cSPaul Walmsley OMAP3430_EN_MCBSP4_MASK, 720b427f92fSKevin Hilman OMAP3430_PER_MOD, PM_WKEN); 721eb350f74SKevin Hilman /* and allow them to wake up MPU */ 722c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask | 723e5863689SGovindraj.R OMAP3430_GRPSEL_GPIO2_MASK | 724275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO3_MASK | 725275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO4_MASK | 726275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO5_MASK | 727275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO6_MASK | 728275f675cSPaul Walmsley OMAP3430_GRPSEL_UART3_MASK | 729275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP2_MASK | 730275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP3_MASK | 731275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP4_MASK, 732eb350f74SKevin Hilman OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); 733eb350f74SKevin Hilman 734d3fd3290SKevin Hilman /* Don't attach IVA interrupts */ 735c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 736c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 737c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 738c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); 739d3fd3290SKevin Hilman 740b1340d17SKevin Hilman /* Clear any pending 'reset' flags */ 741c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); 742c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); 743c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); 744c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); 745c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); 746c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); 747c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); 748b1340d17SKevin Hilman 749014c46dbSKevin Hilman /* Clear any pending PRCM interrupts */ 750c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 751014c46dbSKevin Hilman 7521155e426SKevin Hilman omap3_iva_idle(); 7538111b221SKevin Hilman omap3_d2d_idle(); 7548bd22949SKevin Hilman } 7558bd22949SKevin Hilman 756c40552bcSKevin Hilman void omap3_pm_off_mode_enable(int enable) 757c40552bcSKevin Hilman { 758c40552bcSKevin Hilman struct power_state *pwrst; 759c40552bcSKevin Hilman u32 state; 760c40552bcSKevin Hilman 761c40552bcSKevin Hilman if (enable) 762c40552bcSKevin Hilman state = PWRDM_POWER_OFF; 763c40552bcSKevin Hilman else 764c40552bcSKevin Hilman state = PWRDM_POWER_RET; 765c40552bcSKevin Hilman 766c40552bcSKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 767cc1b6028SEduardo Valentin if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) && 768cc1b6028SEduardo Valentin pwrst->pwrdm == core_pwrdm && 769cc1b6028SEduardo Valentin state == PWRDM_POWER_OFF) { 770cc1b6028SEduardo Valentin pwrst->next_state = PWRDM_POWER_RET; 771e16b41bfSRicardo Salveti de Araujo pr_warn("%s: Core OFF disabled due to errata i583\n", 772cc1b6028SEduardo Valentin __func__); 773cc1b6028SEduardo Valentin } else { 774c40552bcSKevin Hilman pwrst->next_state = state; 775cc1b6028SEduardo Valentin } 776cc1b6028SEduardo Valentin omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 777c40552bcSKevin Hilman } 778c40552bcSKevin Hilman } 779c40552bcSKevin Hilman 78068d4778cSTero Kristo int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) 78168d4778cSTero Kristo { 78268d4778cSTero Kristo struct power_state *pwrst; 78368d4778cSTero Kristo 78468d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 78568d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) 78668d4778cSTero Kristo return pwrst->next_state; 78768d4778cSTero Kristo } 78868d4778cSTero Kristo return -EINVAL; 78968d4778cSTero Kristo } 79068d4778cSTero Kristo 79168d4778cSTero Kristo int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) 79268d4778cSTero Kristo { 79368d4778cSTero Kristo struct power_state *pwrst; 79468d4778cSTero Kristo 79568d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 79668d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) { 79768d4778cSTero Kristo pwrst->next_state = state; 79868d4778cSTero Kristo return 0; 79968d4778cSTero Kristo } 80068d4778cSTero Kristo } 80168d4778cSTero Kristo return -EINVAL; 80268d4778cSTero Kristo } 80368d4778cSTero Kristo 804a23456e9SPeter 'p2' De Schrijver static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) 8058bd22949SKevin Hilman { 8068bd22949SKevin Hilman struct power_state *pwrst; 8078bd22949SKevin Hilman 8088bd22949SKevin Hilman if (!pwrdm->pwrsts) 8098bd22949SKevin Hilman return 0; 8108bd22949SKevin Hilman 811d3d381c6SMing Lei pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); 8128bd22949SKevin Hilman if (!pwrst) 8138bd22949SKevin Hilman return -ENOMEM; 8148bd22949SKevin Hilman pwrst->pwrdm = pwrdm; 8158bd22949SKevin Hilman pwrst->next_state = PWRDM_POWER_RET; 8168bd22949SKevin Hilman list_add(&pwrst->node, &pwrst_list); 8178bd22949SKevin Hilman 8188bd22949SKevin Hilman if (pwrdm_has_hdwr_sar(pwrdm)) 8198bd22949SKevin Hilman pwrdm_enable_hdwr_sar(pwrdm); 8208bd22949SKevin Hilman 821eb6a2c75SSantosh Shilimkar return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 8228bd22949SKevin Hilman } 8238bd22949SKevin Hilman 8248bd22949SKevin Hilman /* 8258bd22949SKevin Hilman * Enable hw supervised mode for all clockdomains if it's 8268bd22949SKevin Hilman * supported. Initiate sleep transition for other clockdomains, if 8278bd22949SKevin Hilman * they are not used 8288bd22949SKevin Hilman */ 829a23456e9SPeter 'p2' De Schrijver static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) 8308bd22949SKevin Hilman { 8318bd22949SKevin Hilman if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) 8325cd1937bSRajendra Nayak clkdm_allow_idle(clkdm); 8338bd22949SKevin Hilman else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && 8348bd22949SKevin Hilman atomic_read(&clkdm->usecount) == 0) 83568b921adSRajendra Nayak clkdm_sleep(clkdm); 8368bd22949SKevin Hilman return 0; 8378bd22949SKevin Hilman } 8388bd22949SKevin Hilman 83946e130d2SJean Pihet /* 84046e130d2SJean Pihet * Push functions to SRAM 84146e130d2SJean Pihet * 84246e130d2SJean Pihet * The minimum set of functions is pushed to SRAM for execution: 84346e130d2SJean Pihet * - omap3_do_wfi for erratum i581 WA, 84446e130d2SJean Pihet * - save_secure_ram_context for security extensions. 84546e130d2SJean Pihet */ 8463231fc88SRajendra Nayak void omap_push_sram_idle(void) 8473231fc88SRajendra Nayak { 84846e130d2SJean Pihet omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz); 84946e130d2SJean Pihet 85027d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) 85127d59a4aSTero Kristo _omap_save_secure_sram = omap_sram_push(save_secure_ram_context, 85227d59a4aSTero Kristo save_secure_ram_context_sz); 8533231fc88SRajendra Nayak } 8543231fc88SRajendra Nayak 8558cdfd834SNishanth Menon static void __init pm_errata_configure(void) 8568cdfd834SNishanth Menon { 857c4236d2eSPeter 'p2' De Schrijver if (cpu_is_omap3630()) { 858458e999eSNishanth Menon pm34xx_errata |= PM_RTA_ERRATUM_i608; 859c4236d2eSPeter 'p2' De Schrijver /* Enable the l2 cache toggling in sleep logic */ 860c4236d2eSPeter 'p2' De Schrijver enable_omap3630_toggle_l2_on_restore(); 861cc1b6028SEduardo Valentin if (omap_rev() < OMAP3630_REV_ES1_2) 862cc1b6028SEduardo Valentin pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583; 863c4236d2eSPeter 'p2' De Schrijver } 8648cdfd834SNishanth Menon } 8658cdfd834SNishanth Menon 8667cc515f7SKevin Hilman static int __init omap3_pm_init(void) 8678bd22949SKevin Hilman { 8688bd22949SKevin Hilman struct power_state *pwrst, *tmp; 86955ed9694SPaul Walmsley struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm; 8708bd22949SKevin Hilman int ret; 8718bd22949SKevin Hilman 8728bd22949SKevin Hilman if (!cpu_is_omap34xx()) 8738bd22949SKevin Hilman return -ENODEV; 8748bd22949SKevin Hilman 875b02b9172SPaul Walmsley if (!omap3_has_io_chain_ctrl()) 876b02b9172SPaul Walmsley pr_warning("PM: no software I/O chain control; some wakeups may be lost\n"); 877b02b9172SPaul Walmsley 8788cdfd834SNishanth Menon pm_errata_configure(); 8798cdfd834SNishanth Menon 8808bd22949SKevin Hilman /* XXX prcm_setup_regs needs to be before enabling hw 8818bd22949SKevin Hilman * supervised mode for powerdomains */ 8828bd22949SKevin Hilman prcm_setup_regs(); 8838bd22949SKevin Hilman 8848bd22949SKevin Hilman ret = request_irq(INT_34XX_PRCM_MPU_IRQ, 8858bd22949SKevin Hilman (irq_handler_t)prcm_interrupt_handler, 8868bd22949SKevin Hilman IRQF_DISABLED, "prcm", NULL); 8878bd22949SKevin Hilman if (ret) { 8888bd22949SKevin Hilman printk(KERN_ERR "request_irq failed to register for 0x%x\n", 8898bd22949SKevin Hilman INT_34XX_PRCM_MPU_IRQ); 8908bd22949SKevin Hilman goto err1; 8918bd22949SKevin Hilman } 8928bd22949SKevin Hilman 893a23456e9SPeter 'p2' De Schrijver ret = pwrdm_for_each(pwrdms_setup, NULL); 8948bd22949SKevin Hilman if (ret) { 8958bd22949SKevin Hilman printk(KERN_ERR "Failed to setup powerdomains\n"); 8968bd22949SKevin Hilman goto err2; 8978bd22949SKevin Hilman } 8988bd22949SKevin Hilman 899a23456e9SPeter 'p2' De Schrijver (void) clkdm_for_each(clkdms_setup, NULL); 9008bd22949SKevin Hilman 9018bd22949SKevin Hilman mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); 9028bd22949SKevin Hilman if (mpu_pwrdm == NULL) { 9038bd22949SKevin Hilman printk(KERN_ERR "Failed to get mpu_pwrdm\n"); 9048bd22949SKevin Hilman goto err2; 9058bd22949SKevin Hilman } 9068bd22949SKevin Hilman 907fa3c2a4fSRajendra Nayak neon_pwrdm = pwrdm_lookup("neon_pwrdm"); 908fa3c2a4fSRajendra Nayak per_pwrdm = pwrdm_lookup("per_pwrdm"); 909fa3c2a4fSRajendra Nayak core_pwrdm = pwrdm_lookup("core_pwrdm"); 910c16c3f67STero Kristo cam_pwrdm = pwrdm_lookup("cam_pwrdm"); 911fa3c2a4fSRajendra Nayak 91255ed9694SPaul Walmsley neon_clkdm = clkdm_lookup("neon_clkdm"); 91355ed9694SPaul Walmsley mpu_clkdm = clkdm_lookup("mpu_clkdm"); 91455ed9694SPaul Walmsley per_clkdm = clkdm_lookup("per_clkdm"); 91555ed9694SPaul Walmsley core_clkdm = clkdm_lookup("core_clkdm"); 91655ed9694SPaul Walmsley 91710f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 9188bd22949SKevin Hilman suspend_set_ops(&omap_pm_ops); 91910f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 9208bd22949SKevin Hilman 9218bd22949SKevin Hilman pm_idle = omap3_pm_idle; 9220343371eSKalle Jokiniemi omap3_idle_init(); 9238bd22949SKevin Hilman 924458e999eSNishanth Menon /* 925458e999eSNishanth Menon * RTA is disabled during initialization as per erratum i608 926458e999eSNishanth Menon * it is safer to disable RTA by the bootloader, but we would like 927458e999eSNishanth Menon * to be doubly sure here and prevent any mishaps. 928458e999eSNishanth Menon */ 929458e999eSNishanth Menon if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608)) 930458e999eSNishanth Menon omap3630_ctrl_disable_rta(); 931458e999eSNishanth Menon 93255ed9694SPaul Walmsley clkdm_add_wkdep(neon_clkdm, mpu_clkdm); 93327d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 93427d59a4aSTero Kristo omap3_secure_ram_storage = 93527d59a4aSTero Kristo kmalloc(0x803F, GFP_KERNEL); 93627d59a4aSTero Kristo if (!omap3_secure_ram_storage) 93727d59a4aSTero Kristo printk(KERN_ERR "Memory allocation failed when" 93827d59a4aSTero Kristo "allocating for secure sram context\n"); 93927d59a4aSTero Kristo 9409d97140bSTero Kristo local_irq_disable(); 9419d97140bSTero Kristo local_fiq_disable(); 9429d97140bSTero Kristo 9439d97140bSTero Kristo omap_dma_global_context_save(); 944617fcc98SKevin Hilman omap3_save_secure_ram_context(); 9459d97140bSTero Kristo omap_dma_global_context_restore(); 9469d97140bSTero Kristo 9479d97140bSTero Kristo local_irq_enable(); 9489d97140bSTero Kristo local_fiq_enable(); 9499d97140bSTero Kristo } 9509d97140bSTero Kristo 9519d97140bSTero Kristo omap3_save_scratchpad_contents(); 9528bd22949SKevin Hilman err1: 9538bd22949SKevin Hilman return ret; 9548bd22949SKevin Hilman err2: 9558bd22949SKevin Hilman free_irq(INT_34XX_PRCM_MPU_IRQ, NULL); 9568bd22949SKevin Hilman list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { 9578bd22949SKevin Hilman list_del(&pwrst->node); 9588bd22949SKevin Hilman kfree(pwrst); 9598bd22949SKevin Hilman } 9608bd22949SKevin Hilman return ret; 9618bd22949SKevin Hilman } 9628bd22949SKevin Hilman 9638bd22949SKevin Hilman late_initcall(omap3_pm_init); 964