18bd22949SKevin Hilman /* 28bd22949SKevin Hilman * OMAP3 Power Management Routines 38bd22949SKevin Hilman * 48bd22949SKevin Hilman * Copyright (C) 2006-2008 Nokia Corporation 58bd22949SKevin Hilman * Tony Lindgren <tony@atomide.com> 68bd22949SKevin Hilman * Jouni Hogander 78bd22949SKevin Hilman * 82f5939c3SRajendra Nayak * Copyright (C) 2007 Texas Instruments, Inc. 92f5939c3SRajendra Nayak * Rajendra Nayak <rnayak@ti.com> 102f5939c3SRajendra Nayak * 118bd22949SKevin Hilman * Copyright (C) 2005 Texas Instruments, Inc. 128bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 138bd22949SKevin Hilman * 148bd22949SKevin Hilman * Based on pm.c for omap1 158bd22949SKevin Hilman * 168bd22949SKevin Hilman * This program is free software; you can redistribute it and/or modify 178bd22949SKevin Hilman * it under the terms of the GNU General Public License version 2 as 188bd22949SKevin Hilman * published by the Free Software Foundation. 198bd22949SKevin Hilman */ 208bd22949SKevin Hilman 218bd22949SKevin Hilman #include <linux/pm.h> 228bd22949SKevin Hilman #include <linux/suspend.h> 238bd22949SKevin Hilman #include <linux/interrupt.h> 248bd22949SKevin Hilman #include <linux/module.h> 258bd22949SKevin Hilman #include <linux/list.h> 268bd22949SKevin Hilman #include <linux/err.h> 278bd22949SKevin Hilman #include <linux/gpio.h> 28c40552bcSKevin Hilman #include <linux/clk.h> 29dccaad89STero Kristo #include <linux/delay.h> 305a0e3ad6STejun Heo #include <linux/slab.h> 318bd22949SKevin Hilman 32ce491cf8STony Lindgren #include <plat/sram.h> 33ce491cf8STony Lindgren #include <plat/clockdomain.h> 34ce491cf8STony Lindgren #include <plat/powerdomain.h> 35ce491cf8STony Lindgren #include <plat/control.h> 36ce491cf8STony Lindgren #include <plat/serial.h> 3761255ab9SRajendra Nayak #include <plat/sdrc.h> 382f5939c3SRajendra Nayak #include <plat/prcm.h> 392f5939c3SRajendra Nayak #include <plat/gpmc.h> 40f2d11858STero Kristo #include <plat/dma.h> 41d7814e4dSKevin Hilman #include <plat/dmtimer.h> 428bd22949SKevin Hilman 4357f277b0SRajendra Nayak #include <asm/tlbflush.h> 4457f277b0SRajendra Nayak 458bd22949SKevin Hilman #include "cm.h" 468bd22949SKevin Hilman #include "cm-regbits-34xx.h" 478bd22949SKevin Hilman #include "prm-regbits-34xx.h" 488bd22949SKevin Hilman 498bd22949SKevin Hilman #include "prm.h" 508bd22949SKevin Hilman #include "pm.h" 5113a6fe0fSTero Kristo #include "sdrc.h" 5213a6fe0fSTero Kristo 532f5939c3SRajendra Nayak /* Scratchpad offsets */ 542f5939c3SRajendra Nayak #define OMAP343X_TABLE_ADDRESS_OFFSET 0x31 552f5939c3SRajendra Nayak #define OMAP343X_TABLE_VALUE_OFFSET 0x30 562f5939c3SRajendra Nayak #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32 572f5939c3SRajendra Nayak 58c40552bcSKevin Hilman u32 enable_off_mode; 59c40552bcSKevin Hilman u32 sleep_while_idle; 60d7814e4dSKevin Hilman u32 wakeup_timer_seconds; 61c40552bcSKevin Hilman 628bd22949SKevin Hilman struct power_state { 638bd22949SKevin Hilman struct powerdomain *pwrdm; 648bd22949SKevin Hilman u32 next_state; 6510f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 668bd22949SKevin Hilman u32 saved_state; 6710f90ed2SKevin Hilman #endif 688bd22949SKevin Hilman struct list_head node; 698bd22949SKevin Hilman }; 708bd22949SKevin Hilman 718bd22949SKevin Hilman static LIST_HEAD(pwrst_list); 728bd22949SKevin Hilman 738bd22949SKevin Hilman static void (*_omap_sram_idle)(u32 *addr, int save_state); 748bd22949SKevin Hilman 7527d59a4aSTero Kristo static int (*_omap_save_secure_sram)(u32 *addr); 7627d59a4aSTero Kristo 77fa3c2a4fSRajendra Nayak static struct powerdomain *mpu_pwrdm, *neon_pwrdm; 78fa3c2a4fSRajendra Nayak static struct powerdomain *core_pwrdm, *per_pwrdm; 79c16c3f67STero Kristo static struct powerdomain *cam_pwrdm; 80fa3c2a4fSRajendra Nayak 812f5939c3SRajendra Nayak static inline void omap3_per_save_context(void) 822f5939c3SRajendra Nayak { 832f5939c3SRajendra Nayak omap_gpio_save_context(); 842f5939c3SRajendra Nayak } 852f5939c3SRajendra Nayak 862f5939c3SRajendra Nayak static inline void omap3_per_restore_context(void) 872f5939c3SRajendra Nayak { 882f5939c3SRajendra Nayak omap_gpio_restore_context(); 892f5939c3SRajendra Nayak } 902f5939c3SRajendra Nayak 913a7ec26bSKalle Jokiniemi static void omap3_enable_io_chain(void) 923a7ec26bSKalle Jokiniemi { 933a7ec26bSKalle Jokiniemi int timeout = 0; 943a7ec26bSKalle Jokiniemi 953a7ec26bSKalle Jokiniemi if (omap_rev() >= OMAP3430_REV_ES3_1) { 963a7ec26bSKalle Jokiniemi prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN); 973a7ec26bSKalle Jokiniemi /* Do a readback to assure write has been done */ 983a7ec26bSKalle Jokiniemi prm_read_mod_reg(WKUP_MOD, PM_WKEN); 993a7ec26bSKalle Jokiniemi 1003a7ec26bSKalle Jokiniemi while (!(prm_read_mod_reg(WKUP_MOD, PM_WKST) & 1013a7ec26bSKalle Jokiniemi OMAP3430_ST_IO_CHAIN)) { 1023a7ec26bSKalle Jokiniemi timeout++; 1033a7ec26bSKalle Jokiniemi if (timeout > 1000) { 1043a7ec26bSKalle Jokiniemi printk(KERN_ERR "Wake up daisy chain " 1053a7ec26bSKalle Jokiniemi "activation failed.\n"); 1063a7ec26bSKalle Jokiniemi return; 1073a7ec26bSKalle Jokiniemi } 1083a7ec26bSKalle Jokiniemi prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN, 1093a7ec26bSKalle Jokiniemi WKUP_MOD, PM_WKST); 1103a7ec26bSKalle Jokiniemi } 1113a7ec26bSKalle Jokiniemi } 1123a7ec26bSKalle Jokiniemi } 1133a7ec26bSKalle Jokiniemi 1143a7ec26bSKalle Jokiniemi static void omap3_disable_io_chain(void) 1153a7ec26bSKalle Jokiniemi { 1163a7ec26bSKalle Jokiniemi if (omap_rev() >= OMAP3430_REV_ES3_1) 1173a7ec26bSKalle Jokiniemi prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN); 1183a7ec26bSKalle Jokiniemi } 1193a7ec26bSKalle Jokiniemi 1202f5939c3SRajendra Nayak static void omap3_core_save_context(void) 1212f5939c3SRajendra Nayak { 1222f5939c3SRajendra Nayak u32 control_padconf_off; 1232f5939c3SRajendra Nayak 1242f5939c3SRajendra Nayak /* Save the padconf registers */ 1252f5939c3SRajendra Nayak control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF); 1262f5939c3SRajendra Nayak control_padconf_off |= START_PADCONF_SAVE; 1272f5939c3SRajendra Nayak omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF); 1282f5939c3SRajendra Nayak /* wait for the save to complete */ 1291b6e821fSRoel Kluin while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) 1301b6e821fSRoel Kluin & PADCONF_SAVE_DONE)) 131dccaad89STero Kristo udelay(1); 132dccaad89STero Kristo 133dccaad89STero Kristo /* 134dccaad89STero Kristo * Force write last pad into memory, as this can fail in some 135dccaad89STero Kristo * cases according to erratas 1.157, 1.185 136dccaad89STero Kristo */ 137dccaad89STero Kristo omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), 138dccaad89STero Kristo OMAP343X_CONTROL_MEM_WKUP + 0x2a0); 139dccaad89STero Kristo 1402f5939c3SRajendra Nayak /* Save the Interrupt controller context */ 1412f5939c3SRajendra Nayak omap_intc_save_context(); 1422f5939c3SRajendra Nayak /* Save the GPMC context */ 1432f5939c3SRajendra Nayak omap3_gpmc_save_context(); 1442f5939c3SRajendra Nayak /* Save the system control module context, padconf already save above*/ 1452f5939c3SRajendra Nayak omap3_control_save_context(); 146f2d11858STero Kristo omap_dma_global_context_save(); 1472f5939c3SRajendra Nayak } 1482f5939c3SRajendra Nayak 1492f5939c3SRajendra Nayak static void omap3_core_restore_context(void) 1502f5939c3SRajendra Nayak { 1512f5939c3SRajendra Nayak /* Restore the control module context, padconf restored by h/w */ 1522f5939c3SRajendra Nayak omap3_control_restore_context(); 1532f5939c3SRajendra Nayak /* Restore the GPMC context */ 1542f5939c3SRajendra Nayak omap3_gpmc_restore_context(); 1552f5939c3SRajendra Nayak /* Restore the interrupt controller context */ 1562f5939c3SRajendra Nayak omap_intc_restore_context(); 157f2d11858STero Kristo omap_dma_global_context_restore(); 1582f5939c3SRajendra Nayak } 1592f5939c3SRajendra Nayak 1609d97140bSTero Kristo /* 1619d97140bSTero Kristo * FIXME: This function should be called before entering off-mode after 1629d97140bSTero Kristo * OMAP3 secure services have been accessed. Currently it is only called 1639d97140bSTero Kristo * once during boot sequence, but this works as we are not using secure 1649d97140bSTero Kristo * services. 1659d97140bSTero Kristo */ 16627d59a4aSTero Kristo static void omap3_save_secure_ram_context(u32 target_mpu_state) 16727d59a4aSTero Kristo { 16827d59a4aSTero Kristo u32 ret; 16927d59a4aSTero Kristo 17027d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 17127d59a4aSTero Kristo /* 17227d59a4aSTero Kristo * MPU next state must be set to POWER_ON temporarily, 17327d59a4aSTero Kristo * otherwise the WFI executed inside the ROM code 17427d59a4aSTero Kristo * will hang the system. 17527d59a4aSTero Kristo */ 17627d59a4aSTero Kristo pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); 17727d59a4aSTero Kristo ret = _omap_save_secure_sram((u32 *) 17827d59a4aSTero Kristo __pa(omap3_secure_ram_storage)); 17927d59a4aSTero Kristo pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state); 18027d59a4aSTero Kristo /* Following is for error tracking, it should not happen */ 18127d59a4aSTero Kristo if (ret) { 18227d59a4aSTero Kristo printk(KERN_ERR "save_secure_sram() returns %08x\n", 18327d59a4aSTero Kristo ret); 18427d59a4aSTero Kristo while (1) 18527d59a4aSTero Kristo ; 18627d59a4aSTero Kristo } 18727d59a4aSTero Kristo } 18827d59a4aSTero Kristo } 18927d59a4aSTero Kristo 19077da2d91SJon Hunter /* 19177da2d91SJon Hunter * PRCM Interrupt Handler Helper Function 19277da2d91SJon Hunter * 19377da2d91SJon Hunter * The purpose of this function is to clear any wake-up events latched 19477da2d91SJon Hunter * in the PRCM PM_WKST_x registers. It is possible that a wake-up event 19577da2d91SJon Hunter * may occur whilst attempting to clear a PM_WKST_x register and thus 19677da2d91SJon Hunter * set another bit in this register. A while loop is used to ensure 19777da2d91SJon Hunter * that any peripheral wake-up events occurring while attempting to 19877da2d91SJon Hunter * clear the PM_WKST_x are detected and cleared. 19977da2d91SJon Hunter */ 2008cb0ac99SPaul Walmsley static int prcm_clear_mod_irqs(s16 module, u8 regs) 20177da2d91SJon Hunter { 20271a80775SVikram Pandita u32 wkst, fclk, iclk, clken; 20377da2d91SJon Hunter u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; 20477da2d91SJon Hunter u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; 20577da2d91SJon Hunter u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; 2065d805978SPaul Walmsley u16 grpsel_off = (regs == 3) ? 2075d805978SPaul Walmsley OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; 2088cb0ac99SPaul Walmsley int c = 0; 20977da2d91SJon Hunter 21077da2d91SJon Hunter wkst = prm_read_mod_reg(module, wkst_off); 2115d805978SPaul Walmsley wkst &= prm_read_mod_reg(module, grpsel_off); 21277da2d91SJon Hunter if (wkst) { 21377da2d91SJon Hunter iclk = cm_read_mod_reg(module, iclk_off); 21477da2d91SJon Hunter fclk = cm_read_mod_reg(module, fclk_off); 21577da2d91SJon Hunter while (wkst) { 21671a80775SVikram Pandita clken = wkst; 21771a80775SVikram Pandita cm_set_mod_reg_bits(clken, module, iclk_off); 21871a80775SVikram Pandita /* 21971a80775SVikram Pandita * For USBHOST, we don't know whether HOST1 or 22071a80775SVikram Pandita * HOST2 woke us up, so enable both f-clocks 22171a80775SVikram Pandita */ 22271a80775SVikram Pandita if (module == OMAP3430ES2_USBHOST_MOD) 22371a80775SVikram Pandita clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; 22471a80775SVikram Pandita cm_set_mod_reg_bits(clken, module, fclk_off); 22577da2d91SJon Hunter prm_write_mod_reg(wkst, module, wkst_off); 22677da2d91SJon Hunter wkst = prm_read_mod_reg(module, wkst_off); 2278cb0ac99SPaul Walmsley c++; 22877da2d91SJon Hunter } 22977da2d91SJon Hunter cm_write_mod_reg(iclk, module, iclk_off); 23077da2d91SJon Hunter cm_write_mod_reg(fclk, module, fclk_off); 23177da2d91SJon Hunter } 2328cb0ac99SPaul Walmsley 2338cb0ac99SPaul Walmsley return c; 2348cb0ac99SPaul Walmsley } 2358cb0ac99SPaul Walmsley 2368cb0ac99SPaul Walmsley static int _prcm_int_handle_wakeup(void) 2378cb0ac99SPaul Walmsley { 2388cb0ac99SPaul Walmsley int c; 2398cb0ac99SPaul Walmsley 2408cb0ac99SPaul Walmsley c = prcm_clear_mod_irqs(WKUP_MOD, 1); 2418cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(CORE_MOD, 1); 2428cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1); 2438cb0ac99SPaul Walmsley if (omap_rev() > OMAP3430_REV_ES1_0) { 2448cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(CORE_MOD, 3); 2458cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1); 2468cb0ac99SPaul Walmsley } 2478cb0ac99SPaul Walmsley 2488cb0ac99SPaul Walmsley return c; 24977da2d91SJon Hunter } 25077da2d91SJon Hunter 25177da2d91SJon Hunter /* 25277da2d91SJon Hunter * PRCM Interrupt Handler 25377da2d91SJon Hunter * 25477da2d91SJon Hunter * The PRM_IRQSTATUS_MPU register indicates if there are any pending 25577da2d91SJon Hunter * interrupts from the PRCM for the MPU. These bits must be cleared in 25677da2d91SJon Hunter * order to clear the PRCM interrupt. The PRCM interrupt handler is 25777da2d91SJon Hunter * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear 25877da2d91SJon Hunter * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU 25977da2d91SJon Hunter * register indicates that a wake-up event is pending for the MPU and 26077da2d91SJon Hunter * this bit can only be cleared if the all the wake-up events latched 26177da2d91SJon Hunter * in the various PM_WKST_x registers have been cleared. The interrupt 26277da2d91SJon Hunter * handler is implemented using a do-while loop so that if a wake-up 26377da2d91SJon Hunter * event occurred during the processing of the prcm interrupt handler 26477da2d91SJon Hunter * (setting a bit in the corresponding PM_WKST_x register and thus 26577da2d91SJon Hunter * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register) 26677da2d91SJon Hunter * this would be handled. 26777da2d91SJon Hunter */ 2688bd22949SKevin Hilman static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) 2698bd22949SKevin Hilman { 27077da2d91SJon Hunter u32 irqstatus_mpu; 2718cb0ac99SPaul Walmsley int c = 0; 2728bd22949SKevin Hilman 27377da2d91SJon Hunter do { 2748bd22949SKevin Hilman irqstatus_mpu = prm_read_mod_reg(OCP_MOD, 2758bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 2768cb0ac99SPaul Walmsley 2778cb0ac99SPaul Walmsley if (irqstatus_mpu & (OMAP3430_WKUP_ST | OMAP3430_IO_ST)) { 2788cb0ac99SPaul Walmsley c = _prcm_int_handle_wakeup(); 2798cb0ac99SPaul Walmsley 2808cb0ac99SPaul Walmsley /* 2818cb0ac99SPaul Walmsley * Is the MPU PRCM interrupt handler racing with the 2828cb0ac99SPaul Walmsley * IVA2 PRCM interrupt handler ? 2838cb0ac99SPaul Walmsley */ 2848cb0ac99SPaul Walmsley WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup " 2858cb0ac99SPaul Walmsley "but no wakeup sources are marked\n"); 2868cb0ac99SPaul Walmsley } else { 2878cb0ac99SPaul Walmsley /* XXX we need to expand our PRCM interrupt handler */ 2888cb0ac99SPaul Walmsley WARN(1, "prcm: WARNING: PRCM interrupt received, but " 2898cb0ac99SPaul Walmsley "no code to handle it (%08x)\n", irqstatus_mpu); 2908cb0ac99SPaul Walmsley } 2918cb0ac99SPaul Walmsley 2928bd22949SKevin Hilman prm_write_mod_reg(irqstatus_mpu, OCP_MOD, 2938bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 2948bd22949SKevin Hilman 29577da2d91SJon Hunter } while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET)); 2968bd22949SKevin Hilman 2978bd22949SKevin Hilman return IRQ_HANDLED; 2988bd22949SKevin Hilman } 2998bd22949SKevin Hilman 30057f277b0SRajendra Nayak static void restore_control_register(u32 val) 30157f277b0SRajendra Nayak { 30257f277b0SRajendra Nayak __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val)); 30357f277b0SRajendra Nayak } 30457f277b0SRajendra Nayak 30557f277b0SRajendra Nayak /* Function to restore the table entry that was modified for enabling MMU */ 30657f277b0SRajendra Nayak static void restore_table_entry(void) 30757f277b0SRajendra Nayak { 30857f277b0SRajendra Nayak u32 *scratchpad_address; 30957f277b0SRajendra Nayak u32 previous_value, control_reg_value; 31057f277b0SRajendra Nayak u32 *address; 31157f277b0SRajendra Nayak 31257f277b0SRajendra Nayak scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD); 31357f277b0SRajendra Nayak 31457f277b0SRajendra Nayak /* Get address of entry that was modified */ 31557f277b0SRajendra Nayak address = (u32 *)__raw_readl(scratchpad_address + 31657f277b0SRajendra Nayak OMAP343X_TABLE_ADDRESS_OFFSET); 31757f277b0SRajendra Nayak /* Get the previous value which needs to be restored */ 31857f277b0SRajendra Nayak previous_value = __raw_readl(scratchpad_address + 31957f277b0SRajendra Nayak OMAP343X_TABLE_VALUE_OFFSET); 32057f277b0SRajendra Nayak address = __va(address); 32157f277b0SRajendra Nayak *address = previous_value; 32257f277b0SRajendra Nayak flush_tlb_all(); 32357f277b0SRajendra Nayak control_reg_value = __raw_readl(scratchpad_address 32457f277b0SRajendra Nayak + OMAP343X_CONTROL_REG_VALUE_OFFSET); 32557f277b0SRajendra Nayak /* This will enable caches and prediction */ 32657f277b0SRajendra Nayak restore_control_register(control_reg_value); 32757f277b0SRajendra Nayak } 32857f277b0SRajendra Nayak 32999e6a4d2SRajendra Nayak void omap_sram_idle(void) 3308bd22949SKevin Hilman { 3318bd22949SKevin Hilman /* Variable to tell what needs to be saved and restored 3328bd22949SKevin Hilman * in omap_sram_idle*/ 3338bd22949SKevin Hilman /* save_state = 0 => Nothing to save and restored */ 3348bd22949SKevin Hilman /* save_state = 1 => Only L1 and logic lost */ 3358bd22949SKevin Hilman /* save_state = 2 => Only L2 lost */ 3368bd22949SKevin Hilman /* save_state = 3 => L1, L2 and logic lost */ 337fa3c2a4fSRajendra Nayak int save_state = 0; 338fa3c2a4fSRajendra Nayak int mpu_next_state = PWRDM_POWER_ON; 339fa3c2a4fSRajendra Nayak int per_next_state = PWRDM_POWER_ON; 340fa3c2a4fSRajendra Nayak int core_next_state = PWRDM_POWER_ON; 3412f5939c3SRajendra Nayak int core_prev_state, per_prev_state; 34213a6fe0fSTero Kristo u32 sdrc_pwr = 0; 343ecf157d0STero Kristo int per_state_modified = 0; 3448bd22949SKevin Hilman 3458bd22949SKevin Hilman if (!_omap_sram_idle) 3468bd22949SKevin Hilman return; 3478bd22949SKevin Hilman 348fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(mpu_pwrdm); 349fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(neon_pwrdm); 350fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(core_pwrdm); 351fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(per_pwrdm); 352fa3c2a4fSRajendra Nayak 3538bd22949SKevin Hilman mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 3548bd22949SKevin Hilman switch (mpu_next_state) { 355fa3c2a4fSRajendra Nayak case PWRDM_POWER_ON: 3568bd22949SKevin Hilman case PWRDM_POWER_RET: 3578bd22949SKevin Hilman /* No need to save context */ 3588bd22949SKevin Hilman save_state = 0; 3598bd22949SKevin Hilman break; 36061255ab9SRajendra Nayak case PWRDM_POWER_OFF: 36161255ab9SRajendra Nayak save_state = 3; 36261255ab9SRajendra Nayak break; 3638bd22949SKevin Hilman default: 3648bd22949SKevin Hilman /* Invalid state */ 3658bd22949SKevin Hilman printk(KERN_ERR "Invalid mpu state in sram_idle\n"); 3668bd22949SKevin Hilman return; 3678bd22949SKevin Hilman } 368fe617af7SPeter 'p2' De Schrijver pwrdm_pre_transition(); 369fe617af7SPeter 'p2' De Schrijver 370fa3c2a4fSRajendra Nayak /* NEON control */ 371fa3c2a4fSRajendra Nayak if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) 3727139178eSJouni Hogander pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); 373fa3c2a4fSRajendra Nayak 374658ce97eSKevin Hilman /* PER */ 375fa3c2a4fSRajendra Nayak per_next_state = pwrdm_read_next_pwrst(per_pwrdm); 376ecf157d0STero Kristo core_next_state = pwrdm_read_next_pwrst(core_pwrdm); 3772f5939c3SRajendra Nayak if (per_next_state < PWRDM_POWER_ON) { 3784af4016cSKevin Hilman omap_uart_prepare_idle(2); 37943ffcd9aSKevin Hilman omap2_gpio_prepare_for_idle(per_next_state); 380ecf157d0STero Kristo if (per_next_state == PWRDM_POWER_OFF) { 381ecf157d0STero Kristo if (core_next_state == PWRDM_POWER_ON) { 382ecf157d0STero Kristo per_next_state = PWRDM_POWER_RET; 383ecf157d0STero Kristo pwrdm_set_next_pwrst(per_pwrdm, per_next_state); 384ecf157d0STero Kristo per_state_modified = 1; 38543ffcd9aSKevin Hilman } else 3862f5939c3SRajendra Nayak omap3_per_save_context(); 3872f5939c3SRajendra Nayak } 388ecf157d0STero Kristo } 389658ce97eSKevin Hilman 390c16c3f67STero Kristo if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON) 391c16c3f67STero Kristo omap2_clkdm_deny_idle(mpu_pwrdm->pwrdm_clkdms[0]); 392c16c3f67STero Kristo 393658ce97eSKevin Hilman /* CORE */ 394658ce97eSKevin Hilman if (core_next_state < PWRDM_POWER_ON) { 395658ce97eSKevin Hilman omap_uart_prepare_idle(0); 396658ce97eSKevin Hilman omap_uart_prepare_idle(1); 3972f5939c3SRajendra Nayak if (core_next_state == PWRDM_POWER_OFF) { 3982f5939c3SRajendra Nayak omap3_core_save_context(); 3992f5939c3SRajendra Nayak omap3_prcm_save_context(); 4002f5939c3SRajendra Nayak } 4013a7ec26bSKalle Jokiniemi /* Enable IO-PAD and IO-CHAIN wakeups */ 402fa3c2a4fSRajendra Nayak prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN); 4033a7ec26bSKalle Jokiniemi omap3_enable_io_chain(); 404fa3c2a4fSRajendra Nayak } 405f18cc2ffSTero Kristo omap3_intc_prepare_idle(); 4068bd22949SKevin Hilman 40761255ab9SRajendra Nayak /* 408f265dc4cSRajendra Nayak * On EMU/HS devices ROM code restores a SRDC value 409f265dc4cSRajendra Nayak * from scratchpad which has automatic self refresh on timeout 410f265dc4cSRajendra Nayak * of AUTO_CNT = 1 enabled. This takes care of errata 1.142. 411f265dc4cSRajendra Nayak * Hence store/restore the SDRC_POWER register here. 41213a6fe0fSTero Kristo */ 41313a6fe0fSTero Kristo if (omap_rev() >= OMAP3430_REV_ES3_0 && 41413a6fe0fSTero Kristo omap_type() != OMAP2_DEVICE_TYPE_GP && 415f265dc4cSRajendra Nayak core_next_state == PWRDM_POWER_OFF) 41613a6fe0fSTero Kristo sdrc_pwr = sdrc_read_reg(SDRC_POWER); 41713a6fe0fSTero Kristo 41813a6fe0fSTero Kristo /* 41961255ab9SRajendra Nayak * omap3_arm_context is the location where ARM registers 42061255ab9SRajendra Nayak * get saved. The restore path then reads from this 42161255ab9SRajendra Nayak * location and restores them back. 42261255ab9SRajendra Nayak */ 42361255ab9SRajendra Nayak _omap_sram_idle(omap3_arm_context, save_state); 4248bd22949SKevin Hilman cpu_init(); 4258bd22949SKevin Hilman 426f265dc4cSRajendra Nayak /* Restore normal SDRC POWER settings */ 42713a6fe0fSTero Kristo if (omap_rev() >= OMAP3430_REV_ES3_0 && 42813a6fe0fSTero Kristo omap_type() != OMAP2_DEVICE_TYPE_GP && 42913a6fe0fSTero Kristo core_next_state == PWRDM_POWER_OFF) 43013a6fe0fSTero Kristo sdrc_write_reg(sdrc_pwr, SDRC_POWER); 43113a6fe0fSTero Kristo 43257f277b0SRajendra Nayak /* Restore table entry modified during MMU restoration */ 43357f277b0SRajendra Nayak if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF) 43457f277b0SRajendra Nayak restore_table_entry(); 43557f277b0SRajendra Nayak 436658ce97eSKevin Hilman /* CORE */ 437fa3c2a4fSRajendra Nayak if (core_next_state < PWRDM_POWER_ON) { 4382f5939c3SRajendra Nayak core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); 4392f5939c3SRajendra Nayak if (core_prev_state == PWRDM_POWER_OFF) { 4402f5939c3SRajendra Nayak omap3_core_restore_context(); 4412f5939c3SRajendra Nayak omap3_prcm_restore_context(); 4422f5939c3SRajendra Nayak omap3_sram_restore_context(); 4438a917d2fSKalle Jokiniemi omap2_sms_restore_context(); 4442f5939c3SRajendra Nayak } 445658ce97eSKevin Hilman omap_uart_resume_idle(0); 446658ce97eSKevin Hilman omap_uart_resume_idle(1); 447658ce97eSKevin Hilman if (core_next_state == PWRDM_POWER_OFF) 448658ce97eSKevin Hilman prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF, 449658ce97eSKevin Hilman OMAP3430_GR_MOD, 450658ce97eSKevin Hilman OMAP3_PRM_VOLTCTRL_OFFSET); 451658ce97eSKevin Hilman } 452f18cc2ffSTero Kristo omap3_intc_resume_idle(); 453658ce97eSKevin Hilman 454658ce97eSKevin Hilman /* PER */ 4552f5939c3SRajendra Nayak if (per_next_state < PWRDM_POWER_ON) { 456658ce97eSKevin Hilman per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); 45743ffcd9aSKevin Hilman omap2_gpio_resume_after_idle(); 45843ffcd9aSKevin Hilman if (per_prev_state == PWRDM_POWER_OFF) 4592f5939c3SRajendra Nayak omap3_per_restore_context(); 460ecf157d0STero Kristo omap_uart_resume_idle(2); 461ecf157d0STero Kristo if (per_state_modified) 462ecf157d0STero Kristo pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF); 463fa3c2a4fSRajendra Nayak } 464fe617af7SPeter 'p2' De Schrijver 4653a7ec26bSKalle Jokiniemi /* Disable IO-PAD and IO-CHAIN wakeup */ 4663a7ec26bSKalle Jokiniemi if (core_next_state < PWRDM_POWER_ON) { 467658ce97eSKevin Hilman prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN); 4683a7ec26bSKalle Jokiniemi omap3_disable_io_chain(); 4693a7ec26bSKalle Jokiniemi } 470658ce97eSKevin Hilman 471fe617af7SPeter 'p2' De Schrijver pwrdm_post_transition(); 472fe617af7SPeter 'p2' De Schrijver 473c16c3f67STero Kristo omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); 4748bd22949SKevin Hilman } 4758bd22949SKevin Hilman 47620b01669SRajendra Nayak int omap3_can_sleep(void) 4778bd22949SKevin Hilman { 478c40552bcSKevin Hilman if (!sleep_while_idle) 479c40552bcSKevin Hilman return 0; 4804af4016cSKevin Hilman if (!omap_uart_can_sleep()) 4814af4016cSKevin Hilman return 0; 4828bd22949SKevin Hilman return 1; 4838bd22949SKevin Hilman } 4848bd22949SKevin Hilman 4858bd22949SKevin Hilman /* This sets pwrdm state (other than mpu & core. Currently only ON & 4868bd22949SKevin Hilman * RET are supported. Function is assuming that clkdm doesn't have 4878bd22949SKevin Hilman * hw_sup mode enabled. */ 48820b01669SRajendra Nayak int set_pwrdm_state(struct powerdomain *pwrdm, u32 state) 4898bd22949SKevin Hilman { 4908bd22949SKevin Hilman u32 cur_state; 4918bd22949SKevin Hilman int sleep_switch = 0; 4928bd22949SKevin Hilman int ret = 0; 4938bd22949SKevin Hilman 4948bd22949SKevin Hilman if (pwrdm == NULL || IS_ERR(pwrdm)) 4958bd22949SKevin Hilman return -EINVAL; 4968bd22949SKevin Hilman 4978bd22949SKevin Hilman while (!(pwrdm->pwrsts & (1 << state))) { 4988bd22949SKevin Hilman if (state == PWRDM_POWER_OFF) 4998bd22949SKevin Hilman return ret; 5008bd22949SKevin Hilman state--; 5018bd22949SKevin Hilman } 5028bd22949SKevin Hilman 5038bd22949SKevin Hilman cur_state = pwrdm_read_next_pwrst(pwrdm); 5048bd22949SKevin Hilman if (cur_state == state) 5058bd22949SKevin Hilman return ret; 5068bd22949SKevin Hilman 5078bd22949SKevin Hilman if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) { 5088bd22949SKevin Hilman omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); 5098bd22949SKevin Hilman sleep_switch = 1; 5108bd22949SKevin Hilman pwrdm_wait_transition(pwrdm); 5118bd22949SKevin Hilman } 5128bd22949SKevin Hilman 5138bd22949SKevin Hilman ret = pwrdm_set_next_pwrst(pwrdm, state); 5148bd22949SKevin Hilman if (ret) { 5158bd22949SKevin Hilman printk(KERN_ERR "Unable to set state of powerdomain: %s\n", 5168bd22949SKevin Hilman pwrdm->name); 5178bd22949SKevin Hilman goto err; 5188bd22949SKevin Hilman } 5198bd22949SKevin Hilman 5208bd22949SKevin Hilman if (sleep_switch) { 5218bd22949SKevin Hilman omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); 5228bd22949SKevin Hilman pwrdm_wait_transition(pwrdm); 523fe617af7SPeter 'p2' De Schrijver pwrdm_state_switch(pwrdm); 5248bd22949SKevin Hilman } 5258bd22949SKevin Hilman 5268bd22949SKevin Hilman err: 5278bd22949SKevin Hilman return ret; 5288bd22949SKevin Hilman } 5298bd22949SKevin Hilman 5308bd22949SKevin Hilman static void omap3_pm_idle(void) 5318bd22949SKevin Hilman { 5328bd22949SKevin Hilman local_irq_disable(); 5338bd22949SKevin Hilman local_fiq_disable(); 5348bd22949SKevin Hilman 5358bd22949SKevin Hilman if (!omap3_can_sleep()) 5368bd22949SKevin Hilman goto out; 5378bd22949SKevin Hilman 538cf22854cSTero Kristo if (omap_irq_pending() || need_resched()) 5398bd22949SKevin Hilman goto out; 5408bd22949SKevin Hilman 5418bd22949SKevin Hilman omap_sram_idle(); 5428bd22949SKevin Hilman 5438bd22949SKevin Hilman out: 5448bd22949SKevin Hilman local_fiq_enable(); 5458bd22949SKevin Hilman local_irq_enable(); 5468bd22949SKevin Hilman } 5478bd22949SKevin Hilman 54810f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 5492466211eSTero Kristo static suspend_state_t suspend_state; 5502466211eSTero Kristo 551d7814e4dSKevin Hilman static void omap2_pm_wakeup_on_timer(u32 seconds) 552d7814e4dSKevin Hilman { 553d7814e4dSKevin Hilman u32 tick_rate, cycles; 554d7814e4dSKevin Hilman 555d7814e4dSKevin Hilman if (!seconds) 556d7814e4dSKevin Hilman return; 557d7814e4dSKevin Hilman 558d7814e4dSKevin Hilman tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup)); 559d7814e4dSKevin Hilman cycles = tick_rate * seconds; 560d7814e4dSKevin Hilman omap_dm_timer_stop(gptimer_wakeup); 561d7814e4dSKevin Hilman omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles); 562d7814e4dSKevin Hilman 563d7814e4dSKevin Hilman pr_info("PM: Resume timer in %d secs (%d ticks at %d ticks/sec.)\n", 564d7814e4dSKevin Hilman seconds, cycles, tick_rate); 565d7814e4dSKevin Hilman } 566d7814e4dSKevin Hilman 5678bd22949SKevin Hilman static int omap3_pm_prepare(void) 5688bd22949SKevin Hilman { 5698bd22949SKevin Hilman disable_hlt(); 5708bd22949SKevin Hilman return 0; 5718bd22949SKevin Hilman } 5728bd22949SKevin Hilman 5738bd22949SKevin Hilman static int omap3_pm_suspend(void) 5748bd22949SKevin Hilman { 5758bd22949SKevin Hilman struct power_state *pwrst; 5768bd22949SKevin Hilman int state, ret = 0; 5778bd22949SKevin Hilman 578d7814e4dSKevin Hilman if (wakeup_timer_seconds) 579d7814e4dSKevin Hilman omap2_pm_wakeup_on_timer(wakeup_timer_seconds); 580d7814e4dSKevin Hilman 5818bd22949SKevin Hilman /* Read current next_pwrsts */ 5828bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) 5838bd22949SKevin Hilman pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 5848bd22949SKevin Hilman /* Set ones wanted by suspend */ 5858bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 5868bd22949SKevin Hilman if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) 5878bd22949SKevin Hilman goto restore; 5888bd22949SKevin Hilman if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) 5898bd22949SKevin Hilman goto restore; 5908bd22949SKevin Hilman } 5918bd22949SKevin Hilman 5924af4016cSKevin Hilman omap_uart_prepare_suspend(); 5932bbe3af3STero Kristo omap3_intc_suspend(); 5942bbe3af3STero Kristo 5958bd22949SKevin Hilman omap_sram_idle(); 5968bd22949SKevin Hilman 5978bd22949SKevin Hilman restore: 5988bd22949SKevin Hilman /* Restore next_pwrsts */ 5998bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 6008bd22949SKevin Hilman state = pwrdm_read_prev_pwrst(pwrst->pwrdm); 6018bd22949SKevin Hilman if (state > pwrst->next_state) { 6028bd22949SKevin Hilman printk(KERN_INFO "Powerdomain (%s) didn't enter " 6038bd22949SKevin Hilman "target state %d\n", 6048bd22949SKevin Hilman pwrst->pwrdm->name, pwrst->next_state); 6058bd22949SKevin Hilman ret = -1; 6068bd22949SKevin Hilman } 6076c5f8039SJouni Hogander set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); 6088bd22949SKevin Hilman } 6098bd22949SKevin Hilman if (ret) 6108bd22949SKevin Hilman printk(KERN_ERR "Could not enter target state in pm_suspend\n"); 6118bd22949SKevin Hilman else 6128bd22949SKevin Hilman printk(KERN_INFO "Successfully put all powerdomains " 6138bd22949SKevin Hilman "to target state\n"); 6148bd22949SKevin Hilman 6158bd22949SKevin Hilman return ret; 6168bd22949SKevin Hilman } 6178bd22949SKevin Hilman 6182466211eSTero Kristo static int omap3_pm_enter(suspend_state_t unused) 6198bd22949SKevin Hilman { 6208bd22949SKevin Hilman int ret = 0; 6218bd22949SKevin Hilman 6222466211eSTero Kristo switch (suspend_state) { 6238bd22949SKevin Hilman case PM_SUSPEND_STANDBY: 6248bd22949SKevin Hilman case PM_SUSPEND_MEM: 6258bd22949SKevin Hilman ret = omap3_pm_suspend(); 6268bd22949SKevin Hilman break; 6278bd22949SKevin Hilman default: 6288bd22949SKevin Hilman ret = -EINVAL; 6298bd22949SKevin Hilman } 6308bd22949SKevin Hilman 6318bd22949SKevin Hilman return ret; 6328bd22949SKevin Hilman } 6338bd22949SKevin Hilman 6348bd22949SKevin Hilman static void omap3_pm_finish(void) 6358bd22949SKevin Hilman { 6368bd22949SKevin Hilman enable_hlt(); 6378bd22949SKevin Hilman } 6388bd22949SKevin Hilman 6392466211eSTero Kristo /* Hooks to enable / disable UART interrupts during suspend */ 6402466211eSTero Kristo static int omap3_pm_begin(suspend_state_t state) 6412466211eSTero Kristo { 6422466211eSTero Kristo suspend_state = state; 6432466211eSTero Kristo omap_uart_enable_irqs(0); 6442466211eSTero Kristo return 0; 6452466211eSTero Kristo } 6462466211eSTero Kristo 6472466211eSTero Kristo static void omap3_pm_end(void) 6482466211eSTero Kristo { 6492466211eSTero Kristo suspend_state = PM_SUSPEND_ON; 6502466211eSTero Kristo omap_uart_enable_irqs(1); 6512466211eSTero Kristo return; 6522466211eSTero Kristo } 6532466211eSTero Kristo 6548bd22949SKevin Hilman static struct platform_suspend_ops omap_pm_ops = { 6552466211eSTero Kristo .begin = omap3_pm_begin, 6562466211eSTero Kristo .end = omap3_pm_end, 6578bd22949SKevin Hilman .prepare = omap3_pm_prepare, 6588bd22949SKevin Hilman .enter = omap3_pm_enter, 6598bd22949SKevin Hilman .finish = omap3_pm_finish, 6608bd22949SKevin Hilman .valid = suspend_valid_only_mem, 6618bd22949SKevin Hilman }; 66210f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 6638bd22949SKevin Hilman 6641155e426SKevin Hilman 6651155e426SKevin Hilman /** 6661155e426SKevin Hilman * omap3_iva_idle(): ensure IVA is in idle so it can be put into 6671155e426SKevin Hilman * retention 6681155e426SKevin Hilman * 6691155e426SKevin Hilman * In cases where IVA2 is activated by bootcode, it may prevent 6701155e426SKevin Hilman * full-chip retention or off-mode because it is not idle. This 6711155e426SKevin Hilman * function forces the IVA2 into idle state so it can go 6721155e426SKevin Hilman * into retention/off and thus allow full-chip retention/off. 6731155e426SKevin Hilman * 6741155e426SKevin Hilman **/ 6751155e426SKevin Hilman static void __init omap3_iva_idle(void) 6761155e426SKevin Hilman { 6771155e426SKevin Hilman /* ensure IVA2 clock is disabled */ 6781155e426SKevin Hilman cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 6791155e426SKevin Hilman 6801155e426SKevin Hilman /* if no clock activity, nothing else to do */ 6811155e426SKevin Hilman if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & 6821155e426SKevin Hilman OMAP3430_CLKACTIVITY_IVA2_MASK)) 6831155e426SKevin Hilman return; 6841155e426SKevin Hilman 6851155e426SKevin Hilman /* Reset IVA2 */ 6861155e426SKevin Hilman prm_write_mod_reg(OMAP3430_RST1_IVA2 | 6871155e426SKevin Hilman OMAP3430_RST2_IVA2 | 6881155e426SKevin Hilman OMAP3430_RST3_IVA2, 68937903009SAbhijit Pagare OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 6901155e426SKevin Hilman 6911155e426SKevin Hilman /* Enable IVA2 clock */ 692dfa6d6f8SKevin Hilman cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, 6931155e426SKevin Hilman OMAP3430_IVA2_MOD, CM_FCLKEN); 6941155e426SKevin Hilman 6951155e426SKevin Hilman /* Set IVA2 boot mode to 'idle' */ 6961155e426SKevin Hilman omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, 6971155e426SKevin Hilman OMAP343X_CONTROL_IVA2_BOOTMOD); 6981155e426SKevin Hilman 6991155e426SKevin Hilman /* Un-reset IVA2 */ 70037903009SAbhijit Pagare prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 7011155e426SKevin Hilman 7021155e426SKevin Hilman /* Disable IVA2 clock */ 7031155e426SKevin Hilman cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 7041155e426SKevin Hilman 7051155e426SKevin Hilman /* Reset IVA2 */ 7061155e426SKevin Hilman prm_write_mod_reg(OMAP3430_RST1_IVA2 | 7071155e426SKevin Hilman OMAP3430_RST2_IVA2 | 7081155e426SKevin Hilman OMAP3430_RST3_IVA2, 70937903009SAbhijit Pagare OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 7101155e426SKevin Hilman } 7111155e426SKevin Hilman 7128111b221SKevin Hilman static void __init omap3_d2d_idle(void) 7138bd22949SKevin Hilman { 7148111b221SKevin Hilman u16 mask, padconf; 7158111b221SKevin Hilman 7168111b221SKevin Hilman /* In a stand alone OMAP3430 where there is not a stacked 7178111b221SKevin Hilman * modem for the D2D Idle Ack and D2D MStandby must be pulled 7188111b221SKevin Hilman * high. S CONTROL_PADCONF_SAD2D_IDLEACK and 7198111b221SKevin Hilman * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ 7208111b221SKevin Hilman mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ 7218111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); 7228111b221SKevin Hilman padconf |= mask; 7238111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); 7248111b221SKevin Hilman 7258111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); 7268111b221SKevin Hilman padconf |= mask; 7278111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 7288111b221SKevin Hilman 7298bd22949SKevin Hilman /* reset modem */ 7308bd22949SKevin Hilman prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON | 7318bd22949SKevin Hilman OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST, 73237903009SAbhijit Pagare CORE_MOD, OMAP2_RM_RSTCTRL); 73337903009SAbhijit Pagare prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); 7348111b221SKevin Hilman } 7358bd22949SKevin Hilman 7368111b221SKevin Hilman static void __init prcm_setup_regs(void) 7378111b221SKevin Hilman { 7388bd22949SKevin Hilman /* XXX Reset all wkdeps. This should be done when initializing 7398bd22949SKevin Hilman * powerdomains */ 7408bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); 7418bd22949SKevin Hilman prm_write_mod_reg(0, MPU_MOD, PM_WKDEP); 7428bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP); 7438bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP); 7448bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP); 7458bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP); 7468bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 7478bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP); 7488bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP); 7498bd22949SKevin Hilman } else 7508bd22949SKevin Hilman prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); 7518bd22949SKevin Hilman 7528bd22949SKevin Hilman /* 7538bd22949SKevin Hilman * Enable interface clock autoidle for all modules. 7548bd22949SKevin Hilman * Note that in the long run this should be done by clockfw 7558bd22949SKevin Hilman */ 7568bd22949SKevin Hilman cm_write_mod_reg( 7578111b221SKevin Hilman OMAP3430_AUTO_MODEM | 7588bd22949SKevin Hilman OMAP3430ES2_AUTO_MMC3 | 7598bd22949SKevin Hilman OMAP3430ES2_AUTO_ICR | 7608bd22949SKevin Hilman OMAP3430_AUTO_AES2 | 7618bd22949SKevin Hilman OMAP3430_AUTO_SHA12 | 7628bd22949SKevin Hilman OMAP3430_AUTO_DES2 | 7638bd22949SKevin Hilman OMAP3430_AUTO_MMC2 | 7648bd22949SKevin Hilman OMAP3430_AUTO_MMC1 | 7658bd22949SKevin Hilman OMAP3430_AUTO_MSPRO | 7668bd22949SKevin Hilman OMAP3430_AUTO_HDQ | 7678bd22949SKevin Hilman OMAP3430_AUTO_MCSPI4 | 7688bd22949SKevin Hilman OMAP3430_AUTO_MCSPI3 | 7698bd22949SKevin Hilman OMAP3430_AUTO_MCSPI2 | 7708bd22949SKevin Hilman OMAP3430_AUTO_MCSPI1 | 7718bd22949SKevin Hilman OMAP3430_AUTO_I2C3 | 7728bd22949SKevin Hilman OMAP3430_AUTO_I2C2 | 7738bd22949SKevin Hilman OMAP3430_AUTO_I2C1 | 7748bd22949SKevin Hilman OMAP3430_AUTO_UART2 | 7758bd22949SKevin Hilman OMAP3430_AUTO_UART1 | 7768bd22949SKevin Hilman OMAP3430_AUTO_GPT11 | 7778bd22949SKevin Hilman OMAP3430_AUTO_GPT10 | 7788bd22949SKevin Hilman OMAP3430_AUTO_MCBSP5 | 7798bd22949SKevin Hilman OMAP3430_AUTO_MCBSP1 | 7808bd22949SKevin Hilman OMAP3430ES1_AUTO_FAC | /* This is es1 only */ 7818bd22949SKevin Hilman OMAP3430_AUTO_MAILBOXES | 7828bd22949SKevin Hilman OMAP3430_AUTO_OMAPCTRL | 7838bd22949SKevin Hilman OMAP3430ES1_AUTO_FSHOSTUSB | 7848bd22949SKevin Hilman OMAP3430_AUTO_HSOTGUSB | 7858111b221SKevin Hilman OMAP3430_AUTO_SAD2D | 7868bd22949SKevin Hilman OMAP3430_AUTO_SSI, 7878bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE1); 7888bd22949SKevin Hilman 7898bd22949SKevin Hilman cm_write_mod_reg( 7908bd22949SKevin Hilman OMAP3430_AUTO_PKA | 7918bd22949SKevin Hilman OMAP3430_AUTO_AES1 | 7928bd22949SKevin Hilman OMAP3430_AUTO_RNG | 7938bd22949SKevin Hilman OMAP3430_AUTO_SHA11 | 7948bd22949SKevin Hilman OMAP3430_AUTO_DES1, 7958bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE2); 7968bd22949SKevin Hilman 7978bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 7988bd22949SKevin Hilman cm_write_mod_reg( 7998111b221SKevin Hilman OMAP3430_AUTO_MAD2D | 8008bd22949SKevin Hilman OMAP3430ES2_AUTO_USBTLL, 8018bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE3); 8028bd22949SKevin Hilman } 8038bd22949SKevin Hilman 8048bd22949SKevin Hilman cm_write_mod_reg( 8058bd22949SKevin Hilman OMAP3430_AUTO_WDT2 | 8068bd22949SKevin Hilman OMAP3430_AUTO_WDT1 | 8078bd22949SKevin Hilman OMAP3430_AUTO_GPIO1 | 8088bd22949SKevin Hilman OMAP3430_AUTO_32KSYNC | 8098bd22949SKevin Hilman OMAP3430_AUTO_GPT12 | 8108bd22949SKevin Hilman OMAP3430_AUTO_GPT1 , 8118bd22949SKevin Hilman WKUP_MOD, CM_AUTOIDLE); 8128bd22949SKevin Hilman 8138bd22949SKevin Hilman cm_write_mod_reg( 8148bd22949SKevin Hilman OMAP3430_AUTO_DSS, 8158bd22949SKevin Hilman OMAP3430_DSS_MOD, 8168bd22949SKevin Hilman CM_AUTOIDLE); 8178bd22949SKevin Hilman 8188bd22949SKevin Hilman cm_write_mod_reg( 8198bd22949SKevin Hilman OMAP3430_AUTO_CAM, 8208bd22949SKevin Hilman OMAP3430_CAM_MOD, 8218bd22949SKevin Hilman CM_AUTOIDLE); 8228bd22949SKevin Hilman 8238bd22949SKevin Hilman cm_write_mod_reg( 8248bd22949SKevin Hilman OMAP3430_AUTO_GPIO6 | 8258bd22949SKevin Hilman OMAP3430_AUTO_GPIO5 | 8268bd22949SKevin Hilman OMAP3430_AUTO_GPIO4 | 8278bd22949SKevin Hilman OMAP3430_AUTO_GPIO3 | 8288bd22949SKevin Hilman OMAP3430_AUTO_GPIO2 | 8298bd22949SKevin Hilman OMAP3430_AUTO_WDT3 | 8308bd22949SKevin Hilman OMAP3430_AUTO_UART3 | 8318bd22949SKevin Hilman OMAP3430_AUTO_GPT9 | 8328bd22949SKevin Hilman OMAP3430_AUTO_GPT8 | 8338bd22949SKevin Hilman OMAP3430_AUTO_GPT7 | 8348bd22949SKevin Hilman OMAP3430_AUTO_GPT6 | 8358bd22949SKevin Hilman OMAP3430_AUTO_GPT5 | 8368bd22949SKevin Hilman OMAP3430_AUTO_GPT4 | 8378bd22949SKevin Hilman OMAP3430_AUTO_GPT3 | 8388bd22949SKevin Hilman OMAP3430_AUTO_GPT2 | 8398bd22949SKevin Hilman OMAP3430_AUTO_MCBSP4 | 8408bd22949SKevin Hilman OMAP3430_AUTO_MCBSP3 | 8418bd22949SKevin Hilman OMAP3430_AUTO_MCBSP2, 8428bd22949SKevin Hilman OMAP3430_PER_MOD, 8438bd22949SKevin Hilman CM_AUTOIDLE); 8448bd22949SKevin Hilman 8458bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 8468bd22949SKevin Hilman cm_write_mod_reg( 8478bd22949SKevin Hilman OMAP3430ES2_AUTO_USBHOST, 8488bd22949SKevin Hilman OMAP3430ES2_USBHOST_MOD, 8498bd22949SKevin Hilman CM_AUTOIDLE); 8508bd22949SKevin Hilman } 8518bd22949SKevin Hilman 852b296c811STero Kristo omap_ctrl_writel(OMAP3430_AUTOIDLE, OMAP2_CONTROL_SYSCONFIG); 853b296c811STero Kristo 8548bd22949SKevin Hilman /* 8558bd22949SKevin Hilman * Set all plls to autoidle. This is needed until autoidle is 8568bd22949SKevin Hilman * enabled by clockfw 8578bd22949SKevin Hilman */ 8588bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, 8598bd22949SKevin Hilman OMAP3430_IVA2_MOD, CM_AUTOIDLE2); 8608bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT, 8618bd22949SKevin Hilman MPU_MOD, 8628bd22949SKevin Hilman CM_AUTOIDLE2); 8638bd22949SKevin Hilman cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | 8648bd22949SKevin Hilman (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT), 8658bd22949SKevin Hilman PLL_MOD, 8668bd22949SKevin Hilman CM_AUTOIDLE); 8678bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, 8688bd22949SKevin Hilman PLL_MOD, 8698bd22949SKevin Hilman CM_AUTOIDLE2); 8708bd22949SKevin Hilman 8718bd22949SKevin Hilman /* 8728bd22949SKevin Hilman * Enable control of expternal oscillator through 8738bd22949SKevin Hilman * sys_clkreq. In the long run clock framework should 8748bd22949SKevin Hilman * take care of this. 8758bd22949SKevin Hilman */ 8768bd22949SKevin Hilman prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 8778bd22949SKevin Hilman 1 << OMAP_AUTOEXTCLKMODE_SHIFT, 8788bd22949SKevin Hilman OMAP3430_GR_MOD, 8798bd22949SKevin Hilman OMAP3_PRM_CLKSRC_CTRL_OFFSET); 8808bd22949SKevin Hilman 8818bd22949SKevin Hilman /* setup wakup source */ 8828bd22949SKevin Hilman prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 | 8838bd22949SKevin Hilman OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12, 8848bd22949SKevin Hilman WKUP_MOD, PM_WKEN); 8858bd22949SKevin Hilman /* No need to write EN_IO, that is always enabled */ 8868bd22949SKevin Hilman prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 | 8878bd22949SKevin Hilman OMAP3430_EN_GPT12, 8888bd22949SKevin Hilman WKUP_MOD, OMAP3430_PM_MPUGRPSEL); 8898bd22949SKevin Hilman /* For some reason IO doesn't generate wakeup event even if 8908bd22949SKevin Hilman * it is selected to mpu wakeup goup */ 8918bd22949SKevin Hilman prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN, 8928bd22949SKevin Hilman OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); 8931155e426SKevin Hilman 894b92c5721SSubramani Venkatesh /* Enable PM_WKEN to support DSS LPR */ 895b92c5721SSubramani Venkatesh prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS, 896b92c5721SSubramani Venkatesh OMAP3430_DSS_MOD, PM_WKEN); 897b92c5721SSubramani Venkatesh 898b427f92fSKevin Hilman /* Enable wakeups in PER */ 899eb350f74SKevin Hilman prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 | 900eb350f74SKevin Hilman OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 | 901e3d93296SPeter Ujfalusi OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3 | 902e3d93296SPeter Ujfalusi OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 | 903e3d93296SPeter Ujfalusi OMAP3430_EN_MCBSP4, 904b427f92fSKevin Hilman OMAP3430_PER_MOD, PM_WKEN); 905eb350f74SKevin Hilman /* and allow them to wake up MPU */ 906eb350f74SKevin Hilman prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 | 907eb350f74SKevin Hilman OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 | 908e3d93296SPeter Ujfalusi OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3 | 909e3d93296SPeter Ujfalusi OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 | 910e3d93296SPeter Ujfalusi OMAP3430_EN_MCBSP4, 911eb350f74SKevin Hilman OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); 912eb350f74SKevin Hilman 913d3fd3290SKevin Hilman /* Don't attach IVA interrupts */ 914d3fd3290SKevin Hilman prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 915d3fd3290SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 916d3fd3290SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 917d3fd3290SKevin Hilman prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); 918d3fd3290SKevin Hilman 919b1340d17SKevin Hilman /* Clear any pending 'reset' flags */ 92037903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); 92137903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); 92237903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); 92337903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); 92437903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); 92537903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); 92637903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); 927b1340d17SKevin Hilman 928014c46dbSKevin Hilman /* Clear any pending PRCM interrupts */ 929014c46dbSKevin Hilman prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 930014c46dbSKevin Hilman 9311155e426SKevin Hilman omap3_iva_idle(); 9328111b221SKevin Hilman omap3_d2d_idle(); 9338bd22949SKevin Hilman } 9348bd22949SKevin Hilman 935c40552bcSKevin Hilman void omap3_pm_off_mode_enable(int enable) 936c40552bcSKevin Hilman { 937c40552bcSKevin Hilman struct power_state *pwrst; 938c40552bcSKevin Hilman u32 state; 939c40552bcSKevin Hilman 940c40552bcSKevin Hilman if (enable) 941c40552bcSKevin Hilman state = PWRDM_POWER_OFF; 942c40552bcSKevin Hilman else 943c40552bcSKevin Hilman state = PWRDM_POWER_RET; 944c40552bcSKevin Hilman 9456af83b38SSanjeev Premi #ifdef CONFIG_CPU_IDLE 9466af83b38SSanjeev Premi omap3_cpuidle_update_states(); 9476af83b38SSanjeev Premi #endif 9486af83b38SSanjeev Premi 949c40552bcSKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 950c40552bcSKevin Hilman pwrst->next_state = state; 951c40552bcSKevin Hilman set_pwrdm_state(pwrst->pwrdm, state); 952c40552bcSKevin Hilman } 953c40552bcSKevin Hilman } 954c40552bcSKevin Hilman 95568d4778cSTero Kristo int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) 95668d4778cSTero Kristo { 95768d4778cSTero Kristo struct power_state *pwrst; 95868d4778cSTero Kristo 95968d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 96068d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) 96168d4778cSTero Kristo return pwrst->next_state; 96268d4778cSTero Kristo } 96368d4778cSTero Kristo return -EINVAL; 96468d4778cSTero Kristo } 96568d4778cSTero Kristo 96668d4778cSTero Kristo int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) 96768d4778cSTero Kristo { 96868d4778cSTero Kristo struct power_state *pwrst; 96968d4778cSTero Kristo 97068d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 97168d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) { 97268d4778cSTero Kristo pwrst->next_state = state; 97368d4778cSTero Kristo return 0; 97468d4778cSTero Kristo } 97568d4778cSTero Kristo } 97668d4778cSTero Kristo return -EINVAL; 97768d4778cSTero Kristo } 97868d4778cSTero Kristo 979a23456e9SPeter 'p2' De Schrijver static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) 9808bd22949SKevin Hilman { 9818bd22949SKevin Hilman struct power_state *pwrst; 9828bd22949SKevin Hilman 9838bd22949SKevin Hilman if (!pwrdm->pwrsts) 9848bd22949SKevin Hilman return 0; 9858bd22949SKevin Hilman 986d3d381c6SMing Lei pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); 9878bd22949SKevin Hilman if (!pwrst) 9888bd22949SKevin Hilman return -ENOMEM; 9898bd22949SKevin Hilman pwrst->pwrdm = pwrdm; 9908bd22949SKevin Hilman pwrst->next_state = PWRDM_POWER_RET; 9918bd22949SKevin Hilman list_add(&pwrst->node, &pwrst_list); 9928bd22949SKevin Hilman 9938bd22949SKevin Hilman if (pwrdm_has_hdwr_sar(pwrdm)) 9948bd22949SKevin Hilman pwrdm_enable_hdwr_sar(pwrdm); 9958bd22949SKevin Hilman 9968bd22949SKevin Hilman return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 9978bd22949SKevin Hilman } 9988bd22949SKevin Hilman 9998bd22949SKevin Hilman /* 10008bd22949SKevin Hilman * Enable hw supervised mode for all clockdomains if it's 10018bd22949SKevin Hilman * supported. Initiate sleep transition for other clockdomains, if 10028bd22949SKevin Hilman * they are not used 10038bd22949SKevin Hilman */ 1004a23456e9SPeter 'p2' De Schrijver static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) 10058bd22949SKevin Hilman { 1006369d5614SPaul Walmsley clkdm_clear_all_wkdeps(clkdm); 1007369d5614SPaul Walmsley clkdm_clear_all_sleepdeps(clkdm); 1008369d5614SPaul Walmsley 10098bd22949SKevin Hilman if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) 10108bd22949SKevin Hilman omap2_clkdm_allow_idle(clkdm); 10118bd22949SKevin Hilman else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && 10128bd22949SKevin Hilman atomic_read(&clkdm->usecount) == 0) 10138bd22949SKevin Hilman omap2_clkdm_sleep(clkdm); 10148bd22949SKevin Hilman return 0; 10158bd22949SKevin Hilman } 10168bd22949SKevin Hilman 10173231fc88SRajendra Nayak void omap_push_sram_idle(void) 10183231fc88SRajendra Nayak { 10193231fc88SRajendra Nayak _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend, 10203231fc88SRajendra Nayak omap34xx_cpu_suspend_sz); 102127d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) 102227d59a4aSTero Kristo _omap_save_secure_sram = omap_sram_push(save_secure_ram_context, 102327d59a4aSTero Kristo save_secure_ram_context_sz); 10243231fc88SRajendra Nayak } 10253231fc88SRajendra Nayak 10267cc515f7SKevin Hilman static int __init omap3_pm_init(void) 10278bd22949SKevin Hilman { 10288bd22949SKevin Hilman struct power_state *pwrst, *tmp; 102955ed9694SPaul Walmsley struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm; 10308bd22949SKevin Hilman int ret; 10318bd22949SKevin Hilman 10328bd22949SKevin Hilman if (!cpu_is_omap34xx()) 10338bd22949SKevin Hilman return -ENODEV; 10348bd22949SKevin Hilman 10358bd22949SKevin Hilman printk(KERN_ERR "Power Management for TI OMAP3.\n"); 10368bd22949SKevin Hilman 10378bd22949SKevin Hilman /* XXX prcm_setup_regs needs to be before enabling hw 10388bd22949SKevin Hilman * supervised mode for powerdomains */ 10398bd22949SKevin Hilman prcm_setup_regs(); 10408bd22949SKevin Hilman 10418bd22949SKevin Hilman ret = request_irq(INT_34XX_PRCM_MPU_IRQ, 10428bd22949SKevin Hilman (irq_handler_t)prcm_interrupt_handler, 10438bd22949SKevin Hilman IRQF_DISABLED, "prcm", NULL); 10448bd22949SKevin Hilman if (ret) { 10458bd22949SKevin Hilman printk(KERN_ERR "request_irq failed to register for 0x%x\n", 10468bd22949SKevin Hilman INT_34XX_PRCM_MPU_IRQ); 10478bd22949SKevin Hilman goto err1; 10488bd22949SKevin Hilman } 10498bd22949SKevin Hilman 1050a23456e9SPeter 'p2' De Schrijver ret = pwrdm_for_each(pwrdms_setup, NULL); 10518bd22949SKevin Hilman if (ret) { 10528bd22949SKevin Hilman printk(KERN_ERR "Failed to setup powerdomains\n"); 10538bd22949SKevin Hilman goto err2; 10548bd22949SKevin Hilman } 10558bd22949SKevin Hilman 1056a23456e9SPeter 'p2' De Schrijver (void) clkdm_for_each(clkdms_setup, NULL); 10578bd22949SKevin Hilman 10588bd22949SKevin Hilman mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); 10598bd22949SKevin Hilman if (mpu_pwrdm == NULL) { 10608bd22949SKevin Hilman printk(KERN_ERR "Failed to get mpu_pwrdm\n"); 10618bd22949SKevin Hilman goto err2; 10628bd22949SKevin Hilman } 10638bd22949SKevin Hilman 1064fa3c2a4fSRajendra Nayak neon_pwrdm = pwrdm_lookup("neon_pwrdm"); 1065fa3c2a4fSRajendra Nayak per_pwrdm = pwrdm_lookup("per_pwrdm"); 1066fa3c2a4fSRajendra Nayak core_pwrdm = pwrdm_lookup("core_pwrdm"); 1067c16c3f67STero Kristo cam_pwrdm = pwrdm_lookup("cam_pwrdm"); 1068fa3c2a4fSRajendra Nayak 106955ed9694SPaul Walmsley neon_clkdm = clkdm_lookup("neon_clkdm"); 107055ed9694SPaul Walmsley mpu_clkdm = clkdm_lookup("mpu_clkdm"); 107155ed9694SPaul Walmsley per_clkdm = clkdm_lookup("per_clkdm"); 107255ed9694SPaul Walmsley core_clkdm = clkdm_lookup("core_clkdm"); 107355ed9694SPaul Walmsley 10743231fc88SRajendra Nayak omap_push_sram_idle(); 107510f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 10768bd22949SKevin Hilman suspend_set_ops(&omap_pm_ops); 107710f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 10788bd22949SKevin Hilman 10798bd22949SKevin Hilman pm_idle = omap3_pm_idle; 10800343371eSKalle Jokiniemi omap3_idle_init(); 10818bd22949SKevin Hilman 108255ed9694SPaul Walmsley clkdm_add_wkdep(neon_clkdm, mpu_clkdm); 1083fa3c2a4fSRajendra Nayak /* 1084fa3c2a4fSRajendra Nayak * REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for 1085fa3c2a4fSRajendra Nayak * IO-pad wakeup. Otherwise it will unnecessarily waste power 1086fa3c2a4fSRajendra Nayak * waking up PER with every CORE wakeup - see 1087fa3c2a4fSRajendra Nayak * http://marc.info/?l=linux-omap&m=121852150710062&w=2 1088fa3c2a4fSRajendra Nayak */ 108955ed9694SPaul Walmsley clkdm_add_wkdep(per_clkdm, core_clkdm); 1090fa3c2a4fSRajendra Nayak 109127d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 109227d59a4aSTero Kristo omap3_secure_ram_storage = 109327d59a4aSTero Kristo kmalloc(0x803F, GFP_KERNEL); 109427d59a4aSTero Kristo if (!omap3_secure_ram_storage) 109527d59a4aSTero Kristo printk(KERN_ERR "Memory allocation failed when" 109627d59a4aSTero Kristo "allocating for secure sram context\n"); 109727d59a4aSTero Kristo 10989d97140bSTero Kristo local_irq_disable(); 10999d97140bSTero Kristo local_fiq_disable(); 11009d97140bSTero Kristo 11019d97140bSTero Kristo omap_dma_global_context_save(); 11029d97140bSTero Kristo omap3_save_secure_ram_context(PWRDM_POWER_ON); 11039d97140bSTero Kristo omap_dma_global_context_restore(); 11049d97140bSTero Kristo 11059d97140bSTero Kristo local_irq_enable(); 11069d97140bSTero Kristo local_fiq_enable(); 11079d97140bSTero Kristo } 11089d97140bSTero Kristo 11099d97140bSTero Kristo omap3_save_scratchpad_contents(); 11108bd22949SKevin Hilman err1: 11118bd22949SKevin Hilman return ret; 11128bd22949SKevin Hilman err2: 11138bd22949SKevin Hilman free_irq(INT_34XX_PRCM_MPU_IRQ, NULL); 11148bd22949SKevin Hilman list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { 11158bd22949SKevin Hilman list_del(&pwrst->node); 11168bd22949SKevin Hilman kfree(pwrst); 11178bd22949SKevin Hilman } 11188bd22949SKevin Hilman return ret; 11198bd22949SKevin Hilman } 11208bd22949SKevin Hilman 11218bd22949SKevin Hilman late_initcall(omap3_pm_init); 1122