18bd22949SKevin Hilman /* 28bd22949SKevin Hilman * OMAP3 Power Management Routines 38bd22949SKevin Hilman * 48bd22949SKevin Hilman * Copyright (C) 2006-2008 Nokia Corporation 58bd22949SKevin Hilman * Tony Lindgren <tony@atomide.com> 68bd22949SKevin Hilman * Jouni Hogander 78bd22949SKevin Hilman * 82f5939c3SRajendra Nayak * Copyright (C) 2007 Texas Instruments, Inc. 92f5939c3SRajendra Nayak * Rajendra Nayak <rnayak@ti.com> 102f5939c3SRajendra Nayak * 118bd22949SKevin Hilman * Copyright (C) 2005 Texas Instruments, Inc. 128bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 138bd22949SKevin Hilman * 148bd22949SKevin Hilman * Based on pm.c for omap1 158bd22949SKevin Hilman * 168bd22949SKevin Hilman * This program is free software; you can redistribute it and/or modify 178bd22949SKevin Hilman * it under the terms of the GNU General Public License version 2 as 188bd22949SKevin Hilman * published by the Free Software Foundation. 198bd22949SKevin Hilman */ 208bd22949SKevin Hilman 218bd22949SKevin Hilman #include <linux/pm.h> 228bd22949SKevin Hilman #include <linux/suspend.h> 238bd22949SKevin Hilman #include <linux/interrupt.h> 248bd22949SKevin Hilman #include <linux/module.h> 258bd22949SKevin Hilman #include <linux/list.h> 268bd22949SKevin Hilman #include <linux/err.h> 278bd22949SKevin Hilman #include <linux/gpio.h> 28c40552bcSKevin Hilman #include <linux/clk.h> 29dccaad89STero Kristo #include <linux/delay.h> 305a0e3ad6STejun Heo #include <linux/slab.h> 3145c3eb7dSTony Lindgren #include <linux/omap-dma.h> 324b25408fSTony Lindgren #include <linux/platform_data/gpio-omap.h> 334b25408fSTony Lindgren 345e7c58dcSJean Pihet #include <trace/events/power.h> 358bd22949SKevin Hilman 36bf027ca1STony Lindgren #include <asm/fncpy.h> 372c74a0ceSRussell King #include <asm/suspend.h> 389f97da78SDavid Howells #include <asm/system_misc.h> 392c74a0ceSRussell King 401540f214SPaul Walmsley #include "clockdomain.h" 4172e06d08SPaul Walmsley #include "powerdomain.h" 42e4c060dbSTony Lindgren #include "soc.h" 434e65331cSTony Lindgren #include "common.h" 44ff4ae5d9SPaul Walmsley #include "cm3xxx.h" 458bd22949SKevin Hilman #include "cm-regbits-34xx.h" 4699f0b8d6STony Lindgren #include "gpmc.h" 478bd22949SKevin Hilman #include "prm-regbits-34xx.h" 48139563adSPaul Walmsley #include "prm3xxx.h" 498bd22949SKevin Hilman #include "pm.h" 5013a6fe0fSTero Kristo #include "sdrc.h" 51bf027ca1STony Lindgren #include "sram.h" 524814ced5SPaul Walmsley #include "control.h" 533b8c4ebbSTony Lindgren #include "vc.h" 5413a6fe0fSTero Kristo 558cdfd834SNishanth Menon /* pm34xx errata defined in pm.h */ 568cdfd834SNishanth Menon u16 pm34xx_errata; 578cdfd834SNishanth Menon 588bd22949SKevin Hilman struct power_state { 598bd22949SKevin Hilman struct powerdomain *pwrdm; 608bd22949SKevin Hilman u32 next_state; 6110f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 628bd22949SKevin Hilman u32 saved_state; 6310f90ed2SKevin Hilman #endif 648bd22949SKevin Hilman struct list_head node; 658bd22949SKevin Hilman }; 668bd22949SKevin Hilman 678bd22949SKevin Hilman static LIST_HEAD(pwrst_list); 688bd22949SKevin Hilman 6927d59a4aSTero Kristo static int (*_omap_save_secure_sram)(u32 *addr); 7046e130d2SJean Pihet void (*omap3_do_wfi_sram)(void); 7127d59a4aSTero Kristo 72fa3c2a4fSRajendra Nayak static struct powerdomain *mpu_pwrdm, *neon_pwrdm; 73fa3c2a4fSRajendra Nayak static struct powerdomain *core_pwrdm, *per_pwrdm; 743a7ec26bSKalle Jokiniemi 752f5939c3SRajendra Nayak static void omap3_core_save_context(void) 762f5939c3SRajendra Nayak { 77596efe47SPaul Walmsley omap3_ctrl_save_padconf(); 78dccaad89STero Kristo 79dccaad89STero Kristo /* 80dccaad89STero Kristo * Force write last pad into memory, as this can fail in some 8183521291SJean Pihet * cases according to errata 1.157, 1.185 82dccaad89STero Kristo */ 83dccaad89STero Kristo omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), 84dccaad89STero Kristo OMAP343X_CONTROL_MEM_WKUP + 0x2a0); 85dccaad89STero Kristo 862f5939c3SRajendra Nayak /* Save the Interrupt controller context */ 872f5939c3SRajendra Nayak omap_intc_save_context(); 882f5939c3SRajendra Nayak /* Save the GPMC context */ 892f5939c3SRajendra Nayak omap3_gpmc_save_context(); 902f5939c3SRajendra Nayak /* Save the system control module context, padconf already save above*/ 912f5939c3SRajendra Nayak omap3_control_save_context(); 92f2d11858STero Kristo omap_dma_global_context_save(); 932f5939c3SRajendra Nayak } 942f5939c3SRajendra Nayak 952f5939c3SRajendra Nayak static void omap3_core_restore_context(void) 962f5939c3SRajendra Nayak { 972f5939c3SRajendra Nayak /* Restore the control module context, padconf restored by h/w */ 982f5939c3SRajendra Nayak omap3_control_restore_context(); 992f5939c3SRajendra Nayak /* Restore the GPMC context */ 1002f5939c3SRajendra Nayak omap3_gpmc_restore_context(); 1012f5939c3SRajendra Nayak /* Restore the interrupt controller context */ 1022f5939c3SRajendra Nayak omap_intc_restore_context(); 103f2d11858STero Kristo omap_dma_global_context_restore(); 1042f5939c3SRajendra Nayak } 1052f5939c3SRajendra Nayak 1069d97140bSTero Kristo /* 1079d97140bSTero Kristo * FIXME: This function should be called before entering off-mode after 1089d97140bSTero Kristo * OMAP3 secure services have been accessed. Currently it is only called 1099d97140bSTero Kristo * once during boot sequence, but this works as we are not using secure 1109d97140bSTero Kristo * services. 1119d97140bSTero Kristo */ 112617fcc98SKevin Hilman static void omap3_save_secure_ram_context(void) 11327d59a4aSTero Kristo { 11427d59a4aSTero Kristo u32 ret; 115617fcc98SKevin Hilman int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 11627d59a4aSTero Kristo 11727d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 11827d59a4aSTero Kristo /* 11927d59a4aSTero Kristo * MPU next state must be set to POWER_ON temporarily, 12027d59a4aSTero Kristo * otherwise the WFI executed inside the ROM code 12127d59a4aSTero Kristo * will hang the system. 12227d59a4aSTero Kristo */ 12327d59a4aSTero Kristo pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); 1246dd1e357SOlof Johansson ret = _omap_save_secure_sram((u32 *)(unsigned long) 12527d59a4aSTero Kristo __pa(omap3_secure_ram_storage)); 126617fcc98SKevin Hilman pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state); 12727d59a4aSTero Kristo /* Following is for error tracking, it should not happen */ 12827d59a4aSTero Kristo if (ret) { 12998179856SMark A. Greer pr_err("save_secure_sram() returns %08x\n", ret); 13027d59a4aSTero Kristo while (1) 13127d59a4aSTero Kristo ; 13227d59a4aSTero Kristo } 13327d59a4aSTero Kristo } 13427d59a4aSTero Kristo } 13527d59a4aSTero Kristo 13677da2d91SJon Hunter /* 13777da2d91SJon Hunter * PRCM Interrupt Handler Helper Function 13877da2d91SJon Hunter * 13977da2d91SJon Hunter * The purpose of this function is to clear any wake-up events latched 14077da2d91SJon Hunter * in the PRCM PM_WKST_x registers. It is possible that a wake-up event 14177da2d91SJon Hunter * may occur whilst attempting to clear a PM_WKST_x register and thus 14277da2d91SJon Hunter * set another bit in this register. A while loop is used to ensure 14377da2d91SJon Hunter * that any peripheral wake-up events occurring while attempting to 14477da2d91SJon Hunter * clear the PM_WKST_x are detected and cleared. 14577da2d91SJon Hunter */ 14622f51371STero Kristo static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits) 14777da2d91SJon Hunter { 14871a80775SVikram Pandita u32 wkst, fclk, iclk, clken; 14977da2d91SJon Hunter u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; 15077da2d91SJon Hunter u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; 15177da2d91SJon Hunter u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; 1525d805978SPaul Walmsley u16 grpsel_off = (regs == 3) ? 1535d805978SPaul Walmsley OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; 1548cb0ac99SPaul Walmsley int c = 0; 15577da2d91SJon Hunter 156c4d7e58fSPaul Walmsley wkst = omap2_prm_read_mod_reg(module, wkst_off); 157c4d7e58fSPaul Walmsley wkst &= omap2_prm_read_mod_reg(module, grpsel_off); 15822f51371STero Kristo wkst &= ~ignore_bits; 15977da2d91SJon Hunter if (wkst) { 160c4d7e58fSPaul Walmsley iclk = omap2_cm_read_mod_reg(module, iclk_off); 161c4d7e58fSPaul Walmsley fclk = omap2_cm_read_mod_reg(module, fclk_off); 16277da2d91SJon Hunter while (wkst) { 16371a80775SVikram Pandita clken = wkst; 164c4d7e58fSPaul Walmsley omap2_cm_set_mod_reg_bits(clken, module, iclk_off); 16571a80775SVikram Pandita /* 16671a80775SVikram Pandita * For USBHOST, we don't know whether HOST1 or 16771a80775SVikram Pandita * HOST2 woke us up, so enable both f-clocks 16871a80775SVikram Pandita */ 16971a80775SVikram Pandita if (module == OMAP3430ES2_USBHOST_MOD) 17071a80775SVikram Pandita clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; 171c4d7e58fSPaul Walmsley omap2_cm_set_mod_reg_bits(clken, module, fclk_off); 172c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(wkst, module, wkst_off); 173c4d7e58fSPaul Walmsley wkst = omap2_prm_read_mod_reg(module, wkst_off); 17422f51371STero Kristo wkst &= ~ignore_bits; 1758cb0ac99SPaul Walmsley c++; 17677da2d91SJon Hunter } 177c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(iclk, module, iclk_off); 178c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(fclk, module, fclk_off); 17977da2d91SJon Hunter } 1808cb0ac99SPaul Walmsley 1818cb0ac99SPaul Walmsley return c; 1828cb0ac99SPaul Walmsley } 1838cb0ac99SPaul Walmsley 18422f51371STero Kristo static irqreturn_t _prcm_int_handle_io(int irq, void *unused) 1858cb0ac99SPaul Walmsley { 1868cb0ac99SPaul Walmsley int c; 1878cb0ac99SPaul Walmsley 18822f51371STero Kristo c = prcm_clear_mod_irqs(WKUP_MOD, 1, 18922f51371STero Kristo ~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK)); 19022f51371STero Kristo 19122f51371STero Kristo return c ? IRQ_HANDLED : IRQ_NONE; 1928cb0ac99SPaul Walmsley } 1938cb0ac99SPaul Walmsley 19422f51371STero Kristo static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused) 1958bd22949SKevin Hilman { 19622f51371STero Kristo int c; 1978cb0ac99SPaul Walmsley 1988cb0ac99SPaul Walmsley /* 19922f51371STero Kristo * Clear all except ST_IO and ST_IO_CHAIN for wkup module, 20022f51371STero Kristo * these are handled in a separate handler to avoid acking 20122f51371STero Kristo * IO events before parsing in mux code 2028cb0ac99SPaul Walmsley */ 20322f51371STero Kristo c = prcm_clear_mod_irqs(WKUP_MOD, 1, 20422f51371STero Kristo OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK); 20522f51371STero Kristo c += prcm_clear_mod_irqs(CORE_MOD, 1, 0); 20622f51371STero Kristo c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0); 20722f51371STero Kristo if (omap_rev() > OMAP3430_REV_ES1_0) { 20822f51371STero Kristo c += prcm_clear_mod_irqs(CORE_MOD, 3, 0); 20922f51371STero Kristo c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0); 2108cb0ac99SPaul Walmsley } 2118cb0ac99SPaul Walmsley 21222f51371STero Kristo return c ? IRQ_HANDLED : IRQ_NONE; 2138bd22949SKevin Hilman } 2148bd22949SKevin Hilman 215cbe26349SRussell King static void omap34xx_save_context(u32 *save) 216cbe26349SRussell King { 217cbe26349SRussell King u32 val; 218cbe26349SRussell King 219cbe26349SRussell King /* Read Auxiliary Control Register */ 220cbe26349SRussell King asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val)); 221cbe26349SRussell King *save++ = 1; 222cbe26349SRussell King *save++ = val; 223cbe26349SRussell King 224cbe26349SRussell King /* Read L2 AUX ctrl register */ 225cbe26349SRussell King asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); 226cbe26349SRussell King *save++ = 1; 227cbe26349SRussell King *save++ = val; 228cbe26349SRussell King } 229cbe26349SRussell King 23029cb3cd2SRussell King static int omap34xx_do_sram_idle(unsigned long save_state) 23157f277b0SRajendra Nayak { 232cbe26349SRussell King omap34xx_cpu_suspend(save_state); 23329cb3cd2SRussell King return 0; 23457f277b0SRajendra Nayak } 23557f277b0SRajendra Nayak 23699e6a4d2SRajendra Nayak void omap_sram_idle(void) 2378bd22949SKevin Hilman { 2388bd22949SKevin Hilman /* Variable to tell what needs to be saved and restored 2398bd22949SKevin Hilman * in omap_sram_idle*/ 2408bd22949SKevin Hilman /* save_state = 0 => Nothing to save and restored */ 2418bd22949SKevin Hilman /* save_state = 1 => Only L1 and logic lost */ 2428bd22949SKevin Hilman /* save_state = 2 => Only L2 lost */ 2438bd22949SKevin Hilman /* save_state = 3 => L1, L2 and logic lost */ 244fa3c2a4fSRajendra Nayak int save_state = 0; 245fa3c2a4fSRajendra Nayak int mpu_next_state = PWRDM_POWER_ON; 246fa3c2a4fSRajendra Nayak int per_next_state = PWRDM_POWER_ON; 247fa3c2a4fSRajendra Nayak int core_next_state = PWRDM_POWER_ON; 24872e06d08SPaul Walmsley int per_going_off; 249eeb3711bSPaul Walmsley int core_prev_state; 25013a6fe0fSTero Kristo u32 sdrc_pwr = 0; 2518bd22949SKevin Hilman 2528bd22949SKevin Hilman mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 2538bd22949SKevin Hilman switch (mpu_next_state) { 254fa3c2a4fSRajendra Nayak case PWRDM_POWER_ON: 2558bd22949SKevin Hilman case PWRDM_POWER_RET: 2568bd22949SKevin Hilman /* No need to save context */ 2578bd22949SKevin Hilman save_state = 0; 2588bd22949SKevin Hilman break; 25961255ab9SRajendra Nayak case PWRDM_POWER_OFF: 26061255ab9SRajendra Nayak save_state = 3; 26161255ab9SRajendra Nayak break; 2628bd22949SKevin Hilman default: 2638bd22949SKevin Hilman /* Invalid state */ 26498179856SMark A. Greer pr_err("Invalid mpu state in sram_idle\n"); 2658bd22949SKevin Hilman return; 2668bd22949SKevin Hilman } 267fe617af7SPeter 'p2' De Schrijver 268fa3c2a4fSRajendra Nayak /* NEON control */ 269fa3c2a4fSRajendra Nayak if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) 2707139178eSJouni Hogander pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); 271fa3c2a4fSRajendra Nayak 27240742fa8SMike Chan /* Enable IO-PAD and IO-CHAIN wakeups */ 273fa3c2a4fSRajendra Nayak per_next_state = pwrdm_read_next_pwrst(per_pwrdm); 274ecf157d0STero Kristo core_next_state = pwrdm_read_next_pwrst(core_pwrdm); 27540742fa8SMike Chan 276e0e29fd7SKevin Hilman pwrdm_pre_transition(NULL); 277ff2f8e5fSCharulatha V 27840742fa8SMike Chan /* PER */ 2792f5939c3SRajendra Nayak if (per_next_state < PWRDM_POWER_ON) { 28072e06d08SPaul Walmsley per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0; 28172e06d08SPaul Walmsley omap2_gpio_prepare_for_idle(per_going_off); 2822f5939c3SRajendra Nayak } 283c16c3f67STero Kristo 284658ce97eSKevin Hilman /* CORE */ 285658ce97eSKevin Hilman if (core_next_state < PWRDM_POWER_ON) { 2862f5939c3SRajendra Nayak if (core_next_state == PWRDM_POWER_OFF) { 2872f5939c3SRajendra Nayak omap3_core_save_context(); 288f0611a5cSPaul Walmsley omap3_cm_save_context(); 2892f5939c3SRajendra Nayak } 290fa3c2a4fSRajendra Nayak } 29140742fa8SMike Chan 2923b8c4ebbSTony Lindgren /* Configure PMIC signaling for I2C4 or sys_off_mode */ 2933b8c4ebbSTony Lindgren omap3_vc_set_pmic_signaling(core_next_state); 2943b8c4ebbSTony Lindgren 295f18cc2ffSTero Kristo omap3_intc_prepare_idle(); 2968bd22949SKevin Hilman 29761255ab9SRajendra Nayak /* 298f265dc4cSRajendra Nayak * On EMU/HS devices ROM code restores a SRDC value 299f265dc4cSRajendra Nayak * from scratchpad which has automatic self refresh on timeout 30083521291SJean Pihet * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443. 301f265dc4cSRajendra Nayak * Hence store/restore the SDRC_POWER register here. 30213a6fe0fSTero Kristo */ 30330474544SPaul Walmsley if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && 30430474544SPaul Walmsley (omap_type() == OMAP2_DEVICE_TYPE_EMU || 30530474544SPaul Walmsley omap_type() == OMAP2_DEVICE_TYPE_SEC) && 306f265dc4cSRajendra Nayak core_next_state == PWRDM_POWER_OFF) 30713a6fe0fSTero Kristo sdrc_pwr = sdrc_read_reg(SDRC_POWER); 30813a6fe0fSTero Kristo 30913a6fe0fSTero Kristo /* 310076f2cc4SRussell King * omap3_arm_context is the location where some ARM context 311076f2cc4SRussell King * get saved. The rest is placed on the stack, and restored 312076f2cc4SRussell King * from there before resuming. 31361255ab9SRajendra Nayak */ 314cbe26349SRussell King if (save_state) 315cbe26349SRussell King omap34xx_save_context(omap3_arm_context); 316076f2cc4SRussell King if (save_state == 1 || save_state == 3) 3172c74a0ceSRussell King cpu_suspend(save_state, omap34xx_do_sram_idle); 318076f2cc4SRussell King else 319076f2cc4SRussell King omap34xx_do_sram_idle(save_state); 3208bd22949SKevin Hilman 321f265dc4cSRajendra Nayak /* Restore normal SDRC POWER settings */ 32230474544SPaul Walmsley if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && 32330474544SPaul Walmsley (omap_type() == OMAP2_DEVICE_TYPE_EMU || 32430474544SPaul Walmsley omap_type() == OMAP2_DEVICE_TYPE_SEC) && 32513a6fe0fSTero Kristo core_next_state == PWRDM_POWER_OFF) 32613a6fe0fSTero Kristo sdrc_write_reg(sdrc_pwr, SDRC_POWER); 32713a6fe0fSTero Kristo 328658ce97eSKevin Hilman /* CORE */ 329fa3c2a4fSRajendra Nayak if (core_next_state < PWRDM_POWER_ON) { 3302f5939c3SRajendra Nayak core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); 3312f5939c3SRajendra Nayak if (core_prev_state == PWRDM_POWER_OFF) { 3322f5939c3SRajendra Nayak omap3_core_restore_context(); 333f0611a5cSPaul Walmsley omap3_cm_restore_context(); 3342f5939c3SRajendra Nayak omap3_sram_restore_context(); 3358a917d2fSKalle Jokiniemi omap2_sms_restore_context(); 3362f5939c3SRajendra Nayak } 337658ce97eSKevin Hilman } 338f18cc2ffSTero Kristo omap3_intc_resume_idle(); 339658ce97eSKevin Hilman 340e0e29fd7SKevin Hilman pwrdm_post_transition(NULL); 341658ce97eSKevin Hilman 342e0e29fd7SKevin Hilman /* PER */ 343e0e29fd7SKevin Hilman if (per_next_state < PWRDM_POWER_ON) 344e0e29fd7SKevin Hilman omap2_gpio_resume_after_idle(); 3458bd22949SKevin Hilman } 3468bd22949SKevin Hilman 3478bd22949SKevin Hilman static void omap3_pm_idle(void) 3488bd22949SKevin Hilman { 3490bcd24b0SNicolas Pitre if (omap_irq_pending()) 3506b85638bSSantosh Shilimkar return; 3518bd22949SKevin Hilman 3525e7c58dcSJean Pihet trace_cpu_idle(1, smp_processor_id()); 3535e7c58dcSJean Pihet 3548bd22949SKevin Hilman omap_sram_idle(); 3558bd22949SKevin Hilman 3565e7c58dcSJean Pihet trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); 3578bd22949SKevin Hilman } 3588bd22949SKevin Hilman 35910f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 3608bd22949SKevin Hilman static int omap3_pm_suspend(void) 3618bd22949SKevin Hilman { 3628bd22949SKevin Hilman struct power_state *pwrst; 3638bd22949SKevin Hilman int state, ret = 0; 3648bd22949SKevin Hilman 3658bd22949SKevin Hilman /* Read current next_pwrsts */ 3668bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) 3678bd22949SKevin Hilman pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 3688bd22949SKevin Hilman /* Set ones wanted by suspend */ 3698bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 370eb6a2c75SSantosh Shilimkar if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) 3718bd22949SKevin Hilman goto restore; 3728bd22949SKevin Hilman if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) 3738bd22949SKevin Hilman goto restore; 3748bd22949SKevin Hilman } 3758bd22949SKevin Hilman 3762bbe3af3STero Kristo omap3_intc_suspend(); 3772bbe3af3STero Kristo 3788bd22949SKevin Hilman omap_sram_idle(); 3798bd22949SKevin Hilman 3808bd22949SKevin Hilman restore: 3818bd22949SKevin Hilman /* Restore next_pwrsts */ 3828bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 3838bd22949SKevin Hilman state = pwrdm_read_prev_pwrst(pwrst->pwrdm); 3848bd22949SKevin Hilman if (state > pwrst->next_state) { 3857852ec05SPaul Walmsley pr_info("Powerdomain (%s) didn't enter target state %d\n", 3868bd22949SKevin Hilman pwrst->pwrdm->name, pwrst->next_state); 3878bd22949SKevin Hilman ret = -1; 3888bd22949SKevin Hilman } 389eb6a2c75SSantosh Shilimkar omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); 3908bd22949SKevin Hilman } 3918bd22949SKevin Hilman if (ret) 39298179856SMark A. Greer pr_err("Could not enter target state in pm_suspend\n"); 3938bd22949SKevin Hilman else 39498179856SMark A. Greer pr_info("Successfully put all powerdomains to target state\n"); 3958bd22949SKevin Hilman 3968bd22949SKevin Hilman return ret; 3978bd22949SKevin Hilman } 3988bd22949SKevin Hilman 39910f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 4008bd22949SKevin Hilman 4011155e426SKevin Hilman 4021155e426SKevin Hilman /** 4031155e426SKevin Hilman * omap3_iva_idle(): ensure IVA is in idle so it can be put into 4041155e426SKevin Hilman * retention 4051155e426SKevin Hilman * 4061155e426SKevin Hilman * In cases where IVA2 is activated by bootcode, it may prevent 4071155e426SKevin Hilman * full-chip retention or off-mode because it is not idle. This 4081155e426SKevin Hilman * function forces the IVA2 into idle state so it can go 4091155e426SKevin Hilman * into retention/off and thus allow full-chip retention/off. 4101155e426SKevin Hilman * 4111155e426SKevin Hilman **/ 4121155e426SKevin Hilman static void __init omap3_iva_idle(void) 4131155e426SKevin Hilman { 4141155e426SKevin Hilman /* ensure IVA2 clock is disabled */ 415c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 4161155e426SKevin Hilman 4171155e426SKevin Hilman /* if no clock activity, nothing else to do */ 418c4d7e58fSPaul Walmsley if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & 4191155e426SKevin Hilman OMAP3430_CLKACTIVITY_IVA2_MASK)) 4201155e426SKevin Hilman return; 4211155e426SKevin Hilman 4221155e426SKevin Hilman /* Reset IVA2 */ 423c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | 4242bc4ef71SPaul Walmsley OMAP3430_RST2_IVA2_MASK | 4252bc4ef71SPaul Walmsley OMAP3430_RST3_IVA2_MASK, 42637903009SAbhijit Pagare OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 4271155e426SKevin Hilman 4281155e426SKevin Hilman /* Enable IVA2 clock */ 429c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, 4301155e426SKevin Hilman OMAP3430_IVA2_MOD, CM_FCLKEN); 4311155e426SKevin Hilman 4321155e426SKevin Hilman /* Set IVA2 boot mode to 'idle' */ 43349e03402STero Kristo omap3_ctrl_set_iva_bootmode_idle(); 4341155e426SKevin Hilman 4351155e426SKevin Hilman /* Un-reset IVA2 */ 436c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 4371155e426SKevin Hilman 4381155e426SKevin Hilman /* Disable IVA2 clock */ 439c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 4401155e426SKevin Hilman 4411155e426SKevin Hilman /* Reset IVA2 */ 442c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | 4432bc4ef71SPaul Walmsley OMAP3430_RST2_IVA2_MASK | 4442bc4ef71SPaul Walmsley OMAP3430_RST3_IVA2_MASK, 44537903009SAbhijit Pagare OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 4461155e426SKevin Hilman } 4471155e426SKevin Hilman 4488111b221SKevin Hilman static void __init omap3_d2d_idle(void) 4498bd22949SKevin Hilman { 4508111b221SKevin Hilman u16 mask, padconf; 4518111b221SKevin Hilman 4528111b221SKevin Hilman /* In a stand alone OMAP3430 where there is not a stacked 4538111b221SKevin Hilman * modem for the D2D Idle Ack and D2D MStandby must be pulled 4548111b221SKevin Hilman * high. S CONTROL_PADCONF_SAD2D_IDLEACK and 4558111b221SKevin Hilman * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ 4568111b221SKevin Hilman mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ 4578111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); 4588111b221SKevin Hilman padconf |= mask; 4598111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); 4608111b221SKevin Hilman 4618111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); 4628111b221SKevin Hilman padconf |= mask; 4638111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 4648111b221SKevin Hilman 4658bd22949SKevin Hilman /* reset modem */ 466c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | 4672bc4ef71SPaul Walmsley OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, 46837903009SAbhijit Pagare CORE_MOD, OMAP2_RM_RSTCTRL); 469c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); 4708111b221SKevin Hilman } 4718bd22949SKevin Hilman 4728111b221SKevin Hilman static void __init prcm_setup_regs(void) 4738111b221SKevin Hilman { 474e5863689SGovindraj.R u32 omap3630_en_uart4_mask = cpu_is_omap3630() ? 475e5863689SGovindraj.R OMAP3630_EN_UART4_MASK : 0; 476e5863689SGovindraj.R u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ? 477e5863689SGovindraj.R OMAP3630_GRPSEL_UART4_MASK : 0; 478e5863689SGovindraj.R 4794ef70c06SPaul Walmsley /* XXX This should be handled by hwmod code or SCM init code */ 4802fd0f75cSPaul Walmsley omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); 481b296c811STero Kristo 4828bd22949SKevin Hilman /* 4838bd22949SKevin Hilman * Enable control of expternal oscillator through 4848bd22949SKevin Hilman * sys_clkreq. In the long run clock framework should 4858bd22949SKevin Hilman * take care of this. 4868bd22949SKevin Hilman */ 487c4d7e58fSPaul Walmsley omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 4888bd22949SKevin Hilman 1 << OMAP_AUTOEXTCLKMODE_SHIFT, 4898bd22949SKevin Hilman OMAP3430_GR_MOD, 4908bd22949SKevin Hilman OMAP3_PRM_CLKSRC_CTRL_OFFSET); 4918bd22949SKevin Hilman 4928bd22949SKevin Hilman /* setup wakup source */ 493c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | 4942fd0f75cSPaul Walmsley OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, 4958bd22949SKevin Hilman WKUP_MOD, PM_WKEN); 4968bd22949SKevin Hilman /* No need to write EN_IO, that is always enabled */ 497c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | 498275f675cSPaul Walmsley OMAP3430_GRPSEL_GPT1_MASK | 499275f675cSPaul Walmsley OMAP3430_GRPSEL_GPT12_MASK, 5008bd22949SKevin Hilman WKUP_MOD, OMAP3430_PM_MPUGRPSEL); 5011155e426SKevin Hilman 502b92c5721SSubramani Venkatesh /* Enable PM_WKEN to support DSS LPR */ 503c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, 504b92c5721SSubramani Venkatesh OMAP3430_DSS_MOD, PM_WKEN); 505b92c5721SSubramani Venkatesh 506b427f92fSKevin Hilman /* Enable wakeups in PER */ 507c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(omap3630_en_uart4_mask | 508e5863689SGovindraj.R OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | 5092fd0f75cSPaul Walmsley OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | 5102fd0f75cSPaul Walmsley OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | 5112fd0f75cSPaul Walmsley OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK | 5122fd0f75cSPaul Walmsley OMAP3430_EN_MCBSP4_MASK, 513b427f92fSKevin Hilman OMAP3430_PER_MOD, PM_WKEN); 514eb350f74SKevin Hilman /* and allow them to wake up MPU */ 515c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask | 516e5863689SGovindraj.R OMAP3430_GRPSEL_GPIO2_MASK | 517275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO3_MASK | 518275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO4_MASK | 519275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO5_MASK | 520275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO6_MASK | 521275f675cSPaul Walmsley OMAP3430_GRPSEL_UART3_MASK | 522275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP2_MASK | 523275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP3_MASK | 524275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP4_MASK, 525eb350f74SKevin Hilman OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); 526eb350f74SKevin Hilman 527d3fd3290SKevin Hilman /* Don't attach IVA interrupts */ 528a819c4f1SMark A. Greer if (omap3_has_iva()) { 529c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 530c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 531c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 532a819c4f1SMark A. Greer omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, 533a819c4f1SMark A. Greer OMAP3430_PM_IVAGRPSEL); 534a819c4f1SMark A. Greer } 535d3fd3290SKevin Hilman 536b1340d17SKevin Hilman /* Clear any pending 'reset' flags */ 537c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); 538c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); 539c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); 540c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); 541c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); 542c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); 543c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); 544b1340d17SKevin Hilman 545014c46dbSKevin Hilman /* Clear any pending PRCM interrupts */ 546c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 547014c46dbSKevin Hilman 5482d403f7bSTony Lindgren /* 5492d403f7bSTony Lindgren * We need to idle iva2_pwrdm even on am3703 with no iva2. 5502d403f7bSTony Lindgren */ 5511155e426SKevin Hilman omap3_iva_idle(); 552a819c4f1SMark A. Greer 5538111b221SKevin Hilman omap3_d2d_idle(); 5548bd22949SKevin Hilman } 5558bd22949SKevin Hilman 556c40552bcSKevin Hilman void omap3_pm_off_mode_enable(int enable) 557c40552bcSKevin Hilman { 558c40552bcSKevin Hilman struct power_state *pwrst; 559c40552bcSKevin Hilman u32 state; 560c40552bcSKevin Hilman 561c40552bcSKevin Hilman if (enable) 562c40552bcSKevin Hilman state = PWRDM_POWER_OFF; 563c40552bcSKevin Hilman else 564c40552bcSKevin Hilman state = PWRDM_POWER_RET; 565c40552bcSKevin Hilman 566c40552bcSKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 567cc1b6028SEduardo Valentin if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) && 568cc1b6028SEduardo Valentin pwrst->pwrdm == core_pwrdm && 569cc1b6028SEduardo Valentin state == PWRDM_POWER_OFF) { 570cc1b6028SEduardo Valentin pwrst->next_state = PWRDM_POWER_RET; 571e16b41bfSRicardo Salveti de Araujo pr_warn("%s: Core OFF disabled due to errata i583\n", 572cc1b6028SEduardo Valentin __func__); 573cc1b6028SEduardo Valentin } else { 574c40552bcSKevin Hilman pwrst->next_state = state; 575cc1b6028SEduardo Valentin } 576cc1b6028SEduardo Valentin omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 577c40552bcSKevin Hilman } 578c40552bcSKevin Hilman } 579c40552bcSKevin Hilman 58068d4778cSTero Kristo int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) 58168d4778cSTero Kristo { 58268d4778cSTero Kristo struct power_state *pwrst; 58368d4778cSTero Kristo 58468d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 58568d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) 58668d4778cSTero Kristo return pwrst->next_state; 58768d4778cSTero Kristo } 58868d4778cSTero Kristo return -EINVAL; 58968d4778cSTero Kristo } 59068d4778cSTero Kristo 59168d4778cSTero Kristo int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) 59268d4778cSTero Kristo { 59368d4778cSTero Kristo struct power_state *pwrst; 59468d4778cSTero Kristo 59568d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 59668d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) { 59768d4778cSTero Kristo pwrst->next_state = state; 59868d4778cSTero Kristo return 0; 59968d4778cSTero Kristo } 60068d4778cSTero Kristo } 60168d4778cSTero Kristo return -EINVAL; 60268d4778cSTero Kristo } 60368d4778cSTero Kristo 604a23456e9SPeter 'p2' De Schrijver static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) 6058bd22949SKevin Hilman { 6068bd22949SKevin Hilman struct power_state *pwrst; 6078bd22949SKevin Hilman 6088bd22949SKevin Hilman if (!pwrdm->pwrsts) 6098bd22949SKevin Hilman return 0; 6108bd22949SKevin Hilman 611d3d381c6SMing Lei pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); 6128bd22949SKevin Hilman if (!pwrst) 6138bd22949SKevin Hilman return -ENOMEM; 6148bd22949SKevin Hilman pwrst->pwrdm = pwrdm; 6158bd22949SKevin Hilman pwrst->next_state = PWRDM_POWER_RET; 6168bd22949SKevin Hilman list_add(&pwrst->node, &pwrst_list); 6178bd22949SKevin Hilman 6188bd22949SKevin Hilman if (pwrdm_has_hdwr_sar(pwrdm)) 6198bd22949SKevin Hilman pwrdm_enable_hdwr_sar(pwrdm); 6208bd22949SKevin Hilman 621eb6a2c75SSantosh Shilimkar return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 6228bd22949SKevin Hilman } 6238bd22949SKevin Hilman 6248bd22949SKevin Hilman /* 62546e130d2SJean Pihet * Push functions to SRAM 62646e130d2SJean Pihet * 62746e130d2SJean Pihet * The minimum set of functions is pushed to SRAM for execution: 62846e130d2SJean Pihet * - omap3_do_wfi for erratum i581 WA, 62946e130d2SJean Pihet * - save_secure_ram_context for security extensions. 63046e130d2SJean Pihet */ 6313231fc88SRajendra Nayak void omap_push_sram_idle(void) 6323231fc88SRajendra Nayak { 63346e130d2SJean Pihet omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz); 63446e130d2SJean Pihet 63527d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) 63627d59a4aSTero Kristo _omap_save_secure_sram = omap_sram_push(save_secure_ram_context, 63727d59a4aSTero Kristo save_secure_ram_context_sz); 6383231fc88SRajendra Nayak } 6393231fc88SRajendra Nayak 6408cdfd834SNishanth Menon static void __init pm_errata_configure(void) 6418cdfd834SNishanth Menon { 642c4236d2eSPeter 'p2' De Schrijver if (cpu_is_omap3630()) { 643458e999eSNishanth Menon pm34xx_errata |= PM_RTA_ERRATUM_i608; 644c4236d2eSPeter 'p2' De Schrijver /* Enable the l2 cache toggling in sleep logic */ 645c4236d2eSPeter 'p2' De Schrijver enable_omap3630_toggle_l2_on_restore(); 646cc1b6028SEduardo Valentin if (omap_rev() < OMAP3630_REV_ES1_2) 647856c3c5bSPaul Walmsley pm34xx_errata |= (PM_SDRC_WAKEUP_ERRATUM_i583 | 648856c3c5bSPaul Walmsley PM_PER_MEMORIES_ERRATUM_i582); 649856c3c5bSPaul Walmsley } else if (cpu_is_omap34xx()) { 650856c3c5bSPaul Walmsley pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582; 651c4236d2eSPeter 'p2' De Schrijver } 6528cdfd834SNishanth Menon } 6538cdfd834SNishanth Menon 654bbd707acSShawn Guo int __init omap3_pm_init(void) 6558bd22949SKevin Hilman { 6568bd22949SKevin Hilman struct power_state *pwrst, *tmp; 657856c3c5bSPaul Walmsley struct clockdomain *neon_clkdm, *mpu_clkdm, *per_clkdm, *wkup_clkdm; 6588bd22949SKevin Hilman int ret; 6598bd22949SKevin Hilman 660b02b9172SPaul Walmsley if (!omap3_has_io_chain_ctrl()) 661b02b9172SPaul Walmsley pr_warning("PM: no software I/O chain control; some wakeups may be lost\n"); 662b02b9172SPaul Walmsley 6638cdfd834SNishanth Menon pm_errata_configure(); 6648cdfd834SNishanth Menon 6658bd22949SKevin Hilman /* XXX prcm_setup_regs needs to be before enabling hw 6668bd22949SKevin Hilman * supervised mode for powerdomains */ 6678bd22949SKevin Hilman prcm_setup_regs(); 6688bd22949SKevin Hilman 66922f51371STero Kristo ret = request_irq(omap_prcm_event_to_irq("wkup"), 67022f51371STero Kristo _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL); 67122f51371STero Kristo 6728bd22949SKevin Hilman if (ret) { 67322f51371STero Kristo pr_err("pm: Failed to request pm_wkup irq\n"); 67422f51371STero Kristo goto err1; 67522f51371STero Kristo } 67622f51371STero Kristo 67722f51371STero Kristo /* IO interrupt is shared with mux code */ 67822f51371STero Kristo ret = request_irq(omap_prcm_event_to_irq("io"), 67922f51371STero Kristo _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io", 68022f51371STero Kristo omap3_pm_init); 68199b59df0SKevin Hilman enable_irq(omap_prcm_event_to_irq("io")); 68222f51371STero Kristo 68322f51371STero Kristo if (ret) { 68422f51371STero Kristo pr_err("pm: Failed to request pm_io irq\n"); 685ce229c5dSMark A. Greer goto err2; 6868bd22949SKevin Hilman } 6878bd22949SKevin Hilman 688a23456e9SPeter 'p2' De Schrijver ret = pwrdm_for_each(pwrdms_setup, NULL); 6898bd22949SKevin Hilman if (ret) { 69098179856SMark A. Greer pr_err("Failed to setup powerdomains\n"); 691ce229c5dSMark A. Greer goto err3; 6928bd22949SKevin Hilman } 6938bd22949SKevin Hilman 69492206fd2SPaul Walmsley (void) clkdm_for_each(omap_pm_clkdms_setup, NULL); 6958bd22949SKevin Hilman 6968bd22949SKevin Hilman mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); 6978bd22949SKevin Hilman if (mpu_pwrdm == NULL) { 69898179856SMark A. Greer pr_err("Failed to get mpu_pwrdm\n"); 699ce229c5dSMark A. Greer ret = -EINVAL; 700ce229c5dSMark A. Greer goto err3; 7018bd22949SKevin Hilman } 7028bd22949SKevin Hilman 703fa3c2a4fSRajendra Nayak neon_pwrdm = pwrdm_lookup("neon_pwrdm"); 704fa3c2a4fSRajendra Nayak per_pwrdm = pwrdm_lookup("per_pwrdm"); 705fa3c2a4fSRajendra Nayak core_pwrdm = pwrdm_lookup("core_pwrdm"); 706fa3c2a4fSRajendra Nayak 70755ed9694SPaul Walmsley neon_clkdm = clkdm_lookup("neon_clkdm"); 70855ed9694SPaul Walmsley mpu_clkdm = clkdm_lookup("mpu_clkdm"); 709856c3c5bSPaul Walmsley per_clkdm = clkdm_lookup("per_clkdm"); 710856c3c5bSPaul Walmsley wkup_clkdm = clkdm_lookup("wkup_clkdm"); 71155ed9694SPaul Walmsley 71210f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 7131416408dSPaul Walmsley omap_pm_suspend = omap3_pm_suspend; 7141416408dSPaul Walmsley #endif 7158bd22949SKevin Hilman 7160bcd24b0SNicolas Pitre arm_pm_idle = omap3_pm_idle; 7170343371eSKalle Jokiniemi omap3_idle_init(); 7188bd22949SKevin Hilman 719458e999eSNishanth Menon /* 720458e999eSNishanth Menon * RTA is disabled during initialization as per erratum i608 721458e999eSNishanth Menon * it is safer to disable RTA by the bootloader, but we would like 722458e999eSNishanth Menon * to be doubly sure here and prevent any mishaps. 723458e999eSNishanth Menon */ 724458e999eSNishanth Menon if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608)) 725458e999eSNishanth Menon omap3630_ctrl_disable_rta(); 726458e999eSNishanth Menon 727856c3c5bSPaul Walmsley /* 728856c3c5bSPaul Walmsley * The UART3/4 FIFO and the sidetone memory in McBSP2/3 are 729856c3c5bSPaul Walmsley * not correctly reset when the PER powerdomain comes back 730856c3c5bSPaul Walmsley * from OFF or OSWR when the CORE powerdomain is kept active. 731856c3c5bSPaul Walmsley * See OMAP36xx Erratum i582 "PER Domain reset issue after 732856c3c5bSPaul Walmsley * Domain-OFF/OSWR Wakeup". This wakeup dependency is not a 733856c3c5bSPaul Walmsley * complete workaround. The kernel must also prevent the PER 734856c3c5bSPaul Walmsley * powerdomain from going to OSWR/OFF while the CORE 735856c3c5bSPaul Walmsley * powerdomain is not going to OSWR/OFF. And if PER last 736856c3c5bSPaul Walmsley * power state was off while CORE last power state was ON, the 737856c3c5bSPaul Walmsley * UART3/4 and McBSP2/3 SIDETONE devices need to run a 738856c3c5bSPaul Walmsley * self-test using their loopback tests; if that fails, those 739856c3c5bSPaul Walmsley * devices are unusable until the PER/CORE can complete a transition 740856c3c5bSPaul Walmsley * from ON to OSWR/OFF and then back to ON. 741856c3c5bSPaul Walmsley * 742856c3c5bSPaul Walmsley * XXX Technically this workaround is only needed if off-mode 743856c3c5bSPaul Walmsley * or OSWR is enabled. 744856c3c5bSPaul Walmsley */ 745856c3c5bSPaul Walmsley if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582)) 746856c3c5bSPaul Walmsley clkdm_add_wkdep(per_clkdm, wkup_clkdm); 747856c3c5bSPaul Walmsley 74855ed9694SPaul Walmsley clkdm_add_wkdep(neon_clkdm, mpu_clkdm); 74927d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 75027d59a4aSTero Kristo omap3_secure_ram_storage = 75127d59a4aSTero Kristo kmalloc(0x803F, GFP_KERNEL); 75227d59a4aSTero Kristo if (!omap3_secure_ram_storage) 7537852ec05SPaul Walmsley pr_err("Memory allocation failed when allocating for secure sram context\n"); 75427d59a4aSTero Kristo 7559d97140bSTero Kristo local_irq_disable(); 7569d97140bSTero Kristo 7579d97140bSTero Kristo omap_dma_global_context_save(); 758617fcc98SKevin Hilman omap3_save_secure_ram_context(); 7599d97140bSTero Kristo omap_dma_global_context_restore(); 7609d97140bSTero Kristo 7619d97140bSTero Kristo local_irq_enable(); 7629d97140bSTero Kristo } 7639d97140bSTero Kristo 7649d97140bSTero Kristo omap3_save_scratchpad_contents(); 7658bd22949SKevin Hilman return ret; 766ce229c5dSMark A. Greer 767ce229c5dSMark A. Greer err3: 7688bd22949SKevin Hilman list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { 7698bd22949SKevin Hilman list_del(&pwrst->node); 7708bd22949SKevin Hilman kfree(pwrst); 7718bd22949SKevin Hilman } 772ce229c5dSMark A. Greer free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init); 773ce229c5dSMark A. Greer err2: 774ce229c5dSMark A. Greer free_irq(omap_prcm_event_to_irq("wkup"), NULL); 775ce229c5dSMark A. Greer err1: 7768bd22949SKevin Hilman return ret; 7778bd22949SKevin Hilman } 778