18bd22949SKevin Hilman /* 28bd22949SKevin Hilman * OMAP3 Power Management Routines 38bd22949SKevin Hilman * 48bd22949SKevin Hilman * Copyright (C) 2006-2008 Nokia Corporation 58bd22949SKevin Hilman * Tony Lindgren <tony@atomide.com> 68bd22949SKevin Hilman * Jouni Hogander 78bd22949SKevin Hilman * 82f5939c3SRajendra Nayak * Copyright (C) 2007 Texas Instruments, Inc. 92f5939c3SRajendra Nayak * Rajendra Nayak <rnayak@ti.com> 102f5939c3SRajendra Nayak * 118bd22949SKevin Hilman * Copyright (C) 2005 Texas Instruments, Inc. 128bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 138bd22949SKevin Hilman * 148bd22949SKevin Hilman * Based on pm.c for omap1 158bd22949SKevin Hilman * 168bd22949SKevin Hilman * This program is free software; you can redistribute it and/or modify 178bd22949SKevin Hilman * it under the terms of the GNU General Public License version 2 as 188bd22949SKevin Hilman * published by the Free Software Foundation. 198bd22949SKevin Hilman */ 208bd22949SKevin Hilman 218bd22949SKevin Hilman #include <linux/pm.h> 228bd22949SKevin Hilman #include <linux/suspend.h> 238bd22949SKevin Hilman #include <linux/interrupt.h> 248bd22949SKevin Hilman #include <linux/module.h> 258bd22949SKevin Hilman #include <linux/list.h> 268bd22949SKevin Hilman #include <linux/err.h> 278bd22949SKevin Hilman #include <linux/gpio.h> 28c40552bcSKevin Hilman #include <linux/clk.h> 29dccaad89STero Kristo #include <linux/delay.h> 305a0e3ad6STejun Heo #include <linux/slab.h> 318bd22949SKevin Hilman 32ce491cf8STony Lindgren #include <plat/sram.h> 33ce491cf8STony Lindgren #include <plat/clockdomain.h> 34ce491cf8STony Lindgren #include <plat/powerdomain.h> 35ce491cf8STony Lindgren #include <plat/serial.h> 3661255ab9SRajendra Nayak #include <plat/sdrc.h> 372f5939c3SRajendra Nayak #include <plat/prcm.h> 382f5939c3SRajendra Nayak #include <plat/gpmc.h> 39f2d11858STero Kristo #include <plat/dma.h> 408bd22949SKevin Hilman 4157f277b0SRajendra Nayak #include <asm/tlbflush.h> 4257f277b0SRajendra Nayak 438bd22949SKevin Hilman #include "cm.h" 448bd22949SKevin Hilman #include "cm-regbits-34xx.h" 458bd22949SKevin Hilman #include "prm-regbits-34xx.h" 468bd22949SKevin Hilman 478bd22949SKevin Hilman #include "prm.h" 488bd22949SKevin Hilman #include "pm.h" 4913a6fe0fSTero Kristo #include "sdrc.h" 504814ced5SPaul Walmsley #include "control.h" 5113a6fe0fSTero Kristo 522f5939c3SRajendra Nayak /* Scratchpad offsets */ 53de658158SKevin Hilman #define OMAP343X_TABLE_ADDRESS_OFFSET 0xc4 54de658158SKevin Hilman #define OMAP343X_TABLE_VALUE_OFFSET 0xc0 55de658158SKevin Hilman #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8 562f5939c3SRajendra Nayak 578bd22949SKevin Hilman struct power_state { 588bd22949SKevin Hilman struct powerdomain *pwrdm; 598bd22949SKevin Hilman u32 next_state; 6010f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 618bd22949SKevin Hilman u32 saved_state; 6210f90ed2SKevin Hilman #endif 638bd22949SKevin Hilman struct list_head node; 648bd22949SKevin Hilman }; 658bd22949SKevin Hilman 668bd22949SKevin Hilman static LIST_HEAD(pwrst_list); 678bd22949SKevin Hilman 688bd22949SKevin Hilman static void (*_omap_sram_idle)(u32 *addr, int save_state); 698bd22949SKevin Hilman 7027d59a4aSTero Kristo static int (*_omap_save_secure_sram)(u32 *addr); 7127d59a4aSTero Kristo 72fa3c2a4fSRajendra Nayak static struct powerdomain *mpu_pwrdm, *neon_pwrdm; 73fa3c2a4fSRajendra Nayak static struct powerdomain *core_pwrdm, *per_pwrdm; 74c16c3f67STero Kristo static struct powerdomain *cam_pwrdm; 75fa3c2a4fSRajendra Nayak 762f5939c3SRajendra Nayak static inline void omap3_per_save_context(void) 772f5939c3SRajendra Nayak { 782f5939c3SRajendra Nayak omap_gpio_save_context(); 792f5939c3SRajendra Nayak } 802f5939c3SRajendra Nayak 812f5939c3SRajendra Nayak static inline void omap3_per_restore_context(void) 822f5939c3SRajendra Nayak { 832f5939c3SRajendra Nayak omap_gpio_restore_context(); 842f5939c3SRajendra Nayak } 852f5939c3SRajendra Nayak 863a7ec26bSKalle Jokiniemi static void omap3_enable_io_chain(void) 873a7ec26bSKalle Jokiniemi { 883a7ec26bSKalle Jokiniemi int timeout = 0; 893a7ec26bSKalle Jokiniemi 903a7ec26bSKalle Jokiniemi if (omap_rev() >= OMAP3430_REV_ES3_1) { 912bc4ef71SPaul Walmsley prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, 922bc4ef71SPaul Walmsley PM_WKEN); 933a7ec26bSKalle Jokiniemi /* Do a readback to assure write has been done */ 943a7ec26bSKalle Jokiniemi prm_read_mod_reg(WKUP_MOD, PM_WKEN); 953a7ec26bSKalle Jokiniemi 960b96a3a3SKevin Hilman while (!(prm_read_mod_reg(WKUP_MOD, PM_WKEN) & 972bc4ef71SPaul Walmsley OMAP3430_ST_IO_CHAIN_MASK)) { 983a7ec26bSKalle Jokiniemi timeout++; 993a7ec26bSKalle Jokiniemi if (timeout > 1000) { 1003a7ec26bSKalle Jokiniemi printk(KERN_ERR "Wake up daisy chain " 1013a7ec26bSKalle Jokiniemi "activation failed.\n"); 1023a7ec26bSKalle Jokiniemi return; 1033a7ec26bSKalle Jokiniemi } 1042bc4ef71SPaul Walmsley prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, 1050b96a3a3SKevin Hilman WKUP_MOD, PM_WKEN); 1063a7ec26bSKalle Jokiniemi } 1073a7ec26bSKalle Jokiniemi } 1083a7ec26bSKalle Jokiniemi } 1093a7ec26bSKalle Jokiniemi 1103a7ec26bSKalle Jokiniemi static void omap3_disable_io_chain(void) 1113a7ec26bSKalle Jokiniemi { 1123a7ec26bSKalle Jokiniemi if (omap_rev() >= OMAP3430_REV_ES3_1) 1132bc4ef71SPaul Walmsley prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, 1142bc4ef71SPaul Walmsley PM_WKEN); 1153a7ec26bSKalle Jokiniemi } 1163a7ec26bSKalle Jokiniemi 1172f5939c3SRajendra Nayak static void omap3_core_save_context(void) 1182f5939c3SRajendra Nayak { 1192f5939c3SRajendra Nayak u32 control_padconf_off; 1202f5939c3SRajendra Nayak 1212f5939c3SRajendra Nayak /* Save the padconf registers */ 1222f5939c3SRajendra Nayak control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF); 1232f5939c3SRajendra Nayak control_padconf_off |= START_PADCONF_SAVE; 1242f5939c3SRajendra Nayak omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF); 1252f5939c3SRajendra Nayak /* wait for the save to complete */ 1261b6e821fSRoel Kluin while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) 1271b6e821fSRoel Kluin & PADCONF_SAVE_DONE)) 128dccaad89STero Kristo udelay(1); 129dccaad89STero Kristo 130dccaad89STero Kristo /* 131dccaad89STero Kristo * Force write last pad into memory, as this can fail in some 132dccaad89STero Kristo * cases according to erratas 1.157, 1.185 133dccaad89STero Kristo */ 134dccaad89STero Kristo omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), 135dccaad89STero Kristo OMAP343X_CONTROL_MEM_WKUP + 0x2a0); 136dccaad89STero Kristo 1372f5939c3SRajendra Nayak /* Save the Interrupt controller context */ 1382f5939c3SRajendra Nayak omap_intc_save_context(); 1392f5939c3SRajendra Nayak /* Save the GPMC context */ 1402f5939c3SRajendra Nayak omap3_gpmc_save_context(); 1412f5939c3SRajendra Nayak /* Save the system control module context, padconf already save above*/ 1422f5939c3SRajendra Nayak omap3_control_save_context(); 143f2d11858STero Kristo omap_dma_global_context_save(); 1442f5939c3SRajendra Nayak } 1452f5939c3SRajendra Nayak 1462f5939c3SRajendra Nayak static void omap3_core_restore_context(void) 1472f5939c3SRajendra Nayak { 1482f5939c3SRajendra Nayak /* Restore the control module context, padconf restored by h/w */ 1492f5939c3SRajendra Nayak omap3_control_restore_context(); 1502f5939c3SRajendra Nayak /* Restore the GPMC context */ 1512f5939c3SRajendra Nayak omap3_gpmc_restore_context(); 1522f5939c3SRajendra Nayak /* Restore the interrupt controller context */ 1532f5939c3SRajendra Nayak omap_intc_restore_context(); 154f2d11858STero Kristo omap_dma_global_context_restore(); 1552f5939c3SRajendra Nayak } 1562f5939c3SRajendra Nayak 1579d97140bSTero Kristo /* 1589d97140bSTero Kristo * FIXME: This function should be called before entering off-mode after 1599d97140bSTero Kristo * OMAP3 secure services have been accessed. Currently it is only called 1609d97140bSTero Kristo * once during boot sequence, but this works as we are not using secure 1619d97140bSTero Kristo * services. 1629d97140bSTero Kristo */ 16327d59a4aSTero Kristo static void omap3_save_secure_ram_context(u32 target_mpu_state) 16427d59a4aSTero Kristo { 16527d59a4aSTero Kristo u32 ret; 16627d59a4aSTero Kristo 16727d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 16827d59a4aSTero Kristo /* 16927d59a4aSTero Kristo * MPU next state must be set to POWER_ON temporarily, 17027d59a4aSTero Kristo * otherwise the WFI executed inside the ROM code 17127d59a4aSTero Kristo * will hang the system. 17227d59a4aSTero Kristo */ 17327d59a4aSTero Kristo pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); 17427d59a4aSTero Kristo ret = _omap_save_secure_sram((u32 *) 17527d59a4aSTero Kristo __pa(omap3_secure_ram_storage)); 17627d59a4aSTero Kristo pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state); 17727d59a4aSTero Kristo /* Following is for error tracking, it should not happen */ 17827d59a4aSTero Kristo if (ret) { 17927d59a4aSTero Kristo printk(KERN_ERR "save_secure_sram() returns %08x\n", 18027d59a4aSTero Kristo ret); 18127d59a4aSTero Kristo while (1) 18227d59a4aSTero Kristo ; 18327d59a4aSTero Kristo } 18427d59a4aSTero Kristo } 18527d59a4aSTero Kristo } 18627d59a4aSTero Kristo 18777da2d91SJon Hunter /* 18877da2d91SJon Hunter * PRCM Interrupt Handler Helper Function 18977da2d91SJon Hunter * 19077da2d91SJon Hunter * The purpose of this function is to clear any wake-up events latched 19177da2d91SJon Hunter * in the PRCM PM_WKST_x registers. It is possible that a wake-up event 19277da2d91SJon Hunter * may occur whilst attempting to clear a PM_WKST_x register and thus 19377da2d91SJon Hunter * set another bit in this register. A while loop is used to ensure 19477da2d91SJon Hunter * that any peripheral wake-up events occurring while attempting to 19577da2d91SJon Hunter * clear the PM_WKST_x are detected and cleared. 19677da2d91SJon Hunter */ 1978cb0ac99SPaul Walmsley static int prcm_clear_mod_irqs(s16 module, u8 regs) 19877da2d91SJon Hunter { 19971a80775SVikram Pandita u32 wkst, fclk, iclk, clken; 20077da2d91SJon Hunter u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; 20177da2d91SJon Hunter u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; 20277da2d91SJon Hunter u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; 2035d805978SPaul Walmsley u16 grpsel_off = (regs == 3) ? 2045d805978SPaul Walmsley OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; 2058cb0ac99SPaul Walmsley int c = 0; 20677da2d91SJon Hunter 20777da2d91SJon Hunter wkst = prm_read_mod_reg(module, wkst_off); 2085d805978SPaul Walmsley wkst &= prm_read_mod_reg(module, grpsel_off); 20977da2d91SJon Hunter if (wkst) { 21077da2d91SJon Hunter iclk = cm_read_mod_reg(module, iclk_off); 21177da2d91SJon Hunter fclk = cm_read_mod_reg(module, fclk_off); 21277da2d91SJon Hunter while (wkst) { 21371a80775SVikram Pandita clken = wkst; 21471a80775SVikram Pandita cm_set_mod_reg_bits(clken, module, iclk_off); 21571a80775SVikram Pandita /* 21671a80775SVikram Pandita * For USBHOST, we don't know whether HOST1 or 21771a80775SVikram Pandita * HOST2 woke us up, so enable both f-clocks 21871a80775SVikram Pandita */ 21971a80775SVikram Pandita if (module == OMAP3430ES2_USBHOST_MOD) 22071a80775SVikram Pandita clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; 22171a80775SVikram Pandita cm_set_mod_reg_bits(clken, module, fclk_off); 22277da2d91SJon Hunter prm_write_mod_reg(wkst, module, wkst_off); 22377da2d91SJon Hunter wkst = prm_read_mod_reg(module, wkst_off); 2248cb0ac99SPaul Walmsley c++; 22577da2d91SJon Hunter } 22677da2d91SJon Hunter cm_write_mod_reg(iclk, module, iclk_off); 22777da2d91SJon Hunter cm_write_mod_reg(fclk, module, fclk_off); 22877da2d91SJon Hunter } 2298cb0ac99SPaul Walmsley 2308cb0ac99SPaul Walmsley return c; 2318cb0ac99SPaul Walmsley } 2328cb0ac99SPaul Walmsley 2338cb0ac99SPaul Walmsley static int _prcm_int_handle_wakeup(void) 2348cb0ac99SPaul Walmsley { 2358cb0ac99SPaul Walmsley int c; 2368cb0ac99SPaul Walmsley 2378cb0ac99SPaul Walmsley c = prcm_clear_mod_irqs(WKUP_MOD, 1); 2388cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(CORE_MOD, 1); 2398cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1); 2408cb0ac99SPaul Walmsley if (omap_rev() > OMAP3430_REV_ES1_0) { 2418cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(CORE_MOD, 3); 2428cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1); 2438cb0ac99SPaul Walmsley } 2448cb0ac99SPaul Walmsley 2458cb0ac99SPaul Walmsley return c; 24677da2d91SJon Hunter } 24777da2d91SJon Hunter 24877da2d91SJon Hunter /* 24977da2d91SJon Hunter * PRCM Interrupt Handler 25077da2d91SJon Hunter * 25177da2d91SJon Hunter * The PRM_IRQSTATUS_MPU register indicates if there are any pending 25277da2d91SJon Hunter * interrupts from the PRCM for the MPU. These bits must be cleared in 25377da2d91SJon Hunter * order to clear the PRCM interrupt. The PRCM interrupt handler is 25477da2d91SJon Hunter * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear 25577da2d91SJon Hunter * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU 25677da2d91SJon Hunter * register indicates that a wake-up event is pending for the MPU and 25777da2d91SJon Hunter * this bit can only be cleared if the all the wake-up events latched 25877da2d91SJon Hunter * in the various PM_WKST_x registers have been cleared. The interrupt 25977da2d91SJon Hunter * handler is implemented using a do-while loop so that if a wake-up 26077da2d91SJon Hunter * event occurred during the processing of the prcm interrupt handler 26177da2d91SJon Hunter * (setting a bit in the corresponding PM_WKST_x register and thus 26277da2d91SJon Hunter * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register) 26377da2d91SJon Hunter * this would be handled. 26477da2d91SJon Hunter */ 2658bd22949SKevin Hilman static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) 2668bd22949SKevin Hilman { 267d6290a3eSKevin Hilman u32 irqenable_mpu, irqstatus_mpu; 2688cb0ac99SPaul Walmsley int c = 0; 2698bd22949SKevin Hilman 270d6290a3eSKevin Hilman irqenable_mpu = prm_read_mod_reg(OCP_MOD, 271d6290a3eSKevin Hilman OMAP3_PRM_IRQENABLE_MPU_OFFSET); 2728bd22949SKevin Hilman irqstatus_mpu = prm_read_mod_reg(OCP_MOD, 2738bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 274d6290a3eSKevin Hilman irqstatus_mpu &= irqenable_mpu; 2758cb0ac99SPaul Walmsley 276d6290a3eSKevin Hilman do { 2772bc4ef71SPaul Walmsley if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK | 2782bc4ef71SPaul Walmsley OMAP3430_IO_ST_MASK)) { 2798cb0ac99SPaul Walmsley c = _prcm_int_handle_wakeup(); 2808cb0ac99SPaul Walmsley 2818cb0ac99SPaul Walmsley /* 2828cb0ac99SPaul Walmsley * Is the MPU PRCM interrupt handler racing with the 2838cb0ac99SPaul Walmsley * IVA2 PRCM interrupt handler ? 2848cb0ac99SPaul Walmsley */ 2858cb0ac99SPaul Walmsley WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup " 2868cb0ac99SPaul Walmsley "but no wakeup sources are marked\n"); 2878cb0ac99SPaul Walmsley } else { 2888cb0ac99SPaul Walmsley /* XXX we need to expand our PRCM interrupt handler */ 2898cb0ac99SPaul Walmsley WARN(1, "prcm: WARNING: PRCM interrupt received, but " 2908cb0ac99SPaul Walmsley "no code to handle it (%08x)\n", irqstatus_mpu); 2918cb0ac99SPaul Walmsley } 2928cb0ac99SPaul Walmsley 2938bd22949SKevin Hilman prm_write_mod_reg(irqstatus_mpu, OCP_MOD, 2948bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 2958bd22949SKevin Hilman 296d6290a3eSKevin Hilman irqstatus_mpu = prm_read_mod_reg(OCP_MOD, 297d6290a3eSKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 298d6290a3eSKevin Hilman irqstatus_mpu &= irqenable_mpu; 299d6290a3eSKevin Hilman 300d6290a3eSKevin Hilman } while (irqstatus_mpu); 3018bd22949SKevin Hilman 3028bd22949SKevin Hilman return IRQ_HANDLED; 3038bd22949SKevin Hilman } 3048bd22949SKevin Hilman 30557f277b0SRajendra Nayak static void restore_control_register(u32 val) 30657f277b0SRajendra Nayak { 30757f277b0SRajendra Nayak __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val)); 30857f277b0SRajendra Nayak } 30957f277b0SRajendra Nayak 31057f277b0SRajendra Nayak /* Function to restore the table entry that was modified for enabling MMU */ 31157f277b0SRajendra Nayak static void restore_table_entry(void) 31257f277b0SRajendra Nayak { 3134d63bc1dSManjunath Kondaiah G void __iomem *scratchpad_address; 31457f277b0SRajendra Nayak u32 previous_value, control_reg_value; 31557f277b0SRajendra Nayak u32 *address; 31657f277b0SRajendra Nayak 31757f277b0SRajendra Nayak scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD); 31857f277b0SRajendra Nayak 31957f277b0SRajendra Nayak /* Get address of entry that was modified */ 32057f277b0SRajendra Nayak address = (u32 *)__raw_readl(scratchpad_address + 32157f277b0SRajendra Nayak OMAP343X_TABLE_ADDRESS_OFFSET); 32257f277b0SRajendra Nayak /* Get the previous value which needs to be restored */ 32357f277b0SRajendra Nayak previous_value = __raw_readl(scratchpad_address + 32457f277b0SRajendra Nayak OMAP343X_TABLE_VALUE_OFFSET); 32557f277b0SRajendra Nayak address = __va(address); 32657f277b0SRajendra Nayak *address = previous_value; 32757f277b0SRajendra Nayak flush_tlb_all(); 32857f277b0SRajendra Nayak control_reg_value = __raw_readl(scratchpad_address 32957f277b0SRajendra Nayak + OMAP343X_CONTROL_REG_VALUE_OFFSET); 33057f277b0SRajendra Nayak /* This will enable caches and prediction */ 33157f277b0SRajendra Nayak restore_control_register(control_reg_value); 33257f277b0SRajendra Nayak } 33357f277b0SRajendra Nayak 33499e6a4d2SRajendra Nayak void omap_sram_idle(void) 3358bd22949SKevin Hilman { 3368bd22949SKevin Hilman /* Variable to tell what needs to be saved and restored 3378bd22949SKevin Hilman * in omap_sram_idle*/ 3388bd22949SKevin Hilman /* save_state = 0 => Nothing to save and restored */ 3398bd22949SKevin Hilman /* save_state = 1 => Only L1 and logic lost */ 3408bd22949SKevin Hilman /* save_state = 2 => Only L2 lost */ 3418bd22949SKevin Hilman /* save_state = 3 => L1, L2 and logic lost */ 342fa3c2a4fSRajendra Nayak int save_state = 0; 343fa3c2a4fSRajendra Nayak int mpu_next_state = PWRDM_POWER_ON; 344fa3c2a4fSRajendra Nayak int per_next_state = PWRDM_POWER_ON; 345fa3c2a4fSRajendra Nayak int core_next_state = PWRDM_POWER_ON; 3462f5939c3SRajendra Nayak int core_prev_state, per_prev_state; 34713a6fe0fSTero Kristo u32 sdrc_pwr = 0; 3488bd22949SKevin Hilman 3498bd22949SKevin Hilman if (!_omap_sram_idle) 3508bd22949SKevin Hilman return; 3518bd22949SKevin Hilman 352fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(mpu_pwrdm); 353fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(neon_pwrdm); 354fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(core_pwrdm); 355fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(per_pwrdm); 356fa3c2a4fSRajendra Nayak 3578bd22949SKevin Hilman mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 3588bd22949SKevin Hilman switch (mpu_next_state) { 359fa3c2a4fSRajendra Nayak case PWRDM_POWER_ON: 3608bd22949SKevin Hilman case PWRDM_POWER_RET: 3618bd22949SKevin Hilman /* No need to save context */ 3628bd22949SKevin Hilman save_state = 0; 3638bd22949SKevin Hilman break; 36461255ab9SRajendra Nayak case PWRDM_POWER_OFF: 36561255ab9SRajendra Nayak save_state = 3; 36661255ab9SRajendra Nayak break; 3678bd22949SKevin Hilman default: 3688bd22949SKevin Hilman /* Invalid state */ 3698bd22949SKevin Hilman printk(KERN_ERR "Invalid mpu state in sram_idle\n"); 3708bd22949SKevin Hilman return; 3718bd22949SKevin Hilman } 372fe617af7SPeter 'p2' De Schrijver pwrdm_pre_transition(); 373fe617af7SPeter 'p2' De Schrijver 374fa3c2a4fSRajendra Nayak /* NEON control */ 375fa3c2a4fSRajendra Nayak if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) 3767139178eSJouni Hogander pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); 377fa3c2a4fSRajendra Nayak 37840742fa8SMike Chan /* Enable IO-PAD and IO-CHAIN wakeups */ 379fa3c2a4fSRajendra Nayak per_next_state = pwrdm_read_next_pwrst(per_pwrdm); 380ecf157d0STero Kristo core_next_state = pwrdm_read_next_pwrst(core_pwrdm); 381d5c47d7eSKevin Hilman if (omap3_has_io_wakeup() && 382ad0c63f1Sstanley.miao (per_next_state < PWRDM_POWER_ON || 383ad0c63f1Sstanley.miao core_next_state < PWRDM_POWER_ON)) { 3842bc4ef71SPaul Walmsley prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); 38540742fa8SMike Chan omap3_enable_io_chain(); 38640742fa8SMike Chan } 38740742fa8SMike Chan 38840742fa8SMike Chan /* PER */ 3892f5939c3SRajendra Nayak if (per_next_state < PWRDM_POWER_ON) { 3904af4016cSKevin Hilman omap_uart_prepare_idle(2); 391cd4f1faeSGovindraj.R omap_uart_prepare_idle(3); 39243ffcd9aSKevin Hilman omap2_gpio_prepare_for_idle(per_next_state); 393e7410cf7SKevin Hilman if (per_next_state == PWRDM_POWER_OFF) 3942f5939c3SRajendra Nayak omap3_per_save_context(); 3952f5939c3SRajendra Nayak } 396c16c3f67STero Kristo 397658ce97eSKevin Hilman /* CORE */ 398658ce97eSKevin Hilman if (core_next_state < PWRDM_POWER_ON) { 399658ce97eSKevin Hilman omap_uart_prepare_idle(0); 400658ce97eSKevin Hilman omap_uart_prepare_idle(1); 4012f5939c3SRajendra Nayak if (core_next_state == PWRDM_POWER_OFF) { 4022f5939c3SRajendra Nayak omap3_core_save_context(); 4032f5939c3SRajendra Nayak omap3_prcm_save_context(); 4042f5939c3SRajendra Nayak } 405fa3c2a4fSRajendra Nayak } 40640742fa8SMike Chan 407f18cc2ffSTero Kristo omap3_intc_prepare_idle(); 4088bd22949SKevin Hilman 40961255ab9SRajendra Nayak /* 410f265dc4cSRajendra Nayak * On EMU/HS devices ROM code restores a SRDC value 411f265dc4cSRajendra Nayak * from scratchpad which has automatic self refresh on timeout 412f265dc4cSRajendra Nayak * of AUTO_CNT = 1 enabled. This takes care of errata 1.142. 413f265dc4cSRajendra Nayak * Hence store/restore the SDRC_POWER register here. 41413a6fe0fSTero Kristo */ 41513a6fe0fSTero Kristo if (omap_rev() >= OMAP3430_REV_ES3_0 && 41613a6fe0fSTero Kristo omap_type() != OMAP2_DEVICE_TYPE_GP && 417f265dc4cSRajendra Nayak core_next_state == PWRDM_POWER_OFF) 41813a6fe0fSTero Kristo sdrc_pwr = sdrc_read_reg(SDRC_POWER); 41913a6fe0fSTero Kristo 42013a6fe0fSTero Kristo /* 42161255ab9SRajendra Nayak * omap3_arm_context is the location where ARM registers 42261255ab9SRajendra Nayak * get saved. The restore path then reads from this 42361255ab9SRajendra Nayak * location and restores them back. 42461255ab9SRajendra Nayak */ 42561255ab9SRajendra Nayak _omap_sram_idle(omap3_arm_context, save_state); 4268bd22949SKevin Hilman cpu_init(); 4278bd22949SKevin Hilman 428f265dc4cSRajendra Nayak /* Restore normal SDRC POWER settings */ 42913a6fe0fSTero Kristo if (omap_rev() >= OMAP3430_REV_ES3_0 && 43013a6fe0fSTero Kristo omap_type() != OMAP2_DEVICE_TYPE_GP && 43113a6fe0fSTero Kristo core_next_state == PWRDM_POWER_OFF) 43213a6fe0fSTero Kristo sdrc_write_reg(sdrc_pwr, SDRC_POWER); 43313a6fe0fSTero Kristo 43457f277b0SRajendra Nayak /* Restore table entry modified during MMU restoration */ 43557f277b0SRajendra Nayak if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF) 43657f277b0SRajendra Nayak restore_table_entry(); 43757f277b0SRajendra Nayak 438658ce97eSKevin Hilman /* CORE */ 439fa3c2a4fSRajendra Nayak if (core_next_state < PWRDM_POWER_ON) { 4402f5939c3SRajendra Nayak core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); 4412f5939c3SRajendra Nayak if (core_prev_state == PWRDM_POWER_OFF) { 4422f5939c3SRajendra Nayak omap3_core_restore_context(); 4432f5939c3SRajendra Nayak omap3_prcm_restore_context(); 4442f5939c3SRajendra Nayak omap3_sram_restore_context(); 4458a917d2fSKalle Jokiniemi omap2_sms_restore_context(); 4462f5939c3SRajendra Nayak } 447658ce97eSKevin Hilman omap_uart_resume_idle(0); 448658ce97eSKevin Hilman omap_uart_resume_idle(1); 449658ce97eSKevin Hilman if (core_next_state == PWRDM_POWER_OFF) 4502bc4ef71SPaul Walmsley prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, 451658ce97eSKevin Hilman OMAP3430_GR_MOD, 452658ce97eSKevin Hilman OMAP3_PRM_VOLTCTRL_OFFSET); 453658ce97eSKevin Hilman } 454f18cc2ffSTero Kristo omap3_intc_resume_idle(); 455658ce97eSKevin Hilman 456658ce97eSKevin Hilman /* PER */ 4572f5939c3SRajendra Nayak if (per_next_state < PWRDM_POWER_ON) { 458658ce97eSKevin Hilman per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); 45943ffcd9aSKevin Hilman omap2_gpio_resume_after_idle(); 46043ffcd9aSKevin Hilman if (per_prev_state == PWRDM_POWER_OFF) 4612f5939c3SRajendra Nayak omap3_per_restore_context(); 462ecf157d0STero Kristo omap_uart_resume_idle(2); 463cd4f1faeSGovindraj.R omap_uart_resume_idle(3); 464fa3c2a4fSRajendra Nayak } 465fe617af7SPeter 'p2' De Schrijver 4663a7ec26bSKalle Jokiniemi /* Disable IO-PAD and IO-CHAIN wakeup */ 46758a5559eSKevin Hilman if (omap3_has_io_wakeup() && 46858a5559eSKevin Hilman (per_next_state < PWRDM_POWER_ON || 46958a5559eSKevin Hilman core_next_state < PWRDM_POWER_ON)) { 4702bc4ef71SPaul Walmsley prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); 4713a7ec26bSKalle Jokiniemi omap3_disable_io_chain(); 4723a7ec26bSKalle Jokiniemi } 473658ce97eSKevin Hilman 474fe617af7SPeter 'p2' De Schrijver pwrdm_post_transition(); 475fe617af7SPeter 'p2' De Schrijver 476c16c3f67STero Kristo omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); 4778bd22949SKevin Hilman } 4788bd22949SKevin Hilman 47920b01669SRajendra Nayak int omap3_can_sleep(void) 4808bd22949SKevin Hilman { 481c40552bcSKevin Hilman if (!sleep_while_idle) 482c40552bcSKevin Hilman return 0; 4834af4016cSKevin Hilman if (!omap_uart_can_sleep()) 4844af4016cSKevin Hilman return 0; 4858bd22949SKevin Hilman return 1; 4868bd22949SKevin Hilman } 4878bd22949SKevin Hilman 4888bd22949SKevin Hilman static void omap3_pm_idle(void) 4898bd22949SKevin Hilman { 4908bd22949SKevin Hilman local_irq_disable(); 4918bd22949SKevin Hilman local_fiq_disable(); 4928bd22949SKevin Hilman 4938bd22949SKevin Hilman if (!omap3_can_sleep()) 4948bd22949SKevin Hilman goto out; 4958bd22949SKevin Hilman 496cf22854cSTero Kristo if (omap_irq_pending() || need_resched()) 4978bd22949SKevin Hilman goto out; 4988bd22949SKevin Hilman 4998bd22949SKevin Hilman omap_sram_idle(); 5008bd22949SKevin Hilman 5018bd22949SKevin Hilman out: 5028bd22949SKevin Hilman local_fiq_enable(); 5038bd22949SKevin Hilman local_irq_enable(); 5048bd22949SKevin Hilman } 5058bd22949SKevin Hilman 50610f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 5072466211eSTero Kristo static suspend_state_t suspend_state; 5082466211eSTero Kristo 5098bd22949SKevin Hilman static int omap3_pm_prepare(void) 5108bd22949SKevin Hilman { 5118bd22949SKevin Hilman disable_hlt(); 5128bd22949SKevin Hilman return 0; 5138bd22949SKevin Hilman } 5148bd22949SKevin Hilman 5158bd22949SKevin Hilman static int omap3_pm_suspend(void) 5168bd22949SKevin Hilman { 5178bd22949SKevin Hilman struct power_state *pwrst; 5188bd22949SKevin Hilman int state, ret = 0; 5198bd22949SKevin Hilman 5208e2efde9SAri Kauppi if (wakeup_timer_seconds || wakeup_timer_milliseconds) 5218e2efde9SAri Kauppi omap2_pm_wakeup_on_timer(wakeup_timer_seconds, 5228e2efde9SAri Kauppi wakeup_timer_milliseconds); 523d7814e4dSKevin Hilman 5248bd22949SKevin Hilman /* Read current next_pwrsts */ 5258bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) 5268bd22949SKevin Hilman pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 5278bd22949SKevin Hilman /* Set ones wanted by suspend */ 5288bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 529eb6a2c75SSantosh Shilimkar if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) 5308bd22949SKevin Hilman goto restore; 5318bd22949SKevin Hilman if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) 5328bd22949SKevin Hilman goto restore; 5338bd22949SKevin Hilman } 5348bd22949SKevin Hilman 5354af4016cSKevin Hilman omap_uart_prepare_suspend(); 5362bbe3af3STero Kristo omap3_intc_suspend(); 5372bbe3af3STero Kristo 5388bd22949SKevin Hilman omap_sram_idle(); 5398bd22949SKevin Hilman 5408bd22949SKevin Hilman restore: 5418bd22949SKevin Hilman /* Restore next_pwrsts */ 5428bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 5438bd22949SKevin Hilman state = pwrdm_read_prev_pwrst(pwrst->pwrdm); 5448bd22949SKevin Hilman if (state > pwrst->next_state) { 5458bd22949SKevin Hilman printk(KERN_INFO "Powerdomain (%s) didn't enter " 5468bd22949SKevin Hilman "target state %d\n", 5478bd22949SKevin Hilman pwrst->pwrdm->name, pwrst->next_state); 5488bd22949SKevin Hilman ret = -1; 5498bd22949SKevin Hilman } 550eb6a2c75SSantosh Shilimkar omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); 5518bd22949SKevin Hilman } 5528bd22949SKevin Hilman if (ret) 5538bd22949SKevin Hilman printk(KERN_ERR "Could not enter target state in pm_suspend\n"); 5548bd22949SKevin Hilman else 5558bd22949SKevin Hilman printk(KERN_INFO "Successfully put all powerdomains " 5568bd22949SKevin Hilman "to target state\n"); 5578bd22949SKevin Hilman 5588bd22949SKevin Hilman return ret; 5598bd22949SKevin Hilman } 5608bd22949SKevin Hilman 5612466211eSTero Kristo static int omap3_pm_enter(suspend_state_t unused) 5628bd22949SKevin Hilman { 5638bd22949SKevin Hilman int ret = 0; 5648bd22949SKevin Hilman 5652466211eSTero Kristo switch (suspend_state) { 5668bd22949SKevin Hilman case PM_SUSPEND_STANDBY: 5678bd22949SKevin Hilman case PM_SUSPEND_MEM: 5688bd22949SKevin Hilman ret = omap3_pm_suspend(); 5698bd22949SKevin Hilman break; 5708bd22949SKevin Hilman default: 5718bd22949SKevin Hilman ret = -EINVAL; 5728bd22949SKevin Hilman } 5738bd22949SKevin Hilman 5748bd22949SKevin Hilman return ret; 5758bd22949SKevin Hilman } 5768bd22949SKevin Hilman 5778bd22949SKevin Hilman static void omap3_pm_finish(void) 5788bd22949SKevin Hilman { 5798bd22949SKevin Hilman enable_hlt(); 5808bd22949SKevin Hilman } 5818bd22949SKevin Hilman 5822466211eSTero Kristo /* Hooks to enable / disable UART interrupts during suspend */ 5832466211eSTero Kristo static int omap3_pm_begin(suspend_state_t state) 5842466211eSTero Kristo { 5852466211eSTero Kristo suspend_state = state; 5862466211eSTero Kristo omap_uart_enable_irqs(0); 5872466211eSTero Kristo return 0; 5882466211eSTero Kristo } 5892466211eSTero Kristo 5902466211eSTero Kristo static void omap3_pm_end(void) 5912466211eSTero Kristo { 5922466211eSTero Kristo suspend_state = PM_SUSPEND_ON; 5932466211eSTero Kristo omap_uart_enable_irqs(1); 5942466211eSTero Kristo return; 5952466211eSTero Kristo } 5962466211eSTero Kristo 5972f55ac07SLionel Debroux static const struct platform_suspend_ops omap_pm_ops = { 5982466211eSTero Kristo .begin = omap3_pm_begin, 5992466211eSTero Kristo .end = omap3_pm_end, 6008bd22949SKevin Hilman .prepare = omap3_pm_prepare, 6018bd22949SKevin Hilman .enter = omap3_pm_enter, 6028bd22949SKevin Hilman .finish = omap3_pm_finish, 6038bd22949SKevin Hilman .valid = suspend_valid_only_mem, 6048bd22949SKevin Hilman }; 60510f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 6068bd22949SKevin Hilman 6071155e426SKevin Hilman 6081155e426SKevin Hilman /** 6091155e426SKevin Hilman * omap3_iva_idle(): ensure IVA is in idle so it can be put into 6101155e426SKevin Hilman * retention 6111155e426SKevin Hilman * 6121155e426SKevin Hilman * In cases where IVA2 is activated by bootcode, it may prevent 6131155e426SKevin Hilman * full-chip retention or off-mode because it is not idle. This 6141155e426SKevin Hilman * function forces the IVA2 into idle state so it can go 6151155e426SKevin Hilman * into retention/off and thus allow full-chip retention/off. 6161155e426SKevin Hilman * 6171155e426SKevin Hilman **/ 6181155e426SKevin Hilman static void __init omap3_iva_idle(void) 6191155e426SKevin Hilman { 6201155e426SKevin Hilman /* ensure IVA2 clock is disabled */ 6211155e426SKevin Hilman cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 6221155e426SKevin Hilman 6231155e426SKevin Hilman /* if no clock activity, nothing else to do */ 6241155e426SKevin Hilman if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & 6251155e426SKevin Hilman OMAP3430_CLKACTIVITY_IVA2_MASK)) 6261155e426SKevin Hilman return; 6271155e426SKevin Hilman 6281155e426SKevin Hilman /* Reset IVA2 */ 6292bc4ef71SPaul Walmsley prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | 6302bc4ef71SPaul Walmsley OMAP3430_RST2_IVA2_MASK | 6312bc4ef71SPaul Walmsley OMAP3430_RST3_IVA2_MASK, 63237903009SAbhijit Pagare OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 6331155e426SKevin Hilman 6341155e426SKevin Hilman /* Enable IVA2 clock */ 635dfa6d6f8SKevin Hilman cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, 6361155e426SKevin Hilman OMAP3430_IVA2_MOD, CM_FCLKEN); 6371155e426SKevin Hilman 6381155e426SKevin Hilman /* Set IVA2 boot mode to 'idle' */ 6391155e426SKevin Hilman omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, 6401155e426SKevin Hilman OMAP343X_CONTROL_IVA2_BOOTMOD); 6411155e426SKevin Hilman 6421155e426SKevin Hilman /* Un-reset IVA2 */ 64337903009SAbhijit Pagare prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 6441155e426SKevin Hilman 6451155e426SKevin Hilman /* Disable IVA2 clock */ 6461155e426SKevin Hilman cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 6471155e426SKevin Hilman 6481155e426SKevin Hilman /* Reset IVA2 */ 6492bc4ef71SPaul Walmsley prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | 6502bc4ef71SPaul Walmsley OMAP3430_RST2_IVA2_MASK | 6512bc4ef71SPaul Walmsley OMAP3430_RST3_IVA2_MASK, 65237903009SAbhijit Pagare OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 6531155e426SKevin Hilman } 6541155e426SKevin Hilman 6558111b221SKevin Hilman static void __init omap3_d2d_idle(void) 6568bd22949SKevin Hilman { 6578111b221SKevin Hilman u16 mask, padconf; 6588111b221SKevin Hilman 6598111b221SKevin Hilman /* In a stand alone OMAP3430 where there is not a stacked 6608111b221SKevin Hilman * modem for the D2D Idle Ack and D2D MStandby must be pulled 6618111b221SKevin Hilman * high. S CONTROL_PADCONF_SAD2D_IDLEACK and 6628111b221SKevin Hilman * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ 6638111b221SKevin Hilman mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ 6648111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); 6658111b221SKevin Hilman padconf |= mask; 6668111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); 6678111b221SKevin Hilman 6688111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); 6698111b221SKevin Hilman padconf |= mask; 6708111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 6718111b221SKevin Hilman 6728bd22949SKevin Hilman /* reset modem */ 6732bc4ef71SPaul Walmsley prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | 6742bc4ef71SPaul Walmsley OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, 67537903009SAbhijit Pagare CORE_MOD, OMAP2_RM_RSTCTRL); 67637903009SAbhijit Pagare prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); 6778111b221SKevin Hilman } 6788bd22949SKevin Hilman 6798111b221SKevin Hilman static void __init prcm_setup_regs(void) 6808111b221SKevin Hilman { 681e5863689SGovindraj.R u32 omap3630_auto_uart4_mask = cpu_is_omap3630() ? 682e5863689SGovindraj.R OMAP3630_AUTO_UART4_MASK : 0; 683e5863689SGovindraj.R u32 omap3630_en_uart4_mask = cpu_is_omap3630() ? 684e5863689SGovindraj.R OMAP3630_EN_UART4_MASK : 0; 685e5863689SGovindraj.R u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ? 686e5863689SGovindraj.R OMAP3630_GRPSEL_UART4_MASK : 0; 687e5863689SGovindraj.R 688e5863689SGovindraj.R 6898bd22949SKevin Hilman /* XXX Reset all wkdeps. This should be done when initializing 6908bd22949SKevin Hilman * powerdomains */ 6918bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); 6928bd22949SKevin Hilman prm_write_mod_reg(0, MPU_MOD, PM_WKDEP); 6938bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP); 6948bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP); 6958bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP); 6968bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP); 6978bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 6988bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP); 6998bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP); 7008bd22949SKevin Hilman } else 7018bd22949SKevin Hilman prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); 7028bd22949SKevin Hilman 7038bd22949SKevin Hilman /* 7048bd22949SKevin Hilman * Enable interface clock autoidle for all modules. 7058bd22949SKevin Hilman * Note that in the long run this should be done by clockfw 7068bd22949SKevin Hilman */ 7078bd22949SKevin Hilman cm_write_mod_reg( 7082bc4ef71SPaul Walmsley OMAP3430_AUTO_MODEM_MASK | 7092bc4ef71SPaul Walmsley OMAP3430ES2_AUTO_MMC3_MASK | 7102bc4ef71SPaul Walmsley OMAP3430ES2_AUTO_ICR_MASK | 7112bc4ef71SPaul Walmsley OMAP3430_AUTO_AES2_MASK | 7122bc4ef71SPaul Walmsley OMAP3430_AUTO_SHA12_MASK | 7132bc4ef71SPaul Walmsley OMAP3430_AUTO_DES2_MASK | 7142bc4ef71SPaul Walmsley OMAP3430_AUTO_MMC2_MASK | 7152bc4ef71SPaul Walmsley OMAP3430_AUTO_MMC1_MASK | 7162bc4ef71SPaul Walmsley OMAP3430_AUTO_MSPRO_MASK | 7172bc4ef71SPaul Walmsley OMAP3430_AUTO_HDQ_MASK | 7182bc4ef71SPaul Walmsley OMAP3430_AUTO_MCSPI4_MASK | 7192bc4ef71SPaul Walmsley OMAP3430_AUTO_MCSPI3_MASK | 7202bc4ef71SPaul Walmsley OMAP3430_AUTO_MCSPI2_MASK | 7212bc4ef71SPaul Walmsley OMAP3430_AUTO_MCSPI1_MASK | 7222bc4ef71SPaul Walmsley OMAP3430_AUTO_I2C3_MASK | 7232bc4ef71SPaul Walmsley OMAP3430_AUTO_I2C2_MASK | 7242bc4ef71SPaul Walmsley OMAP3430_AUTO_I2C1_MASK | 7252bc4ef71SPaul Walmsley OMAP3430_AUTO_UART2_MASK | 7262bc4ef71SPaul Walmsley OMAP3430_AUTO_UART1_MASK | 7272bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT11_MASK | 7282bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT10_MASK | 7292bc4ef71SPaul Walmsley OMAP3430_AUTO_MCBSP5_MASK | 7302bc4ef71SPaul Walmsley OMAP3430_AUTO_MCBSP1_MASK | 7312bc4ef71SPaul Walmsley OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */ 7322bc4ef71SPaul Walmsley OMAP3430_AUTO_MAILBOXES_MASK | 7332bc4ef71SPaul Walmsley OMAP3430_AUTO_OMAPCTRL_MASK | 7342bc4ef71SPaul Walmsley OMAP3430ES1_AUTO_FSHOSTUSB_MASK | 7352bc4ef71SPaul Walmsley OMAP3430_AUTO_HSOTGUSB_MASK | 7362bc4ef71SPaul Walmsley OMAP3430_AUTO_SAD2D_MASK | 7372bc4ef71SPaul Walmsley OMAP3430_AUTO_SSI_MASK, 7388bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE1); 7398bd22949SKevin Hilman 7408bd22949SKevin Hilman cm_write_mod_reg( 7412bc4ef71SPaul Walmsley OMAP3430_AUTO_PKA_MASK | 7422bc4ef71SPaul Walmsley OMAP3430_AUTO_AES1_MASK | 7432bc4ef71SPaul Walmsley OMAP3430_AUTO_RNG_MASK | 7442bc4ef71SPaul Walmsley OMAP3430_AUTO_SHA11_MASK | 7452bc4ef71SPaul Walmsley OMAP3430_AUTO_DES1_MASK, 7468bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE2); 7478bd22949SKevin Hilman 7488bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 7498bd22949SKevin Hilman cm_write_mod_reg( 7502bc4ef71SPaul Walmsley OMAP3430_AUTO_MAD2D_MASK | 7512bc4ef71SPaul Walmsley OMAP3430ES2_AUTO_USBTLL_MASK, 7528bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE3); 7538bd22949SKevin Hilman } 7548bd22949SKevin Hilman 7558bd22949SKevin Hilman cm_write_mod_reg( 7562bc4ef71SPaul Walmsley OMAP3430_AUTO_WDT2_MASK | 7572bc4ef71SPaul Walmsley OMAP3430_AUTO_WDT1_MASK | 7582bc4ef71SPaul Walmsley OMAP3430_AUTO_GPIO1_MASK | 7592bc4ef71SPaul Walmsley OMAP3430_AUTO_32KSYNC_MASK | 7602bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT12_MASK | 7612bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT1_MASK, 7628bd22949SKevin Hilman WKUP_MOD, CM_AUTOIDLE); 7638bd22949SKevin Hilman 7648bd22949SKevin Hilman cm_write_mod_reg( 7652bc4ef71SPaul Walmsley OMAP3430_AUTO_DSS_MASK, 7668bd22949SKevin Hilman OMAP3430_DSS_MOD, 7678bd22949SKevin Hilman CM_AUTOIDLE); 7688bd22949SKevin Hilman 7698bd22949SKevin Hilman cm_write_mod_reg( 7702bc4ef71SPaul Walmsley OMAP3430_AUTO_CAM_MASK, 7718bd22949SKevin Hilman OMAP3430_CAM_MOD, 7728bd22949SKevin Hilman CM_AUTOIDLE); 7738bd22949SKevin Hilman 7748bd22949SKevin Hilman cm_write_mod_reg( 775e5863689SGovindraj.R omap3630_auto_uart4_mask | 7762bc4ef71SPaul Walmsley OMAP3430_AUTO_GPIO6_MASK | 7772bc4ef71SPaul Walmsley OMAP3430_AUTO_GPIO5_MASK | 7782bc4ef71SPaul Walmsley OMAP3430_AUTO_GPIO4_MASK | 7792bc4ef71SPaul Walmsley OMAP3430_AUTO_GPIO3_MASK | 7802bc4ef71SPaul Walmsley OMAP3430_AUTO_GPIO2_MASK | 7812bc4ef71SPaul Walmsley OMAP3430_AUTO_WDT3_MASK | 7822bc4ef71SPaul Walmsley OMAP3430_AUTO_UART3_MASK | 7832bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT9_MASK | 7842bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT8_MASK | 7852bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT7_MASK | 7862bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT6_MASK | 7872bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT5_MASK | 7882bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT4_MASK | 7892bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT3_MASK | 7902bc4ef71SPaul Walmsley OMAP3430_AUTO_GPT2_MASK | 7912bc4ef71SPaul Walmsley OMAP3430_AUTO_MCBSP4_MASK | 7922bc4ef71SPaul Walmsley OMAP3430_AUTO_MCBSP3_MASK | 7932bc4ef71SPaul Walmsley OMAP3430_AUTO_MCBSP2_MASK, 7948bd22949SKevin Hilman OMAP3430_PER_MOD, 7958bd22949SKevin Hilman CM_AUTOIDLE); 7968bd22949SKevin Hilman 7978bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 7988bd22949SKevin Hilman cm_write_mod_reg( 7992bc4ef71SPaul Walmsley OMAP3430ES2_AUTO_USBHOST_MASK, 8008bd22949SKevin Hilman OMAP3430ES2_USBHOST_MOD, 8018bd22949SKevin Hilman CM_AUTOIDLE); 8028bd22949SKevin Hilman } 8038bd22949SKevin Hilman 8042fd0f75cSPaul Walmsley omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); 805b296c811STero Kristo 8068bd22949SKevin Hilman /* 8078bd22949SKevin Hilman * Set all plls to autoidle. This is needed until autoidle is 8088bd22949SKevin Hilman * enabled by clockfw 8098bd22949SKevin Hilman */ 8108bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, 8118bd22949SKevin Hilman OMAP3430_IVA2_MOD, CM_AUTOIDLE2); 8128bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT, 8138bd22949SKevin Hilman MPU_MOD, 8148bd22949SKevin Hilman CM_AUTOIDLE2); 8158bd22949SKevin Hilman cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | 8168bd22949SKevin Hilman (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT), 8178bd22949SKevin Hilman PLL_MOD, 8188bd22949SKevin Hilman CM_AUTOIDLE); 8198bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, 8208bd22949SKevin Hilman PLL_MOD, 8218bd22949SKevin Hilman CM_AUTOIDLE2); 8228bd22949SKevin Hilman 8238bd22949SKevin Hilman /* 8248bd22949SKevin Hilman * Enable control of expternal oscillator through 8258bd22949SKevin Hilman * sys_clkreq. In the long run clock framework should 8268bd22949SKevin Hilman * take care of this. 8278bd22949SKevin Hilman */ 8288bd22949SKevin Hilman prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 8298bd22949SKevin Hilman 1 << OMAP_AUTOEXTCLKMODE_SHIFT, 8308bd22949SKevin Hilman OMAP3430_GR_MOD, 8318bd22949SKevin Hilman OMAP3_PRM_CLKSRC_CTRL_OFFSET); 8328bd22949SKevin Hilman 8338bd22949SKevin Hilman /* setup wakup source */ 8342fd0f75cSPaul Walmsley prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | 8352fd0f75cSPaul Walmsley OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, 8368bd22949SKevin Hilman WKUP_MOD, PM_WKEN); 8378bd22949SKevin Hilman /* No need to write EN_IO, that is always enabled */ 838275f675cSPaul Walmsley prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | 839275f675cSPaul Walmsley OMAP3430_GRPSEL_GPT1_MASK | 840275f675cSPaul Walmsley OMAP3430_GRPSEL_GPT12_MASK, 8418bd22949SKevin Hilman WKUP_MOD, OMAP3430_PM_MPUGRPSEL); 8428bd22949SKevin Hilman /* For some reason IO doesn't generate wakeup event even if 8438bd22949SKevin Hilman * it is selected to mpu wakeup goup */ 8442bc4ef71SPaul Walmsley prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK, 8458bd22949SKevin Hilman OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); 8461155e426SKevin Hilman 847b92c5721SSubramani Venkatesh /* Enable PM_WKEN to support DSS LPR */ 8482bc4ef71SPaul Walmsley prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, 849b92c5721SSubramani Venkatesh OMAP3430_DSS_MOD, PM_WKEN); 850b92c5721SSubramani Venkatesh 851b427f92fSKevin Hilman /* Enable wakeups in PER */ 852e5863689SGovindraj.R prm_write_mod_reg(omap3630_en_uart4_mask | 853e5863689SGovindraj.R OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | 8542fd0f75cSPaul Walmsley OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | 8552fd0f75cSPaul Walmsley OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | 8562fd0f75cSPaul Walmsley OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK | 8572fd0f75cSPaul Walmsley OMAP3430_EN_MCBSP4_MASK, 858b427f92fSKevin Hilman OMAP3430_PER_MOD, PM_WKEN); 859eb350f74SKevin Hilman /* and allow them to wake up MPU */ 860e5863689SGovindraj.R prm_write_mod_reg(omap3630_grpsel_uart4_mask | 861e5863689SGovindraj.R OMAP3430_GRPSEL_GPIO2_MASK | 862275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO3_MASK | 863275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO4_MASK | 864275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO5_MASK | 865275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO6_MASK | 866275f675cSPaul Walmsley OMAP3430_GRPSEL_UART3_MASK | 867275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP2_MASK | 868275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP3_MASK | 869275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP4_MASK, 870eb350f74SKevin Hilman OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); 871eb350f74SKevin Hilman 872d3fd3290SKevin Hilman /* Don't attach IVA interrupts */ 873d3fd3290SKevin Hilman prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 874d3fd3290SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 875d3fd3290SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 876d3fd3290SKevin Hilman prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); 877d3fd3290SKevin Hilman 878b1340d17SKevin Hilman /* Clear any pending 'reset' flags */ 87937903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); 88037903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); 88137903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); 88237903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); 88337903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); 88437903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); 88537903009SAbhijit Pagare prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); 886b1340d17SKevin Hilman 887014c46dbSKevin Hilman /* Clear any pending PRCM interrupts */ 888014c46dbSKevin Hilman prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 889014c46dbSKevin Hilman 8901155e426SKevin Hilman omap3_iva_idle(); 8918111b221SKevin Hilman omap3_d2d_idle(); 8928bd22949SKevin Hilman } 8938bd22949SKevin Hilman 894c40552bcSKevin Hilman void omap3_pm_off_mode_enable(int enable) 895c40552bcSKevin Hilman { 896c40552bcSKevin Hilman struct power_state *pwrst; 897c40552bcSKevin Hilman u32 state; 898c40552bcSKevin Hilman 899c40552bcSKevin Hilman if (enable) 900c40552bcSKevin Hilman state = PWRDM_POWER_OFF; 901c40552bcSKevin Hilman else 902c40552bcSKevin Hilman state = PWRDM_POWER_RET; 903c40552bcSKevin Hilman 9046af83b38SSanjeev Premi #ifdef CONFIG_CPU_IDLE 9056af83b38SSanjeev Premi omap3_cpuidle_update_states(); 9066af83b38SSanjeev Premi #endif 9076af83b38SSanjeev Premi 908c40552bcSKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 909c40552bcSKevin Hilman pwrst->next_state = state; 910eb6a2c75SSantosh Shilimkar omap_set_pwrdm_state(pwrst->pwrdm, state); 911c40552bcSKevin Hilman } 912c40552bcSKevin Hilman } 913c40552bcSKevin Hilman 91468d4778cSTero Kristo int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) 91568d4778cSTero Kristo { 91668d4778cSTero Kristo struct power_state *pwrst; 91768d4778cSTero Kristo 91868d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 91968d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) 92068d4778cSTero Kristo return pwrst->next_state; 92168d4778cSTero Kristo } 92268d4778cSTero Kristo return -EINVAL; 92368d4778cSTero Kristo } 92468d4778cSTero Kristo 92568d4778cSTero Kristo int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) 92668d4778cSTero Kristo { 92768d4778cSTero Kristo struct power_state *pwrst; 92868d4778cSTero Kristo 92968d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 93068d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) { 93168d4778cSTero Kristo pwrst->next_state = state; 93268d4778cSTero Kristo return 0; 93368d4778cSTero Kristo } 93468d4778cSTero Kristo } 93568d4778cSTero Kristo return -EINVAL; 93668d4778cSTero Kristo } 93768d4778cSTero Kristo 938a23456e9SPeter 'p2' De Schrijver static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) 9398bd22949SKevin Hilman { 9408bd22949SKevin Hilman struct power_state *pwrst; 9418bd22949SKevin Hilman 9428bd22949SKevin Hilman if (!pwrdm->pwrsts) 9438bd22949SKevin Hilman return 0; 9448bd22949SKevin Hilman 945d3d381c6SMing Lei pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); 9468bd22949SKevin Hilman if (!pwrst) 9478bd22949SKevin Hilman return -ENOMEM; 9488bd22949SKevin Hilman pwrst->pwrdm = pwrdm; 9498bd22949SKevin Hilman pwrst->next_state = PWRDM_POWER_RET; 9508bd22949SKevin Hilman list_add(&pwrst->node, &pwrst_list); 9518bd22949SKevin Hilman 9528bd22949SKevin Hilman if (pwrdm_has_hdwr_sar(pwrdm)) 9538bd22949SKevin Hilman pwrdm_enable_hdwr_sar(pwrdm); 9548bd22949SKevin Hilman 955eb6a2c75SSantosh Shilimkar return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 9568bd22949SKevin Hilman } 9578bd22949SKevin Hilman 9588bd22949SKevin Hilman /* 9598bd22949SKevin Hilman * Enable hw supervised mode for all clockdomains if it's 9608bd22949SKevin Hilman * supported. Initiate sleep transition for other clockdomains, if 9618bd22949SKevin Hilman * they are not used 9628bd22949SKevin Hilman */ 963a23456e9SPeter 'p2' De Schrijver static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) 9648bd22949SKevin Hilman { 9658bd22949SKevin Hilman if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) 9668bd22949SKevin Hilman omap2_clkdm_allow_idle(clkdm); 9678bd22949SKevin Hilman else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && 9688bd22949SKevin Hilman atomic_read(&clkdm->usecount) == 0) 9698bd22949SKevin Hilman omap2_clkdm_sleep(clkdm); 9708bd22949SKevin Hilman return 0; 9718bd22949SKevin Hilman } 9728bd22949SKevin Hilman 9733231fc88SRajendra Nayak void omap_push_sram_idle(void) 9743231fc88SRajendra Nayak { 9753231fc88SRajendra Nayak _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend, 9763231fc88SRajendra Nayak omap34xx_cpu_suspend_sz); 97727d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) 97827d59a4aSTero Kristo _omap_save_secure_sram = omap_sram_push(save_secure_ram_context, 97927d59a4aSTero Kristo save_secure_ram_context_sz); 9803231fc88SRajendra Nayak } 9813231fc88SRajendra Nayak 9827cc515f7SKevin Hilman static int __init omap3_pm_init(void) 9838bd22949SKevin Hilman { 9848bd22949SKevin Hilman struct power_state *pwrst, *tmp; 98555ed9694SPaul Walmsley struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm; 9868bd22949SKevin Hilman int ret; 9878bd22949SKevin Hilman 9888bd22949SKevin Hilman if (!cpu_is_omap34xx()) 9898bd22949SKevin Hilman return -ENODEV; 9908bd22949SKevin Hilman 9918bd22949SKevin Hilman printk(KERN_ERR "Power Management for TI OMAP3.\n"); 9928bd22949SKevin Hilman 9938bd22949SKevin Hilman /* XXX prcm_setup_regs needs to be before enabling hw 9948bd22949SKevin Hilman * supervised mode for powerdomains */ 9958bd22949SKevin Hilman prcm_setup_regs(); 9968bd22949SKevin Hilman 9978bd22949SKevin Hilman ret = request_irq(INT_34XX_PRCM_MPU_IRQ, 9988bd22949SKevin Hilman (irq_handler_t)prcm_interrupt_handler, 9998bd22949SKevin Hilman IRQF_DISABLED, "prcm", NULL); 10008bd22949SKevin Hilman if (ret) { 10018bd22949SKevin Hilman printk(KERN_ERR "request_irq failed to register for 0x%x\n", 10028bd22949SKevin Hilman INT_34XX_PRCM_MPU_IRQ); 10038bd22949SKevin Hilman goto err1; 10048bd22949SKevin Hilman } 10058bd22949SKevin Hilman 1006a23456e9SPeter 'p2' De Schrijver ret = pwrdm_for_each(pwrdms_setup, NULL); 10078bd22949SKevin Hilman if (ret) { 10088bd22949SKevin Hilman printk(KERN_ERR "Failed to setup powerdomains\n"); 10098bd22949SKevin Hilman goto err2; 10108bd22949SKevin Hilman } 10118bd22949SKevin Hilman 1012a23456e9SPeter 'p2' De Schrijver (void) clkdm_for_each(clkdms_setup, NULL); 10138bd22949SKevin Hilman 10148bd22949SKevin Hilman mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); 10158bd22949SKevin Hilman if (mpu_pwrdm == NULL) { 10168bd22949SKevin Hilman printk(KERN_ERR "Failed to get mpu_pwrdm\n"); 10178bd22949SKevin Hilman goto err2; 10188bd22949SKevin Hilman } 10198bd22949SKevin Hilman 1020fa3c2a4fSRajendra Nayak neon_pwrdm = pwrdm_lookup("neon_pwrdm"); 1021fa3c2a4fSRajendra Nayak per_pwrdm = pwrdm_lookup("per_pwrdm"); 1022fa3c2a4fSRajendra Nayak core_pwrdm = pwrdm_lookup("core_pwrdm"); 1023c16c3f67STero Kristo cam_pwrdm = pwrdm_lookup("cam_pwrdm"); 1024fa3c2a4fSRajendra Nayak 102555ed9694SPaul Walmsley neon_clkdm = clkdm_lookup("neon_clkdm"); 102655ed9694SPaul Walmsley mpu_clkdm = clkdm_lookup("mpu_clkdm"); 102755ed9694SPaul Walmsley per_clkdm = clkdm_lookup("per_clkdm"); 102855ed9694SPaul Walmsley core_clkdm = clkdm_lookup("core_clkdm"); 102955ed9694SPaul Walmsley 10303231fc88SRajendra Nayak omap_push_sram_idle(); 103110f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 10328bd22949SKevin Hilman suspend_set_ops(&omap_pm_ops); 103310f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 10348bd22949SKevin Hilman 10358bd22949SKevin Hilman pm_idle = omap3_pm_idle; 10360343371eSKalle Jokiniemi omap3_idle_init(); 10378bd22949SKevin Hilman 103855ed9694SPaul Walmsley clkdm_add_wkdep(neon_clkdm, mpu_clkdm); 103927d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 104027d59a4aSTero Kristo omap3_secure_ram_storage = 104127d59a4aSTero Kristo kmalloc(0x803F, GFP_KERNEL); 104227d59a4aSTero Kristo if (!omap3_secure_ram_storage) 104327d59a4aSTero Kristo printk(KERN_ERR "Memory allocation failed when" 104427d59a4aSTero Kristo "allocating for secure sram context\n"); 104527d59a4aSTero Kristo 10469d97140bSTero Kristo local_irq_disable(); 10479d97140bSTero Kristo local_fiq_disable(); 10489d97140bSTero Kristo 10499d97140bSTero Kristo omap_dma_global_context_save(); 10509d97140bSTero Kristo omap3_save_secure_ram_context(PWRDM_POWER_ON); 10519d97140bSTero Kristo omap_dma_global_context_restore(); 10529d97140bSTero Kristo 10539d97140bSTero Kristo local_irq_enable(); 10549d97140bSTero Kristo local_fiq_enable(); 10559d97140bSTero Kristo } 10569d97140bSTero Kristo 10579d97140bSTero Kristo omap3_save_scratchpad_contents(); 10588bd22949SKevin Hilman err1: 10598bd22949SKevin Hilman return ret; 10608bd22949SKevin Hilman err2: 10618bd22949SKevin Hilman free_irq(INT_34XX_PRCM_MPU_IRQ, NULL); 10628bd22949SKevin Hilman list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { 10638bd22949SKevin Hilman list_del(&pwrst->node); 10648bd22949SKevin Hilman kfree(pwrst); 10658bd22949SKevin Hilman } 10668bd22949SKevin Hilman return ret; 10678bd22949SKevin Hilman } 10688bd22949SKevin Hilman 10698bd22949SKevin Hilman late_initcall(omap3_pm_init); 1070