18bd22949SKevin Hilman /* 28bd22949SKevin Hilman * OMAP3 Power Management Routines 38bd22949SKevin Hilman * 48bd22949SKevin Hilman * Copyright (C) 2006-2008 Nokia Corporation 58bd22949SKevin Hilman * Tony Lindgren <tony@atomide.com> 68bd22949SKevin Hilman * Jouni Hogander 78bd22949SKevin Hilman * 82f5939c3SRajendra Nayak * Copyright (C) 2007 Texas Instruments, Inc. 92f5939c3SRajendra Nayak * Rajendra Nayak <rnayak@ti.com> 102f5939c3SRajendra Nayak * 118bd22949SKevin Hilman * Copyright (C) 2005 Texas Instruments, Inc. 128bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 138bd22949SKevin Hilman * 148bd22949SKevin Hilman * Based on pm.c for omap1 158bd22949SKevin Hilman * 168bd22949SKevin Hilman * This program is free software; you can redistribute it and/or modify 178bd22949SKevin Hilman * it under the terms of the GNU General Public License version 2 as 188bd22949SKevin Hilman * published by the Free Software Foundation. 198bd22949SKevin Hilman */ 208bd22949SKevin Hilman 218bd22949SKevin Hilman #include <linux/pm.h> 228bd22949SKevin Hilman #include <linux/suspend.h> 238bd22949SKevin Hilman #include <linux/interrupt.h> 248bd22949SKevin Hilman #include <linux/module.h> 258bd22949SKevin Hilman #include <linux/list.h> 268bd22949SKevin Hilman #include <linux/err.h> 278bd22949SKevin Hilman #include <linux/gpio.h> 28c40552bcSKevin Hilman #include <linux/clk.h> 29dccaad89STero Kristo #include <linux/delay.h> 305a0e3ad6STejun Heo #include <linux/slab.h> 310d8e2d0dSPaul Walmsley #include <linux/console.h> 325e7c58dcSJean Pihet #include <trace/events/power.h> 338bd22949SKevin Hilman 342c74a0ceSRussell King #include <asm/suspend.h> 352c74a0ceSRussell King 36ce491cf8STony Lindgren #include <plat/sram.h> 371540f214SPaul Walmsley #include "clockdomain.h" 3872e06d08SPaul Walmsley #include "powerdomain.h" 39ce491cf8STony Lindgren #include <plat/serial.h> 4061255ab9SRajendra Nayak #include <plat/sdrc.h> 412f5939c3SRajendra Nayak #include <plat/prcm.h> 422f5939c3SRajendra Nayak #include <plat/gpmc.h> 43f2d11858STero Kristo #include <plat/dma.h> 448bd22949SKevin Hilman 4559fb659bSPaul Walmsley #include "cm2xxx_3xxx.h" 468bd22949SKevin Hilman #include "cm-regbits-34xx.h" 478bd22949SKevin Hilman #include "prm-regbits-34xx.h" 488bd22949SKevin Hilman 4959fb659bSPaul Walmsley #include "prm2xxx_3xxx.h" 508bd22949SKevin Hilman #include "pm.h" 5113a6fe0fSTero Kristo #include "sdrc.h" 524814ced5SPaul Walmsley #include "control.h" 5313a6fe0fSTero Kristo 54e83df17fSKevin Hilman #ifdef CONFIG_SUSPEND 55e83df17fSKevin Hilman static suspend_state_t suspend_state = PM_SUSPEND_ON; 56e83df17fSKevin Hilman static inline bool is_suspending(void) 57e83df17fSKevin Hilman { 58e83df17fSKevin Hilman return (suspend_state != PM_SUSPEND_ON); 59e83df17fSKevin Hilman } 60e83df17fSKevin Hilman #else 61e83df17fSKevin Hilman static inline bool is_suspending(void) 62e83df17fSKevin Hilman { 63e83df17fSKevin Hilman return false; 64e83df17fSKevin Hilman } 65e83df17fSKevin Hilman #endif 66e83df17fSKevin Hilman 678cdfd834SNishanth Menon /* pm34xx errata defined in pm.h */ 688cdfd834SNishanth Menon u16 pm34xx_errata; 698cdfd834SNishanth Menon 708bd22949SKevin Hilman struct power_state { 718bd22949SKevin Hilman struct powerdomain *pwrdm; 728bd22949SKevin Hilman u32 next_state; 7310f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 748bd22949SKevin Hilman u32 saved_state; 7510f90ed2SKevin Hilman #endif 768bd22949SKevin Hilman struct list_head node; 778bd22949SKevin Hilman }; 788bd22949SKevin Hilman 798bd22949SKevin Hilman static LIST_HEAD(pwrst_list); 808bd22949SKevin Hilman 818bd22949SKevin Hilman static void (*_omap_sram_idle)(u32 *addr, int save_state); 828bd22949SKevin Hilman 8327d59a4aSTero Kristo static int (*_omap_save_secure_sram)(u32 *addr); 8427d59a4aSTero Kristo 85fa3c2a4fSRajendra Nayak static struct powerdomain *mpu_pwrdm, *neon_pwrdm; 86fa3c2a4fSRajendra Nayak static struct powerdomain *core_pwrdm, *per_pwrdm; 87c16c3f67STero Kristo static struct powerdomain *cam_pwrdm; 88fa3c2a4fSRajendra Nayak 892f5939c3SRajendra Nayak static inline void omap3_per_save_context(void) 902f5939c3SRajendra Nayak { 912f5939c3SRajendra Nayak omap_gpio_save_context(); 922f5939c3SRajendra Nayak } 932f5939c3SRajendra Nayak 942f5939c3SRajendra Nayak static inline void omap3_per_restore_context(void) 952f5939c3SRajendra Nayak { 962f5939c3SRajendra Nayak omap_gpio_restore_context(); 972f5939c3SRajendra Nayak } 982f5939c3SRajendra Nayak 993a7ec26bSKalle Jokiniemi static void omap3_enable_io_chain(void) 1003a7ec26bSKalle Jokiniemi { 1013a7ec26bSKalle Jokiniemi int timeout = 0; 1023a7ec26bSKalle Jokiniemi 1033a7ec26bSKalle Jokiniemi if (omap_rev() >= OMAP3430_REV_ES3_1) { 104c4d7e58fSPaul Walmsley omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, 1052bc4ef71SPaul Walmsley PM_WKEN); 1063a7ec26bSKalle Jokiniemi /* Do a readback to assure write has been done */ 107c4d7e58fSPaul Walmsley omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN); 1083a7ec26bSKalle Jokiniemi 109c4d7e58fSPaul Walmsley while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) & 1102bc4ef71SPaul Walmsley OMAP3430_ST_IO_CHAIN_MASK)) { 1113a7ec26bSKalle Jokiniemi timeout++; 1123a7ec26bSKalle Jokiniemi if (timeout > 1000) { 1133a7ec26bSKalle Jokiniemi printk(KERN_ERR "Wake up daisy chain " 1143a7ec26bSKalle Jokiniemi "activation failed.\n"); 1153a7ec26bSKalle Jokiniemi return; 1163a7ec26bSKalle Jokiniemi } 117c4d7e58fSPaul Walmsley omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, 1180b96a3a3SKevin Hilman WKUP_MOD, PM_WKEN); 1193a7ec26bSKalle Jokiniemi } 1203a7ec26bSKalle Jokiniemi } 1213a7ec26bSKalle Jokiniemi } 1223a7ec26bSKalle Jokiniemi 1233a7ec26bSKalle Jokiniemi static void omap3_disable_io_chain(void) 1243a7ec26bSKalle Jokiniemi { 1253a7ec26bSKalle Jokiniemi if (omap_rev() >= OMAP3430_REV_ES3_1) 126c4d7e58fSPaul Walmsley omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, 1272bc4ef71SPaul Walmsley PM_WKEN); 1283a7ec26bSKalle Jokiniemi } 1293a7ec26bSKalle Jokiniemi 1302f5939c3SRajendra Nayak static void omap3_core_save_context(void) 1312f5939c3SRajendra Nayak { 132596efe47SPaul Walmsley omap3_ctrl_save_padconf(); 133dccaad89STero Kristo 134dccaad89STero Kristo /* 135dccaad89STero Kristo * Force write last pad into memory, as this can fail in some 13683521291SJean Pihet * cases according to errata 1.157, 1.185 137dccaad89STero Kristo */ 138dccaad89STero Kristo omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), 139dccaad89STero Kristo OMAP343X_CONTROL_MEM_WKUP + 0x2a0); 140dccaad89STero Kristo 1412f5939c3SRajendra Nayak /* Save the Interrupt controller context */ 1422f5939c3SRajendra Nayak omap_intc_save_context(); 1432f5939c3SRajendra Nayak /* Save the GPMC context */ 1442f5939c3SRajendra Nayak omap3_gpmc_save_context(); 1452f5939c3SRajendra Nayak /* Save the system control module context, padconf already save above*/ 1462f5939c3SRajendra Nayak omap3_control_save_context(); 147f2d11858STero Kristo omap_dma_global_context_save(); 1482f5939c3SRajendra Nayak } 1492f5939c3SRajendra Nayak 1502f5939c3SRajendra Nayak static void omap3_core_restore_context(void) 1512f5939c3SRajendra Nayak { 1522f5939c3SRajendra Nayak /* Restore the control module context, padconf restored by h/w */ 1532f5939c3SRajendra Nayak omap3_control_restore_context(); 1542f5939c3SRajendra Nayak /* Restore the GPMC context */ 1552f5939c3SRajendra Nayak omap3_gpmc_restore_context(); 1562f5939c3SRajendra Nayak /* Restore the interrupt controller context */ 1572f5939c3SRajendra Nayak omap_intc_restore_context(); 158f2d11858STero Kristo omap_dma_global_context_restore(); 1592f5939c3SRajendra Nayak } 1602f5939c3SRajendra Nayak 1619d97140bSTero Kristo /* 1629d97140bSTero Kristo * FIXME: This function should be called before entering off-mode after 1639d97140bSTero Kristo * OMAP3 secure services have been accessed. Currently it is only called 1649d97140bSTero Kristo * once during boot sequence, but this works as we are not using secure 1659d97140bSTero Kristo * services. 1669d97140bSTero Kristo */ 167617fcc98SKevin Hilman static void omap3_save_secure_ram_context(void) 16827d59a4aSTero Kristo { 16927d59a4aSTero Kristo u32 ret; 170617fcc98SKevin Hilman int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 17127d59a4aSTero Kristo 17227d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 17327d59a4aSTero Kristo /* 17427d59a4aSTero Kristo * MPU next state must be set to POWER_ON temporarily, 17527d59a4aSTero Kristo * otherwise the WFI executed inside the ROM code 17627d59a4aSTero Kristo * will hang the system. 17727d59a4aSTero Kristo */ 17827d59a4aSTero Kristo pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); 17927d59a4aSTero Kristo ret = _omap_save_secure_sram((u32 *) 18027d59a4aSTero Kristo __pa(omap3_secure_ram_storage)); 181617fcc98SKevin Hilman pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state); 18227d59a4aSTero Kristo /* Following is for error tracking, it should not happen */ 18327d59a4aSTero Kristo if (ret) { 18427d59a4aSTero Kristo printk(KERN_ERR "save_secure_sram() returns %08x\n", 18527d59a4aSTero Kristo ret); 18627d59a4aSTero Kristo while (1) 18727d59a4aSTero Kristo ; 18827d59a4aSTero Kristo } 18927d59a4aSTero Kristo } 19027d59a4aSTero Kristo } 19127d59a4aSTero Kristo 19277da2d91SJon Hunter /* 19377da2d91SJon Hunter * PRCM Interrupt Handler Helper Function 19477da2d91SJon Hunter * 19577da2d91SJon Hunter * The purpose of this function is to clear any wake-up events latched 19677da2d91SJon Hunter * in the PRCM PM_WKST_x registers. It is possible that a wake-up event 19777da2d91SJon Hunter * may occur whilst attempting to clear a PM_WKST_x register and thus 19877da2d91SJon Hunter * set another bit in this register. A while loop is used to ensure 19977da2d91SJon Hunter * that any peripheral wake-up events occurring while attempting to 20077da2d91SJon Hunter * clear the PM_WKST_x are detected and cleared. 20177da2d91SJon Hunter */ 2028cb0ac99SPaul Walmsley static int prcm_clear_mod_irqs(s16 module, u8 regs) 20377da2d91SJon Hunter { 20471a80775SVikram Pandita u32 wkst, fclk, iclk, clken; 20577da2d91SJon Hunter u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; 20677da2d91SJon Hunter u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; 20777da2d91SJon Hunter u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; 2085d805978SPaul Walmsley u16 grpsel_off = (regs == 3) ? 2095d805978SPaul Walmsley OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; 2108cb0ac99SPaul Walmsley int c = 0; 21177da2d91SJon Hunter 212c4d7e58fSPaul Walmsley wkst = omap2_prm_read_mod_reg(module, wkst_off); 213c4d7e58fSPaul Walmsley wkst &= omap2_prm_read_mod_reg(module, grpsel_off); 21477da2d91SJon Hunter if (wkst) { 215c4d7e58fSPaul Walmsley iclk = omap2_cm_read_mod_reg(module, iclk_off); 216c4d7e58fSPaul Walmsley fclk = omap2_cm_read_mod_reg(module, fclk_off); 21777da2d91SJon Hunter while (wkst) { 21871a80775SVikram Pandita clken = wkst; 219c4d7e58fSPaul Walmsley omap2_cm_set_mod_reg_bits(clken, module, iclk_off); 22071a80775SVikram Pandita /* 22171a80775SVikram Pandita * For USBHOST, we don't know whether HOST1 or 22271a80775SVikram Pandita * HOST2 woke us up, so enable both f-clocks 22371a80775SVikram Pandita */ 22471a80775SVikram Pandita if (module == OMAP3430ES2_USBHOST_MOD) 22571a80775SVikram Pandita clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; 226c4d7e58fSPaul Walmsley omap2_cm_set_mod_reg_bits(clken, module, fclk_off); 227c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(wkst, module, wkst_off); 228c4d7e58fSPaul Walmsley wkst = omap2_prm_read_mod_reg(module, wkst_off); 2298cb0ac99SPaul Walmsley c++; 23077da2d91SJon Hunter } 231c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(iclk, module, iclk_off); 232c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(fclk, module, fclk_off); 23377da2d91SJon Hunter } 2348cb0ac99SPaul Walmsley 2358cb0ac99SPaul Walmsley return c; 2368cb0ac99SPaul Walmsley } 2378cb0ac99SPaul Walmsley 2388cb0ac99SPaul Walmsley static int _prcm_int_handle_wakeup(void) 2398cb0ac99SPaul Walmsley { 2408cb0ac99SPaul Walmsley int c; 2418cb0ac99SPaul Walmsley 2428cb0ac99SPaul Walmsley c = prcm_clear_mod_irqs(WKUP_MOD, 1); 2438cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(CORE_MOD, 1); 2448cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1); 2458cb0ac99SPaul Walmsley if (omap_rev() > OMAP3430_REV_ES1_0) { 2468cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(CORE_MOD, 3); 2478cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1); 2488cb0ac99SPaul Walmsley } 2498cb0ac99SPaul Walmsley 2508cb0ac99SPaul Walmsley return c; 25177da2d91SJon Hunter } 25277da2d91SJon Hunter 25377da2d91SJon Hunter /* 25477da2d91SJon Hunter * PRCM Interrupt Handler 25577da2d91SJon Hunter * 25677da2d91SJon Hunter * The PRM_IRQSTATUS_MPU register indicates if there are any pending 25777da2d91SJon Hunter * interrupts from the PRCM for the MPU. These bits must be cleared in 25877da2d91SJon Hunter * order to clear the PRCM interrupt. The PRCM interrupt handler is 25977da2d91SJon Hunter * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear 26077da2d91SJon Hunter * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU 26177da2d91SJon Hunter * register indicates that a wake-up event is pending for the MPU and 26277da2d91SJon Hunter * this bit can only be cleared if the all the wake-up events latched 26377da2d91SJon Hunter * in the various PM_WKST_x registers have been cleared. The interrupt 26477da2d91SJon Hunter * handler is implemented using a do-while loop so that if a wake-up 26577da2d91SJon Hunter * event occurred during the processing of the prcm interrupt handler 26677da2d91SJon Hunter * (setting a bit in the corresponding PM_WKST_x register and thus 26777da2d91SJon Hunter * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register) 26877da2d91SJon Hunter * this would be handled. 26977da2d91SJon Hunter */ 2708bd22949SKevin Hilman static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) 2718bd22949SKevin Hilman { 272d6290a3eSKevin Hilman u32 irqenable_mpu, irqstatus_mpu; 2738cb0ac99SPaul Walmsley int c = 0; 2748bd22949SKevin Hilman 275c4d7e58fSPaul Walmsley irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD, 276d6290a3eSKevin Hilman OMAP3_PRM_IRQENABLE_MPU_OFFSET); 277c4d7e58fSPaul Walmsley irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD, 2788bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 279d6290a3eSKevin Hilman irqstatus_mpu &= irqenable_mpu; 2808cb0ac99SPaul Walmsley 281d6290a3eSKevin Hilman do { 2822bc4ef71SPaul Walmsley if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK | 2832bc4ef71SPaul Walmsley OMAP3430_IO_ST_MASK)) { 2848cb0ac99SPaul Walmsley c = _prcm_int_handle_wakeup(); 2858cb0ac99SPaul Walmsley 2868cb0ac99SPaul Walmsley /* 2878cb0ac99SPaul Walmsley * Is the MPU PRCM interrupt handler racing with the 2888cb0ac99SPaul Walmsley * IVA2 PRCM interrupt handler ? 2898cb0ac99SPaul Walmsley */ 2908cb0ac99SPaul Walmsley WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup " 2918cb0ac99SPaul Walmsley "but no wakeup sources are marked\n"); 2928cb0ac99SPaul Walmsley } else { 2938cb0ac99SPaul Walmsley /* XXX we need to expand our PRCM interrupt handler */ 2948cb0ac99SPaul Walmsley WARN(1, "prcm: WARNING: PRCM interrupt received, but " 2958cb0ac99SPaul Walmsley "no code to handle it (%08x)\n", irqstatus_mpu); 2968cb0ac99SPaul Walmsley } 2978cb0ac99SPaul Walmsley 298c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD, 2998bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 3008bd22949SKevin Hilman 301c4d7e58fSPaul Walmsley irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD, 302d6290a3eSKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 303d6290a3eSKevin Hilman irqstatus_mpu &= irqenable_mpu; 304d6290a3eSKevin Hilman 305d6290a3eSKevin Hilman } while (irqstatus_mpu); 3068bd22949SKevin Hilman 3078bd22949SKevin Hilman return IRQ_HANDLED; 3088bd22949SKevin Hilman } 3098bd22949SKevin Hilman 310076f2cc4SRussell King static void omap34xx_do_sram_idle(unsigned long save_state) 31157f277b0SRajendra Nayak { 312076f2cc4SRussell King _omap_sram_idle(omap3_arm_context, save_state); 31357f277b0SRajendra Nayak } 31457f277b0SRajendra Nayak 31599e6a4d2SRajendra Nayak void omap_sram_idle(void) 3168bd22949SKevin Hilman { 3178bd22949SKevin Hilman /* Variable to tell what needs to be saved and restored 3188bd22949SKevin Hilman * in omap_sram_idle*/ 3198bd22949SKevin Hilman /* save_state = 0 => Nothing to save and restored */ 3208bd22949SKevin Hilman /* save_state = 1 => Only L1 and logic lost */ 3218bd22949SKevin Hilman /* save_state = 2 => Only L2 lost */ 3228bd22949SKevin Hilman /* save_state = 3 => L1, L2 and logic lost */ 323fa3c2a4fSRajendra Nayak int save_state = 0; 324fa3c2a4fSRajendra Nayak int mpu_next_state = PWRDM_POWER_ON; 325fa3c2a4fSRajendra Nayak int per_next_state = PWRDM_POWER_ON; 326fa3c2a4fSRajendra Nayak int core_next_state = PWRDM_POWER_ON; 32772e06d08SPaul Walmsley int per_going_off; 3282f5939c3SRajendra Nayak int core_prev_state, per_prev_state; 32913a6fe0fSTero Kristo u32 sdrc_pwr = 0; 3308bd22949SKevin Hilman 3318bd22949SKevin Hilman if (!_omap_sram_idle) 3328bd22949SKevin Hilman return; 3338bd22949SKevin Hilman 334fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(mpu_pwrdm); 335fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(neon_pwrdm); 336fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(core_pwrdm); 337fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(per_pwrdm); 338fa3c2a4fSRajendra Nayak 3398bd22949SKevin Hilman mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 3408bd22949SKevin Hilman switch (mpu_next_state) { 341fa3c2a4fSRajendra Nayak case PWRDM_POWER_ON: 3428bd22949SKevin Hilman case PWRDM_POWER_RET: 3438bd22949SKevin Hilman /* No need to save context */ 3448bd22949SKevin Hilman save_state = 0; 3458bd22949SKevin Hilman break; 34661255ab9SRajendra Nayak case PWRDM_POWER_OFF: 34761255ab9SRajendra Nayak save_state = 3; 34861255ab9SRajendra Nayak break; 3498bd22949SKevin Hilman default: 3508bd22949SKevin Hilman /* Invalid state */ 3518bd22949SKevin Hilman printk(KERN_ERR "Invalid mpu state in sram_idle\n"); 3528bd22949SKevin Hilman return; 3538bd22949SKevin Hilman } 354fe617af7SPeter 'p2' De Schrijver pwrdm_pre_transition(); 355fe617af7SPeter 'p2' De Schrijver 356fa3c2a4fSRajendra Nayak /* NEON control */ 357fa3c2a4fSRajendra Nayak if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) 3587139178eSJouni Hogander pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); 359fa3c2a4fSRajendra Nayak 36040742fa8SMike Chan /* Enable IO-PAD and IO-CHAIN wakeups */ 361fa3c2a4fSRajendra Nayak per_next_state = pwrdm_read_next_pwrst(per_pwrdm); 362ecf157d0STero Kristo core_next_state = pwrdm_read_next_pwrst(core_pwrdm); 363d5c47d7eSKevin Hilman if (omap3_has_io_wakeup() && 364ad0c63f1Sstanley.miao (per_next_state < PWRDM_POWER_ON || 365ad0c63f1Sstanley.miao core_next_state < PWRDM_POWER_ON)) { 366c4d7e58fSPaul Walmsley omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); 36740742fa8SMike Chan omap3_enable_io_chain(); 36840742fa8SMike Chan } 36940742fa8SMike Chan 3700d8e2d0dSPaul Walmsley /* Block console output in case it is on one of the OMAP UARTs */ 371e83df17fSKevin Hilman if (!is_suspending()) 3720d8e2d0dSPaul Walmsley if (per_next_state < PWRDM_POWER_ON || 3730d8e2d0dSPaul Walmsley core_next_state < PWRDM_POWER_ON) 374ac751efaSTorben Hohn if (!console_trylock()) 3750d8e2d0dSPaul Walmsley goto console_still_active; 3760d8e2d0dSPaul Walmsley 37740742fa8SMike Chan /* PER */ 3782f5939c3SRajendra Nayak if (per_next_state < PWRDM_POWER_ON) { 37972e06d08SPaul Walmsley per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0; 3804af4016cSKevin Hilman omap_uart_prepare_idle(2); 381cd4f1faeSGovindraj.R omap_uart_prepare_idle(3); 38272e06d08SPaul Walmsley omap2_gpio_prepare_for_idle(per_going_off); 383e7410cf7SKevin Hilman if (per_next_state == PWRDM_POWER_OFF) 3842f5939c3SRajendra Nayak omap3_per_save_context(); 3852f5939c3SRajendra Nayak } 386c16c3f67STero Kristo 387658ce97eSKevin Hilman /* CORE */ 388658ce97eSKevin Hilman if (core_next_state < PWRDM_POWER_ON) { 389658ce97eSKevin Hilman omap_uart_prepare_idle(0); 390658ce97eSKevin Hilman omap_uart_prepare_idle(1); 3912f5939c3SRajendra Nayak if (core_next_state == PWRDM_POWER_OFF) { 3922f5939c3SRajendra Nayak omap3_core_save_context(); 393f0611a5cSPaul Walmsley omap3_cm_save_context(); 3942f5939c3SRajendra Nayak } 395fa3c2a4fSRajendra Nayak } 39640742fa8SMike Chan 397f18cc2ffSTero Kristo omap3_intc_prepare_idle(); 3988bd22949SKevin Hilman 39961255ab9SRajendra Nayak /* 400f265dc4cSRajendra Nayak * On EMU/HS devices ROM code restores a SRDC value 401f265dc4cSRajendra Nayak * from scratchpad which has automatic self refresh on timeout 40283521291SJean Pihet * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443. 403f265dc4cSRajendra Nayak * Hence store/restore the SDRC_POWER register here. 40413a6fe0fSTero Kristo */ 40513a6fe0fSTero Kristo if (omap_rev() >= OMAP3430_REV_ES3_0 && 40613a6fe0fSTero Kristo omap_type() != OMAP2_DEVICE_TYPE_GP && 407f265dc4cSRajendra Nayak core_next_state == PWRDM_POWER_OFF) 40813a6fe0fSTero Kristo sdrc_pwr = sdrc_read_reg(SDRC_POWER); 40913a6fe0fSTero Kristo 41013a6fe0fSTero Kristo /* 411076f2cc4SRussell King * omap3_arm_context is the location where some ARM context 412076f2cc4SRussell King * get saved. The rest is placed on the stack, and restored 413076f2cc4SRussell King * from there before resuming. 41461255ab9SRajendra Nayak */ 415076f2cc4SRussell King if (save_state == 1 || save_state == 3) 4162c74a0ceSRussell King cpu_suspend(save_state, omap34xx_do_sram_idle); 417076f2cc4SRussell King else 418076f2cc4SRussell King omap34xx_do_sram_idle(save_state); 4198bd22949SKevin Hilman 420f265dc4cSRajendra Nayak /* Restore normal SDRC POWER settings */ 42113a6fe0fSTero Kristo if (omap_rev() >= OMAP3430_REV_ES3_0 && 42213a6fe0fSTero Kristo omap_type() != OMAP2_DEVICE_TYPE_GP && 42313a6fe0fSTero Kristo core_next_state == PWRDM_POWER_OFF) 42413a6fe0fSTero Kristo sdrc_write_reg(sdrc_pwr, SDRC_POWER); 42513a6fe0fSTero Kristo 426658ce97eSKevin Hilman /* CORE */ 427fa3c2a4fSRajendra Nayak if (core_next_state < PWRDM_POWER_ON) { 4282f5939c3SRajendra Nayak core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); 4292f5939c3SRajendra Nayak if (core_prev_state == PWRDM_POWER_OFF) { 4302f5939c3SRajendra Nayak omap3_core_restore_context(); 431f0611a5cSPaul Walmsley omap3_cm_restore_context(); 4322f5939c3SRajendra Nayak omap3_sram_restore_context(); 4338a917d2fSKalle Jokiniemi omap2_sms_restore_context(); 4342f5939c3SRajendra Nayak } 435658ce97eSKevin Hilman omap_uart_resume_idle(0); 436658ce97eSKevin Hilman omap_uart_resume_idle(1); 437658ce97eSKevin Hilman if (core_next_state == PWRDM_POWER_OFF) 438c4d7e58fSPaul Walmsley omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, 439658ce97eSKevin Hilman OMAP3430_GR_MOD, 440658ce97eSKevin Hilman OMAP3_PRM_VOLTCTRL_OFFSET); 441658ce97eSKevin Hilman } 442f18cc2ffSTero Kristo omap3_intc_resume_idle(); 443658ce97eSKevin Hilman 444658ce97eSKevin Hilman /* PER */ 4452f5939c3SRajendra Nayak if (per_next_state < PWRDM_POWER_ON) { 446658ce97eSKevin Hilman per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); 44743ffcd9aSKevin Hilman omap2_gpio_resume_after_idle(); 44843ffcd9aSKevin Hilman if (per_prev_state == PWRDM_POWER_OFF) 4492f5939c3SRajendra Nayak omap3_per_restore_context(); 450ecf157d0STero Kristo omap_uart_resume_idle(2); 451cd4f1faeSGovindraj.R omap_uart_resume_idle(3); 452fa3c2a4fSRajendra Nayak } 453fe617af7SPeter 'p2' De Schrijver 454e83df17fSKevin Hilman if (!is_suspending()) 455ac751efaSTorben Hohn console_unlock(); 4560d8e2d0dSPaul Walmsley 4570d8e2d0dSPaul Walmsley console_still_active: 4583a7ec26bSKalle Jokiniemi /* Disable IO-PAD and IO-CHAIN wakeup */ 45958a5559eSKevin Hilman if (omap3_has_io_wakeup() && 46058a5559eSKevin Hilman (per_next_state < PWRDM_POWER_ON || 46158a5559eSKevin Hilman core_next_state < PWRDM_POWER_ON)) { 462c4d7e58fSPaul Walmsley omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, 463c4d7e58fSPaul Walmsley PM_WKEN); 4643a7ec26bSKalle Jokiniemi omap3_disable_io_chain(); 4653a7ec26bSKalle Jokiniemi } 466658ce97eSKevin Hilman 467fe617af7SPeter 'p2' De Schrijver pwrdm_post_transition(); 468fe617af7SPeter 'p2' De Schrijver 4695cd1937bSRajendra Nayak clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); 4708bd22949SKevin Hilman } 4718bd22949SKevin Hilman 47220b01669SRajendra Nayak int omap3_can_sleep(void) 4738bd22949SKevin Hilman { 474c40552bcSKevin Hilman if (!sleep_while_idle) 475c40552bcSKevin Hilman return 0; 4764af4016cSKevin Hilman if (!omap_uart_can_sleep()) 4774af4016cSKevin Hilman return 0; 4788bd22949SKevin Hilman return 1; 4798bd22949SKevin Hilman } 4808bd22949SKevin Hilman 4818bd22949SKevin Hilman static void omap3_pm_idle(void) 4828bd22949SKevin Hilman { 4838bd22949SKevin Hilman local_irq_disable(); 4848bd22949SKevin Hilman local_fiq_disable(); 4858bd22949SKevin Hilman 4868bd22949SKevin Hilman if (!omap3_can_sleep()) 4878bd22949SKevin Hilman goto out; 4888bd22949SKevin Hilman 489cf22854cSTero Kristo if (omap_irq_pending() || need_resched()) 4908bd22949SKevin Hilman goto out; 4918bd22949SKevin Hilman 4925e7c58dcSJean Pihet trace_power_start(POWER_CSTATE, 1, smp_processor_id()); 4935e7c58dcSJean Pihet trace_cpu_idle(1, smp_processor_id()); 4945e7c58dcSJean Pihet 4958bd22949SKevin Hilman omap_sram_idle(); 4968bd22949SKevin Hilman 4975e7c58dcSJean Pihet trace_power_end(smp_processor_id()); 4985e7c58dcSJean Pihet trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); 4995e7c58dcSJean Pihet 5008bd22949SKevin Hilman out: 5018bd22949SKevin Hilman local_fiq_enable(); 5028bd22949SKevin Hilman local_irq_enable(); 5038bd22949SKevin Hilman } 5048bd22949SKevin Hilman 50510f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 5068bd22949SKevin Hilman static int omap3_pm_suspend(void) 5078bd22949SKevin Hilman { 5088bd22949SKevin Hilman struct power_state *pwrst; 5098bd22949SKevin Hilman int state, ret = 0; 5108bd22949SKevin Hilman 5118e2efde9SAri Kauppi if (wakeup_timer_seconds || wakeup_timer_milliseconds) 5128e2efde9SAri Kauppi omap2_pm_wakeup_on_timer(wakeup_timer_seconds, 5138e2efde9SAri Kauppi wakeup_timer_milliseconds); 514d7814e4dSKevin Hilman 5158bd22949SKevin Hilman /* Read current next_pwrsts */ 5168bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) 5178bd22949SKevin Hilman pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 5188bd22949SKevin Hilman /* Set ones wanted by suspend */ 5198bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 520eb6a2c75SSantosh Shilimkar if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) 5218bd22949SKevin Hilman goto restore; 5228bd22949SKevin Hilman if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) 5238bd22949SKevin Hilman goto restore; 5248bd22949SKevin Hilman } 5258bd22949SKevin Hilman 5264af4016cSKevin Hilman omap_uart_prepare_suspend(); 5272bbe3af3STero Kristo omap3_intc_suspend(); 5282bbe3af3STero Kristo 5298bd22949SKevin Hilman omap_sram_idle(); 5308bd22949SKevin Hilman 5318bd22949SKevin Hilman restore: 5328bd22949SKevin Hilman /* Restore next_pwrsts */ 5338bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 5348bd22949SKevin Hilman state = pwrdm_read_prev_pwrst(pwrst->pwrdm); 5358bd22949SKevin Hilman if (state > pwrst->next_state) { 5368bd22949SKevin Hilman printk(KERN_INFO "Powerdomain (%s) didn't enter " 5378bd22949SKevin Hilman "target state %d\n", 5388bd22949SKevin Hilman pwrst->pwrdm->name, pwrst->next_state); 5398bd22949SKevin Hilman ret = -1; 5408bd22949SKevin Hilman } 541eb6a2c75SSantosh Shilimkar omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); 5428bd22949SKevin Hilman } 5438bd22949SKevin Hilman if (ret) 5448bd22949SKevin Hilman printk(KERN_ERR "Could not enter target state in pm_suspend\n"); 5458bd22949SKevin Hilman else 5468bd22949SKevin Hilman printk(KERN_INFO "Successfully put all powerdomains " 5478bd22949SKevin Hilman "to target state\n"); 5488bd22949SKevin Hilman 5498bd22949SKevin Hilman return ret; 5508bd22949SKevin Hilman } 5518bd22949SKevin Hilman 5522466211eSTero Kristo static int omap3_pm_enter(suspend_state_t unused) 5538bd22949SKevin Hilman { 5548bd22949SKevin Hilman int ret = 0; 5558bd22949SKevin Hilman 5562466211eSTero Kristo switch (suspend_state) { 5578bd22949SKevin Hilman case PM_SUSPEND_STANDBY: 5588bd22949SKevin Hilman case PM_SUSPEND_MEM: 5598bd22949SKevin Hilman ret = omap3_pm_suspend(); 5608bd22949SKevin Hilman break; 5618bd22949SKevin Hilman default: 5628bd22949SKevin Hilman ret = -EINVAL; 5638bd22949SKevin Hilman } 5648bd22949SKevin Hilman 5658bd22949SKevin Hilman return ret; 5668bd22949SKevin Hilman } 5678bd22949SKevin Hilman 5682466211eSTero Kristo /* Hooks to enable / disable UART interrupts during suspend */ 5692466211eSTero Kristo static int omap3_pm_begin(suspend_state_t state) 5702466211eSTero Kristo { 571c166381dSJean Pihet disable_hlt(); 5722466211eSTero Kristo suspend_state = state; 5732466211eSTero Kristo omap_uart_enable_irqs(0); 5742466211eSTero Kristo return 0; 5752466211eSTero Kristo } 5762466211eSTero Kristo 5772466211eSTero Kristo static void omap3_pm_end(void) 5782466211eSTero Kristo { 5792466211eSTero Kristo suspend_state = PM_SUSPEND_ON; 5802466211eSTero Kristo omap_uart_enable_irqs(1); 581c166381dSJean Pihet enable_hlt(); 5822466211eSTero Kristo return; 5832466211eSTero Kristo } 5842466211eSTero Kristo 5852f55ac07SLionel Debroux static const struct platform_suspend_ops omap_pm_ops = { 5862466211eSTero Kristo .begin = omap3_pm_begin, 5872466211eSTero Kristo .end = omap3_pm_end, 5888bd22949SKevin Hilman .enter = omap3_pm_enter, 5898bd22949SKevin Hilman .valid = suspend_valid_only_mem, 5908bd22949SKevin Hilman }; 59110f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 5928bd22949SKevin Hilman 5931155e426SKevin Hilman 5941155e426SKevin Hilman /** 5951155e426SKevin Hilman * omap3_iva_idle(): ensure IVA is in idle so it can be put into 5961155e426SKevin Hilman * retention 5971155e426SKevin Hilman * 5981155e426SKevin Hilman * In cases where IVA2 is activated by bootcode, it may prevent 5991155e426SKevin Hilman * full-chip retention or off-mode because it is not idle. This 6001155e426SKevin Hilman * function forces the IVA2 into idle state so it can go 6011155e426SKevin Hilman * into retention/off and thus allow full-chip retention/off. 6021155e426SKevin Hilman * 6031155e426SKevin Hilman **/ 6041155e426SKevin Hilman static void __init omap3_iva_idle(void) 6051155e426SKevin Hilman { 6061155e426SKevin Hilman /* ensure IVA2 clock is disabled */ 607c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 6081155e426SKevin Hilman 6091155e426SKevin Hilman /* if no clock activity, nothing else to do */ 610c4d7e58fSPaul Walmsley if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & 6111155e426SKevin Hilman OMAP3430_CLKACTIVITY_IVA2_MASK)) 6121155e426SKevin Hilman return; 6131155e426SKevin Hilman 6141155e426SKevin Hilman /* Reset IVA2 */ 615c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | 6162bc4ef71SPaul Walmsley OMAP3430_RST2_IVA2_MASK | 6172bc4ef71SPaul Walmsley OMAP3430_RST3_IVA2_MASK, 61837903009SAbhijit Pagare OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 6191155e426SKevin Hilman 6201155e426SKevin Hilman /* Enable IVA2 clock */ 621c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, 6221155e426SKevin Hilman OMAP3430_IVA2_MOD, CM_FCLKEN); 6231155e426SKevin Hilman 6241155e426SKevin Hilman /* Set IVA2 boot mode to 'idle' */ 6251155e426SKevin Hilman omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, 6261155e426SKevin Hilman OMAP343X_CONTROL_IVA2_BOOTMOD); 6271155e426SKevin Hilman 6281155e426SKevin Hilman /* Un-reset IVA2 */ 629c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 6301155e426SKevin Hilman 6311155e426SKevin Hilman /* Disable IVA2 clock */ 632c4d7e58fSPaul Walmsley omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 6331155e426SKevin Hilman 6341155e426SKevin Hilman /* Reset IVA2 */ 635c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | 6362bc4ef71SPaul Walmsley OMAP3430_RST2_IVA2_MASK | 6372bc4ef71SPaul Walmsley OMAP3430_RST3_IVA2_MASK, 63837903009SAbhijit Pagare OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 6391155e426SKevin Hilman } 6401155e426SKevin Hilman 6418111b221SKevin Hilman static void __init omap3_d2d_idle(void) 6428bd22949SKevin Hilman { 6438111b221SKevin Hilman u16 mask, padconf; 6448111b221SKevin Hilman 6458111b221SKevin Hilman /* In a stand alone OMAP3430 where there is not a stacked 6468111b221SKevin Hilman * modem for the D2D Idle Ack and D2D MStandby must be pulled 6478111b221SKevin Hilman * high. S CONTROL_PADCONF_SAD2D_IDLEACK and 6488111b221SKevin Hilman * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ 6498111b221SKevin Hilman mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ 6508111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); 6518111b221SKevin Hilman padconf |= mask; 6528111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); 6538111b221SKevin Hilman 6548111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); 6558111b221SKevin Hilman padconf |= mask; 6568111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 6578111b221SKevin Hilman 6588bd22949SKevin Hilman /* reset modem */ 659c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | 6602bc4ef71SPaul Walmsley OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, 66137903009SAbhijit Pagare CORE_MOD, OMAP2_RM_RSTCTRL); 662c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); 6638111b221SKevin Hilman } 6648bd22949SKevin Hilman 6658111b221SKevin Hilman static void __init prcm_setup_regs(void) 6668111b221SKevin Hilman { 667e5863689SGovindraj.R u32 omap3630_en_uart4_mask = cpu_is_omap3630() ? 668e5863689SGovindraj.R OMAP3630_EN_UART4_MASK : 0; 669e5863689SGovindraj.R u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ? 670e5863689SGovindraj.R OMAP3630_GRPSEL_UART4_MASK : 0; 671e5863689SGovindraj.R 6724ef70c06SPaul Walmsley /* XXX This should be handled by hwmod code or SCM init code */ 6732fd0f75cSPaul Walmsley omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); 674b296c811STero Kristo 6758bd22949SKevin Hilman /* 6768bd22949SKevin Hilman * Enable control of expternal oscillator through 6778bd22949SKevin Hilman * sys_clkreq. In the long run clock framework should 6788bd22949SKevin Hilman * take care of this. 6798bd22949SKevin Hilman */ 680c4d7e58fSPaul Walmsley omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 6818bd22949SKevin Hilman 1 << OMAP_AUTOEXTCLKMODE_SHIFT, 6828bd22949SKevin Hilman OMAP3430_GR_MOD, 6838bd22949SKevin Hilman OMAP3_PRM_CLKSRC_CTRL_OFFSET); 6848bd22949SKevin Hilman 6858bd22949SKevin Hilman /* setup wakup source */ 686c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | 6872fd0f75cSPaul Walmsley OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, 6888bd22949SKevin Hilman WKUP_MOD, PM_WKEN); 6898bd22949SKevin Hilman /* No need to write EN_IO, that is always enabled */ 690c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | 691275f675cSPaul Walmsley OMAP3430_GRPSEL_GPT1_MASK | 692275f675cSPaul Walmsley OMAP3430_GRPSEL_GPT12_MASK, 6938bd22949SKevin Hilman WKUP_MOD, OMAP3430_PM_MPUGRPSEL); 6948bd22949SKevin Hilman /* For some reason IO doesn't generate wakeup event even if 6958bd22949SKevin Hilman * it is selected to mpu wakeup goup */ 696c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK, 6978bd22949SKevin Hilman OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); 6981155e426SKevin Hilman 699b92c5721SSubramani Venkatesh /* Enable PM_WKEN to support DSS LPR */ 700c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, 701b92c5721SSubramani Venkatesh OMAP3430_DSS_MOD, PM_WKEN); 702b92c5721SSubramani Venkatesh 703b427f92fSKevin Hilman /* Enable wakeups in PER */ 704c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(omap3630_en_uart4_mask | 705e5863689SGovindraj.R OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | 7062fd0f75cSPaul Walmsley OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | 7072fd0f75cSPaul Walmsley OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | 7082fd0f75cSPaul Walmsley OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK | 7092fd0f75cSPaul Walmsley OMAP3430_EN_MCBSP4_MASK, 710b427f92fSKevin Hilman OMAP3430_PER_MOD, PM_WKEN); 711eb350f74SKevin Hilman /* and allow them to wake up MPU */ 712c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask | 713e5863689SGovindraj.R OMAP3430_GRPSEL_GPIO2_MASK | 714275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO3_MASK | 715275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO4_MASK | 716275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO5_MASK | 717275f675cSPaul Walmsley OMAP3430_GRPSEL_GPIO6_MASK | 718275f675cSPaul Walmsley OMAP3430_GRPSEL_UART3_MASK | 719275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP2_MASK | 720275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP3_MASK | 721275f675cSPaul Walmsley OMAP3430_GRPSEL_MCBSP4_MASK, 722eb350f74SKevin Hilman OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); 723eb350f74SKevin Hilman 724d3fd3290SKevin Hilman /* Don't attach IVA interrupts */ 725c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 726c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 727c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 728c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); 729d3fd3290SKevin Hilman 730b1340d17SKevin Hilman /* Clear any pending 'reset' flags */ 731c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); 732c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); 733c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); 734c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); 735c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); 736c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); 737c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); 738b1340d17SKevin Hilman 739014c46dbSKevin Hilman /* Clear any pending PRCM interrupts */ 740c4d7e58fSPaul Walmsley omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 741014c46dbSKevin Hilman 7421155e426SKevin Hilman omap3_iva_idle(); 7438111b221SKevin Hilman omap3_d2d_idle(); 7448bd22949SKevin Hilman } 7458bd22949SKevin Hilman 746c40552bcSKevin Hilman void omap3_pm_off_mode_enable(int enable) 747c40552bcSKevin Hilman { 748c40552bcSKevin Hilman struct power_state *pwrst; 749c40552bcSKevin Hilman u32 state; 750c40552bcSKevin Hilman 751c40552bcSKevin Hilman if (enable) 752c40552bcSKevin Hilman state = PWRDM_POWER_OFF; 753c40552bcSKevin Hilman else 754c40552bcSKevin Hilman state = PWRDM_POWER_RET; 755c40552bcSKevin Hilman 756c40552bcSKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 757cc1b6028SEduardo Valentin if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) && 758cc1b6028SEduardo Valentin pwrst->pwrdm == core_pwrdm && 759cc1b6028SEduardo Valentin state == PWRDM_POWER_OFF) { 760cc1b6028SEduardo Valentin pwrst->next_state = PWRDM_POWER_RET; 761e16b41bfSRicardo Salveti de Araujo pr_warn("%s: Core OFF disabled due to errata i583\n", 762cc1b6028SEduardo Valentin __func__); 763cc1b6028SEduardo Valentin } else { 764c40552bcSKevin Hilman pwrst->next_state = state; 765cc1b6028SEduardo Valentin } 766cc1b6028SEduardo Valentin omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 767c40552bcSKevin Hilman } 768c40552bcSKevin Hilman } 769c40552bcSKevin Hilman 77068d4778cSTero Kristo int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) 77168d4778cSTero Kristo { 77268d4778cSTero Kristo struct power_state *pwrst; 77368d4778cSTero Kristo 77468d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 77568d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) 77668d4778cSTero Kristo return pwrst->next_state; 77768d4778cSTero Kristo } 77868d4778cSTero Kristo return -EINVAL; 77968d4778cSTero Kristo } 78068d4778cSTero Kristo 78168d4778cSTero Kristo int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) 78268d4778cSTero Kristo { 78368d4778cSTero Kristo struct power_state *pwrst; 78468d4778cSTero Kristo 78568d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 78668d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) { 78768d4778cSTero Kristo pwrst->next_state = state; 78868d4778cSTero Kristo return 0; 78968d4778cSTero Kristo } 79068d4778cSTero Kristo } 79168d4778cSTero Kristo return -EINVAL; 79268d4778cSTero Kristo } 79368d4778cSTero Kristo 794a23456e9SPeter 'p2' De Schrijver static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) 7958bd22949SKevin Hilman { 7968bd22949SKevin Hilman struct power_state *pwrst; 7978bd22949SKevin Hilman 7988bd22949SKevin Hilman if (!pwrdm->pwrsts) 7998bd22949SKevin Hilman return 0; 8008bd22949SKevin Hilman 801d3d381c6SMing Lei pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); 8028bd22949SKevin Hilman if (!pwrst) 8038bd22949SKevin Hilman return -ENOMEM; 8048bd22949SKevin Hilman pwrst->pwrdm = pwrdm; 8058bd22949SKevin Hilman pwrst->next_state = PWRDM_POWER_RET; 8068bd22949SKevin Hilman list_add(&pwrst->node, &pwrst_list); 8078bd22949SKevin Hilman 8088bd22949SKevin Hilman if (pwrdm_has_hdwr_sar(pwrdm)) 8098bd22949SKevin Hilman pwrdm_enable_hdwr_sar(pwrdm); 8108bd22949SKevin Hilman 811eb6a2c75SSantosh Shilimkar return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 8128bd22949SKevin Hilman } 8138bd22949SKevin Hilman 8148bd22949SKevin Hilman /* 8158bd22949SKevin Hilman * Enable hw supervised mode for all clockdomains if it's 8168bd22949SKevin Hilman * supported. Initiate sleep transition for other clockdomains, if 8178bd22949SKevin Hilman * they are not used 8188bd22949SKevin Hilman */ 819a23456e9SPeter 'p2' De Schrijver static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) 8208bd22949SKevin Hilman { 8218bd22949SKevin Hilman if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) 8225cd1937bSRajendra Nayak clkdm_allow_idle(clkdm); 8238bd22949SKevin Hilman else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && 8248bd22949SKevin Hilman atomic_read(&clkdm->usecount) == 0) 82568b921adSRajendra Nayak clkdm_sleep(clkdm); 8268bd22949SKevin Hilman return 0; 8278bd22949SKevin Hilman } 8288bd22949SKevin Hilman 8293231fc88SRajendra Nayak void omap_push_sram_idle(void) 8303231fc88SRajendra Nayak { 8313231fc88SRajendra Nayak _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend, 8323231fc88SRajendra Nayak omap34xx_cpu_suspend_sz); 83327d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) 83427d59a4aSTero Kristo _omap_save_secure_sram = omap_sram_push(save_secure_ram_context, 83527d59a4aSTero Kristo save_secure_ram_context_sz); 8363231fc88SRajendra Nayak } 8373231fc88SRajendra Nayak 8388cdfd834SNishanth Menon static void __init pm_errata_configure(void) 8398cdfd834SNishanth Menon { 840c4236d2eSPeter 'p2' De Schrijver if (cpu_is_omap3630()) { 841458e999eSNishanth Menon pm34xx_errata |= PM_RTA_ERRATUM_i608; 842c4236d2eSPeter 'p2' De Schrijver /* Enable the l2 cache toggling in sleep logic */ 843c4236d2eSPeter 'p2' De Schrijver enable_omap3630_toggle_l2_on_restore(); 844cc1b6028SEduardo Valentin if (omap_rev() < OMAP3630_REV_ES1_2) 845cc1b6028SEduardo Valentin pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583; 846c4236d2eSPeter 'p2' De Schrijver } 8478cdfd834SNishanth Menon } 8488cdfd834SNishanth Menon 8497cc515f7SKevin Hilman static int __init omap3_pm_init(void) 8508bd22949SKevin Hilman { 8518bd22949SKevin Hilman struct power_state *pwrst, *tmp; 85255ed9694SPaul Walmsley struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm; 8538bd22949SKevin Hilman int ret; 8548bd22949SKevin Hilman 8558bd22949SKevin Hilman if (!cpu_is_omap34xx()) 8568bd22949SKevin Hilman return -ENODEV; 8578bd22949SKevin Hilman 8588cdfd834SNishanth Menon pm_errata_configure(); 8598cdfd834SNishanth Menon 8608bd22949SKevin Hilman /* XXX prcm_setup_regs needs to be before enabling hw 8618bd22949SKevin Hilman * supervised mode for powerdomains */ 8628bd22949SKevin Hilman prcm_setup_regs(); 8638bd22949SKevin Hilman 8648bd22949SKevin Hilman ret = request_irq(INT_34XX_PRCM_MPU_IRQ, 8658bd22949SKevin Hilman (irq_handler_t)prcm_interrupt_handler, 8668bd22949SKevin Hilman IRQF_DISABLED, "prcm", NULL); 8678bd22949SKevin Hilman if (ret) { 8688bd22949SKevin Hilman printk(KERN_ERR "request_irq failed to register for 0x%x\n", 8698bd22949SKevin Hilman INT_34XX_PRCM_MPU_IRQ); 8708bd22949SKevin Hilman goto err1; 8718bd22949SKevin Hilman } 8728bd22949SKevin Hilman 873a23456e9SPeter 'p2' De Schrijver ret = pwrdm_for_each(pwrdms_setup, NULL); 8748bd22949SKevin Hilman if (ret) { 8758bd22949SKevin Hilman printk(KERN_ERR "Failed to setup powerdomains\n"); 8768bd22949SKevin Hilman goto err2; 8778bd22949SKevin Hilman } 8788bd22949SKevin Hilman 879a23456e9SPeter 'p2' De Schrijver (void) clkdm_for_each(clkdms_setup, NULL); 8808bd22949SKevin Hilman 8818bd22949SKevin Hilman mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); 8828bd22949SKevin Hilman if (mpu_pwrdm == NULL) { 8838bd22949SKevin Hilman printk(KERN_ERR "Failed to get mpu_pwrdm\n"); 8848bd22949SKevin Hilman goto err2; 8858bd22949SKevin Hilman } 8868bd22949SKevin Hilman 887fa3c2a4fSRajendra Nayak neon_pwrdm = pwrdm_lookup("neon_pwrdm"); 888fa3c2a4fSRajendra Nayak per_pwrdm = pwrdm_lookup("per_pwrdm"); 889fa3c2a4fSRajendra Nayak core_pwrdm = pwrdm_lookup("core_pwrdm"); 890c16c3f67STero Kristo cam_pwrdm = pwrdm_lookup("cam_pwrdm"); 891fa3c2a4fSRajendra Nayak 89255ed9694SPaul Walmsley neon_clkdm = clkdm_lookup("neon_clkdm"); 89355ed9694SPaul Walmsley mpu_clkdm = clkdm_lookup("mpu_clkdm"); 89455ed9694SPaul Walmsley per_clkdm = clkdm_lookup("per_clkdm"); 89555ed9694SPaul Walmsley core_clkdm = clkdm_lookup("core_clkdm"); 89655ed9694SPaul Walmsley 8973231fc88SRajendra Nayak omap_push_sram_idle(); 89810f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 8998bd22949SKevin Hilman suspend_set_ops(&omap_pm_ops); 90010f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 9018bd22949SKevin Hilman 9028bd22949SKevin Hilman pm_idle = omap3_pm_idle; 9030343371eSKalle Jokiniemi omap3_idle_init(); 9048bd22949SKevin Hilman 905458e999eSNishanth Menon /* 906458e999eSNishanth Menon * RTA is disabled during initialization as per erratum i608 907458e999eSNishanth Menon * it is safer to disable RTA by the bootloader, but we would like 908458e999eSNishanth Menon * to be doubly sure here and prevent any mishaps. 909458e999eSNishanth Menon */ 910458e999eSNishanth Menon if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608)) 911458e999eSNishanth Menon omap3630_ctrl_disable_rta(); 912458e999eSNishanth Menon 91355ed9694SPaul Walmsley clkdm_add_wkdep(neon_clkdm, mpu_clkdm); 91427d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 91527d59a4aSTero Kristo omap3_secure_ram_storage = 91627d59a4aSTero Kristo kmalloc(0x803F, GFP_KERNEL); 91727d59a4aSTero Kristo if (!omap3_secure_ram_storage) 91827d59a4aSTero Kristo printk(KERN_ERR "Memory allocation failed when" 91927d59a4aSTero Kristo "allocating for secure sram context\n"); 92027d59a4aSTero Kristo 9219d97140bSTero Kristo local_irq_disable(); 9229d97140bSTero Kristo local_fiq_disable(); 9239d97140bSTero Kristo 9249d97140bSTero Kristo omap_dma_global_context_save(); 925617fcc98SKevin Hilman omap3_save_secure_ram_context(); 9269d97140bSTero Kristo omap_dma_global_context_restore(); 9279d97140bSTero Kristo 9289d97140bSTero Kristo local_irq_enable(); 9299d97140bSTero Kristo local_fiq_enable(); 9309d97140bSTero Kristo } 9319d97140bSTero Kristo 9329d97140bSTero Kristo omap3_save_scratchpad_contents(); 9338bd22949SKevin Hilman err1: 9348bd22949SKevin Hilman return ret; 9358bd22949SKevin Hilman err2: 9368bd22949SKevin Hilman free_irq(INT_34XX_PRCM_MPU_IRQ, NULL); 9378bd22949SKevin Hilman list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { 9388bd22949SKevin Hilman list_del(&pwrst->node); 9398bd22949SKevin Hilman kfree(pwrst); 9408bd22949SKevin Hilman } 9418bd22949SKevin Hilman return ret; 9428bd22949SKevin Hilman } 9438bd22949SKevin Hilman 9448bd22949SKevin Hilman late_initcall(omap3_pm_init); 945