18bd22949SKevin Hilman /* 28bd22949SKevin Hilman * OMAP3 Power Management Routines 38bd22949SKevin Hilman * 48bd22949SKevin Hilman * Copyright (C) 2006-2008 Nokia Corporation 58bd22949SKevin Hilman * Tony Lindgren <tony@atomide.com> 68bd22949SKevin Hilman * Jouni Hogander 78bd22949SKevin Hilman * 82f5939c3SRajendra Nayak * Copyright (C) 2007 Texas Instruments, Inc. 92f5939c3SRajendra Nayak * Rajendra Nayak <rnayak@ti.com> 102f5939c3SRajendra Nayak * 118bd22949SKevin Hilman * Copyright (C) 2005 Texas Instruments, Inc. 128bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 138bd22949SKevin Hilman * 148bd22949SKevin Hilman * Based on pm.c for omap1 158bd22949SKevin Hilman * 168bd22949SKevin Hilman * This program is free software; you can redistribute it and/or modify 178bd22949SKevin Hilman * it under the terms of the GNU General Public License version 2 as 188bd22949SKevin Hilman * published by the Free Software Foundation. 198bd22949SKevin Hilman */ 208bd22949SKevin Hilman 218bd22949SKevin Hilman #include <linux/pm.h> 228bd22949SKevin Hilman #include <linux/suspend.h> 238bd22949SKevin Hilman #include <linux/interrupt.h> 248bd22949SKevin Hilman #include <linux/module.h> 258bd22949SKevin Hilman #include <linux/list.h> 268bd22949SKevin Hilman #include <linux/err.h> 278bd22949SKevin Hilman #include <linux/gpio.h> 28c40552bcSKevin Hilman #include <linux/clk.h> 298bd22949SKevin Hilman 30ce491cf8STony Lindgren #include <plat/sram.h> 31ce491cf8STony Lindgren #include <plat/clockdomain.h> 32ce491cf8STony Lindgren #include <plat/powerdomain.h> 33ce491cf8STony Lindgren #include <plat/control.h> 34ce491cf8STony Lindgren #include <plat/serial.h> 3561255ab9SRajendra Nayak #include <plat/sdrc.h> 362f5939c3SRajendra Nayak #include <plat/prcm.h> 372f5939c3SRajendra Nayak #include <plat/gpmc.h> 38f2d11858STero Kristo #include <plat/dma.h> 39d7814e4dSKevin Hilman #include <plat/dmtimer.h> 408bd22949SKevin Hilman 4157f277b0SRajendra Nayak #include <asm/tlbflush.h> 4257f277b0SRajendra Nayak 438bd22949SKevin Hilman #include "cm.h" 448bd22949SKevin Hilman #include "cm-regbits-34xx.h" 458bd22949SKevin Hilman #include "prm-regbits-34xx.h" 468bd22949SKevin Hilman 478bd22949SKevin Hilman #include "prm.h" 488bd22949SKevin Hilman #include "pm.h" 4913a6fe0fSTero Kristo #include "sdrc.h" 5013a6fe0fSTero Kristo 512f5939c3SRajendra Nayak /* Scratchpad offsets */ 522f5939c3SRajendra Nayak #define OMAP343X_TABLE_ADDRESS_OFFSET 0x31 532f5939c3SRajendra Nayak #define OMAP343X_TABLE_VALUE_OFFSET 0x30 542f5939c3SRajendra Nayak #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32 552f5939c3SRajendra Nayak 56c40552bcSKevin Hilman u32 enable_off_mode; 57c40552bcSKevin Hilman u32 sleep_while_idle; 58d7814e4dSKevin Hilman u32 wakeup_timer_seconds; 59c40552bcSKevin Hilman 608bd22949SKevin Hilman struct power_state { 618bd22949SKevin Hilman struct powerdomain *pwrdm; 628bd22949SKevin Hilman u32 next_state; 6310f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 648bd22949SKevin Hilman u32 saved_state; 6510f90ed2SKevin Hilman #endif 668bd22949SKevin Hilman struct list_head node; 678bd22949SKevin Hilman }; 688bd22949SKevin Hilman 698bd22949SKevin Hilman static LIST_HEAD(pwrst_list); 708bd22949SKevin Hilman 718bd22949SKevin Hilman static void (*_omap_sram_idle)(u32 *addr, int save_state); 728bd22949SKevin Hilman 7327d59a4aSTero Kristo static int (*_omap_save_secure_sram)(u32 *addr); 7427d59a4aSTero Kristo 75fa3c2a4fSRajendra Nayak static struct powerdomain *mpu_pwrdm, *neon_pwrdm; 76fa3c2a4fSRajendra Nayak static struct powerdomain *core_pwrdm, *per_pwrdm; 77c16c3f67STero Kristo static struct powerdomain *cam_pwrdm; 78fa3c2a4fSRajendra Nayak 792f5939c3SRajendra Nayak static inline void omap3_per_save_context(void) 802f5939c3SRajendra Nayak { 812f5939c3SRajendra Nayak omap_gpio_save_context(); 822f5939c3SRajendra Nayak } 832f5939c3SRajendra Nayak 842f5939c3SRajendra Nayak static inline void omap3_per_restore_context(void) 852f5939c3SRajendra Nayak { 862f5939c3SRajendra Nayak omap_gpio_restore_context(); 872f5939c3SRajendra Nayak } 882f5939c3SRajendra Nayak 893a7ec26bSKalle Jokiniemi static void omap3_enable_io_chain(void) 903a7ec26bSKalle Jokiniemi { 913a7ec26bSKalle Jokiniemi int timeout = 0; 923a7ec26bSKalle Jokiniemi 933a7ec26bSKalle Jokiniemi if (omap_rev() >= OMAP3430_REV_ES3_1) { 943a7ec26bSKalle Jokiniemi prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN); 953a7ec26bSKalle Jokiniemi /* Do a readback to assure write has been done */ 963a7ec26bSKalle Jokiniemi prm_read_mod_reg(WKUP_MOD, PM_WKEN); 973a7ec26bSKalle Jokiniemi 983a7ec26bSKalle Jokiniemi while (!(prm_read_mod_reg(WKUP_MOD, PM_WKST) & 993a7ec26bSKalle Jokiniemi OMAP3430_ST_IO_CHAIN)) { 1003a7ec26bSKalle Jokiniemi timeout++; 1013a7ec26bSKalle Jokiniemi if (timeout > 1000) { 1023a7ec26bSKalle Jokiniemi printk(KERN_ERR "Wake up daisy chain " 1033a7ec26bSKalle Jokiniemi "activation failed.\n"); 1043a7ec26bSKalle Jokiniemi return; 1053a7ec26bSKalle Jokiniemi } 1063a7ec26bSKalle Jokiniemi prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN, 1073a7ec26bSKalle Jokiniemi WKUP_MOD, PM_WKST); 1083a7ec26bSKalle Jokiniemi } 1093a7ec26bSKalle Jokiniemi } 1103a7ec26bSKalle Jokiniemi } 1113a7ec26bSKalle Jokiniemi 1123a7ec26bSKalle Jokiniemi static void omap3_disable_io_chain(void) 1133a7ec26bSKalle Jokiniemi { 1143a7ec26bSKalle Jokiniemi if (omap_rev() >= OMAP3430_REV_ES3_1) 1153a7ec26bSKalle Jokiniemi prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN); 1163a7ec26bSKalle Jokiniemi } 1173a7ec26bSKalle Jokiniemi 1182f5939c3SRajendra Nayak static void omap3_core_save_context(void) 1192f5939c3SRajendra Nayak { 1202f5939c3SRajendra Nayak u32 control_padconf_off; 1212f5939c3SRajendra Nayak 1222f5939c3SRajendra Nayak /* Save the padconf registers */ 1232f5939c3SRajendra Nayak control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF); 1242f5939c3SRajendra Nayak control_padconf_off |= START_PADCONF_SAVE; 1252f5939c3SRajendra Nayak omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF); 1262f5939c3SRajendra Nayak /* wait for the save to complete */ 1271b6e821fSRoel Kluin while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) 1281b6e821fSRoel Kluin & PADCONF_SAVE_DONE)) 1292f5939c3SRajendra Nayak ; 1302f5939c3SRajendra Nayak /* Save the Interrupt controller context */ 1312f5939c3SRajendra Nayak omap_intc_save_context(); 1322f5939c3SRajendra Nayak /* Save the GPMC context */ 1332f5939c3SRajendra Nayak omap3_gpmc_save_context(); 1342f5939c3SRajendra Nayak /* Save the system control module context, padconf already save above*/ 1352f5939c3SRajendra Nayak omap3_control_save_context(); 136f2d11858STero Kristo omap_dma_global_context_save(); 1372f5939c3SRajendra Nayak } 1382f5939c3SRajendra Nayak 1392f5939c3SRajendra Nayak static void omap3_core_restore_context(void) 1402f5939c3SRajendra Nayak { 1412f5939c3SRajendra Nayak /* Restore the control module context, padconf restored by h/w */ 1422f5939c3SRajendra Nayak omap3_control_restore_context(); 1432f5939c3SRajendra Nayak /* Restore the GPMC context */ 1442f5939c3SRajendra Nayak omap3_gpmc_restore_context(); 1452f5939c3SRajendra Nayak /* Restore the interrupt controller context */ 1462f5939c3SRajendra Nayak omap_intc_restore_context(); 147f2d11858STero Kristo omap_dma_global_context_restore(); 1482f5939c3SRajendra Nayak } 1492f5939c3SRajendra Nayak 1509d97140bSTero Kristo /* 1519d97140bSTero Kristo * FIXME: This function should be called before entering off-mode after 1529d97140bSTero Kristo * OMAP3 secure services have been accessed. Currently it is only called 1539d97140bSTero Kristo * once during boot sequence, but this works as we are not using secure 1549d97140bSTero Kristo * services. 1559d97140bSTero Kristo */ 15627d59a4aSTero Kristo static void omap3_save_secure_ram_context(u32 target_mpu_state) 15727d59a4aSTero Kristo { 15827d59a4aSTero Kristo u32 ret; 15927d59a4aSTero Kristo 16027d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 16127d59a4aSTero Kristo /* 16227d59a4aSTero Kristo * MPU next state must be set to POWER_ON temporarily, 16327d59a4aSTero Kristo * otherwise the WFI executed inside the ROM code 16427d59a4aSTero Kristo * will hang the system. 16527d59a4aSTero Kristo */ 16627d59a4aSTero Kristo pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); 16727d59a4aSTero Kristo ret = _omap_save_secure_sram((u32 *) 16827d59a4aSTero Kristo __pa(omap3_secure_ram_storage)); 16927d59a4aSTero Kristo pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state); 17027d59a4aSTero Kristo /* Following is for error tracking, it should not happen */ 17127d59a4aSTero Kristo if (ret) { 17227d59a4aSTero Kristo printk(KERN_ERR "save_secure_sram() returns %08x\n", 17327d59a4aSTero Kristo ret); 17427d59a4aSTero Kristo while (1) 17527d59a4aSTero Kristo ; 17627d59a4aSTero Kristo } 17727d59a4aSTero Kristo } 17827d59a4aSTero Kristo } 17927d59a4aSTero Kristo 18077da2d91SJon Hunter /* 18177da2d91SJon Hunter * PRCM Interrupt Handler Helper Function 18277da2d91SJon Hunter * 18377da2d91SJon Hunter * The purpose of this function is to clear any wake-up events latched 18477da2d91SJon Hunter * in the PRCM PM_WKST_x registers. It is possible that a wake-up event 18577da2d91SJon Hunter * may occur whilst attempting to clear a PM_WKST_x register and thus 18677da2d91SJon Hunter * set another bit in this register. A while loop is used to ensure 18777da2d91SJon Hunter * that any peripheral wake-up events occurring while attempting to 18877da2d91SJon Hunter * clear the PM_WKST_x are detected and cleared. 18977da2d91SJon Hunter */ 1908cb0ac99SPaul Walmsley static int prcm_clear_mod_irqs(s16 module, u8 regs) 19177da2d91SJon Hunter { 19271a80775SVikram Pandita u32 wkst, fclk, iclk, clken; 19377da2d91SJon Hunter u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; 19477da2d91SJon Hunter u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; 19577da2d91SJon Hunter u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; 1965d805978SPaul Walmsley u16 grpsel_off = (regs == 3) ? 1975d805978SPaul Walmsley OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; 1988cb0ac99SPaul Walmsley int c = 0; 19977da2d91SJon Hunter 20077da2d91SJon Hunter wkst = prm_read_mod_reg(module, wkst_off); 2015d805978SPaul Walmsley wkst &= prm_read_mod_reg(module, grpsel_off); 20277da2d91SJon Hunter if (wkst) { 20377da2d91SJon Hunter iclk = cm_read_mod_reg(module, iclk_off); 20477da2d91SJon Hunter fclk = cm_read_mod_reg(module, fclk_off); 20577da2d91SJon Hunter while (wkst) { 20671a80775SVikram Pandita clken = wkst; 20771a80775SVikram Pandita cm_set_mod_reg_bits(clken, module, iclk_off); 20871a80775SVikram Pandita /* 20971a80775SVikram Pandita * For USBHOST, we don't know whether HOST1 or 21071a80775SVikram Pandita * HOST2 woke us up, so enable both f-clocks 21171a80775SVikram Pandita */ 21271a80775SVikram Pandita if (module == OMAP3430ES2_USBHOST_MOD) 21371a80775SVikram Pandita clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; 21471a80775SVikram Pandita cm_set_mod_reg_bits(clken, module, fclk_off); 21577da2d91SJon Hunter prm_write_mod_reg(wkst, module, wkst_off); 21677da2d91SJon Hunter wkst = prm_read_mod_reg(module, wkst_off); 2178cb0ac99SPaul Walmsley c++; 21877da2d91SJon Hunter } 21977da2d91SJon Hunter cm_write_mod_reg(iclk, module, iclk_off); 22077da2d91SJon Hunter cm_write_mod_reg(fclk, module, fclk_off); 22177da2d91SJon Hunter } 2228cb0ac99SPaul Walmsley 2238cb0ac99SPaul Walmsley return c; 2248cb0ac99SPaul Walmsley } 2258cb0ac99SPaul Walmsley 2268cb0ac99SPaul Walmsley static int _prcm_int_handle_wakeup(void) 2278cb0ac99SPaul Walmsley { 2288cb0ac99SPaul Walmsley int c; 2298cb0ac99SPaul Walmsley 2308cb0ac99SPaul Walmsley c = prcm_clear_mod_irqs(WKUP_MOD, 1); 2318cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(CORE_MOD, 1); 2328cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1); 2338cb0ac99SPaul Walmsley if (omap_rev() > OMAP3430_REV_ES1_0) { 2348cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(CORE_MOD, 3); 2358cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1); 2368cb0ac99SPaul Walmsley } 2378cb0ac99SPaul Walmsley 2388cb0ac99SPaul Walmsley return c; 23977da2d91SJon Hunter } 24077da2d91SJon Hunter 24177da2d91SJon Hunter /* 24277da2d91SJon Hunter * PRCM Interrupt Handler 24377da2d91SJon Hunter * 24477da2d91SJon Hunter * The PRM_IRQSTATUS_MPU register indicates if there are any pending 24577da2d91SJon Hunter * interrupts from the PRCM for the MPU. These bits must be cleared in 24677da2d91SJon Hunter * order to clear the PRCM interrupt. The PRCM interrupt handler is 24777da2d91SJon Hunter * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear 24877da2d91SJon Hunter * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU 24977da2d91SJon Hunter * register indicates that a wake-up event is pending for the MPU and 25077da2d91SJon Hunter * this bit can only be cleared if the all the wake-up events latched 25177da2d91SJon Hunter * in the various PM_WKST_x registers have been cleared. The interrupt 25277da2d91SJon Hunter * handler is implemented using a do-while loop so that if a wake-up 25377da2d91SJon Hunter * event occurred during the processing of the prcm interrupt handler 25477da2d91SJon Hunter * (setting a bit in the corresponding PM_WKST_x register and thus 25577da2d91SJon Hunter * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register) 25677da2d91SJon Hunter * this would be handled. 25777da2d91SJon Hunter */ 2588bd22949SKevin Hilman static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) 2598bd22949SKevin Hilman { 26077da2d91SJon Hunter u32 irqstatus_mpu; 2618cb0ac99SPaul Walmsley int c = 0; 2628bd22949SKevin Hilman 26377da2d91SJon Hunter do { 2648bd22949SKevin Hilman irqstatus_mpu = prm_read_mod_reg(OCP_MOD, 2658bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 2668cb0ac99SPaul Walmsley 2678cb0ac99SPaul Walmsley if (irqstatus_mpu & (OMAP3430_WKUP_ST | OMAP3430_IO_ST)) { 2688cb0ac99SPaul Walmsley c = _prcm_int_handle_wakeup(); 2698cb0ac99SPaul Walmsley 2708cb0ac99SPaul Walmsley /* 2718cb0ac99SPaul Walmsley * Is the MPU PRCM interrupt handler racing with the 2728cb0ac99SPaul Walmsley * IVA2 PRCM interrupt handler ? 2738cb0ac99SPaul Walmsley */ 2748cb0ac99SPaul Walmsley WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup " 2758cb0ac99SPaul Walmsley "but no wakeup sources are marked\n"); 2768cb0ac99SPaul Walmsley } else { 2778cb0ac99SPaul Walmsley /* XXX we need to expand our PRCM interrupt handler */ 2788cb0ac99SPaul Walmsley WARN(1, "prcm: WARNING: PRCM interrupt received, but " 2798cb0ac99SPaul Walmsley "no code to handle it (%08x)\n", irqstatus_mpu); 2808cb0ac99SPaul Walmsley } 2818cb0ac99SPaul Walmsley 2828bd22949SKevin Hilman prm_write_mod_reg(irqstatus_mpu, OCP_MOD, 2838bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 2848bd22949SKevin Hilman 28577da2d91SJon Hunter } while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET)); 2868bd22949SKevin Hilman 2878bd22949SKevin Hilman return IRQ_HANDLED; 2888bd22949SKevin Hilman } 2898bd22949SKevin Hilman 29057f277b0SRajendra Nayak static void restore_control_register(u32 val) 29157f277b0SRajendra Nayak { 29257f277b0SRajendra Nayak __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val)); 29357f277b0SRajendra Nayak } 29457f277b0SRajendra Nayak 29557f277b0SRajendra Nayak /* Function to restore the table entry that was modified for enabling MMU */ 29657f277b0SRajendra Nayak static void restore_table_entry(void) 29757f277b0SRajendra Nayak { 29857f277b0SRajendra Nayak u32 *scratchpad_address; 29957f277b0SRajendra Nayak u32 previous_value, control_reg_value; 30057f277b0SRajendra Nayak u32 *address; 30157f277b0SRajendra Nayak 30257f277b0SRajendra Nayak scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD); 30357f277b0SRajendra Nayak 30457f277b0SRajendra Nayak /* Get address of entry that was modified */ 30557f277b0SRajendra Nayak address = (u32 *)__raw_readl(scratchpad_address + 30657f277b0SRajendra Nayak OMAP343X_TABLE_ADDRESS_OFFSET); 30757f277b0SRajendra Nayak /* Get the previous value which needs to be restored */ 30857f277b0SRajendra Nayak previous_value = __raw_readl(scratchpad_address + 30957f277b0SRajendra Nayak OMAP343X_TABLE_VALUE_OFFSET); 31057f277b0SRajendra Nayak address = __va(address); 31157f277b0SRajendra Nayak *address = previous_value; 31257f277b0SRajendra Nayak flush_tlb_all(); 31357f277b0SRajendra Nayak control_reg_value = __raw_readl(scratchpad_address 31457f277b0SRajendra Nayak + OMAP343X_CONTROL_REG_VALUE_OFFSET); 31557f277b0SRajendra Nayak /* This will enable caches and prediction */ 31657f277b0SRajendra Nayak restore_control_register(control_reg_value); 31757f277b0SRajendra Nayak } 31857f277b0SRajendra Nayak 31999e6a4d2SRajendra Nayak void omap_sram_idle(void) 3208bd22949SKevin Hilman { 3218bd22949SKevin Hilman /* Variable to tell what needs to be saved and restored 3228bd22949SKevin Hilman * in omap_sram_idle*/ 3238bd22949SKevin Hilman /* save_state = 0 => Nothing to save and restored */ 3248bd22949SKevin Hilman /* save_state = 1 => Only L1 and logic lost */ 3258bd22949SKevin Hilman /* save_state = 2 => Only L2 lost */ 3268bd22949SKevin Hilman /* save_state = 3 => L1, L2 and logic lost */ 327fa3c2a4fSRajendra Nayak int save_state = 0; 328fa3c2a4fSRajendra Nayak int mpu_next_state = PWRDM_POWER_ON; 329fa3c2a4fSRajendra Nayak int per_next_state = PWRDM_POWER_ON; 330fa3c2a4fSRajendra Nayak int core_next_state = PWRDM_POWER_ON; 3312f5939c3SRajendra Nayak int core_prev_state, per_prev_state; 33213a6fe0fSTero Kristo u32 sdrc_pwr = 0; 333ecf157d0STero Kristo int per_state_modified = 0; 3348bd22949SKevin Hilman 3358bd22949SKevin Hilman if (!_omap_sram_idle) 3368bd22949SKevin Hilman return; 3378bd22949SKevin Hilman 338fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(mpu_pwrdm); 339fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(neon_pwrdm); 340fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(core_pwrdm); 341fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(per_pwrdm); 342fa3c2a4fSRajendra Nayak 3438bd22949SKevin Hilman mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 3448bd22949SKevin Hilman switch (mpu_next_state) { 345fa3c2a4fSRajendra Nayak case PWRDM_POWER_ON: 3468bd22949SKevin Hilman case PWRDM_POWER_RET: 3478bd22949SKevin Hilman /* No need to save context */ 3488bd22949SKevin Hilman save_state = 0; 3498bd22949SKevin Hilman break; 35061255ab9SRajendra Nayak case PWRDM_POWER_OFF: 35161255ab9SRajendra Nayak save_state = 3; 35261255ab9SRajendra Nayak break; 3538bd22949SKevin Hilman default: 3548bd22949SKevin Hilman /* Invalid state */ 3558bd22949SKevin Hilman printk(KERN_ERR "Invalid mpu state in sram_idle\n"); 3568bd22949SKevin Hilman return; 3578bd22949SKevin Hilman } 358fe617af7SPeter 'p2' De Schrijver pwrdm_pre_transition(); 359fe617af7SPeter 'p2' De Schrijver 360fa3c2a4fSRajendra Nayak /* NEON control */ 361fa3c2a4fSRajendra Nayak if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) 3627139178eSJouni Hogander pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); 363fa3c2a4fSRajendra Nayak 364658ce97eSKevin Hilman /* PER */ 365fa3c2a4fSRajendra Nayak per_next_state = pwrdm_read_next_pwrst(per_pwrdm); 366ecf157d0STero Kristo core_next_state = pwrdm_read_next_pwrst(core_pwrdm); 3672f5939c3SRajendra Nayak if (per_next_state < PWRDM_POWER_ON) { 3684af4016cSKevin Hilman omap_uart_prepare_idle(2); 369ecf157d0STero Kristo omap2_gpio_prepare_for_retention(); 370ecf157d0STero Kristo if (per_next_state == PWRDM_POWER_OFF) { 371ecf157d0STero Kristo if (core_next_state == PWRDM_POWER_ON) { 372ecf157d0STero Kristo per_next_state = PWRDM_POWER_RET; 373ecf157d0STero Kristo pwrdm_set_next_pwrst(per_pwrdm, per_next_state); 374ecf157d0STero Kristo per_state_modified = 1; 375ecf157d0STero Kristo } else 3762f5939c3SRajendra Nayak omap3_per_save_context(); 3772f5939c3SRajendra Nayak } 378ecf157d0STero Kristo } 379658ce97eSKevin Hilman 380c16c3f67STero Kristo if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON) 381c16c3f67STero Kristo omap2_clkdm_deny_idle(mpu_pwrdm->pwrdm_clkdms[0]); 382c16c3f67STero Kristo 383658ce97eSKevin Hilman /* CORE */ 384658ce97eSKevin Hilman if (core_next_state < PWRDM_POWER_ON) { 385658ce97eSKevin Hilman omap_uart_prepare_idle(0); 386658ce97eSKevin Hilman omap_uart_prepare_idle(1); 3872f5939c3SRajendra Nayak if (core_next_state == PWRDM_POWER_OFF) { 3882f5939c3SRajendra Nayak omap3_core_save_context(); 3892f5939c3SRajendra Nayak omap3_prcm_save_context(); 3902f5939c3SRajendra Nayak } 3913a7ec26bSKalle Jokiniemi /* Enable IO-PAD and IO-CHAIN wakeups */ 392fa3c2a4fSRajendra Nayak prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN); 3933a7ec26bSKalle Jokiniemi omap3_enable_io_chain(); 394fa3c2a4fSRajendra Nayak } 3958bd22949SKevin Hilman 39661255ab9SRajendra Nayak /* 397f265dc4cSRajendra Nayak * On EMU/HS devices ROM code restores a SRDC value 398f265dc4cSRajendra Nayak * from scratchpad which has automatic self refresh on timeout 399f265dc4cSRajendra Nayak * of AUTO_CNT = 1 enabled. This takes care of errata 1.142. 400f265dc4cSRajendra Nayak * Hence store/restore the SDRC_POWER register here. 40113a6fe0fSTero Kristo */ 40213a6fe0fSTero Kristo if (omap_rev() >= OMAP3430_REV_ES3_0 && 40313a6fe0fSTero Kristo omap_type() != OMAP2_DEVICE_TYPE_GP && 404f265dc4cSRajendra Nayak core_next_state == PWRDM_POWER_OFF) 40513a6fe0fSTero Kristo sdrc_pwr = sdrc_read_reg(SDRC_POWER); 40613a6fe0fSTero Kristo 40713a6fe0fSTero Kristo /* 40861255ab9SRajendra Nayak * omap3_arm_context is the location where ARM registers 40961255ab9SRajendra Nayak * get saved. The restore path then reads from this 41061255ab9SRajendra Nayak * location and restores them back. 41161255ab9SRajendra Nayak */ 41261255ab9SRajendra Nayak _omap_sram_idle(omap3_arm_context, save_state); 4138bd22949SKevin Hilman cpu_init(); 4148bd22949SKevin Hilman 415f265dc4cSRajendra Nayak /* Restore normal SDRC POWER settings */ 41613a6fe0fSTero Kristo if (omap_rev() >= OMAP3430_REV_ES3_0 && 41713a6fe0fSTero Kristo omap_type() != OMAP2_DEVICE_TYPE_GP && 41813a6fe0fSTero Kristo core_next_state == PWRDM_POWER_OFF) 41913a6fe0fSTero Kristo sdrc_write_reg(sdrc_pwr, SDRC_POWER); 42013a6fe0fSTero Kristo 42157f277b0SRajendra Nayak /* Restore table entry modified during MMU restoration */ 42257f277b0SRajendra Nayak if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF) 42357f277b0SRajendra Nayak restore_table_entry(); 42457f277b0SRajendra Nayak 425658ce97eSKevin Hilman /* CORE */ 426fa3c2a4fSRajendra Nayak if (core_next_state < PWRDM_POWER_ON) { 4272f5939c3SRajendra Nayak core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); 4282f5939c3SRajendra Nayak if (core_prev_state == PWRDM_POWER_OFF) { 4292f5939c3SRajendra Nayak omap3_core_restore_context(); 4302f5939c3SRajendra Nayak omap3_prcm_restore_context(); 4312f5939c3SRajendra Nayak omap3_sram_restore_context(); 4328a917d2fSKalle Jokiniemi omap2_sms_restore_context(); 4332f5939c3SRajendra Nayak } 434658ce97eSKevin Hilman omap_uart_resume_idle(0); 435658ce97eSKevin Hilman omap_uart_resume_idle(1); 436658ce97eSKevin Hilman if (core_next_state == PWRDM_POWER_OFF) 437658ce97eSKevin Hilman prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF, 438658ce97eSKevin Hilman OMAP3430_GR_MOD, 439658ce97eSKevin Hilman OMAP3_PRM_VOLTCTRL_OFFSET); 440658ce97eSKevin Hilman } 441658ce97eSKevin Hilman 442658ce97eSKevin Hilman /* PER */ 4432f5939c3SRajendra Nayak if (per_next_state < PWRDM_POWER_ON) { 444658ce97eSKevin Hilman per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); 4452f5939c3SRajendra Nayak if (per_prev_state == PWRDM_POWER_OFF) 4462f5939c3SRajendra Nayak omap3_per_restore_context(); 4478bd22949SKevin Hilman omap2_gpio_resume_after_retention(); 448ecf157d0STero Kristo omap_uart_resume_idle(2); 449ecf157d0STero Kristo if (per_state_modified) 450ecf157d0STero Kristo pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF); 451fa3c2a4fSRajendra Nayak } 452fe617af7SPeter 'p2' De Schrijver 4533a7ec26bSKalle Jokiniemi /* Disable IO-PAD and IO-CHAIN wakeup */ 4543a7ec26bSKalle Jokiniemi if (core_next_state < PWRDM_POWER_ON) { 455658ce97eSKevin Hilman prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN); 4563a7ec26bSKalle Jokiniemi omap3_disable_io_chain(); 4573a7ec26bSKalle Jokiniemi } 458658ce97eSKevin Hilman 459fe617af7SPeter 'p2' De Schrijver pwrdm_post_transition(); 460fe617af7SPeter 'p2' De Schrijver 461c16c3f67STero Kristo omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); 4628bd22949SKevin Hilman } 4638bd22949SKevin Hilman 46420b01669SRajendra Nayak int omap3_can_sleep(void) 4658bd22949SKevin Hilman { 466c40552bcSKevin Hilman if (!sleep_while_idle) 467c40552bcSKevin Hilman return 0; 4684af4016cSKevin Hilman if (!omap_uart_can_sleep()) 4694af4016cSKevin Hilman return 0; 4708bd22949SKevin Hilman return 1; 4718bd22949SKevin Hilman } 4728bd22949SKevin Hilman 4738bd22949SKevin Hilman /* This sets pwrdm state (other than mpu & core. Currently only ON & 4748bd22949SKevin Hilman * RET are supported. Function is assuming that clkdm doesn't have 4758bd22949SKevin Hilman * hw_sup mode enabled. */ 47620b01669SRajendra Nayak int set_pwrdm_state(struct powerdomain *pwrdm, u32 state) 4778bd22949SKevin Hilman { 4788bd22949SKevin Hilman u32 cur_state; 4798bd22949SKevin Hilman int sleep_switch = 0; 4808bd22949SKevin Hilman int ret = 0; 4818bd22949SKevin Hilman 4828bd22949SKevin Hilman if (pwrdm == NULL || IS_ERR(pwrdm)) 4838bd22949SKevin Hilman return -EINVAL; 4848bd22949SKevin Hilman 4858bd22949SKevin Hilman while (!(pwrdm->pwrsts & (1 << state))) { 4868bd22949SKevin Hilman if (state == PWRDM_POWER_OFF) 4878bd22949SKevin Hilman return ret; 4888bd22949SKevin Hilman state--; 4898bd22949SKevin Hilman } 4908bd22949SKevin Hilman 4918bd22949SKevin Hilman cur_state = pwrdm_read_next_pwrst(pwrdm); 4928bd22949SKevin Hilman if (cur_state == state) 4938bd22949SKevin Hilman return ret; 4948bd22949SKevin Hilman 4958bd22949SKevin Hilman if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) { 4968bd22949SKevin Hilman omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); 4978bd22949SKevin Hilman sleep_switch = 1; 4988bd22949SKevin Hilman pwrdm_wait_transition(pwrdm); 4998bd22949SKevin Hilman } 5008bd22949SKevin Hilman 5018bd22949SKevin Hilman ret = pwrdm_set_next_pwrst(pwrdm, state); 5028bd22949SKevin Hilman if (ret) { 5038bd22949SKevin Hilman printk(KERN_ERR "Unable to set state of powerdomain: %s\n", 5048bd22949SKevin Hilman pwrdm->name); 5058bd22949SKevin Hilman goto err; 5068bd22949SKevin Hilman } 5078bd22949SKevin Hilman 5088bd22949SKevin Hilman if (sleep_switch) { 5098bd22949SKevin Hilman omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); 5108bd22949SKevin Hilman pwrdm_wait_transition(pwrdm); 511fe617af7SPeter 'p2' De Schrijver pwrdm_state_switch(pwrdm); 5128bd22949SKevin Hilman } 5138bd22949SKevin Hilman 5148bd22949SKevin Hilman err: 5158bd22949SKevin Hilman return ret; 5168bd22949SKevin Hilman } 5178bd22949SKevin Hilman 5188bd22949SKevin Hilman static void omap3_pm_idle(void) 5198bd22949SKevin Hilman { 5208bd22949SKevin Hilman local_irq_disable(); 5218bd22949SKevin Hilman local_fiq_disable(); 5228bd22949SKevin Hilman 5238bd22949SKevin Hilman if (!omap3_can_sleep()) 5248bd22949SKevin Hilman goto out; 5258bd22949SKevin Hilman 526cf22854cSTero Kristo if (omap_irq_pending() || need_resched()) 5278bd22949SKevin Hilman goto out; 5288bd22949SKevin Hilman 5298bd22949SKevin Hilman omap_sram_idle(); 5308bd22949SKevin Hilman 5318bd22949SKevin Hilman out: 5328bd22949SKevin Hilman local_fiq_enable(); 5338bd22949SKevin Hilman local_irq_enable(); 5348bd22949SKevin Hilman } 5358bd22949SKevin Hilman 53610f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 5372466211eSTero Kristo static suspend_state_t suspend_state; 5382466211eSTero Kristo 539d7814e4dSKevin Hilman static void omap2_pm_wakeup_on_timer(u32 seconds) 540d7814e4dSKevin Hilman { 541d7814e4dSKevin Hilman u32 tick_rate, cycles; 542d7814e4dSKevin Hilman 543d7814e4dSKevin Hilman if (!seconds) 544d7814e4dSKevin Hilman return; 545d7814e4dSKevin Hilman 546d7814e4dSKevin Hilman tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup)); 547d7814e4dSKevin Hilman cycles = tick_rate * seconds; 548d7814e4dSKevin Hilman omap_dm_timer_stop(gptimer_wakeup); 549d7814e4dSKevin Hilman omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles); 550d7814e4dSKevin Hilman 551d7814e4dSKevin Hilman pr_info("PM: Resume timer in %d secs (%d ticks at %d ticks/sec.)\n", 552d7814e4dSKevin Hilman seconds, cycles, tick_rate); 553d7814e4dSKevin Hilman } 554d7814e4dSKevin Hilman 5558bd22949SKevin Hilman static int omap3_pm_prepare(void) 5568bd22949SKevin Hilman { 5578bd22949SKevin Hilman disable_hlt(); 5588bd22949SKevin Hilman return 0; 5598bd22949SKevin Hilman } 5608bd22949SKevin Hilman 5618bd22949SKevin Hilman static int omap3_pm_suspend(void) 5628bd22949SKevin Hilman { 5638bd22949SKevin Hilman struct power_state *pwrst; 5648bd22949SKevin Hilman int state, ret = 0; 5658bd22949SKevin Hilman 566d7814e4dSKevin Hilman if (wakeup_timer_seconds) 567d7814e4dSKevin Hilman omap2_pm_wakeup_on_timer(wakeup_timer_seconds); 568d7814e4dSKevin Hilman 5698bd22949SKevin Hilman /* Read current next_pwrsts */ 5708bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) 5718bd22949SKevin Hilman pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 5728bd22949SKevin Hilman /* Set ones wanted by suspend */ 5738bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 5748bd22949SKevin Hilman if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) 5758bd22949SKevin Hilman goto restore; 5768bd22949SKevin Hilman if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) 5778bd22949SKevin Hilman goto restore; 5788bd22949SKevin Hilman } 5798bd22949SKevin Hilman 5804af4016cSKevin Hilman omap_uart_prepare_suspend(); 5812bbe3af3STero Kristo omap3_intc_suspend(); 5822bbe3af3STero Kristo 5838bd22949SKevin Hilman omap_sram_idle(); 5848bd22949SKevin Hilman 5858bd22949SKevin Hilman restore: 5868bd22949SKevin Hilman /* Restore next_pwrsts */ 5878bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 5888bd22949SKevin Hilman state = pwrdm_read_prev_pwrst(pwrst->pwrdm); 5898bd22949SKevin Hilman if (state > pwrst->next_state) { 5908bd22949SKevin Hilman printk(KERN_INFO "Powerdomain (%s) didn't enter " 5918bd22949SKevin Hilman "target state %d\n", 5928bd22949SKevin Hilman pwrst->pwrdm->name, pwrst->next_state); 5938bd22949SKevin Hilman ret = -1; 5948bd22949SKevin Hilman } 5956c5f8039SJouni Hogander set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); 5968bd22949SKevin Hilman } 5978bd22949SKevin Hilman if (ret) 5988bd22949SKevin Hilman printk(KERN_ERR "Could not enter target state in pm_suspend\n"); 5998bd22949SKevin Hilman else 6008bd22949SKevin Hilman printk(KERN_INFO "Successfully put all powerdomains " 6018bd22949SKevin Hilman "to target state\n"); 6028bd22949SKevin Hilman 6038bd22949SKevin Hilman return ret; 6048bd22949SKevin Hilman } 6058bd22949SKevin Hilman 6062466211eSTero Kristo static int omap3_pm_enter(suspend_state_t unused) 6078bd22949SKevin Hilman { 6088bd22949SKevin Hilman int ret = 0; 6098bd22949SKevin Hilman 6102466211eSTero Kristo switch (suspend_state) { 6118bd22949SKevin Hilman case PM_SUSPEND_STANDBY: 6128bd22949SKevin Hilman case PM_SUSPEND_MEM: 6138bd22949SKevin Hilman ret = omap3_pm_suspend(); 6148bd22949SKevin Hilman break; 6158bd22949SKevin Hilman default: 6168bd22949SKevin Hilman ret = -EINVAL; 6178bd22949SKevin Hilman } 6188bd22949SKevin Hilman 6198bd22949SKevin Hilman return ret; 6208bd22949SKevin Hilman } 6218bd22949SKevin Hilman 6228bd22949SKevin Hilman static void omap3_pm_finish(void) 6238bd22949SKevin Hilman { 6248bd22949SKevin Hilman enable_hlt(); 6258bd22949SKevin Hilman } 6268bd22949SKevin Hilman 6272466211eSTero Kristo /* Hooks to enable / disable UART interrupts during suspend */ 6282466211eSTero Kristo static int omap3_pm_begin(suspend_state_t state) 6292466211eSTero Kristo { 6302466211eSTero Kristo suspend_state = state; 6312466211eSTero Kristo omap_uart_enable_irqs(0); 6322466211eSTero Kristo return 0; 6332466211eSTero Kristo } 6342466211eSTero Kristo 6352466211eSTero Kristo static void omap3_pm_end(void) 6362466211eSTero Kristo { 6372466211eSTero Kristo suspend_state = PM_SUSPEND_ON; 6382466211eSTero Kristo omap_uart_enable_irqs(1); 6392466211eSTero Kristo return; 6402466211eSTero Kristo } 6412466211eSTero Kristo 6428bd22949SKevin Hilman static struct platform_suspend_ops omap_pm_ops = { 6432466211eSTero Kristo .begin = omap3_pm_begin, 6442466211eSTero Kristo .end = omap3_pm_end, 6458bd22949SKevin Hilman .prepare = omap3_pm_prepare, 6468bd22949SKevin Hilman .enter = omap3_pm_enter, 6478bd22949SKevin Hilman .finish = omap3_pm_finish, 6488bd22949SKevin Hilman .valid = suspend_valid_only_mem, 6498bd22949SKevin Hilman }; 65010f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 6518bd22949SKevin Hilman 6521155e426SKevin Hilman 6531155e426SKevin Hilman /** 6541155e426SKevin Hilman * omap3_iva_idle(): ensure IVA is in idle so it can be put into 6551155e426SKevin Hilman * retention 6561155e426SKevin Hilman * 6571155e426SKevin Hilman * In cases where IVA2 is activated by bootcode, it may prevent 6581155e426SKevin Hilman * full-chip retention or off-mode because it is not idle. This 6591155e426SKevin Hilman * function forces the IVA2 into idle state so it can go 6601155e426SKevin Hilman * into retention/off and thus allow full-chip retention/off. 6611155e426SKevin Hilman * 6621155e426SKevin Hilman **/ 6631155e426SKevin Hilman static void __init omap3_iva_idle(void) 6641155e426SKevin Hilman { 6651155e426SKevin Hilman /* ensure IVA2 clock is disabled */ 6661155e426SKevin Hilman cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 6671155e426SKevin Hilman 6681155e426SKevin Hilman /* if no clock activity, nothing else to do */ 6691155e426SKevin Hilman if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & 6701155e426SKevin Hilman OMAP3430_CLKACTIVITY_IVA2_MASK)) 6711155e426SKevin Hilman return; 6721155e426SKevin Hilman 6731155e426SKevin Hilman /* Reset IVA2 */ 6741155e426SKevin Hilman prm_write_mod_reg(OMAP3430_RST1_IVA2 | 6751155e426SKevin Hilman OMAP3430_RST2_IVA2 | 6761155e426SKevin Hilman OMAP3430_RST3_IVA2, 6771155e426SKevin Hilman OMAP3430_IVA2_MOD, RM_RSTCTRL); 6781155e426SKevin Hilman 6791155e426SKevin Hilman /* Enable IVA2 clock */ 6801155e426SKevin Hilman cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2, 6811155e426SKevin Hilman OMAP3430_IVA2_MOD, CM_FCLKEN); 6821155e426SKevin Hilman 6831155e426SKevin Hilman /* Set IVA2 boot mode to 'idle' */ 6841155e426SKevin Hilman omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, 6851155e426SKevin Hilman OMAP343X_CONTROL_IVA2_BOOTMOD); 6861155e426SKevin Hilman 6871155e426SKevin Hilman /* Un-reset IVA2 */ 6881155e426SKevin Hilman prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL); 6891155e426SKevin Hilman 6901155e426SKevin Hilman /* Disable IVA2 clock */ 6911155e426SKevin Hilman cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 6921155e426SKevin Hilman 6931155e426SKevin Hilman /* Reset IVA2 */ 6941155e426SKevin Hilman prm_write_mod_reg(OMAP3430_RST1_IVA2 | 6951155e426SKevin Hilman OMAP3430_RST2_IVA2 | 6961155e426SKevin Hilman OMAP3430_RST3_IVA2, 6971155e426SKevin Hilman OMAP3430_IVA2_MOD, RM_RSTCTRL); 6981155e426SKevin Hilman } 6991155e426SKevin Hilman 7008111b221SKevin Hilman static void __init omap3_d2d_idle(void) 7018bd22949SKevin Hilman { 7028111b221SKevin Hilman u16 mask, padconf; 7038111b221SKevin Hilman 7048111b221SKevin Hilman /* In a stand alone OMAP3430 where there is not a stacked 7058111b221SKevin Hilman * modem for the D2D Idle Ack and D2D MStandby must be pulled 7068111b221SKevin Hilman * high. S CONTROL_PADCONF_SAD2D_IDLEACK and 7078111b221SKevin Hilman * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ 7088111b221SKevin Hilman mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ 7098111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); 7108111b221SKevin Hilman padconf |= mask; 7118111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); 7128111b221SKevin Hilman 7138111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); 7148111b221SKevin Hilman padconf |= mask; 7158111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 7168111b221SKevin Hilman 7178bd22949SKevin Hilman /* reset modem */ 7188bd22949SKevin Hilman prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON | 7198bd22949SKevin Hilman OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST, 7208bd22949SKevin Hilman CORE_MOD, RM_RSTCTRL); 7218bd22949SKevin Hilman prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL); 7228111b221SKevin Hilman } 7238bd22949SKevin Hilman 7248111b221SKevin Hilman static void __init prcm_setup_regs(void) 7258111b221SKevin Hilman { 7268bd22949SKevin Hilman /* XXX Reset all wkdeps. This should be done when initializing 7278bd22949SKevin Hilman * powerdomains */ 7288bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); 7298bd22949SKevin Hilman prm_write_mod_reg(0, MPU_MOD, PM_WKDEP); 7308bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP); 7318bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP); 7328bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP); 7338bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP); 7348bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 7358bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP); 7368bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP); 7378bd22949SKevin Hilman } else 7388bd22949SKevin Hilman prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); 7398bd22949SKevin Hilman 7408bd22949SKevin Hilman /* 7418bd22949SKevin Hilman * Enable interface clock autoidle for all modules. 7428bd22949SKevin Hilman * Note that in the long run this should be done by clockfw 7438bd22949SKevin Hilman */ 7448bd22949SKevin Hilman cm_write_mod_reg( 7458111b221SKevin Hilman OMAP3430_AUTO_MODEM | 7468bd22949SKevin Hilman OMAP3430ES2_AUTO_MMC3 | 7478bd22949SKevin Hilman OMAP3430ES2_AUTO_ICR | 7488bd22949SKevin Hilman OMAP3430_AUTO_AES2 | 7498bd22949SKevin Hilman OMAP3430_AUTO_SHA12 | 7508bd22949SKevin Hilman OMAP3430_AUTO_DES2 | 7518bd22949SKevin Hilman OMAP3430_AUTO_MMC2 | 7528bd22949SKevin Hilman OMAP3430_AUTO_MMC1 | 7538bd22949SKevin Hilman OMAP3430_AUTO_MSPRO | 7548bd22949SKevin Hilman OMAP3430_AUTO_HDQ | 7558bd22949SKevin Hilman OMAP3430_AUTO_MCSPI4 | 7568bd22949SKevin Hilman OMAP3430_AUTO_MCSPI3 | 7578bd22949SKevin Hilman OMAP3430_AUTO_MCSPI2 | 7588bd22949SKevin Hilman OMAP3430_AUTO_MCSPI1 | 7598bd22949SKevin Hilman OMAP3430_AUTO_I2C3 | 7608bd22949SKevin Hilman OMAP3430_AUTO_I2C2 | 7618bd22949SKevin Hilman OMAP3430_AUTO_I2C1 | 7628bd22949SKevin Hilman OMAP3430_AUTO_UART2 | 7638bd22949SKevin Hilman OMAP3430_AUTO_UART1 | 7648bd22949SKevin Hilman OMAP3430_AUTO_GPT11 | 7658bd22949SKevin Hilman OMAP3430_AUTO_GPT10 | 7668bd22949SKevin Hilman OMAP3430_AUTO_MCBSP5 | 7678bd22949SKevin Hilman OMAP3430_AUTO_MCBSP1 | 7688bd22949SKevin Hilman OMAP3430ES1_AUTO_FAC | /* This is es1 only */ 7698bd22949SKevin Hilman OMAP3430_AUTO_MAILBOXES | 7708bd22949SKevin Hilman OMAP3430_AUTO_OMAPCTRL | 7718bd22949SKevin Hilman OMAP3430ES1_AUTO_FSHOSTUSB | 7728bd22949SKevin Hilman OMAP3430_AUTO_HSOTGUSB | 7738111b221SKevin Hilman OMAP3430_AUTO_SAD2D | 7748bd22949SKevin Hilman OMAP3430_AUTO_SSI, 7758bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE1); 7768bd22949SKevin Hilman 7778bd22949SKevin Hilman cm_write_mod_reg( 7788bd22949SKevin Hilman OMAP3430_AUTO_PKA | 7798bd22949SKevin Hilman OMAP3430_AUTO_AES1 | 7808bd22949SKevin Hilman OMAP3430_AUTO_RNG | 7818bd22949SKevin Hilman OMAP3430_AUTO_SHA11 | 7828bd22949SKevin Hilman OMAP3430_AUTO_DES1, 7838bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE2); 7848bd22949SKevin Hilman 7858bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 7868bd22949SKevin Hilman cm_write_mod_reg( 7878111b221SKevin Hilman OMAP3430_AUTO_MAD2D | 7888bd22949SKevin Hilman OMAP3430ES2_AUTO_USBTLL, 7898bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE3); 7908bd22949SKevin Hilman } 7918bd22949SKevin Hilman 7928bd22949SKevin Hilman cm_write_mod_reg( 7938bd22949SKevin Hilman OMAP3430_AUTO_WDT2 | 7948bd22949SKevin Hilman OMAP3430_AUTO_WDT1 | 7958bd22949SKevin Hilman OMAP3430_AUTO_GPIO1 | 7968bd22949SKevin Hilman OMAP3430_AUTO_32KSYNC | 7978bd22949SKevin Hilman OMAP3430_AUTO_GPT12 | 7988bd22949SKevin Hilman OMAP3430_AUTO_GPT1 , 7998bd22949SKevin Hilman WKUP_MOD, CM_AUTOIDLE); 8008bd22949SKevin Hilman 8018bd22949SKevin Hilman cm_write_mod_reg( 8028bd22949SKevin Hilman OMAP3430_AUTO_DSS, 8038bd22949SKevin Hilman OMAP3430_DSS_MOD, 8048bd22949SKevin Hilman CM_AUTOIDLE); 8058bd22949SKevin Hilman 8068bd22949SKevin Hilman cm_write_mod_reg( 8078bd22949SKevin Hilman OMAP3430_AUTO_CAM, 8088bd22949SKevin Hilman OMAP3430_CAM_MOD, 8098bd22949SKevin Hilman CM_AUTOIDLE); 8108bd22949SKevin Hilman 8118bd22949SKevin Hilman cm_write_mod_reg( 8128bd22949SKevin Hilman OMAP3430_AUTO_GPIO6 | 8138bd22949SKevin Hilman OMAP3430_AUTO_GPIO5 | 8148bd22949SKevin Hilman OMAP3430_AUTO_GPIO4 | 8158bd22949SKevin Hilman OMAP3430_AUTO_GPIO3 | 8168bd22949SKevin Hilman OMAP3430_AUTO_GPIO2 | 8178bd22949SKevin Hilman OMAP3430_AUTO_WDT3 | 8188bd22949SKevin Hilman OMAP3430_AUTO_UART3 | 8198bd22949SKevin Hilman OMAP3430_AUTO_GPT9 | 8208bd22949SKevin Hilman OMAP3430_AUTO_GPT8 | 8218bd22949SKevin Hilman OMAP3430_AUTO_GPT7 | 8228bd22949SKevin Hilman OMAP3430_AUTO_GPT6 | 8238bd22949SKevin Hilman OMAP3430_AUTO_GPT5 | 8248bd22949SKevin Hilman OMAP3430_AUTO_GPT4 | 8258bd22949SKevin Hilman OMAP3430_AUTO_GPT3 | 8268bd22949SKevin Hilman OMAP3430_AUTO_GPT2 | 8278bd22949SKevin Hilman OMAP3430_AUTO_MCBSP4 | 8288bd22949SKevin Hilman OMAP3430_AUTO_MCBSP3 | 8298bd22949SKevin Hilman OMAP3430_AUTO_MCBSP2, 8308bd22949SKevin Hilman OMAP3430_PER_MOD, 8318bd22949SKevin Hilman CM_AUTOIDLE); 8328bd22949SKevin Hilman 8338bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 8348bd22949SKevin Hilman cm_write_mod_reg( 8358bd22949SKevin Hilman OMAP3430ES2_AUTO_USBHOST, 8368bd22949SKevin Hilman OMAP3430ES2_USBHOST_MOD, 8378bd22949SKevin Hilman CM_AUTOIDLE); 8388bd22949SKevin Hilman } 8398bd22949SKevin Hilman 8408bd22949SKevin Hilman /* 8418bd22949SKevin Hilman * Set all plls to autoidle. This is needed until autoidle is 8428bd22949SKevin Hilman * enabled by clockfw 8438bd22949SKevin Hilman */ 8448bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, 8458bd22949SKevin Hilman OMAP3430_IVA2_MOD, CM_AUTOIDLE2); 8468bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT, 8478bd22949SKevin Hilman MPU_MOD, 8488bd22949SKevin Hilman CM_AUTOIDLE2); 8498bd22949SKevin Hilman cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | 8508bd22949SKevin Hilman (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT), 8518bd22949SKevin Hilman PLL_MOD, 8528bd22949SKevin Hilman CM_AUTOIDLE); 8538bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, 8548bd22949SKevin Hilman PLL_MOD, 8558bd22949SKevin Hilman CM_AUTOIDLE2); 8568bd22949SKevin Hilman 8578bd22949SKevin Hilman /* 8588bd22949SKevin Hilman * Enable control of expternal oscillator through 8598bd22949SKevin Hilman * sys_clkreq. In the long run clock framework should 8608bd22949SKevin Hilman * take care of this. 8618bd22949SKevin Hilman */ 8628bd22949SKevin Hilman prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 8638bd22949SKevin Hilman 1 << OMAP_AUTOEXTCLKMODE_SHIFT, 8648bd22949SKevin Hilman OMAP3430_GR_MOD, 8658bd22949SKevin Hilman OMAP3_PRM_CLKSRC_CTRL_OFFSET); 8668bd22949SKevin Hilman 8678bd22949SKevin Hilman /* setup wakup source */ 8688bd22949SKevin Hilman prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 | 8698bd22949SKevin Hilman OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12, 8708bd22949SKevin Hilman WKUP_MOD, PM_WKEN); 8718bd22949SKevin Hilman /* No need to write EN_IO, that is always enabled */ 8728bd22949SKevin Hilman prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 | 8738bd22949SKevin Hilman OMAP3430_EN_GPT12, 8748bd22949SKevin Hilman WKUP_MOD, OMAP3430_PM_MPUGRPSEL); 8758bd22949SKevin Hilman /* For some reason IO doesn't generate wakeup event even if 8768bd22949SKevin Hilman * it is selected to mpu wakeup goup */ 8778bd22949SKevin Hilman prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN, 8788bd22949SKevin Hilman OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); 8791155e426SKevin Hilman 880b427f92fSKevin Hilman /* Enable wakeups in PER */ 881eb350f74SKevin Hilman prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 | 882eb350f74SKevin Hilman OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 | 883b427f92fSKevin Hilman OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3, 884b427f92fSKevin Hilman OMAP3430_PER_MOD, PM_WKEN); 885eb350f74SKevin Hilman /* and allow them to wake up MPU */ 886eb350f74SKevin Hilman prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 | 887eb350f74SKevin Hilman OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 | 888b427f92fSKevin Hilman OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3, 889eb350f74SKevin Hilman OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); 890eb350f74SKevin Hilman 891d3fd3290SKevin Hilman /* Don't attach IVA interrupts */ 892d3fd3290SKevin Hilman prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 893d3fd3290SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 894d3fd3290SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 895d3fd3290SKevin Hilman prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); 896d3fd3290SKevin Hilman 897b1340d17SKevin Hilman /* Clear any pending 'reset' flags */ 898b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST); 899b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST); 900b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST); 901b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST); 902b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST); 903b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST); 904b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST); 905b1340d17SKevin Hilman 906014c46dbSKevin Hilman /* Clear any pending PRCM interrupts */ 907014c46dbSKevin Hilman prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 908014c46dbSKevin Hilman 909040fed05SKevin Hilman /* Don't attach IVA interrupts */ 910040fed05SKevin Hilman prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 911040fed05SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 912040fed05SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 913040fed05SKevin Hilman prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); 914040fed05SKevin Hilman 9153a07ae30SKevin Hilman /* Clear any pending 'reset' flags */ 9163a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST); 9173a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST); 9183a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST); 9193a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST); 9203a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST); 9213a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST); 9223a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST); 9233a07ae30SKevin Hilman 9243a6667acSKevin Hilman /* Clear any pending PRCM interrupts */ 9253a6667acSKevin Hilman prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 9263a6667acSKevin Hilman 9271155e426SKevin Hilman omap3_iva_idle(); 9288111b221SKevin Hilman omap3_d2d_idle(); 9298bd22949SKevin Hilman } 9308bd22949SKevin Hilman 931c40552bcSKevin Hilman void omap3_pm_off_mode_enable(int enable) 932c40552bcSKevin Hilman { 933c40552bcSKevin Hilman struct power_state *pwrst; 934c40552bcSKevin Hilman u32 state; 935c40552bcSKevin Hilman 936c40552bcSKevin Hilman if (enable) 937c40552bcSKevin Hilman state = PWRDM_POWER_OFF; 938c40552bcSKevin Hilman else 939c40552bcSKevin Hilman state = PWRDM_POWER_RET; 940c40552bcSKevin Hilman 941c40552bcSKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 942c40552bcSKevin Hilman pwrst->next_state = state; 943c40552bcSKevin Hilman set_pwrdm_state(pwrst->pwrdm, state); 944c40552bcSKevin Hilman } 945c40552bcSKevin Hilman } 946c40552bcSKevin Hilman 94768d4778cSTero Kristo int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) 94868d4778cSTero Kristo { 94968d4778cSTero Kristo struct power_state *pwrst; 95068d4778cSTero Kristo 95168d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 95268d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) 95368d4778cSTero Kristo return pwrst->next_state; 95468d4778cSTero Kristo } 95568d4778cSTero Kristo return -EINVAL; 95668d4778cSTero Kristo } 95768d4778cSTero Kristo 95868d4778cSTero Kristo int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) 95968d4778cSTero Kristo { 96068d4778cSTero Kristo struct power_state *pwrst; 96168d4778cSTero Kristo 96268d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 96368d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) { 96468d4778cSTero Kristo pwrst->next_state = state; 96568d4778cSTero Kristo return 0; 96668d4778cSTero Kristo } 96768d4778cSTero Kristo } 96868d4778cSTero Kristo return -EINVAL; 96968d4778cSTero Kristo } 97068d4778cSTero Kristo 971a23456e9SPeter 'p2' De Schrijver static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) 9728bd22949SKevin Hilman { 9738bd22949SKevin Hilman struct power_state *pwrst; 9748bd22949SKevin Hilman 9758bd22949SKevin Hilman if (!pwrdm->pwrsts) 9768bd22949SKevin Hilman return 0; 9778bd22949SKevin Hilman 978d3d381c6SMing Lei pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); 9798bd22949SKevin Hilman if (!pwrst) 9808bd22949SKevin Hilman return -ENOMEM; 9818bd22949SKevin Hilman pwrst->pwrdm = pwrdm; 9828bd22949SKevin Hilman pwrst->next_state = PWRDM_POWER_RET; 9838bd22949SKevin Hilman list_add(&pwrst->node, &pwrst_list); 9848bd22949SKevin Hilman 9858bd22949SKevin Hilman if (pwrdm_has_hdwr_sar(pwrdm)) 9868bd22949SKevin Hilman pwrdm_enable_hdwr_sar(pwrdm); 9878bd22949SKevin Hilman 9888bd22949SKevin Hilman return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 9898bd22949SKevin Hilman } 9908bd22949SKevin Hilman 9918bd22949SKevin Hilman /* 9928bd22949SKevin Hilman * Enable hw supervised mode for all clockdomains if it's 9938bd22949SKevin Hilman * supported. Initiate sleep transition for other clockdomains, if 9948bd22949SKevin Hilman * they are not used 9958bd22949SKevin Hilman */ 996a23456e9SPeter 'p2' De Schrijver static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) 9978bd22949SKevin Hilman { 9988bd22949SKevin Hilman if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) 9998bd22949SKevin Hilman omap2_clkdm_allow_idle(clkdm); 10008bd22949SKevin Hilman else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && 10018bd22949SKevin Hilman atomic_read(&clkdm->usecount) == 0) 10028bd22949SKevin Hilman omap2_clkdm_sleep(clkdm); 10038bd22949SKevin Hilman return 0; 10048bd22949SKevin Hilman } 10058bd22949SKevin Hilman 10063231fc88SRajendra Nayak void omap_push_sram_idle(void) 10073231fc88SRajendra Nayak { 10083231fc88SRajendra Nayak _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend, 10093231fc88SRajendra Nayak omap34xx_cpu_suspend_sz); 101027d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) 101127d59a4aSTero Kristo _omap_save_secure_sram = omap_sram_push(save_secure_ram_context, 101227d59a4aSTero Kristo save_secure_ram_context_sz); 10133231fc88SRajendra Nayak } 10143231fc88SRajendra Nayak 10157cc515f7SKevin Hilman static int __init omap3_pm_init(void) 10168bd22949SKevin Hilman { 10178bd22949SKevin Hilman struct power_state *pwrst, *tmp; 10188bd22949SKevin Hilman int ret; 10198bd22949SKevin Hilman 10208bd22949SKevin Hilman if (!cpu_is_omap34xx()) 10218bd22949SKevin Hilman return -ENODEV; 10228bd22949SKevin Hilman 10238bd22949SKevin Hilman printk(KERN_ERR "Power Management for TI OMAP3.\n"); 10248bd22949SKevin Hilman 10258bd22949SKevin Hilman /* XXX prcm_setup_regs needs to be before enabling hw 10268bd22949SKevin Hilman * supervised mode for powerdomains */ 10278bd22949SKevin Hilman prcm_setup_regs(); 10288bd22949SKevin Hilman 10298bd22949SKevin Hilman ret = request_irq(INT_34XX_PRCM_MPU_IRQ, 10308bd22949SKevin Hilman (irq_handler_t)prcm_interrupt_handler, 10318bd22949SKevin Hilman IRQF_DISABLED, "prcm", NULL); 10328bd22949SKevin Hilman if (ret) { 10338bd22949SKevin Hilman printk(KERN_ERR "request_irq failed to register for 0x%x\n", 10348bd22949SKevin Hilman INT_34XX_PRCM_MPU_IRQ); 10358bd22949SKevin Hilman goto err1; 10368bd22949SKevin Hilman } 10378bd22949SKevin Hilman 1038a23456e9SPeter 'p2' De Schrijver ret = pwrdm_for_each(pwrdms_setup, NULL); 10398bd22949SKevin Hilman if (ret) { 10408bd22949SKevin Hilman printk(KERN_ERR "Failed to setup powerdomains\n"); 10418bd22949SKevin Hilman goto err2; 10428bd22949SKevin Hilman } 10438bd22949SKevin Hilman 1044a23456e9SPeter 'p2' De Schrijver (void) clkdm_for_each(clkdms_setup, NULL); 10458bd22949SKevin Hilman 10468bd22949SKevin Hilman mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); 10478bd22949SKevin Hilman if (mpu_pwrdm == NULL) { 10488bd22949SKevin Hilman printk(KERN_ERR "Failed to get mpu_pwrdm\n"); 10498bd22949SKevin Hilman goto err2; 10508bd22949SKevin Hilman } 10518bd22949SKevin Hilman 1052fa3c2a4fSRajendra Nayak neon_pwrdm = pwrdm_lookup("neon_pwrdm"); 1053fa3c2a4fSRajendra Nayak per_pwrdm = pwrdm_lookup("per_pwrdm"); 1054fa3c2a4fSRajendra Nayak core_pwrdm = pwrdm_lookup("core_pwrdm"); 1055c16c3f67STero Kristo cam_pwrdm = pwrdm_lookup("cam_pwrdm"); 1056fa3c2a4fSRajendra Nayak 10573231fc88SRajendra Nayak omap_push_sram_idle(); 105810f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 10598bd22949SKevin Hilman suspend_set_ops(&omap_pm_ops); 106010f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 10618bd22949SKevin Hilman 10628bd22949SKevin Hilman pm_idle = omap3_pm_idle; 10630343371eSKalle Jokiniemi omap3_idle_init(); 10648bd22949SKevin Hilman 1065fa3c2a4fSRajendra Nayak pwrdm_add_wkdep(neon_pwrdm, mpu_pwrdm); 1066fa3c2a4fSRajendra Nayak /* 1067fa3c2a4fSRajendra Nayak * REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for 1068fa3c2a4fSRajendra Nayak * IO-pad wakeup. Otherwise it will unnecessarily waste power 1069fa3c2a4fSRajendra Nayak * waking up PER with every CORE wakeup - see 1070fa3c2a4fSRajendra Nayak * http://marc.info/?l=linux-omap&m=121852150710062&w=2 1071fa3c2a4fSRajendra Nayak */ 1072fa3c2a4fSRajendra Nayak pwrdm_add_wkdep(per_pwrdm, core_pwrdm); 1073fa3c2a4fSRajendra Nayak 107427d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 107527d59a4aSTero Kristo omap3_secure_ram_storage = 107627d59a4aSTero Kristo kmalloc(0x803F, GFP_KERNEL); 107727d59a4aSTero Kristo if (!omap3_secure_ram_storage) 107827d59a4aSTero Kristo printk(KERN_ERR "Memory allocation failed when" 107927d59a4aSTero Kristo "allocating for secure sram context\n"); 108027d59a4aSTero Kristo 10819d97140bSTero Kristo local_irq_disable(); 10829d97140bSTero Kristo local_fiq_disable(); 10839d97140bSTero Kristo 10849d97140bSTero Kristo omap_dma_global_context_save(); 10859d97140bSTero Kristo omap3_save_secure_ram_context(PWRDM_POWER_ON); 10869d97140bSTero Kristo omap_dma_global_context_restore(); 10879d97140bSTero Kristo 10889d97140bSTero Kristo local_irq_enable(); 10899d97140bSTero Kristo local_fiq_enable(); 10909d97140bSTero Kristo } 10919d97140bSTero Kristo 10929d97140bSTero Kristo omap3_save_scratchpad_contents(); 10938bd22949SKevin Hilman err1: 10948bd22949SKevin Hilman return ret; 10958bd22949SKevin Hilman err2: 10968bd22949SKevin Hilman free_irq(INT_34XX_PRCM_MPU_IRQ, NULL); 10978bd22949SKevin Hilman list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { 10988bd22949SKevin Hilman list_del(&pwrst->node); 10998bd22949SKevin Hilman kfree(pwrst); 11008bd22949SKevin Hilman } 11018bd22949SKevin Hilman return ret; 11028bd22949SKevin Hilman } 11038bd22949SKevin Hilman 11048bd22949SKevin Hilman late_initcall(omap3_pm_init); 1105