18bd22949SKevin Hilman /* 28bd22949SKevin Hilman * OMAP3 Power Management Routines 38bd22949SKevin Hilman * 48bd22949SKevin Hilman * Copyright (C) 2006-2008 Nokia Corporation 58bd22949SKevin Hilman * Tony Lindgren <tony@atomide.com> 68bd22949SKevin Hilman * Jouni Hogander 78bd22949SKevin Hilman * 82f5939c3SRajendra Nayak * Copyright (C) 2007 Texas Instruments, Inc. 92f5939c3SRajendra Nayak * Rajendra Nayak <rnayak@ti.com> 102f5939c3SRajendra Nayak * 118bd22949SKevin Hilman * Copyright (C) 2005 Texas Instruments, Inc. 128bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 138bd22949SKevin Hilman * 148bd22949SKevin Hilman * Based on pm.c for omap1 158bd22949SKevin Hilman * 168bd22949SKevin Hilman * This program is free software; you can redistribute it and/or modify 178bd22949SKevin Hilman * it under the terms of the GNU General Public License version 2 as 188bd22949SKevin Hilman * published by the Free Software Foundation. 198bd22949SKevin Hilman */ 208bd22949SKevin Hilman 218bd22949SKevin Hilman #include <linux/pm.h> 228bd22949SKevin Hilman #include <linux/suspend.h> 238bd22949SKevin Hilman #include <linux/interrupt.h> 248bd22949SKevin Hilman #include <linux/module.h> 258bd22949SKevin Hilman #include <linux/list.h> 268bd22949SKevin Hilman #include <linux/err.h> 278bd22949SKevin Hilman #include <linux/gpio.h> 288bd22949SKevin Hilman 29ce491cf8STony Lindgren #include <plat/sram.h> 30ce491cf8STony Lindgren #include <plat/clockdomain.h> 31ce491cf8STony Lindgren #include <plat/powerdomain.h> 32ce491cf8STony Lindgren #include <plat/control.h> 33ce491cf8STony Lindgren #include <plat/serial.h> 3461255ab9SRajendra Nayak #include <plat/sdrc.h> 352f5939c3SRajendra Nayak #include <plat/prcm.h> 362f5939c3SRajendra Nayak #include <plat/gpmc.h> 37f2d11858STero Kristo #include <plat/dma.h> 388bd22949SKevin Hilman 3957f277b0SRajendra Nayak #include <asm/tlbflush.h> 4057f277b0SRajendra Nayak 418bd22949SKevin Hilman #include "cm.h" 428bd22949SKevin Hilman #include "cm-regbits-34xx.h" 438bd22949SKevin Hilman #include "prm-regbits-34xx.h" 448bd22949SKevin Hilman 458bd22949SKevin Hilman #include "prm.h" 468bd22949SKevin Hilman #include "pm.h" 478bd22949SKevin Hilman 482f5939c3SRajendra Nayak /* Scratchpad offsets */ 492f5939c3SRajendra Nayak #define OMAP343X_TABLE_ADDRESS_OFFSET 0x31 502f5939c3SRajendra Nayak #define OMAP343X_TABLE_VALUE_OFFSET 0x30 512f5939c3SRajendra Nayak #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32 522f5939c3SRajendra Nayak 538bd22949SKevin Hilman struct power_state { 548bd22949SKevin Hilman struct powerdomain *pwrdm; 558bd22949SKevin Hilman u32 next_state; 5610f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 578bd22949SKevin Hilman u32 saved_state; 5810f90ed2SKevin Hilman #endif 598bd22949SKevin Hilman struct list_head node; 608bd22949SKevin Hilman }; 618bd22949SKevin Hilman 628bd22949SKevin Hilman static LIST_HEAD(pwrst_list); 638bd22949SKevin Hilman 648bd22949SKevin Hilman static void (*_omap_sram_idle)(u32 *addr, int save_state); 658bd22949SKevin Hilman 6627d59a4aSTero Kristo static int (*_omap_save_secure_sram)(u32 *addr); 6727d59a4aSTero Kristo 68fa3c2a4fSRajendra Nayak static struct powerdomain *mpu_pwrdm, *neon_pwrdm; 69fa3c2a4fSRajendra Nayak static struct powerdomain *core_pwrdm, *per_pwrdm; 70fa3c2a4fSRajendra Nayak 71fa3c2a4fSRajendra Nayak static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state); 728bd22949SKevin Hilman 732f5939c3SRajendra Nayak static inline void omap3_per_save_context(void) 742f5939c3SRajendra Nayak { 752f5939c3SRajendra Nayak omap_gpio_save_context(); 762f5939c3SRajendra Nayak } 772f5939c3SRajendra Nayak 782f5939c3SRajendra Nayak static inline void omap3_per_restore_context(void) 792f5939c3SRajendra Nayak { 802f5939c3SRajendra Nayak omap_gpio_restore_context(); 812f5939c3SRajendra Nayak } 822f5939c3SRajendra Nayak 832f5939c3SRajendra Nayak static void omap3_core_save_context(void) 842f5939c3SRajendra Nayak { 852f5939c3SRajendra Nayak u32 control_padconf_off; 862f5939c3SRajendra Nayak 872f5939c3SRajendra Nayak /* Save the padconf registers */ 882f5939c3SRajendra Nayak control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF); 892f5939c3SRajendra Nayak control_padconf_off |= START_PADCONF_SAVE; 902f5939c3SRajendra Nayak omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF); 912f5939c3SRajendra Nayak /* wait for the save to complete */ 922f5939c3SRajendra Nayak while (!omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) 932f5939c3SRajendra Nayak & PADCONF_SAVE_DONE) 942f5939c3SRajendra Nayak ; 952f5939c3SRajendra Nayak /* Save the Interrupt controller context */ 962f5939c3SRajendra Nayak omap_intc_save_context(); 972f5939c3SRajendra Nayak /* Save the GPMC context */ 982f5939c3SRajendra Nayak omap3_gpmc_save_context(); 992f5939c3SRajendra Nayak /* Save the system control module context, padconf already save above*/ 1002f5939c3SRajendra Nayak omap3_control_save_context(); 101f2d11858STero Kristo omap_dma_global_context_save(); 1022f5939c3SRajendra Nayak } 1032f5939c3SRajendra Nayak 1042f5939c3SRajendra Nayak static void omap3_core_restore_context(void) 1052f5939c3SRajendra Nayak { 1062f5939c3SRajendra Nayak /* Restore the control module context, padconf restored by h/w */ 1072f5939c3SRajendra Nayak omap3_control_restore_context(); 1082f5939c3SRajendra Nayak /* Restore the GPMC context */ 1092f5939c3SRajendra Nayak omap3_gpmc_restore_context(); 1102f5939c3SRajendra Nayak /* Restore the interrupt controller context */ 1112f5939c3SRajendra Nayak omap_intc_restore_context(); 112f2d11858STero Kristo omap_dma_global_context_restore(); 1132f5939c3SRajendra Nayak } 1142f5939c3SRajendra Nayak 11527d59a4aSTero Kristo static void omap3_save_secure_ram_context(u32 target_mpu_state) 11627d59a4aSTero Kristo { 11727d59a4aSTero Kristo u32 ret; 11827d59a4aSTero Kristo 11927d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 12027d59a4aSTero Kristo /* Disable dma irq before calling secure rom code API */ 12127d59a4aSTero Kristo omap_dma_disable_irq(0); 12227d59a4aSTero Kristo omap_dma_disable_irq(1); 12327d59a4aSTero Kristo /* 12427d59a4aSTero Kristo * MPU next state must be set to POWER_ON temporarily, 12527d59a4aSTero Kristo * otherwise the WFI executed inside the ROM code 12627d59a4aSTero Kristo * will hang the system. 12727d59a4aSTero Kristo */ 12827d59a4aSTero Kristo pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); 12927d59a4aSTero Kristo ret = _omap_save_secure_sram((u32 *) 13027d59a4aSTero Kristo __pa(omap3_secure_ram_storage)); 13127d59a4aSTero Kristo pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state); 13227d59a4aSTero Kristo /* Following is for error tracking, it should not happen */ 13327d59a4aSTero Kristo if (ret) { 13427d59a4aSTero Kristo printk(KERN_ERR "save_secure_sram() returns %08x\n", 13527d59a4aSTero Kristo ret); 13627d59a4aSTero Kristo while (1) 13727d59a4aSTero Kristo ; 13827d59a4aSTero Kristo } 13927d59a4aSTero Kristo } 14027d59a4aSTero Kristo } 14127d59a4aSTero Kristo 14277da2d91SJon Hunter /* 14377da2d91SJon Hunter * PRCM Interrupt Handler Helper Function 14477da2d91SJon Hunter * 14577da2d91SJon Hunter * The purpose of this function is to clear any wake-up events latched 14677da2d91SJon Hunter * in the PRCM PM_WKST_x registers. It is possible that a wake-up event 14777da2d91SJon Hunter * may occur whilst attempting to clear a PM_WKST_x register and thus 14877da2d91SJon Hunter * set another bit in this register. A while loop is used to ensure 14977da2d91SJon Hunter * that any peripheral wake-up events occurring while attempting to 15077da2d91SJon Hunter * clear the PM_WKST_x are detected and cleared. 15177da2d91SJon Hunter */ 1528cb0ac99SPaul Walmsley static int prcm_clear_mod_irqs(s16 module, u8 regs) 15377da2d91SJon Hunter { 15471a80775SVikram Pandita u32 wkst, fclk, iclk, clken; 15577da2d91SJon Hunter u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; 15677da2d91SJon Hunter u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; 15777da2d91SJon Hunter u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; 1585d805978SPaul Walmsley u16 grpsel_off = (regs == 3) ? 1595d805978SPaul Walmsley OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; 1608cb0ac99SPaul Walmsley int c = 0; 16177da2d91SJon Hunter 16277da2d91SJon Hunter wkst = prm_read_mod_reg(module, wkst_off); 1635d805978SPaul Walmsley wkst &= prm_read_mod_reg(module, grpsel_off); 16477da2d91SJon Hunter if (wkst) { 16577da2d91SJon Hunter iclk = cm_read_mod_reg(module, iclk_off); 16677da2d91SJon Hunter fclk = cm_read_mod_reg(module, fclk_off); 16777da2d91SJon Hunter while (wkst) { 16871a80775SVikram Pandita clken = wkst; 16971a80775SVikram Pandita cm_set_mod_reg_bits(clken, module, iclk_off); 17071a80775SVikram Pandita /* 17171a80775SVikram Pandita * For USBHOST, we don't know whether HOST1 or 17271a80775SVikram Pandita * HOST2 woke us up, so enable both f-clocks 17371a80775SVikram Pandita */ 17471a80775SVikram Pandita if (module == OMAP3430ES2_USBHOST_MOD) 17571a80775SVikram Pandita clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; 17671a80775SVikram Pandita cm_set_mod_reg_bits(clken, module, fclk_off); 17777da2d91SJon Hunter prm_write_mod_reg(wkst, module, wkst_off); 17877da2d91SJon Hunter wkst = prm_read_mod_reg(module, wkst_off); 1798cb0ac99SPaul Walmsley c++; 18077da2d91SJon Hunter } 18177da2d91SJon Hunter cm_write_mod_reg(iclk, module, iclk_off); 18277da2d91SJon Hunter cm_write_mod_reg(fclk, module, fclk_off); 18377da2d91SJon Hunter } 1848cb0ac99SPaul Walmsley 1858cb0ac99SPaul Walmsley return c; 1868cb0ac99SPaul Walmsley } 1878cb0ac99SPaul Walmsley 1888cb0ac99SPaul Walmsley static int _prcm_int_handle_wakeup(void) 1898cb0ac99SPaul Walmsley { 1908cb0ac99SPaul Walmsley int c; 1918cb0ac99SPaul Walmsley 1928cb0ac99SPaul Walmsley c = prcm_clear_mod_irqs(WKUP_MOD, 1); 1938cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(CORE_MOD, 1); 1948cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1); 1958cb0ac99SPaul Walmsley if (omap_rev() > OMAP3430_REV_ES1_0) { 1968cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(CORE_MOD, 3); 1978cb0ac99SPaul Walmsley c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1); 1988cb0ac99SPaul Walmsley } 1998cb0ac99SPaul Walmsley 2008cb0ac99SPaul Walmsley return c; 20177da2d91SJon Hunter } 20277da2d91SJon Hunter 20377da2d91SJon Hunter /* 20477da2d91SJon Hunter * PRCM Interrupt Handler 20577da2d91SJon Hunter * 20677da2d91SJon Hunter * The PRM_IRQSTATUS_MPU register indicates if there are any pending 20777da2d91SJon Hunter * interrupts from the PRCM for the MPU. These bits must be cleared in 20877da2d91SJon Hunter * order to clear the PRCM interrupt. The PRCM interrupt handler is 20977da2d91SJon Hunter * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear 21077da2d91SJon Hunter * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU 21177da2d91SJon Hunter * register indicates that a wake-up event is pending for the MPU and 21277da2d91SJon Hunter * this bit can only be cleared if the all the wake-up events latched 21377da2d91SJon Hunter * in the various PM_WKST_x registers have been cleared. The interrupt 21477da2d91SJon Hunter * handler is implemented using a do-while loop so that if a wake-up 21577da2d91SJon Hunter * event occurred during the processing of the prcm interrupt handler 21677da2d91SJon Hunter * (setting a bit in the corresponding PM_WKST_x register and thus 21777da2d91SJon Hunter * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register) 21877da2d91SJon Hunter * this would be handled. 21977da2d91SJon Hunter */ 2208bd22949SKevin Hilman static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) 2218bd22949SKevin Hilman { 22277da2d91SJon Hunter u32 irqstatus_mpu; 2238cb0ac99SPaul Walmsley int c = 0; 2248bd22949SKevin Hilman 22577da2d91SJon Hunter do { 2268bd22949SKevin Hilman irqstatus_mpu = prm_read_mod_reg(OCP_MOD, 2278bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 2288cb0ac99SPaul Walmsley 2298cb0ac99SPaul Walmsley if (irqstatus_mpu & (OMAP3430_WKUP_ST | OMAP3430_IO_ST)) { 2308cb0ac99SPaul Walmsley c = _prcm_int_handle_wakeup(); 2318cb0ac99SPaul Walmsley 2328cb0ac99SPaul Walmsley /* 2338cb0ac99SPaul Walmsley * Is the MPU PRCM interrupt handler racing with the 2348cb0ac99SPaul Walmsley * IVA2 PRCM interrupt handler ? 2358cb0ac99SPaul Walmsley */ 2368cb0ac99SPaul Walmsley WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup " 2378cb0ac99SPaul Walmsley "but no wakeup sources are marked\n"); 2388cb0ac99SPaul Walmsley } else { 2398cb0ac99SPaul Walmsley /* XXX we need to expand our PRCM interrupt handler */ 2408cb0ac99SPaul Walmsley WARN(1, "prcm: WARNING: PRCM interrupt received, but " 2418cb0ac99SPaul Walmsley "no code to handle it (%08x)\n", irqstatus_mpu); 2428cb0ac99SPaul Walmsley } 2438cb0ac99SPaul Walmsley 2448bd22949SKevin Hilman prm_write_mod_reg(irqstatus_mpu, OCP_MOD, 2458bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 2468bd22949SKevin Hilman 24777da2d91SJon Hunter } while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET)); 2488bd22949SKevin Hilman 2498bd22949SKevin Hilman return IRQ_HANDLED; 2508bd22949SKevin Hilman } 2518bd22949SKevin Hilman 25257f277b0SRajendra Nayak static void restore_control_register(u32 val) 25357f277b0SRajendra Nayak { 25457f277b0SRajendra Nayak __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val)); 25557f277b0SRajendra Nayak } 25657f277b0SRajendra Nayak 25757f277b0SRajendra Nayak /* Function to restore the table entry that was modified for enabling MMU */ 25857f277b0SRajendra Nayak static void restore_table_entry(void) 25957f277b0SRajendra Nayak { 26057f277b0SRajendra Nayak u32 *scratchpad_address; 26157f277b0SRajendra Nayak u32 previous_value, control_reg_value; 26257f277b0SRajendra Nayak u32 *address; 26357f277b0SRajendra Nayak 26457f277b0SRajendra Nayak scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD); 26557f277b0SRajendra Nayak 26657f277b0SRajendra Nayak /* Get address of entry that was modified */ 26757f277b0SRajendra Nayak address = (u32 *)__raw_readl(scratchpad_address + 26857f277b0SRajendra Nayak OMAP343X_TABLE_ADDRESS_OFFSET); 26957f277b0SRajendra Nayak /* Get the previous value which needs to be restored */ 27057f277b0SRajendra Nayak previous_value = __raw_readl(scratchpad_address + 27157f277b0SRajendra Nayak OMAP343X_TABLE_VALUE_OFFSET); 27257f277b0SRajendra Nayak address = __va(address); 27357f277b0SRajendra Nayak *address = previous_value; 27457f277b0SRajendra Nayak flush_tlb_all(); 27557f277b0SRajendra Nayak control_reg_value = __raw_readl(scratchpad_address 27657f277b0SRajendra Nayak + OMAP343X_CONTROL_REG_VALUE_OFFSET); 27757f277b0SRajendra Nayak /* This will enable caches and prediction */ 27857f277b0SRajendra Nayak restore_control_register(control_reg_value); 27957f277b0SRajendra Nayak } 28057f277b0SRajendra Nayak 2818bd22949SKevin Hilman static void omap_sram_idle(void) 2828bd22949SKevin Hilman { 2838bd22949SKevin Hilman /* Variable to tell what needs to be saved and restored 2848bd22949SKevin Hilman * in omap_sram_idle*/ 2858bd22949SKevin Hilman /* save_state = 0 => Nothing to save and restored */ 2868bd22949SKevin Hilman /* save_state = 1 => Only L1 and logic lost */ 2878bd22949SKevin Hilman /* save_state = 2 => Only L2 lost */ 2888bd22949SKevin Hilman /* save_state = 3 => L1, L2 and logic lost */ 289fa3c2a4fSRajendra Nayak int save_state = 0; 290fa3c2a4fSRajendra Nayak int mpu_next_state = PWRDM_POWER_ON; 291fa3c2a4fSRajendra Nayak int per_next_state = PWRDM_POWER_ON; 292fa3c2a4fSRajendra Nayak int core_next_state = PWRDM_POWER_ON; 2932f5939c3SRajendra Nayak int core_prev_state, per_prev_state; 2948bd22949SKevin Hilman 2958bd22949SKevin Hilman if (!_omap_sram_idle) 2968bd22949SKevin Hilman return; 2978bd22949SKevin Hilman 298fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(mpu_pwrdm); 299fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(neon_pwrdm); 300fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(core_pwrdm); 301fa3c2a4fSRajendra Nayak pwrdm_clear_all_prev_pwrst(per_pwrdm); 302fa3c2a4fSRajendra Nayak 3038bd22949SKevin Hilman mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 3048bd22949SKevin Hilman switch (mpu_next_state) { 305fa3c2a4fSRajendra Nayak case PWRDM_POWER_ON: 3068bd22949SKevin Hilman case PWRDM_POWER_RET: 3078bd22949SKevin Hilman /* No need to save context */ 3088bd22949SKevin Hilman save_state = 0; 3098bd22949SKevin Hilman break; 31061255ab9SRajendra Nayak case PWRDM_POWER_OFF: 31161255ab9SRajendra Nayak save_state = 3; 31261255ab9SRajendra Nayak break; 3138bd22949SKevin Hilman default: 3148bd22949SKevin Hilman /* Invalid state */ 3158bd22949SKevin Hilman printk(KERN_ERR "Invalid mpu state in sram_idle\n"); 3168bd22949SKevin Hilman return; 3178bd22949SKevin Hilman } 318fe617af7SPeter 'p2' De Schrijver pwrdm_pre_transition(); 319fe617af7SPeter 'p2' De Schrijver 320fa3c2a4fSRajendra Nayak /* NEON control */ 321fa3c2a4fSRajendra Nayak if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) 322fa3c2a4fSRajendra Nayak set_pwrdm_state(neon_pwrdm, mpu_next_state); 323fa3c2a4fSRajendra Nayak 324fa3c2a4fSRajendra Nayak /* CORE & PER */ 325fa3c2a4fSRajendra Nayak core_next_state = pwrdm_read_next_pwrst(core_pwrdm); 326fa3c2a4fSRajendra Nayak if (core_next_state < PWRDM_POWER_ON) { 3278bd22949SKevin Hilman omap2_gpio_prepare_for_retention(); 3284af4016cSKevin Hilman omap_uart_prepare_idle(0); 3294af4016cSKevin Hilman omap_uart_prepare_idle(1); 330fa3c2a4fSRajendra Nayak /* PER changes only with core */ 331fa3c2a4fSRajendra Nayak per_next_state = pwrdm_read_next_pwrst(per_pwrdm); 3322f5939c3SRajendra Nayak if (per_next_state < PWRDM_POWER_ON) { 3334af4016cSKevin Hilman omap_uart_prepare_idle(2); 3342f5939c3SRajendra Nayak if (per_next_state == PWRDM_POWER_OFF) 3352f5939c3SRajendra Nayak omap3_per_save_context(); 3362f5939c3SRajendra Nayak } 3372f5939c3SRajendra Nayak if (core_next_state == PWRDM_POWER_OFF) { 3382f5939c3SRajendra Nayak omap3_core_save_context(); 3392f5939c3SRajendra Nayak omap3_prcm_save_context(); 34027d59a4aSTero Kristo omap3_save_secure_ram_context(mpu_next_state); 3412f5939c3SRajendra Nayak } 342fa3c2a4fSRajendra Nayak /* Enable IO-PAD wakeup */ 343fa3c2a4fSRajendra Nayak prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN); 344fa3c2a4fSRajendra Nayak } 3458bd22949SKevin Hilman 34661255ab9SRajendra Nayak /* 34761255ab9SRajendra Nayak * omap3_arm_context is the location where ARM registers 34861255ab9SRajendra Nayak * get saved. The restore path then reads from this 34961255ab9SRajendra Nayak * location and restores them back. 35061255ab9SRajendra Nayak */ 35161255ab9SRajendra Nayak _omap_sram_idle(omap3_arm_context, save_state); 3528bd22949SKevin Hilman cpu_init(); 3538bd22949SKevin Hilman 35457f277b0SRajendra Nayak /* Restore table entry modified during MMU restoration */ 35557f277b0SRajendra Nayak if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF) 35657f277b0SRajendra Nayak restore_table_entry(); 35757f277b0SRajendra Nayak 358fa3c2a4fSRajendra Nayak if (core_next_state < PWRDM_POWER_ON) { 359fa3c2a4fSRajendra Nayak if (per_next_state < PWRDM_POWER_ON) 3604af4016cSKevin Hilman omap_uart_resume_idle(2); 3614af4016cSKevin Hilman omap_uart_resume_idle(1); 3624af4016cSKevin Hilman omap_uart_resume_idle(0); 363fa3c2a4fSRajendra Nayak 364fa3c2a4fSRajendra Nayak /* Disable IO-PAD wakeup */ 365fa3c2a4fSRajendra Nayak prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN); 3662f5939c3SRajendra Nayak core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); 3672f5939c3SRajendra Nayak if (core_prev_state == PWRDM_POWER_OFF) { 3682f5939c3SRajendra Nayak omap3_core_restore_context(); 3692f5939c3SRajendra Nayak omap3_prcm_restore_context(); 3702f5939c3SRajendra Nayak omap3_sram_restore_context(); 3712f5939c3SRajendra Nayak } 3722f5939c3SRajendra Nayak if (per_next_state < PWRDM_POWER_ON) { 3732f5939c3SRajendra Nayak per_prev_state = 3742f5939c3SRajendra Nayak pwrdm_read_prev_pwrst(per_pwrdm); 3752f5939c3SRajendra Nayak if (per_prev_state == PWRDM_POWER_OFF) 3762f5939c3SRajendra Nayak omap3_per_restore_context(); 3772f5939c3SRajendra Nayak } 3788bd22949SKevin Hilman omap2_gpio_resume_after_retention(); 379fa3c2a4fSRajendra Nayak } 380fe617af7SPeter 'p2' De Schrijver 381fe617af7SPeter 'p2' De Schrijver pwrdm_post_transition(); 382fe617af7SPeter 'p2' De Schrijver 3838bd22949SKevin Hilman } 3848bd22949SKevin Hilman 3858bd22949SKevin Hilman /* 3868bd22949SKevin Hilman * Check if functional clocks are enabled before entering 3878bd22949SKevin Hilman * sleep. This function could be behind CONFIG_PM_DEBUG 3888bd22949SKevin Hilman * when all drivers are configuring their sysconfig registers 3898bd22949SKevin Hilman * properly and using their clocks properly. 3908bd22949SKevin Hilman */ 3918bd22949SKevin Hilman static int omap3_fclks_active(void) 3928bd22949SKevin Hilman { 3938bd22949SKevin Hilman u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0, 3948bd22949SKevin Hilman fck_cam = 0, fck_per = 0, fck_usbhost = 0; 3958bd22949SKevin Hilman 3968bd22949SKevin Hilman fck_core1 = cm_read_mod_reg(CORE_MOD, 3978bd22949SKevin Hilman CM_FCLKEN1); 3988bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 3998bd22949SKevin Hilman fck_core3 = cm_read_mod_reg(CORE_MOD, 4008bd22949SKevin Hilman OMAP3430ES2_CM_FCLKEN3); 4018bd22949SKevin Hilman fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD, 4028bd22949SKevin Hilman CM_FCLKEN); 4038bd22949SKevin Hilman fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, 4048bd22949SKevin Hilman CM_FCLKEN); 4058bd22949SKevin Hilman } else 4068bd22949SKevin Hilman fck_sgx = cm_read_mod_reg(GFX_MOD, 4078bd22949SKevin Hilman OMAP3430ES2_CM_FCLKEN3); 4088bd22949SKevin Hilman fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD, 4098bd22949SKevin Hilman CM_FCLKEN); 4108bd22949SKevin Hilman fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD, 4118bd22949SKevin Hilman CM_FCLKEN); 4128bd22949SKevin Hilman fck_per = cm_read_mod_reg(OMAP3430_PER_MOD, 4138bd22949SKevin Hilman CM_FCLKEN); 4144af4016cSKevin Hilman 4154af4016cSKevin Hilman /* Ignore UART clocks. These are handled by UART core (serial.c) */ 4164af4016cSKevin Hilman fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2); 4174af4016cSKevin Hilman fck_per &= ~OMAP3430_EN_UART3; 4184af4016cSKevin Hilman 4198bd22949SKevin Hilman if (fck_core1 | fck_core3 | fck_sgx | fck_dss | 4208bd22949SKevin Hilman fck_cam | fck_per | fck_usbhost) 4218bd22949SKevin Hilman return 1; 4228bd22949SKevin Hilman return 0; 4238bd22949SKevin Hilman } 4248bd22949SKevin Hilman 4258bd22949SKevin Hilman static int omap3_can_sleep(void) 4268bd22949SKevin Hilman { 4274af4016cSKevin Hilman if (!omap_uart_can_sleep()) 4284af4016cSKevin Hilman return 0; 4298bd22949SKevin Hilman if (omap3_fclks_active()) 4308bd22949SKevin Hilman return 0; 4318bd22949SKevin Hilman return 1; 4328bd22949SKevin Hilman } 4338bd22949SKevin Hilman 4348bd22949SKevin Hilman /* This sets pwrdm state (other than mpu & core. Currently only ON & 4358bd22949SKevin Hilman * RET are supported. Function is assuming that clkdm doesn't have 4368bd22949SKevin Hilman * hw_sup mode enabled. */ 4378bd22949SKevin Hilman static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state) 4388bd22949SKevin Hilman { 4398bd22949SKevin Hilman u32 cur_state; 4408bd22949SKevin Hilman int sleep_switch = 0; 4418bd22949SKevin Hilman int ret = 0; 4428bd22949SKevin Hilman 4438bd22949SKevin Hilman if (pwrdm == NULL || IS_ERR(pwrdm)) 4448bd22949SKevin Hilman return -EINVAL; 4458bd22949SKevin Hilman 4468bd22949SKevin Hilman while (!(pwrdm->pwrsts & (1 << state))) { 4478bd22949SKevin Hilman if (state == PWRDM_POWER_OFF) 4488bd22949SKevin Hilman return ret; 4498bd22949SKevin Hilman state--; 4508bd22949SKevin Hilman } 4518bd22949SKevin Hilman 4528bd22949SKevin Hilman cur_state = pwrdm_read_next_pwrst(pwrdm); 4538bd22949SKevin Hilman if (cur_state == state) 4548bd22949SKevin Hilman return ret; 4558bd22949SKevin Hilman 4568bd22949SKevin Hilman if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) { 4578bd22949SKevin Hilman omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); 4588bd22949SKevin Hilman sleep_switch = 1; 4598bd22949SKevin Hilman pwrdm_wait_transition(pwrdm); 4608bd22949SKevin Hilman } 4618bd22949SKevin Hilman 4628bd22949SKevin Hilman ret = pwrdm_set_next_pwrst(pwrdm, state); 4638bd22949SKevin Hilman if (ret) { 4648bd22949SKevin Hilman printk(KERN_ERR "Unable to set state of powerdomain: %s\n", 4658bd22949SKevin Hilman pwrdm->name); 4668bd22949SKevin Hilman goto err; 4678bd22949SKevin Hilman } 4688bd22949SKevin Hilman 4698bd22949SKevin Hilman if (sleep_switch) { 4708bd22949SKevin Hilman omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); 4718bd22949SKevin Hilman pwrdm_wait_transition(pwrdm); 472fe617af7SPeter 'p2' De Schrijver pwrdm_state_switch(pwrdm); 4738bd22949SKevin Hilman } 4748bd22949SKevin Hilman 4758bd22949SKevin Hilman err: 4768bd22949SKevin Hilman return ret; 4778bd22949SKevin Hilman } 4788bd22949SKevin Hilman 4798bd22949SKevin Hilman static void omap3_pm_idle(void) 4808bd22949SKevin Hilman { 4818bd22949SKevin Hilman local_irq_disable(); 4828bd22949SKevin Hilman local_fiq_disable(); 4838bd22949SKevin Hilman 4848bd22949SKevin Hilman if (!omap3_can_sleep()) 4858bd22949SKevin Hilman goto out; 4868bd22949SKevin Hilman 4878bd22949SKevin Hilman if (omap_irq_pending()) 4888bd22949SKevin Hilman goto out; 4898bd22949SKevin Hilman 4908bd22949SKevin Hilman omap_sram_idle(); 4918bd22949SKevin Hilman 4928bd22949SKevin Hilman out: 4938bd22949SKevin Hilman local_fiq_enable(); 4948bd22949SKevin Hilman local_irq_enable(); 4958bd22949SKevin Hilman } 4968bd22949SKevin Hilman 49710f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 4982466211eSTero Kristo static suspend_state_t suspend_state; 4992466211eSTero Kristo 5008bd22949SKevin Hilman static int omap3_pm_prepare(void) 5018bd22949SKevin Hilman { 5028bd22949SKevin Hilman disable_hlt(); 5038bd22949SKevin Hilman return 0; 5048bd22949SKevin Hilman } 5058bd22949SKevin Hilman 5068bd22949SKevin Hilman static int omap3_pm_suspend(void) 5078bd22949SKevin Hilman { 5088bd22949SKevin Hilman struct power_state *pwrst; 5098bd22949SKevin Hilman int state, ret = 0; 5108bd22949SKevin Hilman 5118bd22949SKevin Hilman /* Read current next_pwrsts */ 5128bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) 5138bd22949SKevin Hilman pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 5148bd22949SKevin Hilman /* Set ones wanted by suspend */ 5158bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 5168bd22949SKevin Hilman if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) 5178bd22949SKevin Hilman goto restore; 5188bd22949SKevin Hilman if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) 5198bd22949SKevin Hilman goto restore; 5208bd22949SKevin Hilman } 5218bd22949SKevin Hilman 5224af4016cSKevin Hilman omap_uart_prepare_suspend(); 5238bd22949SKevin Hilman omap_sram_idle(); 5248bd22949SKevin Hilman 5258bd22949SKevin Hilman restore: 5268bd22949SKevin Hilman /* Restore next_pwrsts */ 5278bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 5288bd22949SKevin Hilman state = pwrdm_read_prev_pwrst(pwrst->pwrdm); 5298bd22949SKevin Hilman if (state > pwrst->next_state) { 5308bd22949SKevin Hilman printk(KERN_INFO "Powerdomain (%s) didn't enter " 5318bd22949SKevin Hilman "target state %d\n", 5328bd22949SKevin Hilman pwrst->pwrdm->name, pwrst->next_state); 5338bd22949SKevin Hilman ret = -1; 5348bd22949SKevin Hilman } 5356c5f8039SJouni Hogander set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); 5368bd22949SKevin Hilman } 5378bd22949SKevin Hilman if (ret) 5388bd22949SKevin Hilman printk(KERN_ERR "Could not enter target state in pm_suspend\n"); 5398bd22949SKevin Hilman else 5408bd22949SKevin Hilman printk(KERN_INFO "Successfully put all powerdomains " 5418bd22949SKevin Hilman "to target state\n"); 5428bd22949SKevin Hilman 5438bd22949SKevin Hilman return ret; 5448bd22949SKevin Hilman } 5458bd22949SKevin Hilman 5462466211eSTero Kristo static int omap3_pm_enter(suspend_state_t unused) 5478bd22949SKevin Hilman { 5488bd22949SKevin Hilman int ret = 0; 5498bd22949SKevin Hilman 5502466211eSTero Kristo switch (suspend_state) { 5518bd22949SKevin Hilman case PM_SUSPEND_STANDBY: 5528bd22949SKevin Hilman case PM_SUSPEND_MEM: 5538bd22949SKevin Hilman ret = omap3_pm_suspend(); 5548bd22949SKevin Hilman break; 5558bd22949SKevin Hilman default: 5568bd22949SKevin Hilman ret = -EINVAL; 5578bd22949SKevin Hilman } 5588bd22949SKevin Hilman 5598bd22949SKevin Hilman return ret; 5608bd22949SKevin Hilman } 5618bd22949SKevin Hilman 5628bd22949SKevin Hilman static void omap3_pm_finish(void) 5638bd22949SKevin Hilman { 5648bd22949SKevin Hilman enable_hlt(); 5658bd22949SKevin Hilman } 5668bd22949SKevin Hilman 5672466211eSTero Kristo /* Hooks to enable / disable UART interrupts during suspend */ 5682466211eSTero Kristo static int omap3_pm_begin(suspend_state_t state) 5692466211eSTero Kristo { 5702466211eSTero Kristo suspend_state = state; 5712466211eSTero Kristo omap_uart_enable_irqs(0); 5722466211eSTero Kristo return 0; 5732466211eSTero Kristo } 5742466211eSTero Kristo 5752466211eSTero Kristo static void omap3_pm_end(void) 5762466211eSTero Kristo { 5772466211eSTero Kristo suspend_state = PM_SUSPEND_ON; 5782466211eSTero Kristo omap_uart_enable_irqs(1); 5792466211eSTero Kristo return; 5802466211eSTero Kristo } 5812466211eSTero Kristo 5828bd22949SKevin Hilman static struct platform_suspend_ops omap_pm_ops = { 5832466211eSTero Kristo .begin = omap3_pm_begin, 5842466211eSTero Kristo .end = omap3_pm_end, 5858bd22949SKevin Hilman .prepare = omap3_pm_prepare, 5868bd22949SKevin Hilman .enter = omap3_pm_enter, 5878bd22949SKevin Hilman .finish = omap3_pm_finish, 5888bd22949SKevin Hilman .valid = suspend_valid_only_mem, 5898bd22949SKevin Hilman }; 59010f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 5918bd22949SKevin Hilman 5921155e426SKevin Hilman 5931155e426SKevin Hilman /** 5941155e426SKevin Hilman * omap3_iva_idle(): ensure IVA is in idle so it can be put into 5951155e426SKevin Hilman * retention 5961155e426SKevin Hilman * 5971155e426SKevin Hilman * In cases where IVA2 is activated by bootcode, it may prevent 5981155e426SKevin Hilman * full-chip retention or off-mode because it is not idle. This 5991155e426SKevin Hilman * function forces the IVA2 into idle state so it can go 6001155e426SKevin Hilman * into retention/off and thus allow full-chip retention/off. 6011155e426SKevin Hilman * 6021155e426SKevin Hilman **/ 6031155e426SKevin Hilman static void __init omap3_iva_idle(void) 6041155e426SKevin Hilman { 6051155e426SKevin Hilman /* ensure IVA2 clock is disabled */ 6061155e426SKevin Hilman cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 6071155e426SKevin Hilman 6081155e426SKevin Hilman /* if no clock activity, nothing else to do */ 6091155e426SKevin Hilman if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & 6101155e426SKevin Hilman OMAP3430_CLKACTIVITY_IVA2_MASK)) 6111155e426SKevin Hilman return; 6121155e426SKevin Hilman 6131155e426SKevin Hilman /* Reset IVA2 */ 6141155e426SKevin Hilman prm_write_mod_reg(OMAP3430_RST1_IVA2 | 6151155e426SKevin Hilman OMAP3430_RST2_IVA2 | 6161155e426SKevin Hilman OMAP3430_RST3_IVA2, 6171155e426SKevin Hilman OMAP3430_IVA2_MOD, RM_RSTCTRL); 6181155e426SKevin Hilman 6191155e426SKevin Hilman /* Enable IVA2 clock */ 6201155e426SKevin Hilman cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2, 6211155e426SKevin Hilman OMAP3430_IVA2_MOD, CM_FCLKEN); 6221155e426SKevin Hilman 6231155e426SKevin Hilman /* Set IVA2 boot mode to 'idle' */ 6241155e426SKevin Hilman omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, 6251155e426SKevin Hilman OMAP343X_CONTROL_IVA2_BOOTMOD); 6261155e426SKevin Hilman 6271155e426SKevin Hilman /* Un-reset IVA2 */ 6281155e426SKevin Hilman prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL); 6291155e426SKevin Hilman 6301155e426SKevin Hilman /* Disable IVA2 clock */ 6311155e426SKevin Hilman cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 6321155e426SKevin Hilman 6331155e426SKevin Hilman /* Reset IVA2 */ 6341155e426SKevin Hilman prm_write_mod_reg(OMAP3430_RST1_IVA2 | 6351155e426SKevin Hilman OMAP3430_RST2_IVA2 | 6361155e426SKevin Hilman OMAP3430_RST3_IVA2, 6371155e426SKevin Hilman OMAP3430_IVA2_MOD, RM_RSTCTRL); 6381155e426SKevin Hilman } 6391155e426SKevin Hilman 6408111b221SKevin Hilman static void __init omap3_d2d_idle(void) 6418bd22949SKevin Hilman { 6428111b221SKevin Hilman u16 mask, padconf; 6438111b221SKevin Hilman 6448111b221SKevin Hilman /* In a stand alone OMAP3430 where there is not a stacked 6458111b221SKevin Hilman * modem for the D2D Idle Ack and D2D MStandby must be pulled 6468111b221SKevin Hilman * high. S CONTROL_PADCONF_SAD2D_IDLEACK and 6478111b221SKevin Hilman * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ 6488111b221SKevin Hilman mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ 6498111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); 6508111b221SKevin Hilman padconf |= mask; 6518111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); 6528111b221SKevin Hilman 6538111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); 6548111b221SKevin Hilman padconf |= mask; 6558111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 6568111b221SKevin Hilman 6578bd22949SKevin Hilman /* reset modem */ 6588bd22949SKevin Hilman prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON | 6598bd22949SKevin Hilman OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST, 6608bd22949SKevin Hilman CORE_MOD, RM_RSTCTRL); 6618bd22949SKevin Hilman prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL); 6628111b221SKevin Hilman } 6638bd22949SKevin Hilman 6648111b221SKevin Hilman static void __init prcm_setup_regs(void) 6658111b221SKevin Hilman { 6668bd22949SKevin Hilman /* XXX Reset all wkdeps. This should be done when initializing 6678bd22949SKevin Hilman * powerdomains */ 6688bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); 6698bd22949SKevin Hilman prm_write_mod_reg(0, MPU_MOD, PM_WKDEP); 6708bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP); 6718bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP); 6728bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP); 6738bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP); 6748bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 6758bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP); 6768bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP); 6778bd22949SKevin Hilman } else 6788bd22949SKevin Hilman prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); 6798bd22949SKevin Hilman 6808bd22949SKevin Hilman /* 6818bd22949SKevin Hilman * Enable interface clock autoidle for all modules. 6828bd22949SKevin Hilman * Note that in the long run this should be done by clockfw 6838bd22949SKevin Hilman */ 6848bd22949SKevin Hilman cm_write_mod_reg( 6858111b221SKevin Hilman OMAP3430_AUTO_MODEM | 6868bd22949SKevin Hilman OMAP3430ES2_AUTO_MMC3 | 6878bd22949SKevin Hilman OMAP3430ES2_AUTO_ICR | 6888bd22949SKevin Hilman OMAP3430_AUTO_AES2 | 6898bd22949SKevin Hilman OMAP3430_AUTO_SHA12 | 6908bd22949SKevin Hilman OMAP3430_AUTO_DES2 | 6918bd22949SKevin Hilman OMAP3430_AUTO_MMC2 | 6928bd22949SKevin Hilman OMAP3430_AUTO_MMC1 | 6938bd22949SKevin Hilman OMAP3430_AUTO_MSPRO | 6948bd22949SKevin Hilman OMAP3430_AUTO_HDQ | 6958bd22949SKevin Hilman OMAP3430_AUTO_MCSPI4 | 6968bd22949SKevin Hilman OMAP3430_AUTO_MCSPI3 | 6978bd22949SKevin Hilman OMAP3430_AUTO_MCSPI2 | 6988bd22949SKevin Hilman OMAP3430_AUTO_MCSPI1 | 6998bd22949SKevin Hilman OMAP3430_AUTO_I2C3 | 7008bd22949SKevin Hilman OMAP3430_AUTO_I2C2 | 7018bd22949SKevin Hilman OMAP3430_AUTO_I2C1 | 7028bd22949SKevin Hilman OMAP3430_AUTO_UART2 | 7038bd22949SKevin Hilman OMAP3430_AUTO_UART1 | 7048bd22949SKevin Hilman OMAP3430_AUTO_GPT11 | 7058bd22949SKevin Hilman OMAP3430_AUTO_GPT10 | 7068bd22949SKevin Hilman OMAP3430_AUTO_MCBSP5 | 7078bd22949SKevin Hilman OMAP3430_AUTO_MCBSP1 | 7088bd22949SKevin Hilman OMAP3430ES1_AUTO_FAC | /* This is es1 only */ 7098bd22949SKevin Hilman OMAP3430_AUTO_MAILBOXES | 7108bd22949SKevin Hilman OMAP3430_AUTO_OMAPCTRL | 7118bd22949SKevin Hilman OMAP3430ES1_AUTO_FSHOSTUSB | 7128bd22949SKevin Hilman OMAP3430_AUTO_HSOTGUSB | 7138111b221SKevin Hilman OMAP3430_AUTO_SAD2D | 7148bd22949SKevin Hilman OMAP3430_AUTO_SSI, 7158bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE1); 7168bd22949SKevin Hilman 7178bd22949SKevin Hilman cm_write_mod_reg( 7188bd22949SKevin Hilman OMAP3430_AUTO_PKA | 7198bd22949SKevin Hilman OMAP3430_AUTO_AES1 | 7208bd22949SKevin Hilman OMAP3430_AUTO_RNG | 7218bd22949SKevin Hilman OMAP3430_AUTO_SHA11 | 7228bd22949SKevin Hilman OMAP3430_AUTO_DES1, 7238bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE2); 7248bd22949SKevin Hilman 7258bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 7268bd22949SKevin Hilman cm_write_mod_reg( 7278111b221SKevin Hilman OMAP3430_AUTO_MAD2D | 7288bd22949SKevin Hilman OMAP3430ES2_AUTO_USBTLL, 7298bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE3); 7308bd22949SKevin Hilman } 7318bd22949SKevin Hilman 7328bd22949SKevin Hilman cm_write_mod_reg( 7338bd22949SKevin Hilman OMAP3430_AUTO_WDT2 | 7348bd22949SKevin Hilman OMAP3430_AUTO_WDT1 | 7358bd22949SKevin Hilman OMAP3430_AUTO_GPIO1 | 7368bd22949SKevin Hilman OMAP3430_AUTO_32KSYNC | 7378bd22949SKevin Hilman OMAP3430_AUTO_GPT12 | 7388bd22949SKevin Hilman OMAP3430_AUTO_GPT1 , 7398bd22949SKevin Hilman WKUP_MOD, CM_AUTOIDLE); 7408bd22949SKevin Hilman 7418bd22949SKevin Hilman cm_write_mod_reg( 7428bd22949SKevin Hilman OMAP3430_AUTO_DSS, 7438bd22949SKevin Hilman OMAP3430_DSS_MOD, 7448bd22949SKevin Hilman CM_AUTOIDLE); 7458bd22949SKevin Hilman 7468bd22949SKevin Hilman cm_write_mod_reg( 7478bd22949SKevin Hilman OMAP3430_AUTO_CAM, 7488bd22949SKevin Hilman OMAP3430_CAM_MOD, 7498bd22949SKevin Hilman CM_AUTOIDLE); 7508bd22949SKevin Hilman 7518bd22949SKevin Hilman cm_write_mod_reg( 7528bd22949SKevin Hilman OMAP3430_AUTO_GPIO6 | 7538bd22949SKevin Hilman OMAP3430_AUTO_GPIO5 | 7548bd22949SKevin Hilman OMAP3430_AUTO_GPIO4 | 7558bd22949SKevin Hilman OMAP3430_AUTO_GPIO3 | 7568bd22949SKevin Hilman OMAP3430_AUTO_GPIO2 | 7578bd22949SKevin Hilman OMAP3430_AUTO_WDT3 | 7588bd22949SKevin Hilman OMAP3430_AUTO_UART3 | 7598bd22949SKevin Hilman OMAP3430_AUTO_GPT9 | 7608bd22949SKevin Hilman OMAP3430_AUTO_GPT8 | 7618bd22949SKevin Hilman OMAP3430_AUTO_GPT7 | 7628bd22949SKevin Hilman OMAP3430_AUTO_GPT6 | 7638bd22949SKevin Hilman OMAP3430_AUTO_GPT5 | 7648bd22949SKevin Hilman OMAP3430_AUTO_GPT4 | 7658bd22949SKevin Hilman OMAP3430_AUTO_GPT3 | 7668bd22949SKevin Hilman OMAP3430_AUTO_GPT2 | 7678bd22949SKevin Hilman OMAP3430_AUTO_MCBSP4 | 7688bd22949SKevin Hilman OMAP3430_AUTO_MCBSP3 | 7698bd22949SKevin Hilman OMAP3430_AUTO_MCBSP2, 7708bd22949SKevin Hilman OMAP3430_PER_MOD, 7718bd22949SKevin Hilman CM_AUTOIDLE); 7728bd22949SKevin Hilman 7738bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 7748bd22949SKevin Hilman cm_write_mod_reg( 7758bd22949SKevin Hilman OMAP3430ES2_AUTO_USBHOST, 7768bd22949SKevin Hilman OMAP3430ES2_USBHOST_MOD, 7778bd22949SKevin Hilman CM_AUTOIDLE); 7788bd22949SKevin Hilman } 7798bd22949SKevin Hilman 7808bd22949SKevin Hilman /* 7818bd22949SKevin Hilman * Set all plls to autoidle. This is needed until autoidle is 7828bd22949SKevin Hilman * enabled by clockfw 7838bd22949SKevin Hilman */ 7848bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, 7858bd22949SKevin Hilman OMAP3430_IVA2_MOD, CM_AUTOIDLE2); 7868bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT, 7878bd22949SKevin Hilman MPU_MOD, 7888bd22949SKevin Hilman CM_AUTOIDLE2); 7898bd22949SKevin Hilman cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | 7908bd22949SKevin Hilman (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT), 7918bd22949SKevin Hilman PLL_MOD, 7928bd22949SKevin Hilman CM_AUTOIDLE); 7938bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, 7948bd22949SKevin Hilman PLL_MOD, 7958bd22949SKevin Hilman CM_AUTOIDLE2); 7968bd22949SKevin Hilman 7978bd22949SKevin Hilman /* 7988bd22949SKevin Hilman * Enable control of expternal oscillator through 7998bd22949SKevin Hilman * sys_clkreq. In the long run clock framework should 8008bd22949SKevin Hilman * take care of this. 8018bd22949SKevin Hilman */ 8028bd22949SKevin Hilman prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 8038bd22949SKevin Hilman 1 << OMAP_AUTOEXTCLKMODE_SHIFT, 8048bd22949SKevin Hilman OMAP3430_GR_MOD, 8058bd22949SKevin Hilman OMAP3_PRM_CLKSRC_CTRL_OFFSET); 8068bd22949SKevin Hilman 8078bd22949SKevin Hilman /* setup wakup source */ 8088bd22949SKevin Hilman prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 | 8098bd22949SKevin Hilman OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12, 8108bd22949SKevin Hilman WKUP_MOD, PM_WKEN); 8118bd22949SKevin Hilman /* No need to write EN_IO, that is always enabled */ 8128bd22949SKevin Hilman prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 | 8138bd22949SKevin Hilman OMAP3430_EN_GPT12, 8148bd22949SKevin Hilman WKUP_MOD, OMAP3430_PM_MPUGRPSEL); 8158bd22949SKevin Hilman /* For some reason IO doesn't generate wakeup event even if 8168bd22949SKevin Hilman * it is selected to mpu wakeup goup */ 8178bd22949SKevin Hilman prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN, 8188bd22949SKevin Hilman OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); 8191155e426SKevin Hilman 820b427f92fSKevin Hilman /* Enable wakeups in PER */ 821eb350f74SKevin Hilman prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 | 822eb350f74SKevin Hilman OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 | 823b427f92fSKevin Hilman OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3, 824b427f92fSKevin Hilman OMAP3430_PER_MOD, PM_WKEN); 825eb350f74SKevin Hilman /* and allow them to wake up MPU */ 826eb350f74SKevin Hilman prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 | 827eb350f74SKevin Hilman OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 | 828b427f92fSKevin Hilman OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3, 829eb350f74SKevin Hilman OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); 830eb350f74SKevin Hilman 831d3fd3290SKevin Hilman /* Don't attach IVA interrupts */ 832d3fd3290SKevin Hilman prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 833d3fd3290SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 834d3fd3290SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 835d3fd3290SKevin Hilman prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); 836d3fd3290SKevin Hilman 837b1340d17SKevin Hilman /* Clear any pending 'reset' flags */ 838b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST); 839b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST); 840b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST); 841b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST); 842b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST); 843b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST); 844b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST); 845b1340d17SKevin Hilman 846014c46dbSKevin Hilman /* Clear any pending PRCM interrupts */ 847014c46dbSKevin Hilman prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 848014c46dbSKevin Hilman 849040fed05SKevin Hilman /* Don't attach IVA interrupts */ 850040fed05SKevin Hilman prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 851040fed05SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 852040fed05SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 853040fed05SKevin Hilman prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); 854040fed05SKevin Hilman 8553a07ae30SKevin Hilman /* Clear any pending 'reset' flags */ 8563a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST); 8573a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST); 8583a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST); 8593a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST); 8603a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST); 8613a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST); 8623a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST); 8633a07ae30SKevin Hilman 8643a6667acSKevin Hilman /* Clear any pending PRCM interrupts */ 8653a6667acSKevin Hilman prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 8663a6667acSKevin Hilman 8671155e426SKevin Hilman omap3_iva_idle(); 8688111b221SKevin Hilman omap3_d2d_idle(); 8698bd22949SKevin Hilman } 8708bd22949SKevin Hilman 87168d4778cSTero Kristo int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) 87268d4778cSTero Kristo { 87368d4778cSTero Kristo struct power_state *pwrst; 87468d4778cSTero Kristo 87568d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 87668d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) 87768d4778cSTero Kristo return pwrst->next_state; 87868d4778cSTero Kristo } 87968d4778cSTero Kristo return -EINVAL; 88068d4778cSTero Kristo } 88168d4778cSTero Kristo 88268d4778cSTero Kristo int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) 88368d4778cSTero Kristo { 88468d4778cSTero Kristo struct power_state *pwrst; 88568d4778cSTero Kristo 88668d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) { 88768d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) { 88868d4778cSTero Kristo pwrst->next_state = state; 88968d4778cSTero Kristo return 0; 89068d4778cSTero Kristo } 89168d4778cSTero Kristo } 89268d4778cSTero Kristo return -EINVAL; 89368d4778cSTero Kristo } 89468d4778cSTero Kristo 895a23456e9SPeter 'p2' De Schrijver static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) 8968bd22949SKevin Hilman { 8978bd22949SKevin Hilman struct power_state *pwrst; 8988bd22949SKevin Hilman 8998bd22949SKevin Hilman if (!pwrdm->pwrsts) 9008bd22949SKevin Hilman return 0; 9018bd22949SKevin Hilman 902d3d381c6SMing Lei pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); 9038bd22949SKevin Hilman if (!pwrst) 9048bd22949SKevin Hilman return -ENOMEM; 9058bd22949SKevin Hilman pwrst->pwrdm = pwrdm; 9068bd22949SKevin Hilman pwrst->next_state = PWRDM_POWER_RET; 9078bd22949SKevin Hilman list_add(&pwrst->node, &pwrst_list); 9088bd22949SKevin Hilman 9098bd22949SKevin Hilman if (pwrdm_has_hdwr_sar(pwrdm)) 9108bd22949SKevin Hilman pwrdm_enable_hdwr_sar(pwrdm); 9118bd22949SKevin Hilman 9128bd22949SKevin Hilman return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 9138bd22949SKevin Hilman } 9148bd22949SKevin Hilman 9158bd22949SKevin Hilman /* 9168bd22949SKevin Hilman * Enable hw supervised mode for all clockdomains if it's 9178bd22949SKevin Hilman * supported. Initiate sleep transition for other clockdomains, if 9188bd22949SKevin Hilman * they are not used 9198bd22949SKevin Hilman */ 920a23456e9SPeter 'p2' De Schrijver static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) 9218bd22949SKevin Hilman { 9228bd22949SKevin Hilman if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) 9238bd22949SKevin Hilman omap2_clkdm_allow_idle(clkdm); 9248bd22949SKevin Hilman else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && 9258bd22949SKevin Hilman atomic_read(&clkdm->usecount) == 0) 9268bd22949SKevin Hilman omap2_clkdm_sleep(clkdm); 9278bd22949SKevin Hilman return 0; 9288bd22949SKevin Hilman } 9298bd22949SKevin Hilman 9303231fc88SRajendra Nayak void omap_push_sram_idle(void) 9313231fc88SRajendra Nayak { 9323231fc88SRajendra Nayak _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend, 9333231fc88SRajendra Nayak omap34xx_cpu_suspend_sz); 93427d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) 93527d59a4aSTero Kristo _omap_save_secure_sram = omap_sram_push(save_secure_ram_context, 93627d59a4aSTero Kristo save_secure_ram_context_sz); 9373231fc88SRajendra Nayak } 9383231fc88SRajendra Nayak 9397cc515f7SKevin Hilman static int __init omap3_pm_init(void) 9408bd22949SKevin Hilman { 9418bd22949SKevin Hilman struct power_state *pwrst, *tmp; 9428bd22949SKevin Hilman int ret; 9438bd22949SKevin Hilman 9448bd22949SKevin Hilman if (!cpu_is_omap34xx()) 9458bd22949SKevin Hilman return -ENODEV; 9468bd22949SKevin Hilman 9478bd22949SKevin Hilman printk(KERN_ERR "Power Management for TI OMAP3.\n"); 9488bd22949SKevin Hilman 9498bd22949SKevin Hilman /* XXX prcm_setup_regs needs to be before enabling hw 9508bd22949SKevin Hilman * supervised mode for powerdomains */ 9518bd22949SKevin Hilman prcm_setup_regs(); 9528bd22949SKevin Hilman 9538bd22949SKevin Hilman ret = request_irq(INT_34XX_PRCM_MPU_IRQ, 9548bd22949SKevin Hilman (irq_handler_t)prcm_interrupt_handler, 9558bd22949SKevin Hilman IRQF_DISABLED, "prcm", NULL); 9568bd22949SKevin Hilman if (ret) { 9578bd22949SKevin Hilman printk(KERN_ERR "request_irq failed to register for 0x%x\n", 9588bd22949SKevin Hilman INT_34XX_PRCM_MPU_IRQ); 9598bd22949SKevin Hilman goto err1; 9608bd22949SKevin Hilman } 9618bd22949SKevin Hilman 962a23456e9SPeter 'p2' De Schrijver ret = pwrdm_for_each(pwrdms_setup, NULL); 9638bd22949SKevin Hilman if (ret) { 9648bd22949SKevin Hilman printk(KERN_ERR "Failed to setup powerdomains\n"); 9658bd22949SKevin Hilman goto err2; 9668bd22949SKevin Hilman } 9678bd22949SKevin Hilman 968a23456e9SPeter 'p2' De Schrijver (void) clkdm_for_each(clkdms_setup, NULL); 9698bd22949SKevin Hilman 9708bd22949SKevin Hilman mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); 9718bd22949SKevin Hilman if (mpu_pwrdm == NULL) { 9728bd22949SKevin Hilman printk(KERN_ERR "Failed to get mpu_pwrdm\n"); 9738bd22949SKevin Hilman goto err2; 9748bd22949SKevin Hilman } 9758bd22949SKevin Hilman 976fa3c2a4fSRajendra Nayak neon_pwrdm = pwrdm_lookup("neon_pwrdm"); 977fa3c2a4fSRajendra Nayak per_pwrdm = pwrdm_lookup("per_pwrdm"); 978fa3c2a4fSRajendra Nayak core_pwrdm = pwrdm_lookup("core_pwrdm"); 979fa3c2a4fSRajendra Nayak 9803231fc88SRajendra Nayak omap_push_sram_idle(); 98110f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 9828bd22949SKevin Hilman suspend_set_ops(&omap_pm_ops); 98310f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 9848bd22949SKevin Hilman 9858bd22949SKevin Hilman pm_idle = omap3_pm_idle; 9868bd22949SKevin Hilman 987fa3c2a4fSRajendra Nayak pwrdm_add_wkdep(neon_pwrdm, mpu_pwrdm); 988fa3c2a4fSRajendra Nayak /* 989fa3c2a4fSRajendra Nayak * REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for 990fa3c2a4fSRajendra Nayak * IO-pad wakeup. Otherwise it will unnecessarily waste power 991fa3c2a4fSRajendra Nayak * waking up PER with every CORE wakeup - see 992fa3c2a4fSRajendra Nayak * http://marc.info/?l=linux-omap&m=121852150710062&w=2 993fa3c2a4fSRajendra Nayak */ 994fa3c2a4fSRajendra Nayak pwrdm_add_wkdep(per_pwrdm, core_pwrdm); 995fa3c2a4fSRajendra Nayak 99627d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) { 99727d59a4aSTero Kristo omap3_secure_ram_storage = 99827d59a4aSTero Kristo kmalloc(0x803F, GFP_KERNEL); 99927d59a4aSTero Kristo if (!omap3_secure_ram_storage) 100027d59a4aSTero Kristo printk(KERN_ERR "Memory allocation failed when" 100127d59a4aSTero Kristo "allocating for secure sram context\n"); 100227d59a4aSTero Kristo } 100327d59a4aSTero Kristo omap3_save_scratchpad_contents(); 100427d59a4aSTero Kristo 10058bd22949SKevin Hilman err1: 10068bd22949SKevin Hilman return ret; 10078bd22949SKevin Hilman err2: 10088bd22949SKevin Hilman free_irq(INT_34XX_PRCM_MPU_IRQ, NULL); 10098bd22949SKevin Hilman list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { 10108bd22949SKevin Hilman list_del(&pwrst->node); 10118bd22949SKevin Hilman kfree(pwrst); 10128bd22949SKevin Hilman } 10138bd22949SKevin Hilman return ret; 10148bd22949SKevin Hilman } 10158bd22949SKevin Hilman 10168bd22949SKevin Hilman late_initcall(omap3_pm_init); 1017