18bd22949SKevin Hilman /* 28bd22949SKevin Hilman * OMAP3 Power Management Routines 38bd22949SKevin Hilman * 48bd22949SKevin Hilman * Copyright (C) 2006-2008 Nokia Corporation 58bd22949SKevin Hilman * Tony Lindgren <tony@atomide.com> 68bd22949SKevin Hilman * Jouni Hogander 78bd22949SKevin Hilman * 88bd22949SKevin Hilman * Copyright (C) 2005 Texas Instruments, Inc. 98bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 108bd22949SKevin Hilman * 118bd22949SKevin Hilman * Based on pm.c for omap1 128bd22949SKevin Hilman * 138bd22949SKevin Hilman * This program is free software; you can redistribute it and/or modify 148bd22949SKevin Hilman * it under the terms of the GNU General Public License version 2 as 158bd22949SKevin Hilman * published by the Free Software Foundation. 168bd22949SKevin Hilman */ 178bd22949SKevin Hilman 188bd22949SKevin Hilman #include <linux/pm.h> 198bd22949SKevin Hilman #include <linux/suspend.h> 208bd22949SKevin Hilman #include <linux/interrupt.h> 218bd22949SKevin Hilman #include <linux/module.h> 228bd22949SKevin Hilman #include <linux/list.h> 238bd22949SKevin Hilman #include <linux/err.h> 248bd22949SKevin Hilman #include <linux/gpio.h> 258bd22949SKevin Hilman 268bd22949SKevin Hilman #include <mach/sram.h> 278bd22949SKevin Hilman #include <mach/clockdomain.h> 288bd22949SKevin Hilman #include <mach/powerdomain.h> 298bd22949SKevin Hilman #include <mach/control.h> 304af4016cSKevin Hilman #include <mach/serial.h> 318bd22949SKevin Hilman 328bd22949SKevin Hilman #include "cm.h" 338bd22949SKevin Hilman #include "cm-regbits-34xx.h" 348bd22949SKevin Hilman #include "prm-regbits-34xx.h" 358bd22949SKevin Hilman 368bd22949SKevin Hilman #include "prm.h" 378bd22949SKevin Hilman #include "pm.h" 388bd22949SKevin Hilman 398bd22949SKevin Hilman struct power_state { 408bd22949SKevin Hilman struct powerdomain *pwrdm; 418bd22949SKevin Hilman u32 next_state; 4210f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 438bd22949SKevin Hilman u32 saved_state; 4410f90ed2SKevin Hilman #endif 458bd22949SKevin Hilman struct list_head node; 468bd22949SKevin Hilman }; 478bd22949SKevin Hilman 488bd22949SKevin Hilman static LIST_HEAD(pwrst_list); 498bd22949SKevin Hilman 508bd22949SKevin Hilman static void (*_omap_sram_idle)(u32 *addr, int save_state); 518bd22949SKevin Hilman 528bd22949SKevin Hilman static struct powerdomain *mpu_pwrdm; 538bd22949SKevin Hilman 548bd22949SKevin Hilman /* PRCM Interrupt Handler for wakeups */ 558bd22949SKevin Hilman static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) 568bd22949SKevin Hilman { 578bd22949SKevin Hilman u32 wkst, irqstatus_mpu; 588bd22949SKevin Hilman u32 fclk, iclk; 598bd22949SKevin Hilman 608bd22949SKevin Hilman /* WKUP */ 618bd22949SKevin Hilman wkst = prm_read_mod_reg(WKUP_MOD, PM_WKST); 628bd22949SKevin Hilman if (wkst) { 638bd22949SKevin Hilman iclk = cm_read_mod_reg(WKUP_MOD, CM_ICLKEN); 648bd22949SKevin Hilman fclk = cm_read_mod_reg(WKUP_MOD, CM_FCLKEN); 658bd22949SKevin Hilman cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_ICLKEN); 668bd22949SKevin Hilman cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_FCLKEN); 678bd22949SKevin Hilman prm_write_mod_reg(wkst, WKUP_MOD, PM_WKST); 688bd22949SKevin Hilman while (prm_read_mod_reg(WKUP_MOD, PM_WKST)) 698bd22949SKevin Hilman cpu_relax(); 708bd22949SKevin Hilman cm_write_mod_reg(iclk, WKUP_MOD, CM_ICLKEN); 718bd22949SKevin Hilman cm_write_mod_reg(fclk, WKUP_MOD, CM_FCLKEN); 728bd22949SKevin Hilman } 738bd22949SKevin Hilman 748bd22949SKevin Hilman /* CORE */ 758bd22949SKevin Hilman wkst = prm_read_mod_reg(CORE_MOD, PM_WKST1); 768bd22949SKevin Hilman if (wkst) { 778bd22949SKevin Hilman iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN1); 788bd22949SKevin Hilman fclk = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); 798bd22949SKevin Hilman cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN1); 808bd22949SKevin Hilman cm_set_mod_reg_bits(wkst, CORE_MOD, CM_FCLKEN1); 818bd22949SKevin Hilman prm_write_mod_reg(wkst, CORE_MOD, PM_WKST1); 828bd22949SKevin Hilman while (prm_read_mod_reg(CORE_MOD, PM_WKST1)) 838bd22949SKevin Hilman cpu_relax(); 848bd22949SKevin Hilman cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN1); 858bd22949SKevin Hilman cm_write_mod_reg(fclk, CORE_MOD, CM_FCLKEN1); 868bd22949SKevin Hilman } 878bd22949SKevin Hilman wkst = prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3); 888bd22949SKevin Hilman if (wkst) { 898bd22949SKevin Hilman iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN3); 908bd22949SKevin Hilman fclk = cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3); 918bd22949SKevin Hilman cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN3); 928bd22949SKevin Hilman cm_set_mod_reg_bits(wkst, CORE_MOD, OMAP3430ES2_CM_FCLKEN3); 938bd22949SKevin Hilman prm_write_mod_reg(wkst, CORE_MOD, OMAP3430ES2_PM_WKST3); 948bd22949SKevin Hilman while (prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3)) 958bd22949SKevin Hilman cpu_relax(); 968bd22949SKevin Hilman cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN3); 978bd22949SKevin Hilman cm_write_mod_reg(fclk, CORE_MOD, OMAP3430ES2_CM_FCLKEN3); 988bd22949SKevin Hilman } 998bd22949SKevin Hilman 1008bd22949SKevin Hilman /* PER */ 1018bd22949SKevin Hilman wkst = prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST); 1028bd22949SKevin Hilman if (wkst) { 1038bd22949SKevin Hilman iclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN); 1048bd22949SKevin Hilman fclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN); 1058bd22949SKevin Hilman cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_ICLKEN); 1068bd22949SKevin Hilman cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_FCLKEN); 1078bd22949SKevin Hilman prm_write_mod_reg(wkst, OMAP3430_PER_MOD, PM_WKST); 1088bd22949SKevin Hilman while (prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST)) 1098bd22949SKevin Hilman cpu_relax(); 1108bd22949SKevin Hilman cm_write_mod_reg(iclk, OMAP3430_PER_MOD, CM_ICLKEN); 1118bd22949SKevin Hilman cm_write_mod_reg(fclk, OMAP3430_PER_MOD, CM_FCLKEN); 1128bd22949SKevin Hilman } 1138bd22949SKevin Hilman 1148bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 1158bd22949SKevin Hilman /* USBHOST */ 1168bd22949SKevin Hilman wkst = prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKST); 1178bd22949SKevin Hilman if (wkst) { 1188bd22949SKevin Hilman iclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, 1198bd22949SKevin Hilman CM_ICLKEN); 1208bd22949SKevin Hilman fclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, 1218bd22949SKevin Hilman CM_FCLKEN); 1228bd22949SKevin Hilman cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD, 1238bd22949SKevin Hilman CM_ICLKEN); 1248bd22949SKevin Hilman cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD, 1258bd22949SKevin Hilman CM_FCLKEN); 1268bd22949SKevin Hilman prm_write_mod_reg(wkst, OMAP3430ES2_USBHOST_MOD, 1278bd22949SKevin Hilman PM_WKST); 1288bd22949SKevin Hilman while (prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, 1298bd22949SKevin Hilman PM_WKST)) 1308bd22949SKevin Hilman cpu_relax(); 1318bd22949SKevin Hilman cm_write_mod_reg(iclk, OMAP3430ES2_USBHOST_MOD, 1328bd22949SKevin Hilman CM_ICLKEN); 1338bd22949SKevin Hilman cm_write_mod_reg(fclk, OMAP3430ES2_USBHOST_MOD, 1348bd22949SKevin Hilman CM_FCLKEN); 1358bd22949SKevin Hilman } 1368bd22949SKevin Hilman } 1378bd22949SKevin Hilman 1388bd22949SKevin Hilman irqstatus_mpu = prm_read_mod_reg(OCP_MOD, 1398bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 1408bd22949SKevin Hilman prm_write_mod_reg(irqstatus_mpu, OCP_MOD, 1418bd22949SKevin Hilman OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 1428bd22949SKevin Hilman 1438bd22949SKevin Hilman while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET)) 1448bd22949SKevin Hilman cpu_relax(); 1458bd22949SKevin Hilman 1468bd22949SKevin Hilman return IRQ_HANDLED; 1478bd22949SKevin Hilman } 1488bd22949SKevin Hilman 1498bd22949SKevin Hilman static void omap_sram_idle(void) 1508bd22949SKevin Hilman { 1518bd22949SKevin Hilman /* Variable to tell what needs to be saved and restored 1528bd22949SKevin Hilman * in omap_sram_idle*/ 1538bd22949SKevin Hilman /* save_state = 0 => Nothing to save and restored */ 1548bd22949SKevin Hilman /* save_state = 1 => Only L1 and logic lost */ 1558bd22949SKevin Hilman /* save_state = 2 => Only L2 lost */ 1568bd22949SKevin Hilman /* save_state = 3 => L1, L2 and logic lost */ 1578bd22949SKevin Hilman int save_state = 0, mpu_next_state; 1588bd22949SKevin Hilman 1598bd22949SKevin Hilman if (!_omap_sram_idle) 1608bd22949SKevin Hilman return; 1618bd22949SKevin Hilman 1628bd22949SKevin Hilman mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 1638bd22949SKevin Hilman switch (mpu_next_state) { 1648bd22949SKevin Hilman case PWRDM_POWER_RET: 1658bd22949SKevin Hilman /* No need to save context */ 1668bd22949SKevin Hilman save_state = 0; 1678bd22949SKevin Hilman break; 1688bd22949SKevin Hilman default: 1698bd22949SKevin Hilman /* Invalid state */ 1708bd22949SKevin Hilman printk(KERN_ERR "Invalid mpu state in sram_idle\n"); 1718bd22949SKevin Hilman return; 1728bd22949SKevin Hilman } 1738bd22949SKevin Hilman omap2_gpio_prepare_for_retention(); 1744af4016cSKevin Hilman omap_uart_prepare_idle(0); 1754af4016cSKevin Hilman omap_uart_prepare_idle(1); 1764af4016cSKevin Hilman omap_uart_prepare_idle(2); 1778bd22949SKevin Hilman 1788bd22949SKevin Hilman _omap_sram_idle(NULL, save_state); 1798bd22949SKevin Hilman cpu_init(); 1808bd22949SKevin Hilman 1814af4016cSKevin Hilman omap_uart_resume_idle(2); 1824af4016cSKevin Hilman omap_uart_resume_idle(1); 1834af4016cSKevin Hilman omap_uart_resume_idle(0); 1848bd22949SKevin Hilman omap2_gpio_resume_after_retention(); 1858bd22949SKevin Hilman } 1868bd22949SKevin Hilman 1878bd22949SKevin Hilman /* 1888bd22949SKevin Hilman * Check if functional clocks are enabled before entering 1898bd22949SKevin Hilman * sleep. This function could be behind CONFIG_PM_DEBUG 1908bd22949SKevin Hilman * when all drivers are configuring their sysconfig registers 1918bd22949SKevin Hilman * properly and using their clocks properly. 1928bd22949SKevin Hilman */ 1938bd22949SKevin Hilman static int omap3_fclks_active(void) 1948bd22949SKevin Hilman { 1958bd22949SKevin Hilman u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0, 1968bd22949SKevin Hilman fck_cam = 0, fck_per = 0, fck_usbhost = 0; 1978bd22949SKevin Hilman 1988bd22949SKevin Hilman fck_core1 = cm_read_mod_reg(CORE_MOD, 1998bd22949SKevin Hilman CM_FCLKEN1); 2008bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 2018bd22949SKevin Hilman fck_core3 = cm_read_mod_reg(CORE_MOD, 2028bd22949SKevin Hilman OMAP3430ES2_CM_FCLKEN3); 2038bd22949SKevin Hilman fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD, 2048bd22949SKevin Hilman CM_FCLKEN); 2058bd22949SKevin Hilman fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, 2068bd22949SKevin Hilman CM_FCLKEN); 2078bd22949SKevin Hilman } else 2088bd22949SKevin Hilman fck_sgx = cm_read_mod_reg(GFX_MOD, 2098bd22949SKevin Hilman OMAP3430ES2_CM_FCLKEN3); 2108bd22949SKevin Hilman fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD, 2118bd22949SKevin Hilman CM_FCLKEN); 2128bd22949SKevin Hilman fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD, 2138bd22949SKevin Hilman CM_FCLKEN); 2148bd22949SKevin Hilman fck_per = cm_read_mod_reg(OMAP3430_PER_MOD, 2158bd22949SKevin Hilman CM_FCLKEN); 2164af4016cSKevin Hilman 2174af4016cSKevin Hilman /* Ignore UART clocks. These are handled by UART core (serial.c) */ 2184af4016cSKevin Hilman fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2); 2194af4016cSKevin Hilman fck_per &= ~OMAP3430_EN_UART3; 2204af4016cSKevin Hilman 2218bd22949SKevin Hilman if (fck_core1 | fck_core3 | fck_sgx | fck_dss | 2228bd22949SKevin Hilman fck_cam | fck_per | fck_usbhost) 2238bd22949SKevin Hilman return 1; 2248bd22949SKevin Hilman return 0; 2258bd22949SKevin Hilman } 2268bd22949SKevin Hilman 2278bd22949SKevin Hilman static int omap3_can_sleep(void) 2288bd22949SKevin Hilman { 2294af4016cSKevin Hilman if (!omap_uart_can_sleep()) 2304af4016cSKevin Hilman return 0; 2318bd22949SKevin Hilman if (omap3_fclks_active()) 2328bd22949SKevin Hilman return 0; 2338bd22949SKevin Hilman return 1; 2348bd22949SKevin Hilman } 2358bd22949SKevin Hilman 2368bd22949SKevin Hilman /* This sets pwrdm state (other than mpu & core. Currently only ON & 2378bd22949SKevin Hilman * RET are supported. Function is assuming that clkdm doesn't have 2388bd22949SKevin Hilman * hw_sup mode enabled. */ 2398bd22949SKevin Hilman static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state) 2408bd22949SKevin Hilman { 2418bd22949SKevin Hilman u32 cur_state; 2428bd22949SKevin Hilman int sleep_switch = 0; 2438bd22949SKevin Hilman int ret = 0; 2448bd22949SKevin Hilman 2458bd22949SKevin Hilman if (pwrdm == NULL || IS_ERR(pwrdm)) 2468bd22949SKevin Hilman return -EINVAL; 2478bd22949SKevin Hilman 2488bd22949SKevin Hilman while (!(pwrdm->pwrsts & (1 << state))) { 2498bd22949SKevin Hilman if (state == PWRDM_POWER_OFF) 2508bd22949SKevin Hilman return ret; 2518bd22949SKevin Hilman state--; 2528bd22949SKevin Hilman } 2538bd22949SKevin Hilman 2548bd22949SKevin Hilman cur_state = pwrdm_read_next_pwrst(pwrdm); 2558bd22949SKevin Hilman if (cur_state == state) 2568bd22949SKevin Hilman return ret; 2578bd22949SKevin Hilman 2588bd22949SKevin Hilman if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) { 2598bd22949SKevin Hilman omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); 2608bd22949SKevin Hilman sleep_switch = 1; 2618bd22949SKevin Hilman pwrdm_wait_transition(pwrdm); 2628bd22949SKevin Hilman } 2638bd22949SKevin Hilman 2648bd22949SKevin Hilman ret = pwrdm_set_next_pwrst(pwrdm, state); 2658bd22949SKevin Hilman if (ret) { 2668bd22949SKevin Hilman printk(KERN_ERR "Unable to set state of powerdomain: %s\n", 2678bd22949SKevin Hilman pwrdm->name); 2688bd22949SKevin Hilman goto err; 2698bd22949SKevin Hilman } 2708bd22949SKevin Hilman 2718bd22949SKevin Hilman if (sleep_switch) { 2728bd22949SKevin Hilman omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); 2738bd22949SKevin Hilman pwrdm_wait_transition(pwrdm); 2748bd22949SKevin Hilman } 2758bd22949SKevin Hilman 2768bd22949SKevin Hilman err: 2778bd22949SKevin Hilman return ret; 2788bd22949SKevin Hilman } 2798bd22949SKevin Hilman 2808bd22949SKevin Hilman static void omap3_pm_idle(void) 2818bd22949SKevin Hilman { 2828bd22949SKevin Hilman local_irq_disable(); 2838bd22949SKevin Hilman local_fiq_disable(); 2848bd22949SKevin Hilman 2858bd22949SKevin Hilman if (!omap3_can_sleep()) 2868bd22949SKevin Hilman goto out; 2878bd22949SKevin Hilman 2888bd22949SKevin Hilman if (omap_irq_pending()) 2898bd22949SKevin Hilman goto out; 2908bd22949SKevin Hilman 2918bd22949SKevin Hilman omap_sram_idle(); 2928bd22949SKevin Hilman 2938bd22949SKevin Hilman out: 2948bd22949SKevin Hilman local_fiq_enable(); 2958bd22949SKevin Hilman local_irq_enable(); 2968bd22949SKevin Hilman } 2978bd22949SKevin Hilman 29810f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 2992466211eSTero Kristo static suspend_state_t suspend_state; 3002466211eSTero Kristo 3018bd22949SKevin Hilman static int omap3_pm_prepare(void) 3028bd22949SKevin Hilman { 3038bd22949SKevin Hilman disable_hlt(); 3048bd22949SKevin Hilman return 0; 3058bd22949SKevin Hilman } 3068bd22949SKevin Hilman 3078bd22949SKevin Hilman static int omap3_pm_suspend(void) 3088bd22949SKevin Hilman { 3098bd22949SKevin Hilman struct power_state *pwrst; 3108bd22949SKevin Hilman int state, ret = 0; 3118bd22949SKevin Hilman 3128bd22949SKevin Hilman /* Read current next_pwrsts */ 3138bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) 3148bd22949SKevin Hilman pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 3158bd22949SKevin Hilman /* Set ones wanted by suspend */ 3168bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 3178bd22949SKevin Hilman if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) 3188bd22949SKevin Hilman goto restore; 3198bd22949SKevin Hilman if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) 3208bd22949SKevin Hilman goto restore; 3218bd22949SKevin Hilman } 3228bd22949SKevin Hilman 3234af4016cSKevin Hilman omap_uart_prepare_suspend(); 3248bd22949SKevin Hilman omap_sram_idle(); 3258bd22949SKevin Hilman 3268bd22949SKevin Hilman restore: 3278bd22949SKevin Hilman /* Restore next_pwrsts */ 3288bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) { 3298bd22949SKevin Hilman set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); 3308bd22949SKevin Hilman state = pwrdm_read_prev_pwrst(pwrst->pwrdm); 3318bd22949SKevin Hilman if (state > pwrst->next_state) { 3328bd22949SKevin Hilman printk(KERN_INFO "Powerdomain (%s) didn't enter " 3338bd22949SKevin Hilman "target state %d\n", 3348bd22949SKevin Hilman pwrst->pwrdm->name, pwrst->next_state); 3358bd22949SKevin Hilman ret = -1; 3368bd22949SKevin Hilman } 3378bd22949SKevin Hilman } 3388bd22949SKevin Hilman if (ret) 3398bd22949SKevin Hilman printk(KERN_ERR "Could not enter target state in pm_suspend\n"); 3408bd22949SKevin Hilman else 3418bd22949SKevin Hilman printk(KERN_INFO "Successfully put all powerdomains " 3428bd22949SKevin Hilman "to target state\n"); 3438bd22949SKevin Hilman 3448bd22949SKevin Hilman return ret; 3458bd22949SKevin Hilman } 3468bd22949SKevin Hilman 3472466211eSTero Kristo static int omap3_pm_enter(suspend_state_t unused) 3488bd22949SKevin Hilman { 3498bd22949SKevin Hilman int ret = 0; 3508bd22949SKevin Hilman 3512466211eSTero Kristo switch (suspend_state) { 3528bd22949SKevin Hilman case PM_SUSPEND_STANDBY: 3538bd22949SKevin Hilman case PM_SUSPEND_MEM: 3548bd22949SKevin Hilman ret = omap3_pm_suspend(); 3558bd22949SKevin Hilman break; 3568bd22949SKevin Hilman default: 3578bd22949SKevin Hilman ret = -EINVAL; 3588bd22949SKevin Hilman } 3598bd22949SKevin Hilman 3608bd22949SKevin Hilman return ret; 3618bd22949SKevin Hilman } 3628bd22949SKevin Hilman 3638bd22949SKevin Hilman static void omap3_pm_finish(void) 3648bd22949SKevin Hilman { 3658bd22949SKevin Hilman enable_hlt(); 3668bd22949SKevin Hilman } 3678bd22949SKevin Hilman 3682466211eSTero Kristo /* Hooks to enable / disable UART interrupts during suspend */ 3692466211eSTero Kristo static int omap3_pm_begin(suspend_state_t state) 3702466211eSTero Kristo { 3712466211eSTero Kristo suspend_state = state; 3722466211eSTero Kristo omap_uart_enable_irqs(0); 3732466211eSTero Kristo return 0; 3742466211eSTero Kristo } 3752466211eSTero Kristo 3762466211eSTero Kristo static void omap3_pm_end(void) 3772466211eSTero Kristo { 3782466211eSTero Kristo suspend_state = PM_SUSPEND_ON; 3792466211eSTero Kristo omap_uart_enable_irqs(1); 3802466211eSTero Kristo return; 3812466211eSTero Kristo } 3822466211eSTero Kristo 3838bd22949SKevin Hilman static struct platform_suspend_ops omap_pm_ops = { 3842466211eSTero Kristo .begin = omap3_pm_begin, 3852466211eSTero Kristo .end = omap3_pm_end, 3868bd22949SKevin Hilman .prepare = omap3_pm_prepare, 3878bd22949SKevin Hilman .enter = omap3_pm_enter, 3888bd22949SKevin Hilman .finish = omap3_pm_finish, 3898bd22949SKevin Hilman .valid = suspend_valid_only_mem, 3908bd22949SKevin Hilman }; 39110f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 3928bd22949SKevin Hilman 3931155e426SKevin Hilman 3941155e426SKevin Hilman /** 3951155e426SKevin Hilman * omap3_iva_idle(): ensure IVA is in idle so it can be put into 3961155e426SKevin Hilman * retention 3971155e426SKevin Hilman * 3981155e426SKevin Hilman * In cases where IVA2 is activated by bootcode, it may prevent 3991155e426SKevin Hilman * full-chip retention or off-mode because it is not idle. This 4001155e426SKevin Hilman * function forces the IVA2 into idle state so it can go 4011155e426SKevin Hilman * into retention/off and thus allow full-chip retention/off. 4021155e426SKevin Hilman * 4031155e426SKevin Hilman **/ 4041155e426SKevin Hilman static void __init omap3_iva_idle(void) 4051155e426SKevin Hilman { 4061155e426SKevin Hilman /* ensure IVA2 clock is disabled */ 4071155e426SKevin Hilman cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 4081155e426SKevin Hilman 4091155e426SKevin Hilman /* if no clock activity, nothing else to do */ 4101155e426SKevin Hilman if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & 4111155e426SKevin Hilman OMAP3430_CLKACTIVITY_IVA2_MASK)) 4121155e426SKevin Hilman return; 4131155e426SKevin Hilman 4141155e426SKevin Hilman /* Reset IVA2 */ 4151155e426SKevin Hilman prm_write_mod_reg(OMAP3430_RST1_IVA2 | 4161155e426SKevin Hilman OMAP3430_RST2_IVA2 | 4171155e426SKevin Hilman OMAP3430_RST3_IVA2, 4181155e426SKevin Hilman OMAP3430_IVA2_MOD, RM_RSTCTRL); 4191155e426SKevin Hilman 4201155e426SKevin Hilman /* Enable IVA2 clock */ 4211155e426SKevin Hilman cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2, 4221155e426SKevin Hilman OMAP3430_IVA2_MOD, CM_FCLKEN); 4231155e426SKevin Hilman 4241155e426SKevin Hilman /* Set IVA2 boot mode to 'idle' */ 4251155e426SKevin Hilman omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, 4261155e426SKevin Hilman OMAP343X_CONTROL_IVA2_BOOTMOD); 4271155e426SKevin Hilman 4281155e426SKevin Hilman /* Un-reset IVA2 */ 4291155e426SKevin Hilman prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL); 4301155e426SKevin Hilman 4311155e426SKevin Hilman /* Disable IVA2 clock */ 4321155e426SKevin Hilman cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 4331155e426SKevin Hilman 4341155e426SKevin Hilman /* Reset IVA2 */ 4351155e426SKevin Hilman prm_write_mod_reg(OMAP3430_RST1_IVA2 | 4361155e426SKevin Hilman OMAP3430_RST2_IVA2 | 4371155e426SKevin Hilman OMAP3430_RST3_IVA2, 4381155e426SKevin Hilman OMAP3430_IVA2_MOD, RM_RSTCTRL); 4391155e426SKevin Hilman } 4401155e426SKevin Hilman 4418111b221SKevin Hilman static void __init omap3_d2d_idle(void) 4428bd22949SKevin Hilman { 4438111b221SKevin Hilman u16 mask, padconf; 4448111b221SKevin Hilman 4458111b221SKevin Hilman /* In a stand alone OMAP3430 where there is not a stacked 4468111b221SKevin Hilman * modem for the D2D Idle Ack and D2D MStandby must be pulled 4478111b221SKevin Hilman * high. S CONTROL_PADCONF_SAD2D_IDLEACK and 4488111b221SKevin Hilman * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ 4498111b221SKevin Hilman mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ 4508111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); 4518111b221SKevin Hilman padconf |= mask; 4528111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); 4538111b221SKevin Hilman 4548111b221SKevin Hilman padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); 4558111b221SKevin Hilman padconf |= mask; 4568111b221SKevin Hilman omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 4578111b221SKevin Hilman 4588bd22949SKevin Hilman /* reset modem */ 4598bd22949SKevin Hilman prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON | 4608bd22949SKevin Hilman OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST, 4618bd22949SKevin Hilman CORE_MOD, RM_RSTCTRL); 4628bd22949SKevin Hilman prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL); 4638111b221SKevin Hilman } 4648bd22949SKevin Hilman 4658111b221SKevin Hilman static void __init prcm_setup_regs(void) 4668111b221SKevin Hilman { 4678bd22949SKevin Hilman /* XXX Reset all wkdeps. This should be done when initializing 4688bd22949SKevin Hilman * powerdomains */ 4698bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); 4708bd22949SKevin Hilman prm_write_mod_reg(0, MPU_MOD, PM_WKDEP); 4718bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP); 4728bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP); 4738bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP); 4748bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP); 4758bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 4768bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP); 4778bd22949SKevin Hilman prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP); 4788bd22949SKevin Hilman } else 4798bd22949SKevin Hilman prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); 4808bd22949SKevin Hilman 4818bd22949SKevin Hilman /* 4828bd22949SKevin Hilman * Enable interface clock autoidle for all modules. 4838bd22949SKevin Hilman * Note that in the long run this should be done by clockfw 4848bd22949SKevin Hilman */ 4858bd22949SKevin Hilman cm_write_mod_reg( 4868111b221SKevin Hilman OMAP3430_AUTO_MODEM | 4878bd22949SKevin Hilman OMAP3430ES2_AUTO_MMC3 | 4888bd22949SKevin Hilman OMAP3430ES2_AUTO_ICR | 4898bd22949SKevin Hilman OMAP3430_AUTO_AES2 | 4908bd22949SKevin Hilman OMAP3430_AUTO_SHA12 | 4918bd22949SKevin Hilman OMAP3430_AUTO_DES2 | 4928bd22949SKevin Hilman OMAP3430_AUTO_MMC2 | 4938bd22949SKevin Hilman OMAP3430_AUTO_MMC1 | 4948bd22949SKevin Hilman OMAP3430_AUTO_MSPRO | 4958bd22949SKevin Hilman OMAP3430_AUTO_HDQ | 4968bd22949SKevin Hilman OMAP3430_AUTO_MCSPI4 | 4978bd22949SKevin Hilman OMAP3430_AUTO_MCSPI3 | 4988bd22949SKevin Hilman OMAP3430_AUTO_MCSPI2 | 4998bd22949SKevin Hilman OMAP3430_AUTO_MCSPI1 | 5008bd22949SKevin Hilman OMAP3430_AUTO_I2C3 | 5018bd22949SKevin Hilman OMAP3430_AUTO_I2C2 | 5028bd22949SKevin Hilman OMAP3430_AUTO_I2C1 | 5038bd22949SKevin Hilman OMAP3430_AUTO_UART2 | 5048bd22949SKevin Hilman OMAP3430_AUTO_UART1 | 5058bd22949SKevin Hilman OMAP3430_AUTO_GPT11 | 5068bd22949SKevin Hilman OMAP3430_AUTO_GPT10 | 5078bd22949SKevin Hilman OMAP3430_AUTO_MCBSP5 | 5088bd22949SKevin Hilman OMAP3430_AUTO_MCBSP1 | 5098bd22949SKevin Hilman OMAP3430ES1_AUTO_FAC | /* This is es1 only */ 5108bd22949SKevin Hilman OMAP3430_AUTO_MAILBOXES | 5118bd22949SKevin Hilman OMAP3430_AUTO_OMAPCTRL | 5128bd22949SKevin Hilman OMAP3430ES1_AUTO_FSHOSTUSB | 5138bd22949SKevin Hilman OMAP3430_AUTO_HSOTGUSB | 5148111b221SKevin Hilman OMAP3430_AUTO_SAD2D | 5158bd22949SKevin Hilman OMAP3430_AUTO_SSI, 5168bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE1); 5178bd22949SKevin Hilman 5188bd22949SKevin Hilman cm_write_mod_reg( 5198bd22949SKevin Hilman OMAP3430_AUTO_PKA | 5208bd22949SKevin Hilman OMAP3430_AUTO_AES1 | 5218bd22949SKevin Hilman OMAP3430_AUTO_RNG | 5228bd22949SKevin Hilman OMAP3430_AUTO_SHA11 | 5238bd22949SKevin Hilman OMAP3430_AUTO_DES1, 5248bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE2); 5258bd22949SKevin Hilman 5268bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 5278bd22949SKevin Hilman cm_write_mod_reg( 5288111b221SKevin Hilman OMAP3430_AUTO_MAD2D | 5298bd22949SKevin Hilman OMAP3430ES2_AUTO_USBTLL, 5308bd22949SKevin Hilman CORE_MOD, CM_AUTOIDLE3); 5318bd22949SKevin Hilman } 5328bd22949SKevin Hilman 5338bd22949SKevin Hilman cm_write_mod_reg( 5348bd22949SKevin Hilman OMAP3430_AUTO_WDT2 | 5358bd22949SKevin Hilman OMAP3430_AUTO_WDT1 | 5368bd22949SKevin Hilman OMAP3430_AUTO_GPIO1 | 5378bd22949SKevin Hilman OMAP3430_AUTO_32KSYNC | 5388bd22949SKevin Hilman OMAP3430_AUTO_GPT12 | 5398bd22949SKevin Hilman OMAP3430_AUTO_GPT1 , 5408bd22949SKevin Hilman WKUP_MOD, CM_AUTOIDLE); 5418bd22949SKevin Hilman 5428bd22949SKevin Hilman cm_write_mod_reg( 5438bd22949SKevin Hilman OMAP3430_AUTO_DSS, 5448bd22949SKevin Hilman OMAP3430_DSS_MOD, 5458bd22949SKevin Hilman CM_AUTOIDLE); 5468bd22949SKevin Hilman 5478bd22949SKevin Hilman cm_write_mod_reg( 5488bd22949SKevin Hilman OMAP3430_AUTO_CAM, 5498bd22949SKevin Hilman OMAP3430_CAM_MOD, 5508bd22949SKevin Hilman CM_AUTOIDLE); 5518bd22949SKevin Hilman 5528bd22949SKevin Hilman cm_write_mod_reg( 5538bd22949SKevin Hilman OMAP3430_AUTO_GPIO6 | 5548bd22949SKevin Hilman OMAP3430_AUTO_GPIO5 | 5558bd22949SKevin Hilman OMAP3430_AUTO_GPIO4 | 5568bd22949SKevin Hilman OMAP3430_AUTO_GPIO3 | 5578bd22949SKevin Hilman OMAP3430_AUTO_GPIO2 | 5588bd22949SKevin Hilman OMAP3430_AUTO_WDT3 | 5598bd22949SKevin Hilman OMAP3430_AUTO_UART3 | 5608bd22949SKevin Hilman OMAP3430_AUTO_GPT9 | 5618bd22949SKevin Hilman OMAP3430_AUTO_GPT8 | 5628bd22949SKevin Hilman OMAP3430_AUTO_GPT7 | 5638bd22949SKevin Hilman OMAP3430_AUTO_GPT6 | 5648bd22949SKevin Hilman OMAP3430_AUTO_GPT5 | 5658bd22949SKevin Hilman OMAP3430_AUTO_GPT4 | 5668bd22949SKevin Hilman OMAP3430_AUTO_GPT3 | 5678bd22949SKevin Hilman OMAP3430_AUTO_GPT2 | 5688bd22949SKevin Hilman OMAP3430_AUTO_MCBSP4 | 5698bd22949SKevin Hilman OMAP3430_AUTO_MCBSP3 | 5708bd22949SKevin Hilman OMAP3430_AUTO_MCBSP2, 5718bd22949SKevin Hilman OMAP3430_PER_MOD, 5728bd22949SKevin Hilman CM_AUTOIDLE); 5738bd22949SKevin Hilman 5748bd22949SKevin Hilman if (omap_rev() > OMAP3430_REV_ES1_0) { 5758bd22949SKevin Hilman cm_write_mod_reg( 5768bd22949SKevin Hilman OMAP3430ES2_AUTO_USBHOST, 5778bd22949SKevin Hilman OMAP3430ES2_USBHOST_MOD, 5788bd22949SKevin Hilman CM_AUTOIDLE); 5798bd22949SKevin Hilman } 5808bd22949SKevin Hilman 5818bd22949SKevin Hilman /* 5828bd22949SKevin Hilman * Set all plls to autoidle. This is needed until autoidle is 5838bd22949SKevin Hilman * enabled by clockfw 5848bd22949SKevin Hilman */ 5858bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, 5868bd22949SKevin Hilman OMAP3430_IVA2_MOD, CM_AUTOIDLE2); 5878bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT, 5888bd22949SKevin Hilman MPU_MOD, 5898bd22949SKevin Hilman CM_AUTOIDLE2); 5908bd22949SKevin Hilman cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | 5918bd22949SKevin Hilman (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT), 5928bd22949SKevin Hilman PLL_MOD, 5938bd22949SKevin Hilman CM_AUTOIDLE); 5948bd22949SKevin Hilman cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, 5958bd22949SKevin Hilman PLL_MOD, 5968bd22949SKevin Hilman CM_AUTOIDLE2); 5978bd22949SKevin Hilman 5988bd22949SKevin Hilman /* 5998bd22949SKevin Hilman * Enable control of expternal oscillator through 6008bd22949SKevin Hilman * sys_clkreq. In the long run clock framework should 6018bd22949SKevin Hilman * take care of this. 6028bd22949SKevin Hilman */ 6038bd22949SKevin Hilman prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 6048bd22949SKevin Hilman 1 << OMAP_AUTOEXTCLKMODE_SHIFT, 6058bd22949SKevin Hilman OMAP3430_GR_MOD, 6068bd22949SKevin Hilman OMAP3_PRM_CLKSRC_CTRL_OFFSET); 6078bd22949SKevin Hilman 6088bd22949SKevin Hilman /* setup wakup source */ 6098bd22949SKevin Hilman prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 | 6108bd22949SKevin Hilman OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12, 6118bd22949SKevin Hilman WKUP_MOD, PM_WKEN); 6128bd22949SKevin Hilman /* No need to write EN_IO, that is always enabled */ 6138bd22949SKevin Hilman prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 | 6148bd22949SKevin Hilman OMAP3430_EN_GPT12, 6158bd22949SKevin Hilman WKUP_MOD, OMAP3430_PM_MPUGRPSEL); 6168bd22949SKevin Hilman /* For some reason IO doesn't generate wakeup event even if 6178bd22949SKevin Hilman * it is selected to mpu wakeup goup */ 6188bd22949SKevin Hilman prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN, 6198bd22949SKevin Hilman OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); 6201155e426SKevin Hilman 621d3fd3290SKevin Hilman /* Don't attach IVA interrupts */ 622d3fd3290SKevin Hilman prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 623d3fd3290SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 624d3fd3290SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 625d3fd3290SKevin Hilman prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); 626d3fd3290SKevin Hilman 627b1340d17SKevin Hilman /* Clear any pending 'reset' flags */ 628b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST); 629b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST); 630b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST); 631b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST); 632b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST); 633b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST); 634b1340d17SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST); 635b1340d17SKevin Hilman 636014c46dbSKevin Hilman /* Clear any pending PRCM interrupts */ 637014c46dbSKevin Hilman prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 638014c46dbSKevin Hilman 639040fed05SKevin Hilman /* Don't attach IVA interrupts */ 640040fed05SKevin Hilman prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 641040fed05SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 642040fed05SKevin Hilman prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 643040fed05SKevin Hilman prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); 644040fed05SKevin Hilman 6453a07ae30SKevin Hilman /* Clear any pending 'reset' flags */ 6463a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST); 6473a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST); 6483a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST); 6493a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST); 6503a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST); 6513a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST); 6523a07ae30SKevin Hilman prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST); 6533a07ae30SKevin Hilman 6543a6667acSKevin Hilman /* Clear any pending PRCM interrupts */ 6553a6667acSKevin Hilman prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 6563a6667acSKevin Hilman 6571155e426SKevin Hilman omap3_iva_idle(); 6588111b221SKevin Hilman omap3_d2d_idle(); 6598bd22949SKevin Hilman } 6608bd22949SKevin Hilman 6618bd22949SKevin Hilman static int __init pwrdms_setup(struct powerdomain *pwrdm) 6628bd22949SKevin Hilman { 6638bd22949SKevin Hilman struct power_state *pwrst; 6648bd22949SKevin Hilman 6658bd22949SKevin Hilman if (!pwrdm->pwrsts) 6668bd22949SKevin Hilman return 0; 6678bd22949SKevin Hilman 6688bd22949SKevin Hilman pwrst = kmalloc(sizeof(struct power_state), GFP_KERNEL); 6698bd22949SKevin Hilman if (!pwrst) 6708bd22949SKevin Hilman return -ENOMEM; 6718bd22949SKevin Hilman pwrst->pwrdm = pwrdm; 6728bd22949SKevin Hilman pwrst->next_state = PWRDM_POWER_RET; 6738bd22949SKevin Hilman list_add(&pwrst->node, &pwrst_list); 6748bd22949SKevin Hilman 6758bd22949SKevin Hilman if (pwrdm_has_hdwr_sar(pwrdm)) 6768bd22949SKevin Hilman pwrdm_enable_hdwr_sar(pwrdm); 6778bd22949SKevin Hilman 6788bd22949SKevin Hilman return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 6798bd22949SKevin Hilman } 6808bd22949SKevin Hilman 6818bd22949SKevin Hilman /* 6828bd22949SKevin Hilman * Enable hw supervised mode for all clockdomains if it's 6838bd22949SKevin Hilman * supported. Initiate sleep transition for other clockdomains, if 6848bd22949SKevin Hilman * they are not used 6858bd22949SKevin Hilman */ 6868bd22949SKevin Hilman static int __init clkdms_setup(struct clockdomain *clkdm) 6878bd22949SKevin Hilman { 6888bd22949SKevin Hilman if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) 6898bd22949SKevin Hilman omap2_clkdm_allow_idle(clkdm); 6908bd22949SKevin Hilman else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && 6918bd22949SKevin Hilman atomic_read(&clkdm->usecount) == 0) 6928bd22949SKevin Hilman omap2_clkdm_sleep(clkdm); 6938bd22949SKevin Hilman return 0; 6948bd22949SKevin Hilman } 6958bd22949SKevin Hilman 6967cc515f7SKevin Hilman static int __init omap3_pm_init(void) 6978bd22949SKevin Hilman { 6988bd22949SKevin Hilman struct power_state *pwrst, *tmp; 6998bd22949SKevin Hilman int ret; 7008bd22949SKevin Hilman 7018bd22949SKevin Hilman if (!cpu_is_omap34xx()) 7028bd22949SKevin Hilman return -ENODEV; 7038bd22949SKevin Hilman 7048bd22949SKevin Hilman printk(KERN_ERR "Power Management for TI OMAP3.\n"); 7058bd22949SKevin Hilman 7068bd22949SKevin Hilman /* XXX prcm_setup_regs needs to be before enabling hw 7078bd22949SKevin Hilman * supervised mode for powerdomains */ 7088bd22949SKevin Hilman prcm_setup_regs(); 7098bd22949SKevin Hilman 7108bd22949SKevin Hilman ret = request_irq(INT_34XX_PRCM_MPU_IRQ, 7118bd22949SKevin Hilman (irq_handler_t)prcm_interrupt_handler, 7128bd22949SKevin Hilman IRQF_DISABLED, "prcm", NULL); 7138bd22949SKevin Hilman if (ret) { 7148bd22949SKevin Hilman printk(KERN_ERR "request_irq failed to register for 0x%x\n", 7158bd22949SKevin Hilman INT_34XX_PRCM_MPU_IRQ); 7168bd22949SKevin Hilman goto err1; 7178bd22949SKevin Hilman } 7188bd22949SKevin Hilman 7198bd22949SKevin Hilman ret = pwrdm_for_each(pwrdms_setup); 7208bd22949SKevin Hilman if (ret) { 7218bd22949SKevin Hilman printk(KERN_ERR "Failed to setup powerdomains\n"); 7228bd22949SKevin Hilman goto err2; 7238bd22949SKevin Hilman } 7248bd22949SKevin Hilman 7258bd22949SKevin Hilman (void) clkdm_for_each(clkdms_setup); 7268bd22949SKevin Hilman 7278bd22949SKevin Hilman mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); 7288bd22949SKevin Hilman if (mpu_pwrdm == NULL) { 7298bd22949SKevin Hilman printk(KERN_ERR "Failed to get mpu_pwrdm\n"); 7308bd22949SKevin Hilman goto err2; 7318bd22949SKevin Hilman } 7328bd22949SKevin Hilman 7338bd22949SKevin Hilman _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend, 7348bd22949SKevin Hilman omap34xx_cpu_suspend_sz); 7358bd22949SKevin Hilman 73610f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND 7378bd22949SKevin Hilman suspend_set_ops(&omap_pm_ops); 73810f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */ 7398bd22949SKevin Hilman 7408bd22949SKevin Hilman pm_idle = omap3_pm_idle; 7418bd22949SKevin Hilman 7428bd22949SKevin Hilman err1: 7438bd22949SKevin Hilman return ret; 7448bd22949SKevin Hilman err2: 7458bd22949SKevin Hilman free_irq(INT_34XX_PRCM_MPU_IRQ, NULL); 7468bd22949SKevin Hilman list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { 7478bd22949SKevin Hilman list_del(&pwrst->node); 7488bd22949SKevin Hilman kfree(pwrst); 7498bd22949SKevin Hilman } 7508bd22949SKevin Hilman return ret; 7518bd22949SKevin Hilman } 7528bd22949SKevin Hilman 7538bd22949SKevin Hilman late_initcall(omap3_pm_init); 754