1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
28bd22949SKevin Hilman /*
38bd22949SKevin Hilman * OMAP3 Power Management Routines
48bd22949SKevin Hilman *
58bd22949SKevin Hilman * Copyright (C) 2006-2008 Nokia Corporation
68bd22949SKevin Hilman * Tony Lindgren <tony@atomide.com>
78bd22949SKevin Hilman * Jouni Hogander
88bd22949SKevin Hilman *
92f5939c3SRajendra Nayak * Copyright (C) 2007 Texas Instruments, Inc.
102f5939c3SRajendra Nayak * Rajendra Nayak <rnayak@ti.com>
112f5939c3SRajendra Nayak *
128bd22949SKevin Hilman * Copyright (C) 2005 Texas Instruments, Inc.
138bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com>
148bd22949SKevin Hilman *
158bd22949SKevin Hilman * Based on pm.c for omap1
168bd22949SKevin Hilman */
178bd22949SKevin Hilman
18b764a586STony Lindgren #include <linux/cpu_pm.h>
198bd22949SKevin Hilman #include <linux/pm.h>
208bd22949SKevin Hilman #include <linux/suspend.h>
218bd22949SKevin Hilman #include <linux/interrupt.h>
228bd22949SKevin Hilman #include <linux/module.h>
238bd22949SKevin Hilman #include <linux/list.h>
248bd22949SKevin Hilman #include <linux/err.h>
25c40552bcSKevin Hilman #include <linux/clk.h>
26dccaad89STero Kristo #include <linux/delay.h>
275a0e3ad6STejun Heo #include <linux/slab.h>
28fb2c599fSAndreas Kemnade #include <linux/of.h>
298c0956aaSPeter Zijlstra #include <linux/cpuidle.h>
304b25408fSTony Lindgren
315e7c58dcSJean Pihet #include <trace/events/power.h>
328bd22949SKevin Hilman
33bf027ca1STony Lindgren #include <asm/fncpy.h>
342c74a0ceSRussell King #include <asm/suspend.h>
359f97da78SDavid Howells #include <asm/system_misc.h>
362c74a0ceSRussell King
371540f214SPaul Walmsley #include "clockdomain.h"
3872e06d08SPaul Walmsley #include "powerdomain.h"
39e4c060dbSTony Lindgren #include "soc.h"
404e65331cSTony Lindgren #include "common.h"
41ff4ae5d9SPaul Walmsley #include "cm3xxx.h"
428bd22949SKevin Hilman #include "cm-regbits-34xx.h"
438bd22949SKevin Hilman #include "prm-regbits-34xx.h"
44139563adSPaul Walmsley #include "prm3xxx.h"
458bd22949SKevin Hilman #include "pm.h"
4613a6fe0fSTero Kristo #include "sdrc.h"
47d09220a8STony Lindgren #include "omap-secure.h"
48bf027ca1STony Lindgren #include "sram.h"
494814ced5SPaul Walmsley #include "control.h"
503b8c4ebbSTony Lindgren #include "vc.h"
5113a6fe0fSTero Kristo
528cdfd834SNishanth Menon /* pm34xx errata defined in pm.h */
538cdfd834SNishanth Menon u16 pm34xx_errata;
548cdfd834SNishanth Menon
558bd22949SKevin Hilman struct power_state {
568bd22949SKevin Hilman struct powerdomain *pwrdm;
578bd22949SKevin Hilman u32 next_state;
5810f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND
598bd22949SKevin Hilman u32 saved_state;
6010f90ed2SKevin Hilman #endif
618bd22949SKevin Hilman struct list_head node;
628bd22949SKevin Hilman };
638bd22949SKevin Hilman
648bd22949SKevin Hilman static LIST_HEAD(pwrst_list);
658bd22949SKevin Hilman
6646e130d2SJean Pihet void (*omap3_do_wfi_sram)(void);
6727d59a4aSTero Kristo
68fa3c2a4fSRajendra Nayak static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
69fa3c2a4fSRajendra Nayak static struct powerdomain *core_pwrdm, *per_pwrdm;
703a7ec26bSKalle Jokiniemi
omap3_core_save_context(void)712f5939c3SRajendra Nayak static void omap3_core_save_context(void)
722f5939c3SRajendra Nayak {
73596efe47SPaul Walmsley omap3_ctrl_save_padconf();
74dccaad89STero Kristo
75dccaad89STero Kristo /*
76dccaad89STero Kristo * Force write last pad into memory, as this can fail in some
7783521291SJean Pihet * cases according to errata 1.157, 1.185
78dccaad89STero Kristo */
79dccaad89STero Kristo omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
80dccaad89STero Kristo OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
81dccaad89STero Kristo
822f5939c3SRajendra Nayak /* Save the Interrupt controller context */
832f5939c3SRajendra Nayak omap_intc_save_context();
842f5939c3SRajendra Nayak /* Save the system control module context, padconf already save above*/
852f5939c3SRajendra Nayak omap3_control_save_context();
862f5939c3SRajendra Nayak }
872f5939c3SRajendra Nayak
omap3_core_restore_context(void)882f5939c3SRajendra Nayak static void omap3_core_restore_context(void)
892f5939c3SRajendra Nayak {
902f5939c3SRajendra Nayak /* Restore the control module context, padconf restored by h/w */
912f5939c3SRajendra Nayak omap3_control_restore_context();
922f5939c3SRajendra Nayak /* Restore the interrupt controller context */
932f5939c3SRajendra Nayak omap_intc_restore_context();
942f5939c3SRajendra Nayak }
952f5939c3SRajendra Nayak
969d97140bSTero Kristo /*
979d97140bSTero Kristo * FIXME: This function should be called before entering off-mode after
989d97140bSTero Kristo * OMAP3 secure services have been accessed. Currently it is only called
999d97140bSTero Kristo * once during boot sequence, but this works as we are not using secure
1009d97140bSTero Kristo * services.
1019d97140bSTero Kristo */
omap3_save_secure_ram_context(void)102617fcc98SKevin Hilman static void omap3_save_secure_ram_context(void)
10327d59a4aSTero Kristo {
10427d59a4aSTero Kristo u32 ret;
105617fcc98SKevin Hilman int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
10627d59a4aSTero Kristo
10727d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
10827d59a4aSTero Kristo /*
10927d59a4aSTero Kristo * MPU next state must be set to POWER_ON temporarily,
11027d59a4aSTero Kristo * otherwise the WFI executed inside the ROM code
11127d59a4aSTero Kristo * will hang the system.
11227d59a4aSTero Kristo */
11327d59a4aSTero Kristo pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
114d09220a8STony Lindgren ret = omap3_save_secure_ram(omap3_secure_ram_storage,
115d09220a8STony Lindgren OMAP3_SAVE_SECURE_RAM_SZ);
116617fcc98SKevin Hilman pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
11727d59a4aSTero Kristo /* Following is for error tracking, it should not happen */
11827d59a4aSTero Kristo if (ret) {
11998179856SMark A. Greer pr_err("save_secure_sram() returns %08x\n", ret);
12027d59a4aSTero Kristo while (1)
12127d59a4aSTero Kristo ;
12227d59a4aSTero Kristo }
12327d59a4aSTero Kristo }
12427d59a4aSTero Kristo }
12527d59a4aSTero Kristo
_prcm_int_handle_io(int irq,void * unused)12622f51371STero Kristo static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
1278cb0ac99SPaul Walmsley {
1288cb0ac99SPaul Walmsley int c;
1298cb0ac99SPaul Walmsley
1309cb6d363STero Kristo c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, OMAP3430_ST_IO_MASK |
131f0caa527STero Kristo OMAP3430_ST_IO_CHAIN_MASK);
13222f51371STero Kristo
13322f51371STero Kristo return c ? IRQ_HANDLED : IRQ_NONE;
1348cb0ac99SPaul Walmsley }
1358cb0ac99SPaul Walmsley
_prcm_int_handle_wakeup(int irq,void * unused)13622f51371STero Kristo static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
1378bd22949SKevin Hilman {
13822f51371STero Kristo int c;
1398cb0ac99SPaul Walmsley
1408cb0ac99SPaul Walmsley /*
14122f51371STero Kristo * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
14222f51371STero Kristo * these are handled in a separate handler to avoid acking
14322f51371STero Kristo * IO events before parsing in mux code
1448cb0ac99SPaul Walmsley */
1459cb6d363STero Kristo c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, ~(OMAP3430_ST_IO_MASK |
146f0caa527STero Kristo OMAP3430_ST_IO_CHAIN_MASK));
1479cb6d363STero Kristo c += omap_prm_clear_mod_irqs(CORE_MOD, 1, ~0);
1489cb6d363STero Kristo c += omap_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, ~0);
14922f51371STero Kristo if (omap_rev() > OMAP3430_REV_ES1_0) {
1509cb6d363STero Kristo c += omap_prm_clear_mod_irqs(CORE_MOD, 3, ~0);
1519cb6d363STero Kristo c += omap_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, ~0);
1528cb0ac99SPaul Walmsley }
1538cb0ac99SPaul Walmsley
15422f51371STero Kristo return c ? IRQ_HANDLED : IRQ_NONE;
1558bd22949SKevin Hilman }
1568bd22949SKevin Hilman
omap34xx_save_context(u32 * save)157cbe26349SRussell King static void omap34xx_save_context(u32 *save)
158cbe26349SRussell King {
159cbe26349SRussell King u32 val;
160cbe26349SRussell King
161cbe26349SRussell King /* Read Auxiliary Control Register */
162cbe26349SRussell King asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
163cbe26349SRussell King *save++ = 1;
164cbe26349SRussell King *save++ = val;
165cbe26349SRussell King
166cbe26349SRussell King /* Read L2 AUX ctrl register */
167cbe26349SRussell King asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
168cbe26349SRussell King *save++ = 1;
169cbe26349SRussell King *save++ = val;
170cbe26349SRussell King }
171cbe26349SRussell King
omap34xx_do_sram_idle(unsigned long save_state)17229cb3cd2SRussell King static int omap34xx_do_sram_idle(unsigned long save_state)
17357f277b0SRajendra Nayak {
174cbe26349SRussell King omap34xx_cpu_suspend(save_state);
17529cb3cd2SRussell King return 0;
17657f277b0SRajendra Nayak }
17757f277b0SRajendra Nayak
omap_sram_idle(bool rcuidle)178*69e26b4fSPeter Zijlstra __cpuidle void omap_sram_idle(bool rcuidle)
1798bd22949SKevin Hilman {
1808bd22949SKevin Hilman /* Variable to tell what needs to be saved and restored
1818bd22949SKevin Hilman * in omap_sram_idle*/
1828bd22949SKevin Hilman /* save_state = 0 => Nothing to save and restored */
1838bd22949SKevin Hilman /* save_state = 1 => Only L1 and logic lost */
1848bd22949SKevin Hilman /* save_state = 2 => Only L2 lost */
1858bd22949SKevin Hilman /* save_state = 3 => L1, L2 and logic lost */
186fa3c2a4fSRajendra Nayak int save_state = 0;
187fa3c2a4fSRajendra Nayak int mpu_next_state = PWRDM_POWER_ON;
188fa3c2a4fSRajendra Nayak int per_next_state = PWRDM_POWER_ON;
189fa3c2a4fSRajendra Nayak int core_next_state = PWRDM_POWER_ON;
19013a6fe0fSTero Kristo u32 sdrc_pwr = 0;
19155be2f50STony Lindgren int error;
1928bd22949SKevin Hilman
1938bd22949SKevin Hilman mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
1948bd22949SKevin Hilman switch (mpu_next_state) {
195fa3c2a4fSRajendra Nayak case PWRDM_POWER_ON:
1968bd22949SKevin Hilman case PWRDM_POWER_RET:
1978bd22949SKevin Hilman /* No need to save context */
1988bd22949SKevin Hilman save_state = 0;
1998bd22949SKevin Hilman break;
20061255ab9SRajendra Nayak case PWRDM_POWER_OFF:
20161255ab9SRajendra Nayak save_state = 3;
20261255ab9SRajendra Nayak break;
2038bd22949SKevin Hilman default:
2048bd22949SKevin Hilman /* Invalid state */
20598179856SMark A. Greer pr_err("Invalid mpu state in sram_idle\n");
2068bd22949SKevin Hilman return;
2078bd22949SKevin Hilman }
208fe617af7SPeter 'p2' De Schrijver
209fa3c2a4fSRajendra Nayak /* NEON control */
210fa3c2a4fSRajendra Nayak if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
2117139178eSJouni Hogander pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
212fa3c2a4fSRajendra Nayak
21340742fa8SMike Chan /* Enable IO-PAD and IO-CHAIN wakeups */
214fa3c2a4fSRajendra Nayak per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
215ecf157d0STero Kristo core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
21640742fa8SMike Chan
217e0e29fd7SKevin Hilman pwrdm_pre_transition(NULL);
218ff2f8e5fSCharulatha V
21940742fa8SMike Chan /* PER */
22055be2f50STony Lindgren if (per_next_state == PWRDM_POWER_OFF) {
22155be2f50STony Lindgren error = cpu_cluster_pm_enter();
22255be2f50STony Lindgren if (error)
22355be2f50STony Lindgren return;
22455be2f50STony Lindgren }
225c16c3f67STero Kristo
226658ce97eSKevin Hilman /* CORE */
227658ce97eSKevin Hilman if (core_next_state < PWRDM_POWER_ON) {
2282f5939c3SRajendra Nayak if (core_next_state == PWRDM_POWER_OFF) {
2292f5939c3SRajendra Nayak omap3_core_save_context();
230f0611a5cSPaul Walmsley omap3_cm_save_context();
2312f5939c3SRajendra Nayak }
232fa3c2a4fSRajendra Nayak }
23340742fa8SMike Chan
2343b8c4ebbSTony Lindgren /* Configure PMIC signaling for I2C4 or sys_off_mode */
2353b8c4ebbSTony Lindgren omap3_vc_set_pmic_signaling(core_next_state);
2363b8c4ebbSTony Lindgren
237f18cc2ffSTero Kristo omap3_intc_prepare_idle();
2388bd22949SKevin Hilman
23961255ab9SRajendra Nayak /*
240f265dc4cSRajendra Nayak * On EMU/HS devices ROM code restores a SRDC value
241f265dc4cSRajendra Nayak * from scratchpad which has automatic self refresh on timeout
24283521291SJean Pihet * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
243f265dc4cSRajendra Nayak * Hence store/restore the SDRC_POWER register here.
24413a6fe0fSTero Kristo */
24530474544SPaul Walmsley if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
24630474544SPaul Walmsley (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
24730474544SPaul Walmsley omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
248f265dc4cSRajendra Nayak core_next_state == PWRDM_POWER_OFF)
24913a6fe0fSTero Kristo sdrc_pwr = sdrc_read_reg(SDRC_POWER);
25013a6fe0fSTero Kristo
25113a6fe0fSTero Kristo /*
252076f2cc4SRussell King * omap3_arm_context is the location where some ARM context
253076f2cc4SRussell King * get saved. The rest is placed on the stack, and restored
254076f2cc4SRussell King * from there before resuming.
25561255ab9SRajendra Nayak */
256cbe26349SRussell King if (save_state)
257cbe26349SRussell King omap34xx_save_context(omap3_arm_context);
2588c0956aaSPeter Zijlstra
2598c0956aaSPeter Zijlstra if (rcuidle)
2608c0956aaSPeter Zijlstra ct_cpuidle_enter();
2618c0956aaSPeter Zijlstra
262076f2cc4SRussell King if (save_state == 1 || save_state == 3)
2632c74a0ceSRussell King cpu_suspend(save_state, omap34xx_do_sram_idle);
264076f2cc4SRussell King else
265076f2cc4SRussell King omap34xx_do_sram_idle(save_state);
2668bd22949SKevin Hilman
2678c0956aaSPeter Zijlstra if (rcuidle)
2688c0956aaSPeter Zijlstra ct_cpuidle_exit();
2698c0956aaSPeter Zijlstra
270f265dc4cSRajendra Nayak /* Restore normal SDRC POWER settings */
27130474544SPaul Walmsley if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
27230474544SPaul Walmsley (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
27330474544SPaul Walmsley omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
27413a6fe0fSTero Kristo core_next_state == PWRDM_POWER_OFF)
27513a6fe0fSTero Kristo sdrc_write_reg(sdrc_pwr, SDRC_POWER);
27613a6fe0fSTero Kristo
277658ce97eSKevin Hilman /* CORE */
2781560d158SDave Gerlach if (core_next_state < PWRDM_POWER_ON &&
2791560d158SDave Gerlach pwrdm_read_prev_pwrst(core_pwrdm) == PWRDM_POWER_OFF) {
2802f5939c3SRajendra Nayak omap3_core_restore_context();
281f0611a5cSPaul Walmsley omap3_cm_restore_context();
2822f5939c3SRajendra Nayak omap3_sram_restore_context();
2838a917d2fSKalle Jokiniemi omap2_sms_restore_context();
2841560d158SDave Gerlach } else {
2851560d158SDave Gerlach /*
2861560d158SDave Gerlach * In off-mode resume path above, omap3_core_restore_context
2871560d158SDave Gerlach * also handles the INTC autoidle restore done here so limit
2881560d158SDave Gerlach * this to non-off mode resume paths so we don't do it twice.
2891560d158SDave Gerlach */
290f18cc2ffSTero Kristo omap3_intc_resume_idle();
2911560d158SDave Gerlach }
292658ce97eSKevin Hilman
293e0e29fd7SKevin Hilman pwrdm_post_transition(NULL);
294658ce97eSKevin Hilman
295e0e29fd7SKevin Hilman /* PER */
296b764a586STony Lindgren if (per_next_state == PWRDM_POWER_OFF)
297b764a586STony Lindgren cpu_cluster_pm_exit();
2988bd22949SKevin Hilman }
2998bd22949SKevin Hilman
omap3_pm_idle(void)3008bd22949SKevin Hilman static void omap3_pm_idle(void)
3018bd22949SKevin Hilman {
3020bcd24b0SNicolas Pitre if (omap_irq_pending())
3036b85638bSSantosh Shilimkar return;
3048bd22949SKevin Hilman
30540dbea96SPeter Zijlstra omap3_do_wfi();
3068bd22949SKevin Hilman }
3078bd22949SKevin Hilman
30810f90ed2SKevin Hilman #ifdef CONFIG_SUSPEND
omap3_pm_suspend(void)3098bd22949SKevin Hilman static int omap3_pm_suspend(void)
3108bd22949SKevin Hilman {
3118bd22949SKevin Hilman struct power_state *pwrst;
3128bd22949SKevin Hilman int state, ret = 0;
3138bd22949SKevin Hilman
3148bd22949SKevin Hilman /* Read current next_pwrsts */
3158bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node)
3168bd22949SKevin Hilman pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
3178bd22949SKevin Hilman /* Set ones wanted by suspend */
3188bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) {
319eb6a2c75SSantosh Shilimkar if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
3208bd22949SKevin Hilman goto restore;
3218bd22949SKevin Hilman if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
3228bd22949SKevin Hilman goto restore;
3238bd22949SKevin Hilman }
3248bd22949SKevin Hilman
3252bbe3af3STero Kristo omap3_intc_suspend();
3262bbe3af3STero Kristo
3278c0956aaSPeter Zijlstra omap_sram_idle(false);
3288bd22949SKevin Hilman
3298bd22949SKevin Hilman restore:
3308bd22949SKevin Hilman /* Restore next_pwrsts */
3318bd22949SKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) {
3328bd22949SKevin Hilman state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
3338bd22949SKevin Hilman if (state > pwrst->next_state) {
3347852ec05SPaul Walmsley pr_info("Powerdomain (%s) didn't enter target state %d\n",
3358bd22949SKevin Hilman pwrst->pwrdm->name, pwrst->next_state);
3368bd22949SKevin Hilman ret = -1;
3378bd22949SKevin Hilman }
338eb6a2c75SSantosh Shilimkar omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
3398bd22949SKevin Hilman }
3408bd22949SKevin Hilman if (ret)
34198179856SMark A. Greer pr_err("Could not enter target state in pm_suspend\n");
3428bd22949SKevin Hilman else
34398179856SMark A. Greer pr_info("Successfully put all powerdomains to target state\n");
3448bd22949SKevin Hilman
3458bd22949SKevin Hilman return ret;
3468bd22949SKevin Hilman }
3472e4b62dcSDave Gerlach #else
3482e4b62dcSDave Gerlach #define omap3_pm_suspend NULL
34910f90ed2SKevin Hilman #endif /* CONFIG_SUSPEND */
3508bd22949SKevin Hilman
prcm_setup_regs(void)3518111b221SKevin Hilman static void __init prcm_setup_regs(void)
3528111b221SKevin Hilman {
353ba12c242STero Kristo omap3_ctrl_init();
354b296c811STero Kristo
355c5180a2bSTero Kristo omap3_prm_init_pm(cpu_is_omap3630(), omap3_has_iva());
3568bd22949SKevin Hilman }
3578bd22949SKevin Hilman
omap3_pm_off_mode_enable(int enable)358c40552bcSKevin Hilman void omap3_pm_off_mode_enable(int enable)
359c40552bcSKevin Hilman {
360c40552bcSKevin Hilman struct power_state *pwrst;
361c40552bcSKevin Hilman u32 state;
362c40552bcSKevin Hilman
363c40552bcSKevin Hilman if (enable)
364c40552bcSKevin Hilman state = PWRDM_POWER_OFF;
365c40552bcSKevin Hilman else
366c40552bcSKevin Hilman state = PWRDM_POWER_RET;
367c40552bcSKevin Hilman
368c40552bcSKevin Hilman list_for_each_entry(pwrst, &pwrst_list, node) {
369cc1b6028SEduardo Valentin if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
370cc1b6028SEduardo Valentin pwrst->pwrdm == core_pwrdm &&
371cc1b6028SEduardo Valentin state == PWRDM_POWER_OFF) {
372cc1b6028SEduardo Valentin pwrst->next_state = PWRDM_POWER_RET;
373e16b41bfSRicardo Salveti de Araujo pr_warn("%s: Core OFF disabled due to errata i583\n",
374cc1b6028SEduardo Valentin __func__);
375cc1b6028SEduardo Valentin } else {
376c40552bcSKevin Hilman pwrst->next_state = state;
377cc1b6028SEduardo Valentin }
378cc1b6028SEduardo Valentin omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
379c40552bcSKevin Hilman }
380c40552bcSKevin Hilman }
381c40552bcSKevin Hilman
omap3_pm_get_suspend_state(struct powerdomain * pwrdm)38268d4778cSTero Kristo int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
38368d4778cSTero Kristo {
38468d4778cSTero Kristo struct power_state *pwrst;
38568d4778cSTero Kristo
38668d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) {
38768d4778cSTero Kristo if (pwrst->pwrdm == pwrdm)
38868d4778cSTero Kristo return pwrst->next_state;
38968d4778cSTero Kristo }
39068d4778cSTero Kristo return -EINVAL;
39168d4778cSTero Kristo }
39268d4778cSTero Kristo
omap3_pm_set_suspend_state(struct powerdomain * pwrdm,int state)39368d4778cSTero Kristo int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
39468d4778cSTero Kristo {
39568d4778cSTero Kristo struct power_state *pwrst;
39668d4778cSTero Kristo
39768d4778cSTero Kristo list_for_each_entry(pwrst, &pwrst_list, node) {
39868d4778cSTero Kristo if (pwrst->pwrdm == pwrdm) {
39968d4778cSTero Kristo pwrst->next_state = state;
40068d4778cSTero Kristo return 0;
40168d4778cSTero Kristo }
40268d4778cSTero Kristo }
40368d4778cSTero Kristo return -EINVAL;
40468d4778cSTero Kristo }
40568d4778cSTero Kristo
pwrdms_setup(struct powerdomain * pwrdm,void * unused)406a23456e9SPeter 'p2' De Schrijver static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
4078bd22949SKevin Hilman {
4088bd22949SKevin Hilman struct power_state *pwrst;
4098bd22949SKevin Hilman
4108bd22949SKevin Hilman if (!pwrdm->pwrsts)
4118bd22949SKevin Hilman return 0;
4128bd22949SKevin Hilman
413d3d381c6SMing Lei pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
4148bd22949SKevin Hilman if (!pwrst)
4158bd22949SKevin Hilman return -ENOMEM;
4168bd22949SKevin Hilman pwrst->pwrdm = pwrdm;
417fb2c599fSAndreas Kemnade
418fb2c599fSAndreas Kemnade if (enable_off_mode)
419fb2c599fSAndreas Kemnade pwrst->next_state = PWRDM_POWER_OFF;
420fb2c599fSAndreas Kemnade else
4218bd22949SKevin Hilman pwrst->next_state = PWRDM_POWER_RET;
422fb2c599fSAndreas Kemnade
4238bd22949SKevin Hilman list_add(&pwrst->node, &pwrst_list);
4248bd22949SKevin Hilman
4258bd22949SKevin Hilman if (pwrdm_has_hdwr_sar(pwrdm))
4268bd22949SKevin Hilman pwrdm_enable_hdwr_sar(pwrdm);
4278bd22949SKevin Hilman
428eb6a2c75SSantosh Shilimkar return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
4298bd22949SKevin Hilman }
4308bd22949SKevin Hilman
4318bd22949SKevin Hilman /*
43246e130d2SJean Pihet * Push functions to SRAM
43346e130d2SJean Pihet *
43446e130d2SJean Pihet * The minimum set of functions is pushed to SRAM for execution:
43546e130d2SJean Pihet * - omap3_do_wfi for erratum i581 WA,
43646e130d2SJean Pihet */
omap_push_sram_idle(void)4373231fc88SRajendra Nayak void omap_push_sram_idle(void)
4383231fc88SRajendra Nayak {
43946e130d2SJean Pihet omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
4403231fc88SRajendra Nayak }
4413231fc88SRajendra Nayak
pm_errata_configure(void)4428cdfd834SNishanth Menon static void __init pm_errata_configure(void)
4438cdfd834SNishanth Menon {
444c4236d2eSPeter 'p2' De Schrijver if (cpu_is_omap3630()) {
445458e999eSNishanth Menon pm34xx_errata |= PM_RTA_ERRATUM_i608;
446c4236d2eSPeter 'p2' De Schrijver /* Enable the l2 cache toggling in sleep logic */
447c4236d2eSPeter 'p2' De Schrijver enable_omap3630_toggle_l2_on_restore();
448cc1b6028SEduardo Valentin if (omap_rev() < OMAP3630_REV_ES1_2)
449856c3c5bSPaul Walmsley pm34xx_errata |= (PM_SDRC_WAKEUP_ERRATUM_i583 |
450856c3c5bSPaul Walmsley PM_PER_MEMORIES_ERRATUM_i582);
451856c3c5bSPaul Walmsley } else if (cpu_is_omap34xx()) {
452856c3c5bSPaul Walmsley pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582;
453c4236d2eSPeter 'p2' De Schrijver }
4548cdfd834SNishanth Menon }
4558cdfd834SNishanth Menon
omap3_pm_check_pmic(void)456fb2c599fSAndreas Kemnade static void __init omap3_pm_check_pmic(void)
457fb2c599fSAndreas Kemnade {
458fb2c599fSAndreas Kemnade struct device_node *np;
459fb2c599fSAndreas Kemnade
460fb2c599fSAndreas Kemnade np = of_find_compatible_node(NULL, NULL, "ti,twl4030-power-idle");
461fb2c599fSAndreas Kemnade if (!np)
462fb2c599fSAndreas Kemnade np = of_find_compatible_node(NULL, NULL, "ti,twl4030-power-idle-osc-off");
463fb2c599fSAndreas Kemnade
464fb2c599fSAndreas Kemnade if (np) {
465fb2c599fSAndreas Kemnade of_node_put(np);
466fb2c599fSAndreas Kemnade enable_off_mode = 1;
467fb2c599fSAndreas Kemnade } else {
468fb2c599fSAndreas Kemnade enable_off_mode = 0;
469fb2c599fSAndreas Kemnade }
470fb2c599fSAndreas Kemnade }
471fb2c599fSAndreas Kemnade
omap3_pm_init(void)472bbd707acSShawn Guo int __init omap3_pm_init(void)
4738bd22949SKevin Hilman {
4748bd22949SKevin Hilman struct power_state *pwrst, *tmp;
475856c3c5bSPaul Walmsley struct clockdomain *neon_clkdm, *mpu_clkdm, *per_clkdm, *wkup_clkdm;
4768bd22949SKevin Hilman int ret;
4778bd22949SKevin Hilman
478b02b9172SPaul Walmsley if (!omap3_has_io_chain_ctrl())
4793d0cb73eSJoe Perches pr_warn("PM: no software I/O chain control; some wakeups may be lost\n");
480b02b9172SPaul Walmsley
4818cdfd834SNishanth Menon pm_errata_configure();
4828cdfd834SNishanth Menon
4838bd22949SKevin Hilman /* XXX prcm_setup_regs needs to be before enabling hw
4848bd22949SKevin Hilman * supervised mode for powerdomains */
4858bd22949SKevin Hilman prcm_setup_regs();
4868bd22949SKevin Hilman
48722f51371STero Kristo ret = request_irq(omap_prcm_event_to_irq("wkup"),
48822f51371STero Kristo _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
48922f51371STero Kristo
4908bd22949SKevin Hilman if (ret) {
49122f51371STero Kristo pr_err("pm: Failed to request pm_wkup irq\n");
49222f51371STero Kristo goto err1;
49322f51371STero Kristo }
49422f51371STero Kristo
49522f51371STero Kristo /* IO interrupt is shared with mux code */
49622f51371STero Kristo ret = request_irq(omap_prcm_event_to_irq("io"),
49722f51371STero Kristo _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
49822f51371STero Kristo omap3_pm_init);
49922f51371STero Kristo
50022f51371STero Kristo if (ret) {
50122f51371STero Kristo pr_err("pm: Failed to request pm_io irq\n");
502ce229c5dSMark A. Greer goto err2;
5038bd22949SKevin Hilman }
5048bd22949SKevin Hilman
505fb2c599fSAndreas Kemnade omap3_pm_check_pmic();
506fb2c599fSAndreas Kemnade
507a23456e9SPeter 'p2' De Schrijver ret = pwrdm_for_each(pwrdms_setup, NULL);
5088bd22949SKevin Hilman if (ret) {
50998179856SMark A. Greer pr_err("Failed to setup powerdomains\n");
510ce229c5dSMark A. Greer goto err3;
5118bd22949SKevin Hilman }
5128bd22949SKevin Hilman
51392206fd2SPaul Walmsley (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
5148bd22949SKevin Hilman
5158bd22949SKevin Hilman mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
5168bd22949SKevin Hilman if (mpu_pwrdm == NULL) {
51798179856SMark A. Greer pr_err("Failed to get mpu_pwrdm\n");
518ce229c5dSMark A. Greer ret = -EINVAL;
519ce229c5dSMark A. Greer goto err3;
5208bd22949SKevin Hilman }
5218bd22949SKevin Hilman
522fa3c2a4fSRajendra Nayak neon_pwrdm = pwrdm_lookup("neon_pwrdm");
523fa3c2a4fSRajendra Nayak per_pwrdm = pwrdm_lookup("per_pwrdm");
524fa3c2a4fSRajendra Nayak core_pwrdm = pwrdm_lookup("core_pwrdm");
525fa3c2a4fSRajendra Nayak
52655ed9694SPaul Walmsley neon_clkdm = clkdm_lookup("neon_clkdm");
52755ed9694SPaul Walmsley mpu_clkdm = clkdm_lookup("mpu_clkdm");
528856c3c5bSPaul Walmsley per_clkdm = clkdm_lookup("per_clkdm");
529856c3c5bSPaul Walmsley wkup_clkdm = clkdm_lookup("wkup_clkdm");
53055ed9694SPaul Walmsley
5312e4b62dcSDave Gerlach omap_common_suspend_init(omap3_pm_suspend);
5328bd22949SKevin Hilman
5330bcd24b0SNicolas Pitre arm_pm_idle = omap3_pm_idle;
5340343371eSKalle Jokiniemi omap3_idle_init();
5358bd22949SKevin Hilman
536458e999eSNishanth Menon /*
537458e999eSNishanth Menon * RTA is disabled during initialization as per erratum i608
538458e999eSNishanth Menon * it is safer to disable RTA by the bootloader, but we would like
539458e999eSNishanth Menon * to be doubly sure here and prevent any mishaps.
540458e999eSNishanth Menon */
541458e999eSNishanth Menon if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
542458e999eSNishanth Menon omap3630_ctrl_disable_rta();
543458e999eSNishanth Menon
544856c3c5bSPaul Walmsley /*
545856c3c5bSPaul Walmsley * The UART3/4 FIFO and the sidetone memory in McBSP2/3 are
546856c3c5bSPaul Walmsley * not correctly reset when the PER powerdomain comes back
547856c3c5bSPaul Walmsley * from OFF or OSWR when the CORE powerdomain is kept active.
548856c3c5bSPaul Walmsley * See OMAP36xx Erratum i582 "PER Domain reset issue after
549856c3c5bSPaul Walmsley * Domain-OFF/OSWR Wakeup". This wakeup dependency is not a
550856c3c5bSPaul Walmsley * complete workaround. The kernel must also prevent the PER
551856c3c5bSPaul Walmsley * powerdomain from going to OSWR/OFF while the CORE
552856c3c5bSPaul Walmsley * powerdomain is not going to OSWR/OFF. And if PER last
553856c3c5bSPaul Walmsley * power state was off while CORE last power state was ON, the
554856c3c5bSPaul Walmsley * UART3/4 and McBSP2/3 SIDETONE devices need to run a
555856c3c5bSPaul Walmsley * self-test using their loopback tests; if that fails, those
556856c3c5bSPaul Walmsley * devices are unusable until the PER/CORE can complete a transition
557856c3c5bSPaul Walmsley * from ON to OSWR/OFF and then back to ON.
558856c3c5bSPaul Walmsley *
559856c3c5bSPaul Walmsley * XXX Technically this workaround is only needed if off-mode
560856c3c5bSPaul Walmsley * or OSWR is enabled.
561856c3c5bSPaul Walmsley */
562856c3c5bSPaul Walmsley if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582))
563856c3c5bSPaul Walmsley clkdm_add_wkdep(per_clkdm, wkup_clkdm);
564856c3c5bSPaul Walmsley
56555ed9694SPaul Walmsley clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
56627d59a4aSTero Kristo if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
56727d59a4aSTero Kristo omap3_secure_ram_storage =
568d09220a8STony Lindgren kmalloc(OMAP3_SAVE_SECURE_RAM_SZ, GFP_KERNEL);
56927d59a4aSTero Kristo if (!omap3_secure_ram_storage)
5707852ec05SPaul Walmsley pr_err("Memory allocation failed when allocating for secure sram context\n");
57127d59a4aSTero Kristo
5729d97140bSTero Kristo local_irq_disable();
5739d97140bSTero Kristo
574617fcc98SKevin Hilman omap3_save_secure_ram_context();
5759d97140bSTero Kristo
5769d97140bSTero Kristo local_irq_enable();
5779d97140bSTero Kristo }
5789d97140bSTero Kristo
5799d97140bSTero Kristo omap3_save_scratchpad_contents();
5808bd22949SKevin Hilman return ret;
581ce229c5dSMark A. Greer
582ce229c5dSMark A. Greer err3:
5838bd22949SKevin Hilman list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
5848bd22949SKevin Hilman list_del(&pwrst->node);
5858bd22949SKevin Hilman kfree(pwrst);
5868bd22949SKevin Hilman }
587ce229c5dSMark A. Greer free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init);
588ce229c5dSMark A. Greer err2:
589ce229c5dSMark A. Greer free_irq(omap_prcm_event_to_irq("wkup"), NULL);
590ce229c5dSMark A. Greer err1:
5918bd22949SKevin Hilman return ret;
5928bd22949SKevin Hilman }
593