1 /* 2 * OMAP Power Management debug routines 3 * 4 * Copyright (C) 2005 Texas Instruments, Inc. 5 * Copyright (C) 2006-2008 Nokia Corporation 6 * 7 * Written by: 8 * Richard Woodruff <r-woodruff2@ti.com> 9 * Tony Lindgren 10 * Juha Yrjola 11 * Amit Kucheria <amit.kucheria@nokia.com> 12 * Igor Stoppa <igor.stoppa@nokia.com> 13 * Jouni Hogander 14 * 15 * Based on pm.c for omap2 16 * 17 * This program is free software; you can redistribute it and/or modify 18 * it under the terms of the GNU General Public License version 2 as 19 * published by the Free Software Foundation. 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/sched.h> 24 #include <linux/clk.h> 25 #include <linux/err.h> 26 #include <linux/io.h> 27 #include <linux/module.h> 28 29 #include <plat/clock.h> 30 #include <plat/board.h> 31 #include <plat/powerdomain.h> 32 #include <plat/clockdomain.h> 33 34 #include "prm.h" 35 #include "cm.h" 36 #include "pm.h" 37 38 int omap2_pm_debug; 39 40 #define DUMP_PRM_MOD_REG(mod, reg) \ 41 regs[reg_count].name = #mod "." #reg; \ 42 regs[reg_count++].val = prm_read_mod_reg(mod, reg) 43 #define DUMP_CM_MOD_REG(mod, reg) \ 44 regs[reg_count].name = #mod "." #reg; \ 45 regs[reg_count++].val = cm_read_mod_reg(mod, reg) 46 #define DUMP_PRM_REG(reg) \ 47 regs[reg_count].name = #reg; \ 48 regs[reg_count++].val = __raw_readl(reg) 49 #define DUMP_CM_REG(reg) \ 50 regs[reg_count].name = #reg; \ 51 regs[reg_count++].val = __raw_readl(reg) 52 #define DUMP_INTC_REG(reg, off) \ 53 regs[reg_count].name = #reg; \ 54 regs[reg_count++].val = \ 55 __raw_readl(OMAP2_L4_IO_ADDRESS(0x480fe000 + (off))) 56 57 static int __init pm_dbg_init(void); 58 59 void omap2_pm_dump(int mode, int resume, unsigned int us) 60 { 61 struct reg { 62 const char *name; 63 u32 val; 64 } regs[32]; 65 int reg_count = 0, i; 66 const char *s1 = NULL, *s2 = NULL; 67 68 if (!resume) { 69 #if 0 70 /* MPU */ 71 DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET); 72 DUMP_CM_MOD_REG(MPU_MOD, CM_CLKSTCTRL); 73 DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTCTRL); 74 DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTST); 75 DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP); 76 #endif 77 #if 0 78 /* INTC */ 79 DUMP_INTC_REG(INTC_MIR0, 0x0084); 80 DUMP_INTC_REG(INTC_MIR1, 0x00a4); 81 DUMP_INTC_REG(INTC_MIR2, 0x00c4); 82 #endif 83 #if 0 84 DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1); 85 if (cpu_is_omap24xx()) { 86 DUMP_CM_MOD_REG(CORE_MOD, OMAP24XX_CM_FCLKEN2); 87 DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD, 88 OMAP2_PRCM_CLKEMUL_CTRL_OFFSET); 89 DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD, 90 OMAP2_PRCM_CLKSRC_CTRL_OFFSET); 91 } 92 DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN); 93 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1); 94 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2); 95 DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN); 96 DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN); 97 DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE); 98 DUMP_PRM_MOD_REG(CORE_MOD, PM_PWSTST); 99 #endif 100 #if 0 101 /* DSP */ 102 if (cpu_is_omap24xx()) { 103 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN); 104 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN); 105 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST); 106 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE); 107 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL); 108 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSTCTRL); 109 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTCTRL); 110 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTST); 111 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTCTRL); 112 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTST); 113 } 114 #endif 115 } else { 116 DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1); 117 if (cpu_is_omap24xx()) 118 DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2); 119 DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST); 120 DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); 121 #if 1 122 DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098); 123 DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8); 124 DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8); 125 #endif 126 } 127 128 switch (mode) { 129 case 0: 130 s1 = "full"; 131 s2 = "retention"; 132 break; 133 case 1: 134 s1 = "MPU"; 135 s2 = "retention"; 136 break; 137 case 2: 138 s1 = "MPU"; 139 s2 = "idle"; 140 break; 141 } 142 143 if (!resume) 144 #ifdef CONFIG_NO_HZ 145 printk(KERN_INFO 146 "--- Going to %s %s (next timer after %u ms)\n", s1, s2, 147 jiffies_to_msecs(get_next_timer_interrupt(jiffies) - 148 jiffies)); 149 #else 150 printk(KERN_INFO "--- Going to %s %s\n", s1, s2); 151 #endif 152 else 153 printk(KERN_INFO "--- Woke up (slept for %u.%03u ms)\n", 154 us / 1000, us % 1000); 155 156 for (i = 0; i < reg_count; i++) 157 printk(KERN_INFO "%-20s: 0x%08x\n", regs[i].name, regs[i].val); 158 } 159 160 #ifdef CONFIG_DEBUG_FS 161 #include <linux/debugfs.h> 162 #include <linux/seq_file.h> 163 164 static void pm_dbg_regset_store(u32 *ptr); 165 166 struct dentry *pm_dbg_dir; 167 168 static int pm_dbg_init_done; 169 170 enum { 171 DEBUG_FILE_COUNTERS = 0, 172 DEBUG_FILE_TIMERS, 173 }; 174 175 struct pm_module_def { 176 char name[8]; /* Name of the module */ 177 short type; /* CM or PRM */ 178 unsigned short offset; 179 int low; /* First register address on this module */ 180 int high; /* Last register address on this module */ 181 }; 182 183 #define MOD_CM 0 184 #define MOD_PRM 1 185 186 static const struct pm_module_def *pm_dbg_reg_modules; 187 static const struct pm_module_def omap3_pm_reg_modules[] = { 188 { "IVA2", MOD_CM, OMAP3430_IVA2_MOD, 0, 0x4c }, 189 { "OCP", MOD_CM, OCP_MOD, 0, 0x10 }, 190 { "MPU", MOD_CM, MPU_MOD, 4, 0x4c }, 191 { "CORE", MOD_CM, CORE_MOD, 0, 0x4c }, 192 { "SGX", MOD_CM, OMAP3430ES2_SGX_MOD, 0, 0x4c }, 193 { "WKUP", MOD_CM, WKUP_MOD, 0, 0x40 }, 194 { "CCR", MOD_CM, PLL_MOD, 0, 0x70 }, 195 { "DSS", MOD_CM, OMAP3430_DSS_MOD, 0, 0x4c }, 196 { "CAM", MOD_CM, OMAP3430_CAM_MOD, 0, 0x4c }, 197 { "PER", MOD_CM, OMAP3430_PER_MOD, 0, 0x4c }, 198 { "EMU", MOD_CM, OMAP3430_EMU_MOD, 0x40, 0x54 }, 199 { "NEON", MOD_CM, OMAP3430_NEON_MOD, 0x20, 0x48 }, 200 { "USB", MOD_CM, OMAP3430ES2_USBHOST_MOD, 0, 0x4c }, 201 202 { "IVA2", MOD_PRM, OMAP3430_IVA2_MOD, 0x50, 0xfc }, 203 { "OCP", MOD_PRM, OCP_MOD, 4, 0x1c }, 204 { "MPU", MOD_PRM, MPU_MOD, 0x58, 0xe8 }, 205 { "CORE", MOD_PRM, CORE_MOD, 0x58, 0xf8 }, 206 { "SGX", MOD_PRM, OMAP3430ES2_SGX_MOD, 0x58, 0xe8 }, 207 { "WKUP", MOD_PRM, WKUP_MOD, 0xa0, 0xb0 }, 208 { "CCR", MOD_PRM, PLL_MOD, 0x40, 0x70 }, 209 { "DSS", MOD_PRM, OMAP3430_DSS_MOD, 0x58, 0xe8 }, 210 { "CAM", MOD_PRM, OMAP3430_CAM_MOD, 0x58, 0xe8 }, 211 { "PER", MOD_PRM, OMAP3430_PER_MOD, 0x58, 0xe8 }, 212 { "EMU", MOD_PRM, OMAP3430_EMU_MOD, 0x58, 0xe4 }, 213 { "GLBL", MOD_PRM, OMAP3430_GR_MOD, 0x20, 0xe4 }, 214 { "NEON", MOD_PRM, OMAP3430_NEON_MOD, 0x58, 0xe8 }, 215 { "USB", MOD_PRM, OMAP3430ES2_USBHOST_MOD, 0x58, 0xe8 }, 216 { "", 0, 0, 0, 0 }, 217 }; 218 219 #define PM_DBG_MAX_REG_SETS 4 220 221 static void *pm_dbg_reg_set[PM_DBG_MAX_REG_SETS]; 222 223 static int pm_dbg_get_regset_size(void) 224 { 225 static int regset_size; 226 227 if (regset_size == 0) { 228 int i = 0; 229 230 while (pm_dbg_reg_modules[i].name[0] != 0) { 231 regset_size += pm_dbg_reg_modules[i].high + 232 4 - pm_dbg_reg_modules[i].low; 233 i++; 234 } 235 } 236 return regset_size; 237 } 238 239 static int pm_dbg_show_regs(struct seq_file *s, void *unused) 240 { 241 int i, j; 242 unsigned long val; 243 int reg_set = (int)s->private; 244 u32 *ptr; 245 void *store = NULL; 246 int regs; 247 int linefeed; 248 249 if (reg_set == 0) { 250 store = kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL); 251 ptr = store; 252 pm_dbg_regset_store(ptr); 253 } else { 254 ptr = pm_dbg_reg_set[reg_set - 1]; 255 } 256 257 i = 0; 258 259 while (pm_dbg_reg_modules[i].name[0] != 0) { 260 regs = 0; 261 linefeed = 0; 262 if (pm_dbg_reg_modules[i].type == MOD_CM) 263 seq_printf(s, "MOD: CM_%s (%08x)\n", 264 pm_dbg_reg_modules[i].name, 265 (u32)(OMAP3430_CM_BASE + 266 pm_dbg_reg_modules[i].offset)); 267 else 268 seq_printf(s, "MOD: PRM_%s (%08x)\n", 269 pm_dbg_reg_modules[i].name, 270 (u32)(OMAP3430_PRM_BASE + 271 pm_dbg_reg_modules[i].offset)); 272 273 for (j = pm_dbg_reg_modules[i].low; 274 j <= pm_dbg_reg_modules[i].high; j += 4) { 275 val = *(ptr++); 276 if (val != 0) { 277 regs++; 278 if (linefeed) { 279 seq_printf(s, "\n"); 280 linefeed = 0; 281 } 282 seq_printf(s, " %02x => %08lx", j, val); 283 if (regs % 4 == 0) 284 linefeed = 1; 285 } 286 } 287 seq_printf(s, "\n"); 288 i++; 289 } 290 291 if (store != NULL) 292 kfree(store); 293 294 return 0; 295 } 296 297 static void pm_dbg_regset_store(u32 *ptr) 298 { 299 int i, j; 300 u32 val; 301 302 i = 0; 303 304 while (pm_dbg_reg_modules[i].name[0] != 0) { 305 for (j = pm_dbg_reg_modules[i].low; 306 j <= pm_dbg_reg_modules[i].high; j += 4) { 307 if (pm_dbg_reg_modules[i].type == MOD_CM) 308 val = cm_read_mod_reg( 309 pm_dbg_reg_modules[i].offset, j); 310 else 311 val = prm_read_mod_reg( 312 pm_dbg_reg_modules[i].offset, j); 313 *(ptr++) = val; 314 } 315 i++; 316 } 317 } 318 319 int pm_dbg_regset_save(int reg_set) 320 { 321 if (pm_dbg_reg_set[reg_set-1] == NULL) 322 return -EINVAL; 323 324 pm_dbg_regset_store(pm_dbg_reg_set[reg_set-1]); 325 326 return 0; 327 } 328 329 static const char pwrdm_state_names[][PWRDM_MAX_PWRSTS] = { 330 "OFF", 331 "RET", 332 "INA", 333 "ON" 334 }; 335 336 void pm_dbg_update_time(struct powerdomain *pwrdm, int prev) 337 { 338 s64 t; 339 340 if (!pm_dbg_init_done) 341 return ; 342 343 /* Update timer for previous state */ 344 t = sched_clock(); 345 346 pwrdm->state_timer[prev] += t - pwrdm->timer; 347 348 pwrdm->timer = t; 349 } 350 351 static int clkdm_dbg_show_counter(struct clockdomain *clkdm, void *user) 352 { 353 struct seq_file *s = (struct seq_file *)user; 354 355 if (strcmp(clkdm->name, "emu_clkdm") == 0 || 356 strcmp(clkdm->name, "wkup_clkdm") == 0 || 357 strncmp(clkdm->name, "dpll", 4) == 0) 358 return 0; 359 360 seq_printf(s, "%s->%s (%d)", clkdm->name, 361 clkdm->pwrdm.ptr->name, 362 atomic_read(&clkdm->usecount)); 363 seq_printf(s, "\n"); 364 365 return 0; 366 } 367 368 static int pwrdm_dbg_show_counter(struct powerdomain *pwrdm, void *user) 369 { 370 struct seq_file *s = (struct seq_file *)user; 371 int i; 372 373 if (strcmp(pwrdm->name, "emu_pwrdm") == 0 || 374 strcmp(pwrdm->name, "wkup_pwrdm") == 0 || 375 strncmp(pwrdm->name, "dpll", 4) == 0) 376 return 0; 377 378 if (pwrdm->state != pwrdm_read_pwrst(pwrdm)) 379 printk(KERN_ERR "pwrdm state mismatch(%s) %d != %d\n", 380 pwrdm->name, pwrdm->state, pwrdm_read_pwrst(pwrdm)); 381 382 seq_printf(s, "%s (%s)", pwrdm->name, 383 pwrdm_state_names[pwrdm->state]); 384 for (i = 0; i < PWRDM_MAX_PWRSTS; i++) 385 seq_printf(s, ",%s:%d", pwrdm_state_names[i], 386 pwrdm->state_counter[i]); 387 388 seq_printf(s, "\n"); 389 390 return 0; 391 } 392 393 static int pwrdm_dbg_show_timer(struct powerdomain *pwrdm, void *user) 394 { 395 struct seq_file *s = (struct seq_file *)user; 396 int i; 397 398 if (strcmp(pwrdm->name, "emu_pwrdm") == 0 || 399 strcmp(pwrdm->name, "wkup_pwrdm") == 0 || 400 strncmp(pwrdm->name, "dpll", 4) == 0) 401 return 0; 402 403 pwrdm_state_switch(pwrdm); 404 405 seq_printf(s, "%s (%s)", pwrdm->name, 406 pwrdm_state_names[pwrdm->state]); 407 408 for (i = 0; i < 4; i++) 409 seq_printf(s, ",%s:%lld", pwrdm_state_names[i], 410 pwrdm->state_timer[i]); 411 412 seq_printf(s, "\n"); 413 return 0; 414 } 415 416 static int pm_dbg_show_counters(struct seq_file *s, void *unused) 417 { 418 pwrdm_for_each(pwrdm_dbg_show_counter, s); 419 clkdm_for_each(clkdm_dbg_show_counter, s); 420 421 return 0; 422 } 423 424 static int pm_dbg_show_timers(struct seq_file *s, void *unused) 425 { 426 pwrdm_for_each(pwrdm_dbg_show_timer, s); 427 return 0; 428 } 429 430 static int pm_dbg_open(struct inode *inode, struct file *file) 431 { 432 switch ((int)inode->i_private) { 433 case DEBUG_FILE_COUNTERS: 434 return single_open(file, pm_dbg_show_counters, 435 &inode->i_private); 436 case DEBUG_FILE_TIMERS: 437 default: 438 return single_open(file, pm_dbg_show_timers, 439 &inode->i_private); 440 }; 441 } 442 443 static int pm_dbg_reg_open(struct inode *inode, struct file *file) 444 { 445 return single_open(file, pm_dbg_show_regs, inode->i_private); 446 } 447 448 static const struct file_operations debug_fops = { 449 .open = pm_dbg_open, 450 .read = seq_read, 451 .llseek = seq_lseek, 452 .release = single_release, 453 }; 454 455 static const struct file_operations debug_reg_fops = { 456 .open = pm_dbg_reg_open, 457 .read = seq_read, 458 .llseek = seq_lseek, 459 .release = single_release, 460 }; 461 462 int pm_dbg_regset_init(int reg_set) 463 { 464 char name[2]; 465 466 if (!pm_dbg_init_done) 467 pm_dbg_init(); 468 469 if (reg_set < 1 || reg_set > PM_DBG_MAX_REG_SETS || 470 pm_dbg_reg_set[reg_set-1] != NULL) 471 return -EINVAL; 472 473 pm_dbg_reg_set[reg_set-1] = 474 kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL); 475 476 if (pm_dbg_reg_set[reg_set-1] == NULL) 477 return -ENOMEM; 478 479 if (pm_dbg_dir != NULL) { 480 sprintf(name, "%d", reg_set); 481 482 (void) debugfs_create_file(name, S_IRUGO, 483 pm_dbg_dir, (void *)reg_set, &debug_reg_fops); 484 } 485 486 return 0; 487 } 488 489 static int pwrdm_suspend_get(void *data, u64 *val) 490 { 491 *val = omap3_pm_get_suspend_state((struct powerdomain *)data); 492 493 if (*val >= 0) 494 return 0; 495 return *val; 496 } 497 498 static int pwrdm_suspend_set(void *data, u64 val) 499 { 500 return omap3_pm_set_suspend_state((struct powerdomain *)data, (int)val); 501 } 502 503 DEFINE_SIMPLE_ATTRIBUTE(pwrdm_suspend_fops, pwrdm_suspend_get, 504 pwrdm_suspend_set, "%llu\n"); 505 506 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *dir) 507 { 508 int i; 509 s64 t; 510 struct dentry *d; 511 512 t = sched_clock(); 513 514 for (i = 0; i < 4; i++) 515 pwrdm->state_timer[i] = 0; 516 517 pwrdm->timer = t; 518 519 if (strncmp(pwrdm->name, "dpll", 4) == 0) 520 return 0; 521 522 d = debugfs_create_dir(pwrdm->name, (struct dentry *)dir); 523 524 (void) debugfs_create_file("suspend", S_IRUGO|S_IWUSR, d, 525 (void *)pwrdm, &pwrdm_suspend_fops); 526 527 return 0; 528 } 529 530 static int option_get(void *data, u64 *val) 531 { 532 u32 *option = data; 533 534 *val = *option; 535 536 return 0; 537 } 538 539 static int option_set(void *data, u64 val) 540 { 541 u32 *option = data; 542 543 *option = val; 544 545 if (option == &enable_off_mode) 546 omap3_pm_off_mode_enable(val); 547 548 return 0; 549 } 550 551 DEFINE_SIMPLE_ATTRIBUTE(pm_dbg_option_fops, option_get, option_set, "%llu\n"); 552 553 static int __init pm_dbg_init(void) 554 { 555 int i; 556 struct dentry *d; 557 char name[2]; 558 559 if (pm_dbg_init_done) 560 return 0; 561 562 if (cpu_is_omap34xx()) 563 pm_dbg_reg_modules = omap3_pm_reg_modules; 564 else { 565 printk(KERN_ERR "%s: only OMAP3 supported\n", __func__); 566 return -ENODEV; 567 } 568 569 d = debugfs_create_dir("pm_debug", NULL); 570 if (IS_ERR(d)) 571 return PTR_ERR(d); 572 573 (void) debugfs_create_file("count", S_IRUGO, 574 d, (void *)DEBUG_FILE_COUNTERS, &debug_fops); 575 (void) debugfs_create_file("time", S_IRUGO, 576 d, (void *)DEBUG_FILE_TIMERS, &debug_fops); 577 578 pwrdm_for_each_nolock(pwrdms_setup, (void *)d); 579 580 pm_dbg_dir = debugfs_create_dir("registers", d); 581 if (IS_ERR(pm_dbg_dir)) 582 return PTR_ERR(pm_dbg_dir); 583 584 (void) debugfs_create_file("current", S_IRUGO, 585 pm_dbg_dir, (void *)0, &debug_reg_fops); 586 587 for (i = 0; i < PM_DBG_MAX_REG_SETS; i++) 588 if (pm_dbg_reg_set[i] != NULL) { 589 sprintf(name, "%d", i+1); 590 (void) debugfs_create_file(name, S_IRUGO, 591 pm_dbg_dir, (void *)(i+1), &debug_reg_fops); 592 593 } 594 595 (void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUGO, d, 596 &enable_off_mode, &pm_dbg_option_fops); 597 (void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUGO, d, 598 &sleep_while_idle, &pm_dbg_option_fops); 599 (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUGO, d, 600 &wakeup_timer_seconds, &pm_dbg_option_fops); 601 pm_dbg_init_done = 1; 602 603 return 0; 604 } 605 arch_initcall(pm_dbg_init); 606 607 #else 608 void pm_dbg_update_time(struct powerdomain *pwrdm, int prev) {} 609 #endif 610