xref: /openbmc/linux/arch/arm/mach-omap2/pm-debug.c (revision 4800cd83)
1 /*
2  * OMAP Power Management debug routines
3  *
4  * Copyright (C) 2005 Texas Instruments, Inc.
5  * Copyright (C) 2006-2008 Nokia Corporation
6  *
7  * Written by:
8  * Richard Woodruff <r-woodruff2@ti.com>
9  * Tony Lindgren
10  * Juha Yrjola
11  * Amit Kucheria <amit.kucheria@nokia.com>
12  * Igor Stoppa <igor.stoppa@nokia.com>
13  * Jouni Hogander
14  *
15  * Based on pm.c for omap2
16  *
17  * This program is free software; you can redistribute it and/or modify
18  * it under the terms of the GNU General Public License version 2 as
19  * published by the Free Software Foundation.
20  */
21 
22 #include <linux/kernel.h>
23 #include <linux/sched.h>
24 #include <linux/clk.h>
25 #include <linux/err.h>
26 #include <linux/io.h>
27 #include <linux/module.h>
28 #include <linux/slab.h>
29 
30 #include <plat/clock.h>
31 #include <plat/board.h>
32 #include "powerdomain.h"
33 #include "clockdomain.h"
34 #include <plat/dmtimer.h>
35 #include <plat/omap-pm.h>
36 
37 #include "cm2xxx_3xxx.h"
38 #include "prm2xxx_3xxx.h"
39 #include "pm.h"
40 
41 int omap2_pm_debug;
42 u32 enable_off_mode;
43 u32 sleep_while_idle;
44 u32 wakeup_timer_seconds;
45 u32 wakeup_timer_milliseconds;
46 
47 #define DUMP_PRM_MOD_REG(mod, reg)    \
48 	regs[reg_count].name = #mod "." #reg; \
49 	regs[reg_count++].val = omap2_prm_read_mod_reg(mod, reg)
50 #define DUMP_CM_MOD_REG(mod, reg)     \
51 	regs[reg_count].name = #mod "." #reg; \
52 	regs[reg_count++].val = omap2_cm_read_mod_reg(mod, reg)
53 #define DUMP_PRM_REG(reg) \
54 	regs[reg_count].name = #reg; \
55 	regs[reg_count++].val = __raw_readl(reg)
56 #define DUMP_CM_REG(reg) \
57 	regs[reg_count].name = #reg; \
58 	regs[reg_count++].val = __raw_readl(reg)
59 #define DUMP_INTC_REG(reg, off) \
60 	regs[reg_count].name = #reg; \
61 	regs[reg_count++].val = \
62 			 __raw_readl(OMAP2_L4_IO_ADDRESS(0x480fe000 + (off)))
63 
64 void omap2_pm_dump(int mode, int resume, unsigned int us)
65 {
66 	struct reg {
67 		const char *name;
68 		u32 val;
69 	} regs[32];
70 	int reg_count = 0, i;
71 	const char *s1 = NULL, *s2 = NULL;
72 
73 	if (!resume) {
74 #if 0
75 		/* MPU */
76 		DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET);
77 		DUMP_CM_MOD_REG(MPU_MOD, OMAP2_CM_CLKSTCTRL);
78 		DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTCTRL);
79 		DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTST);
80 		DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP);
81 #endif
82 #if 0
83 		/* INTC */
84 		DUMP_INTC_REG(INTC_MIR0, 0x0084);
85 		DUMP_INTC_REG(INTC_MIR1, 0x00a4);
86 		DUMP_INTC_REG(INTC_MIR2, 0x00c4);
87 #endif
88 #if 0
89 		DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1);
90 		if (cpu_is_omap24xx()) {
91 			DUMP_CM_MOD_REG(CORE_MOD, OMAP24XX_CM_FCLKEN2);
92 			DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD,
93 					OMAP2_PRCM_CLKEMUL_CTRL_OFFSET);
94 			DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD,
95 					OMAP2_PRCM_CLKSRC_CTRL_OFFSET);
96 		}
97 		DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN);
98 		DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1);
99 		DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2);
100 		DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN);
101 		DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN);
102 		DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE);
103 		DUMP_PRM_MOD_REG(CORE_MOD, OMAP2_PM_PWSTST);
104 #endif
105 #if 0
106 		/* DSP */
107 		if (cpu_is_omap24xx()) {
108 			DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN);
109 			DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN);
110 			DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST);
111 			DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
112 			DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL);
113 			DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_CM_CLKSTCTRL);
114 			DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTCTRL);
115 			DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTST);
116 			DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTCTRL);
117 			DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTST);
118 		}
119 #endif
120 	} else {
121 		DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1);
122 		if (cpu_is_omap24xx())
123 			DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2);
124 		DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST);
125 		DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
126 #if 1
127 		DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
128 		DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);
129 		DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8);
130 #endif
131 	}
132 
133 	switch (mode) {
134 	case 0:
135 		s1 = "full";
136 		s2 = "retention";
137 		break;
138 	case 1:
139 		s1 = "MPU";
140 		s2 = "retention";
141 		break;
142 	case 2:
143 		s1 = "MPU";
144 		s2 = "idle";
145 		break;
146 	}
147 
148 	if (!resume)
149 #ifdef CONFIG_NO_HZ
150 		printk(KERN_INFO
151 		       "--- Going to %s %s (next timer after %u ms)\n", s1, s2,
152 		       jiffies_to_msecs(get_next_timer_interrupt(jiffies) -
153 					jiffies));
154 #else
155 		printk(KERN_INFO "--- Going to %s %s\n", s1, s2);
156 #endif
157 	else
158 		printk(KERN_INFO "--- Woke up (slept for %u.%03u ms)\n",
159 			us / 1000, us % 1000);
160 
161 	for (i = 0; i < reg_count; i++)
162 		printk(KERN_INFO "%-20s: 0x%08x\n", regs[i].name, regs[i].val);
163 }
164 
165 void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
166 {
167 	u32 tick_rate, cycles;
168 
169 	if (!seconds && !milliseconds)
170 		return;
171 
172 	tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
173 	cycles = tick_rate * seconds + tick_rate * milliseconds / 1000;
174 	omap_dm_timer_stop(gptimer_wakeup);
175 	omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
176 
177 	pr_info("PM: Resume timer in %u.%03u secs"
178 		" (%d ticks at %d ticks/sec.)\n",
179 		seconds, milliseconds, cycles, tick_rate);
180 }
181 
182 #ifdef CONFIG_DEBUG_FS
183 #include <linux/debugfs.h>
184 #include <linux/seq_file.h>
185 
186 static void pm_dbg_regset_store(u32 *ptr);
187 
188 static struct dentry *pm_dbg_dir;
189 
190 static int pm_dbg_init_done;
191 
192 static int __init pm_dbg_init(void);
193 
194 enum {
195 	DEBUG_FILE_COUNTERS = 0,
196 	DEBUG_FILE_TIMERS,
197 };
198 
199 struct pm_module_def {
200 	char name[8]; /* Name of the module */
201 	short type; /* CM or PRM */
202 	unsigned short offset;
203 	int low; /* First register address on this module */
204 	int high; /* Last register address on this module */
205 };
206 
207 #define MOD_CM 0
208 #define MOD_PRM 1
209 
210 static const struct pm_module_def *pm_dbg_reg_modules;
211 static const struct pm_module_def omap3_pm_reg_modules[] = {
212 	{ "IVA2", MOD_CM, OMAP3430_IVA2_MOD, 0, 0x4c },
213 	{ "OCP", MOD_CM, OCP_MOD, 0, 0x10 },
214 	{ "MPU", MOD_CM, MPU_MOD, 4, 0x4c },
215 	{ "CORE", MOD_CM, CORE_MOD, 0, 0x4c },
216 	{ "SGX", MOD_CM, OMAP3430ES2_SGX_MOD, 0, 0x4c },
217 	{ "WKUP", MOD_CM, WKUP_MOD, 0, 0x40 },
218 	{ "CCR", MOD_CM, PLL_MOD, 0, 0x70 },
219 	{ "DSS", MOD_CM, OMAP3430_DSS_MOD, 0, 0x4c },
220 	{ "CAM", MOD_CM, OMAP3430_CAM_MOD, 0, 0x4c },
221 	{ "PER", MOD_CM, OMAP3430_PER_MOD, 0, 0x4c },
222 	{ "EMU", MOD_CM, OMAP3430_EMU_MOD, 0x40, 0x54 },
223 	{ "NEON", MOD_CM, OMAP3430_NEON_MOD, 0x20, 0x48 },
224 	{ "USB", MOD_CM, OMAP3430ES2_USBHOST_MOD, 0, 0x4c },
225 
226 	{ "IVA2", MOD_PRM, OMAP3430_IVA2_MOD, 0x50, 0xfc },
227 	{ "OCP", MOD_PRM, OCP_MOD, 4, 0x1c },
228 	{ "MPU", MOD_PRM, MPU_MOD, 0x58, 0xe8 },
229 	{ "CORE", MOD_PRM, CORE_MOD, 0x58, 0xf8 },
230 	{ "SGX", MOD_PRM, OMAP3430ES2_SGX_MOD, 0x58, 0xe8 },
231 	{ "WKUP", MOD_PRM, WKUP_MOD, 0xa0, 0xb0 },
232 	{ "CCR", MOD_PRM, PLL_MOD, 0x40, 0x70 },
233 	{ "DSS", MOD_PRM, OMAP3430_DSS_MOD, 0x58, 0xe8 },
234 	{ "CAM", MOD_PRM, OMAP3430_CAM_MOD, 0x58, 0xe8 },
235 	{ "PER", MOD_PRM, OMAP3430_PER_MOD, 0x58, 0xe8 },
236 	{ "EMU", MOD_PRM, OMAP3430_EMU_MOD, 0x58, 0xe4 },
237 	{ "GLBL", MOD_PRM, OMAP3430_GR_MOD, 0x20, 0xe4 },
238 	{ "NEON", MOD_PRM, OMAP3430_NEON_MOD, 0x58, 0xe8 },
239 	{ "USB", MOD_PRM, OMAP3430ES2_USBHOST_MOD, 0x58, 0xe8 },
240 	{ "", 0, 0, 0, 0 },
241 };
242 
243 #define PM_DBG_MAX_REG_SETS 4
244 
245 static void *pm_dbg_reg_set[PM_DBG_MAX_REG_SETS];
246 
247 static int pm_dbg_get_regset_size(void)
248 {
249 	static int regset_size;
250 
251 	if (regset_size == 0) {
252 		int i = 0;
253 
254 		while (pm_dbg_reg_modules[i].name[0] != 0) {
255 			regset_size += pm_dbg_reg_modules[i].high +
256 				4 - pm_dbg_reg_modules[i].low;
257 			i++;
258 		}
259 	}
260 	return regset_size;
261 }
262 
263 static int pm_dbg_show_regs(struct seq_file *s, void *unused)
264 {
265 	int i, j;
266 	unsigned long val;
267 	int reg_set = (int)s->private;
268 	u32 *ptr;
269 	void *store = NULL;
270 	int regs;
271 	int linefeed;
272 
273 	if (reg_set == 0) {
274 		store = kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL);
275 		ptr = store;
276 		pm_dbg_regset_store(ptr);
277 	} else {
278 		ptr = pm_dbg_reg_set[reg_set - 1];
279 	}
280 
281 	i = 0;
282 
283 	while (pm_dbg_reg_modules[i].name[0] != 0) {
284 		regs = 0;
285 		linefeed = 0;
286 		if (pm_dbg_reg_modules[i].type == MOD_CM)
287 			seq_printf(s, "MOD: CM_%s (%08x)\n",
288 				pm_dbg_reg_modules[i].name,
289 				(u32)(OMAP3430_CM_BASE +
290 				pm_dbg_reg_modules[i].offset));
291 		else
292 			seq_printf(s, "MOD: PRM_%s (%08x)\n",
293 				pm_dbg_reg_modules[i].name,
294 				(u32)(OMAP3430_PRM_BASE +
295 				pm_dbg_reg_modules[i].offset));
296 
297 		for (j = pm_dbg_reg_modules[i].low;
298 			j <= pm_dbg_reg_modules[i].high; j += 4) {
299 			val = *(ptr++);
300 			if (val != 0) {
301 				regs++;
302 				if (linefeed) {
303 					seq_printf(s, "\n");
304 					linefeed = 0;
305 				}
306 				seq_printf(s, "  %02x => %08lx", j, val);
307 				if (regs % 4 == 0)
308 					linefeed = 1;
309 			}
310 		}
311 		seq_printf(s, "\n");
312 		i++;
313 	}
314 
315 	if (store != NULL)
316 		kfree(store);
317 
318 	return 0;
319 }
320 
321 static void pm_dbg_regset_store(u32 *ptr)
322 {
323 	int i, j;
324 	u32 val;
325 
326 	i = 0;
327 
328 	while (pm_dbg_reg_modules[i].name[0] != 0) {
329 		for (j = pm_dbg_reg_modules[i].low;
330 			j <= pm_dbg_reg_modules[i].high; j += 4) {
331 			if (pm_dbg_reg_modules[i].type == MOD_CM)
332 				val = omap2_cm_read_mod_reg(
333 					pm_dbg_reg_modules[i].offset, j);
334 			else
335 				val = omap2_prm_read_mod_reg(
336 					pm_dbg_reg_modules[i].offset, j);
337 			*(ptr++) = val;
338 		}
339 		i++;
340 	}
341 }
342 
343 int pm_dbg_regset_save(int reg_set)
344 {
345 	if (pm_dbg_reg_set[reg_set-1] == NULL)
346 		return -EINVAL;
347 
348 	pm_dbg_regset_store(pm_dbg_reg_set[reg_set-1]);
349 
350 	return 0;
351 }
352 
353 static const char pwrdm_state_names[][PWRDM_MAX_PWRSTS] = {
354 	"OFF",
355 	"RET",
356 	"INA",
357 	"ON"
358 };
359 
360 void pm_dbg_update_time(struct powerdomain *pwrdm, int prev)
361 {
362 	s64 t;
363 
364 	if (!pm_dbg_init_done)
365 		return ;
366 
367 	/* Update timer for previous state */
368 	t = sched_clock();
369 
370 	pwrdm->state_timer[prev] += t - pwrdm->timer;
371 
372 	pwrdm->timer = t;
373 }
374 
375 static int clkdm_dbg_show_counter(struct clockdomain *clkdm, void *user)
376 {
377 	struct seq_file *s = (struct seq_file *)user;
378 
379 	if (strcmp(clkdm->name, "emu_clkdm") == 0 ||
380 		strcmp(clkdm->name, "wkup_clkdm") == 0 ||
381 		strncmp(clkdm->name, "dpll", 4) == 0)
382 		return 0;
383 
384 	seq_printf(s, "%s->%s (%d)", clkdm->name,
385 			clkdm->pwrdm.ptr->name,
386 			atomic_read(&clkdm->usecount));
387 	seq_printf(s, "\n");
388 
389 	return 0;
390 }
391 
392 static int pwrdm_dbg_show_counter(struct powerdomain *pwrdm, void *user)
393 {
394 	struct seq_file *s = (struct seq_file *)user;
395 	int i;
396 
397 	if (strcmp(pwrdm->name, "emu_pwrdm") == 0 ||
398 		strcmp(pwrdm->name, "wkup_pwrdm") == 0 ||
399 		strncmp(pwrdm->name, "dpll", 4) == 0)
400 		return 0;
401 
402 	if (pwrdm->state != pwrdm_read_pwrst(pwrdm))
403 		printk(KERN_ERR "pwrdm state mismatch(%s) %d != %d\n",
404 			pwrdm->name, pwrdm->state, pwrdm_read_pwrst(pwrdm));
405 
406 	seq_printf(s, "%s (%s)", pwrdm->name,
407 			pwrdm_state_names[pwrdm->state]);
408 	for (i = 0; i < PWRDM_MAX_PWRSTS; i++)
409 		seq_printf(s, ",%s:%d", pwrdm_state_names[i],
410 			pwrdm->state_counter[i]);
411 
412 	seq_printf(s, ",RET-LOGIC-OFF:%d", pwrdm->ret_logic_off_counter);
413 	for (i = 0; i < pwrdm->banks; i++)
414 		seq_printf(s, ",RET-MEMBANK%d-OFF:%d", i + 1,
415 				pwrdm->ret_mem_off_counter[i]);
416 
417 	seq_printf(s, "\n");
418 
419 	return 0;
420 }
421 
422 static int pwrdm_dbg_show_timer(struct powerdomain *pwrdm, void *user)
423 {
424 	struct seq_file *s = (struct seq_file *)user;
425 	int i;
426 
427 	if (strcmp(pwrdm->name, "emu_pwrdm") == 0 ||
428 		strcmp(pwrdm->name, "wkup_pwrdm") == 0 ||
429 		strncmp(pwrdm->name, "dpll", 4) == 0)
430 		return 0;
431 
432 	pwrdm_state_switch(pwrdm);
433 
434 	seq_printf(s, "%s (%s)", pwrdm->name,
435 		pwrdm_state_names[pwrdm->state]);
436 
437 	for (i = 0; i < 4; i++)
438 		seq_printf(s, ",%s:%lld", pwrdm_state_names[i],
439 			pwrdm->state_timer[i]);
440 
441 	seq_printf(s, "\n");
442 	return 0;
443 }
444 
445 static int pm_dbg_show_counters(struct seq_file *s, void *unused)
446 {
447 	pwrdm_for_each(pwrdm_dbg_show_counter, s);
448 	clkdm_for_each(clkdm_dbg_show_counter, s);
449 
450 	return 0;
451 }
452 
453 static int pm_dbg_show_timers(struct seq_file *s, void *unused)
454 {
455 	pwrdm_for_each(pwrdm_dbg_show_timer, s);
456 	return 0;
457 }
458 
459 static int pm_dbg_open(struct inode *inode, struct file *file)
460 {
461 	switch ((int)inode->i_private) {
462 	case DEBUG_FILE_COUNTERS:
463 		return single_open(file, pm_dbg_show_counters,
464 			&inode->i_private);
465 	case DEBUG_FILE_TIMERS:
466 	default:
467 		return single_open(file, pm_dbg_show_timers,
468 			&inode->i_private);
469 	};
470 }
471 
472 static int pm_dbg_reg_open(struct inode *inode, struct file *file)
473 {
474 	return single_open(file, pm_dbg_show_regs, inode->i_private);
475 }
476 
477 static const struct file_operations debug_fops = {
478 	.open           = pm_dbg_open,
479 	.read           = seq_read,
480 	.llseek         = seq_lseek,
481 	.release        = single_release,
482 };
483 
484 static const struct file_operations debug_reg_fops = {
485 	.open           = pm_dbg_reg_open,
486 	.read           = seq_read,
487 	.llseek         = seq_lseek,
488 	.release        = single_release,
489 };
490 
491 int pm_dbg_regset_init(int reg_set)
492 {
493 	char name[2];
494 
495 	if (!pm_dbg_init_done)
496 		pm_dbg_init();
497 
498 	if (reg_set < 1 || reg_set > PM_DBG_MAX_REG_SETS ||
499 		pm_dbg_reg_set[reg_set-1] != NULL)
500 		return -EINVAL;
501 
502 	pm_dbg_reg_set[reg_set-1] =
503 		kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL);
504 
505 	if (pm_dbg_reg_set[reg_set-1] == NULL)
506 		return -ENOMEM;
507 
508 	if (pm_dbg_dir != NULL) {
509 		sprintf(name, "%d", reg_set);
510 
511 		(void) debugfs_create_file(name, S_IRUGO,
512 			pm_dbg_dir, (void *)reg_set, &debug_reg_fops);
513 	}
514 
515 	return 0;
516 }
517 
518 static int pwrdm_suspend_get(void *data, u64 *val)
519 {
520 	int ret = -EINVAL;
521 
522 	if (cpu_is_omap34xx())
523 		ret = omap3_pm_get_suspend_state((struct powerdomain *)data);
524 	*val = ret;
525 
526 	if (ret >= 0)
527 		return 0;
528 	return *val;
529 }
530 
531 static int pwrdm_suspend_set(void *data, u64 val)
532 {
533 	if (cpu_is_omap34xx())
534 		return omap3_pm_set_suspend_state(
535 			(struct powerdomain *)data, (int)val);
536 	return -EINVAL;
537 }
538 
539 DEFINE_SIMPLE_ATTRIBUTE(pwrdm_suspend_fops, pwrdm_suspend_get,
540 			pwrdm_suspend_set, "%llu\n");
541 
542 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *dir)
543 {
544 	int i;
545 	s64 t;
546 	struct dentry *d;
547 
548 	t = sched_clock();
549 
550 	for (i = 0; i < 4; i++)
551 		pwrdm->state_timer[i] = 0;
552 
553 	pwrdm->timer = t;
554 
555 	if (strncmp(pwrdm->name, "dpll", 4) == 0)
556 		return 0;
557 
558 	d = debugfs_create_dir(pwrdm->name, (struct dentry *)dir);
559 
560 	(void) debugfs_create_file("suspend", S_IRUGO|S_IWUSR, d,
561 			(void *)pwrdm, &pwrdm_suspend_fops);
562 
563 	return 0;
564 }
565 
566 static int option_get(void *data, u64 *val)
567 {
568 	u32 *option = data;
569 
570 	*val = *option;
571 
572 	return 0;
573 }
574 
575 static int option_set(void *data, u64 val)
576 {
577 	u32 *option = data;
578 
579 	if (option == &wakeup_timer_milliseconds && val >= 1000)
580 		return -EINVAL;
581 
582 	*option = val;
583 
584 	if (option == &enable_off_mode) {
585 		if (val)
586 			omap_pm_enable_off_mode();
587 		else
588 			omap_pm_disable_off_mode();
589 		if (cpu_is_omap34xx())
590 			omap3_pm_off_mode_enable(val);
591 	}
592 
593 	return 0;
594 }
595 
596 DEFINE_SIMPLE_ATTRIBUTE(pm_dbg_option_fops, option_get, option_set, "%llu\n");
597 
598 static int __init pm_dbg_init(void)
599 {
600 	int i;
601 	struct dentry *d;
602 	char name[2];
603 
604 	if (pm_dbg_init_done)
605 		return 0;
606 
607 	if (cpu_is_omap34xx())
608 		pm_dbg_reg_modules = omap3_pm_reg_modules;
609 	else {
610 		printk(KERN_ERR "%s: only OMAP3 supported\n", __func__);
611 		return -ENODEV;
612 	}
613 
614 	d = debugfs_create_dir("pm_debug", NULL);
615 	if (IS_ERR(d))
616 		return PTR_ERR(d);
617 
618 	(void) debugfs_create_file("count", S_IRUGO,
619 		d, (void *)DEBUG_FILE_COUNTERS, &debug_fops);
620 	(void) debugfs_create_file("time", S_IRUGO,
621 		d, (void *)DEBUG_FILE_TIMERS, &debug_fops);
622 
623 	pwrdm_for_each(pwrdms_setup, (void *)d);
624 
625 	pm_dbg_dir = debugfs_create_dir("registers", d);
626 	if (IS_ERR(pm_dbg_dir))
627 		return PTR_ERR(pm_dbg_dir);
628 
629 	(void) debugfs_create_file("current", S_IRUGO,
630 		pm_dbg_dir, (void *)0, &debug_reg_fops);
631 
632 	for (i = 0; i < PM_DBG_MAX_REG_SETS; i++)
633 		if (pm_dbg_reg_set[i] != NULL) {
634 			sprintf(name, "%d", i+1);
635 			(void) debugfs_create_file(name, S_IRUGO,
636 				pm_dbg_dir, (void *)(i+1), &debug_reg_fops);
637 
638 		}
639 
640 	(void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUSR, d,
641 				   &enable_off_mode, &pm_dbg_option_fops);
642 	(void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUSR, d,
643 				   &sleep_while_idle, &pm_dbg_option_fops);
644 	(void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUSR, d,
645 				   &wakeup_timer_seconds, &pm_dbg_option_fops);
646 	(void) debugfs_create_file("wakeup_timer_milliseconds",
647 			S_IRUGO | S_IWUSR, d, &wakeup_timer_milliseconds,
648 			&pm_dbg_option_fops);
649 	pm_dbg_init_done = 1;
650 
651 	return 0;
652 }
653 arch_initcall(pm_dbg_init);
654 
655 #endif
656