1d8a94458SPaul Walmsley /* 2d8a94458SPaul Walmsley * opp2xxx.h - macros for old-style OMAP2xxx "OPP" definitions 3d8a94458SPaul Walmsley * 4d8a94458SPaul Walmsley * Copyright (C) 2005-2009 Texas Instruments, Inc. 5d8a94458SPaul Walmsley * Copyright (C) 2004-2009 Nokia Corporation 6d8a94458SPaul Walmsley * 7d8a94458SPaul Walmsley * Richard Woodruff <r-woodruff2@ti.com> 8d8a94458SPaul Walmsley * 9d8a94458SPaul Walmsley * The OMAP2 processor can be run at several discrete 'PRCM configurations'. 10d8a94458SPaul Walmsley * These configurations are characterized by voltage and speed for clocks. 11d8a94458SPaul Walmsley * The device is only validated for certain combinations. One way to express 12d8a94458SPaul Walmsley * these combinations is via the 'ratio's' which the clocks operate with 13d8a94458SPaul Walmsley * respect to each other. These ratio sets are for a given voltage/DPLL 14d8a94458SPaul Walmsley * setting. All configurations can be described by a DPLL setting and a ratio 15d8a94458SPaul Walmsley * There are 3 ratio sets for the 2430 and X ratio sets for 2420. 16d8a94458SPaul Walmsley * 17d8a94458SPaul Walmsley * 2430 differs from 2420 in that there are no more phase synchronizers used. 18d8a94458SPaul Walmsley * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs 19d8a94458SPaul Walmsley * 2430 (iva2.1, NOdsp, mdm) 20d8a94458SPaul Walmsley * 21d8a94458SPaul Walmsley * XXX Missing voltage data. 22d8a94458SPaul Walmsley * 23d8a94458SPaul Walmsley * THe format described in this file is deprecated. Once a reasonable 24d8a94458SPaul Walmsley * OPP API exists, the data in this file should be converted to use it. 25d8a94458SPaul Walmsley * 26d8a94458SPaul Walmsley * This is technically part of the OMAP2xxx clock code. 27d8a94458SPaul Walmsley */ 28d8a94458SPaul Walmsley 29d8a94458SPaul Walmsley #ifndef __ARCH_ARM_MACH_OMAP2_OPP2XXX_H 30d8a94458SPaul Walmsley #define __ARCH_ARM_MACH_OMAP2_OPP2XXX_H 31d8a94458SPaul Walmsley 32d8a94458SPaul Walmsley /** 33d8a94458SPaul Walmsley * struct prcm_config - define clock rates on a per-OPP basis (24xx) 34d8a94458SPaul Walmsley * 35d8a94458SPaul Walmsley * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. 36d8a94458SPaul Walmsley * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP 37d8a94458SPaul Walmsley * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM 38d8a94458SPaul Walmsley * 39d8a94458SPaul Walmsley * This is deprecated. As soon as we have a decent OPP API, we should 40d8a94458SPaul Walmsley * move all this stuff to it. 41d8a94458SPaul Walmsley */ 42d8a94458SPaul Walmsley struct prcm_config { 43d8a94458SPaul Walmsley unsigned long xtal_speed; /* crystal rate */ 44d8a94458SPaul Walmsley unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */ 45d8a94458SPaul Walmsley unsigned long mpu_speed; /* speed of MPU */ 46d8a94458SPaul Walmsley unsigned long cm_clksel_mpu; /* mpu divider */ 47d8a94458SPaul Walmsley unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */ 48d8a94458SPaul Walmsley unsigned long cm_clksel_gfx; /* gfx dividers */ 49d8a94458SPaul Walmsley unsigned long cm_clksel1_core; /* major subsystem dividers */ 50d8a94458SPaul Walmsley unsigned long cm_clksel1_pll; /* m,n */ 51d8a94458SPaul Walmsley unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */ 52d8a94458SPaul Walmsley unsigned long cm_clksel_mdm; /* modem dividers 2430 only */ 53d8a94458SPaul Walmsley unsigned long base_sdrc_rfr; /* base refresh timing for a set */ 54d8a94458SPaul Walmsley unsigned char flags; 55d8a94458SPaul Walmsley }; 56d8a94458SPaul Walmsley 57d8a94458SPaul Walmsley 58d8a94458SPaul Walmsley /* Core fields for cm_clksel, not ratio governed */ 59d8a94458SPaul Walmsley #define RX_CLKSEL_DSS1 (0x10 << 8) 60d8a94458SPaul Walmsley #define RX_CLKSEL_DSS2 (0x0 << 13) 61d8a94458SPaul Walmsley #define RX_CLKSEL_SSI (0x5 << 20) 62d8a94458SPaul Walmsley 63d8a94458SPaul Walmsley /*------------------------------------------------------------------------- 64d8a94458SPaul Walmsley * Voltage/DPLL ratios 65d8a94458SPaul Walmsley *-------------------------------------------------------------------------*/ 66d8a94458SPaul Walmsley 67d8a94458SPaul Walmsley /* 2430 Ratio's, 2430-Ratio Config 1 */ 68d8a94458SPaul Walmsley #define R1_CLKSEL_L3 (4 << 0) 69d8a94458SPaul Walmsley #define R1_CLKSEL_L4 (2 << 5) 70d8a94458SPaul Walmsley #define R1_CLKSEL_USB (4 << 25) 71d8a94458SPaul Walmsley #define R1_CM_CLKSEL1_CORE_VAL (R1_CLKSEL_USB | RX_CLKSEL_SSI | \ 72d8a94458SPaul Walmsley RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ 73d8a94458SPaul Walmsley R1_CLKSEL_L4 | R1_CLKSEL_L3) 74d8a94458SPaul Walmsley #define R1_CLKSEL_MPU (2 << 0) 75d8a94458SPaul Walmsley #define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU 76d8a94458SPaul Walmsley #define R1_CLKSEL_DSP (2 << 0) 77d8a94458SPaul Walmsley #define R1_CLKSEL_DSP_IF (2 << 5) 78d8a94458SPaul Walmsley #define R1_CM_CLKSEL_DSP_VAL (R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF) 79d8a94458SPaul Walmsley #define R1_CLKSEL_GFX (2 << 0) 80d8a94458SPaul Walmsley #define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX 81d8a94458SPaul Walmsley #define R1_CLKSEL_MDM (4 << 0) 82d8a94458SPaul Walmsley #define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM 83d8a94458SPaul Walmsley 84d8a94458SPaul Walmsley /* 2430-Ratio Config 2 */ 85d8a94458SPaul Walmsley #define R2_CLKSEL_L3 (6 << 0) 86d8a94458SPaul Walmsley #define R2_CLKSEL_L4 (2 << 5) 87d8a94458SPaul Walmsley #define R2_CLKSEL_USB (2 << 25) 88d8a94458SPaul Walmsley #define R2_CM_CLKSEL1_CORE_VAL (R2_CLKSEL_USB | RX_CLKSEL_SSI | \ 89d8a94458SPaul Walmsley RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ 90d8a94458SPaul Walmsley R2_CLKSEL_L4 | R2_CLKSEL_L3) 91d8a94458SPaul Walmsley #define R2_CLKSEL_MPU (2 << 0) 92d8a94458SPaul Walmsley #define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU 93d8a94458SPaul Walmsley #define R2_CLKSEL_DSP (2 << 0) 94d8a94458SPaul Walmsley #define R2_CLKSEL_DSP_IF (3 << 5) 95d8a94458SPaul Walmsley #define R2_CM_CLKSEL_DSP_VAL (R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF) 96d8a94458SPaul Walmsley #define R2_CLKSEL_GFX (2 << 0) 97d8a94458SPaul Walmsley #define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX 98d8a94458SPaul Walmsley #define R2_CLKSEL_MDM (6 << 0) 99d8a94458SPaul Walmsley #define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM 100d8a94458SPaul Walmsley 101d8a94458SPaul Walmsley /* 2430-Ratio Bootm (BYPASS) */ 102d8a94458SPaul Walmsley #define RB_CLKSEL_L3 (1 << 0) 103d8a94458SPaul Walmsley #define RB_CLKSEL_L4 (1 << 5) 104d8a94458SPaul Walmsley #define RB_CLKSEL_USB (1 << 25) 105d8a94458SPaul Walmsley #define RB_CM_CLKSEL1_CORE_VAL (RB_CLKSEL_USB | RX_CLKSEL_SSI | \ 106d8a94458SPaul Walmsley RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ 107d8a94458SPaul Walmsley RB_CLKSEL_L4 | RB_CLKSEL_L3) 108d8a94458SPaul Walmsley #define RB_CLKSEL_MPU (1 << 0) 109d8a94458SPaul Walmsley #define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU 110d8a94458SPaul Walmsley #define RB_CLKSEL_DSP (1 << 0) 111d8a94458SPaul Walmsley #define RB_CLKSEL_DSP_IF (1 << 5) 112d8a94458SPaul Walmsley #define RB_CM_CLKSEL_DSP_VAL (RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF) 113d8a94458SPaul Walmsley #define RB_CLKSEL_GFX (1 << 0) 114d8a94458SPaul Walmsley #define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX 115d8a94458SPaul Walmsley #define RB_CLKSEL_MDM (1 << 0) 116d8a94458SPaul Walmsley #define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM 117d8a94458SPaul Walmsley 118d8a94458SPaul Walmsley /* 2420 Ratio Equivalents */ 119d8a94458SPaul Walmsley #define RXX_CLKSEL_VLYNQ (0x12 << 15) 120d8a94458SPaul Walmsley #define RXX_CLKSEL_SSI (0x8 << 20) 121d8a94458SPaul Walmsley 122d8a94458SPaul Walmsley /* 2420-PRCM III 532MHz core */ 123d8a94458SPaul Walmsley #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */ 124d8a94458SPaul Walmsley #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */ 125d8a94458SPaul Walmsley #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */ 126d8a94458SPaul Walmsley #define RIII_CM_CLKSEL1_CORE_VAL (RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \ 127d8a94458SPaul Walmsley RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \ 128d8a94458SPaul Walmsley RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \ 129d8a94458SPaul Walmsley RIII_CLKSEL_L3) 130d8a94458SPaul Walmsley #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */ 131d8a94458SPaul Walmsley #define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU 132d8a94458SPaul Walmsley #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */ 133d8a94458SPaul Walmsley #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */ 134d8a94458SPaul Walmsley #define RIII_SYNC_DSP (1 << 7) /* Enable sync */ 135d8a94458SPaul Walmsley #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */ 136d8a94458SPaul Walmsley #define RIII_SYNC_IVA (1 << 13) /* Enable sync */ 137d8a94458SPaul Walmsley #define RIII_CM_CLKSEL_DSP_VAL (RIII_SYNC_IVA | RIII_CLKSEL_IVA | \ 138d8a94458SPaul Walmsley RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \ 139d8a94458SPaul Walmsley RIII_CLKSEL_DSP) 140d8a94458SPaul Walmsley #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */ 141d8a94458SPaul Walmsley #define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX 142d8a94458SPaul Walmsley 143d8a94458SPaul Walmsley /* 2420-PRCM II 600MHz core */ 144d8a94458SPaul Walmsley #define RII_CLKSEL_L3 (6 << 0) /* 100MHz */ 145d8a94458SPaul Walmsley #define RII_CLKSEL_L4 (2 << 5) /* 50MHz */ 146d8a94458SPaul Walmsley #define RII_CLKSEL_USB (2 << 25) /* 50MHz */ 147d8a94458SPaul Walmsley #define RII_CM_CLKSEL1_CORE_VAL (RII_CLKSEL_USB | RXX_CLKSEL_SSI | \ 148d8a94458SPaul Walmsley RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \ 149d8a94458SPaul Walmsley RX_CLKSEL_DSS1 | RII_CLKSEL_L4 | \ 150d8a94458SPaul Walmsley RII_CLKSEL_L3) 151d8a94458SPaul Walmsley #define RII_CLKSEL_MPU (2 << 0) /* 300MHz */ 152d8a94458SPaul Walmsley #define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU 153d8a94458SPaul Walmsley #define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */ 154d8a94458SPaul Walmsley #define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */ 155d8a94458SPaul Walmsley #define RII_SYNC_DSP (0 << 7) /* Bypass sync */ 156d8a94458SPaul Walmsley #define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */ 157d8a94458SPaul Walmsley #define RII_SYNC_IVA (0 << 13) /* Bypass sync */ 158d8a94458SPaul Walmsley #define RII_CM_CLKSEL_DSP_VAL (RII_SYNC_IVA | RII_CLKSEL_IVA | \ 159d8a94458SPaul Walmsley RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \ 160d8a94458SPaul Walmsley RII_CLKSEL_DSP) 161d8a94458SPaul Walmsley #define RII_CLKSEL_GFX (2 << 0) /* 50MHz */ 162d8a94458SPaul Walmsley #define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX 163d8a94458SPaul Walmsley 164d8a94458SPaul Walmsley /* 2420-PRCM I 660MHz core */ 165d8a94458SPaul Walmsley #define RI_CLKSEL_L3 (4 << 0) /* 165MHz */ 166d8a94458SPaul Walmsley #define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */ 167d8a94458SPaul Walmsley #define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */ 168d8a94458SPaul Walmsley #define RI_CM_CLKSEL1_CORE_VAL (RI_CLKSEL_USB | \ 169d8a94458SPaul Walmsley RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \ 170d8a94458SPaul Walmsley RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ 171d8a94458SPaul Walmsley RI_CLKSEL_L4 | RI_CLKSEL_L3) 172d8a94458SPaul Walmsley #define RI_CLKSEL_MPU (2 << 0) /* 330MHz */ 173d8a94458SPaul Walmsley #define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU 174d8a94458SPaul Walmsley #define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */ 175d8a94458SPaul Walmsley #define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */ 176d8a94458SPaul Walmsley #define RI_SYNC_DSP (1 << 7) /* Activate sync */ 177d8a94458SPaul Walmsley #define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */ 178d8a94458SPaul Walmsley #define RI_SYNC_IVA (0 << 13) /* Bypass sync */ 179d8a94458SPaul Walmsley #define RI_CM_CLKSEL_DSP_VAL (RI_SYNC_IVA | RI_CLKSEL_IVA | \ 180d8a94458SPaul Walmsley RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \ 181d8a94458SPaul Walmsley RI_CLKSEL_DSP) 182d8a94458SPaul Walmsley #define RI_CLKSEL_GFX (1 << 0) /* 165MHz */ 183d8a94458SPaul Walmsley #define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX 184d8a94458SPaul Walmsley 185d8a94458SPaul Walmsley /* 2420-PRCM VII (boot) */ 186d8a94458SPaul Walmsley #define RVII_CLKSEL_L3 (1 << 0) 187d8a94458SPaul Walmsley #define RVII_CLKSEL_L4 (1 << 5) 188d8a94458SPaul Walmsley #define RVII_CLKSEL_DSS1 (1 << 8) 189d8a94458SPaul Walmsley #define RVII_CLKSEL_DSS2 (0 << 13) 190d8a94458SPaul Walmsley #define RVII_CLKSEL_VLYNQ (1 << 15) 191d8a94458SPaul Walmsley #define RVII_CLKSEL_SSI (1 << 20) 192d8a94458SPaul Walmsley #define RVII_CLKSEL_USB (1 << 25) 193d8a94458SPaul Walmsley 194d8a94458SPaul Walmsley #define RVII_CM_CLKSEL1_CORE_VAL (RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \ 195d8a94458SPaul Walmsley RVII_CLKSEL_VLYNQ | \ 196d8a94458SPaul Walmsley RVII_CLKSEL_DSS2 | RVII_CLKSEL_DSS1 | \ 197d8a94458SPaul Walmsley RVII_CLKSEL_L4 | RVII_CLKSEL_L3) 198d8a94458SPaul Walmsley 199d8a94458SPaul Walmsley #define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */ 200d8a94458SPaul Walmsley #define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU 201d8a94458SPaul Walmsley 202d8a94458SPaul Walmsley #define RVII_CLKSEL_DSP (1 << 0) 203d8a94458SPaul Walmsley #define RVII_CLKSEL_DSP_IF (1 << 5) 204d8a94458SPaul Walmsley #define RVII_SYNC_DSP (0 << 7) 205d8a94458SPaul Walmsley #define RVII_CLKSEL_IVA (1 << 8) 206d8a94458SPaul Walmsley #define RVII_SYNC_IVA (0 << 13) 207d8a94458SPaul Walmsley #define RVII_CM_CLKSEL_DSP_VAL (RVII_SYNC_IVA | RVII_CLKSEL_IVA | \ 208d8a94458SPaul Walmsley RVII_SYNC_DSP | RVII_CLKSEL_DSP_IF | \ 209d8a94458SPaul Walmsley RVII_CLKSEL_DSP) 210d8a94458SPaul Walmsley 211d8a94458SPaul Walmsley #define RVII_CLKSEL_GFX (1 << 0) 212d8a94458SPaul Walmsley #define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX 213d8a94458SPaul Walmsley 214d8a94458SPaul Walmsley /*------------------------------------------------------------------------- 215d8a94458SPaul Walmsley * 2430 Target modes: Along with each configuration the CPU has several 216d8a94458SPaul Walmsley * modes which goes along with them. Modes mainly are the addition of 217d8a94458SPaul Walmsley * describe DPLL combinations to go along with a ratio. 218d8a94458SPaul Walmsley *-------------------------------------------------------------------------*/ 219d8a94458SPaul Walmsley 220d8a94458SPaul Walmsley /* Hardware governed */ 221d8a94458SPaul Walmsley #define MX_48M_SRC (0 << 3) 222d8a94458SPaul Walmsley #define MX_54M_SRC (0 << 5) 223d8a94458SPaul Walmsley #define MX_APLLS_CLIKIN_12 (3 << 23) 224d8a94458SPaul Walmsley #define MX_APLLS_CLIKIN_13 (2 << 23) 225d8a94458SPaul Walmsley #define MX_APLLS_CLIKIN_19_2 (0 << 23) 226d8a94458SPaul Walmsley 227d8a94458SPaul Walmsley /* 228d8a94458SPaul Walmsley * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed 229d8a94458SPaul Walmsley * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz 230d8a94458SPaul Walmsley */ 231d8a94458SPaul Walmsley #define M5A_DPLL_MULT_12 (133 << 12) 232d8a94458SPaul Walmsley #define M5A_DPLL_DIV_12 (5 << 8) 233d8a94458SPaul Walmsley #define M5A_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 234d8a94458SPaul Walmsley M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \ 235d8a94458SPaul Walmsley MX_APLLS_CLIKIN_12) 236d8a94458SPaul Walmsley #define M5A_DPLL_MULT_13 (61 << 12) 237d8a94458SPaul Walmsley #define M5A_DPLL_DIV_13 (2 << 8) 238d8a94458SPaul Walmsley #define M5A_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 239d8a94458SPaul Walmsley M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \ 240d8a94458SPaul Walmsley MX_APLLS_CLIKIN_13) 241d8a94458SPaul Walmsley #define M5A_DPLL_MULT_19 (55 << 12) 242d8a94458SPaul Walmsley #define M5A_DPLL_DIV_19 (3 << 8) 243d8a94458SPaul Walmsley #define M5A_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ 244d8a94458SPaul Walmsley M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \ 245d8a94458SPaul Walmsley MX_APLLS_CLIKIN_19_2) 246d8a94458SPaul Walmsley /* #5b (ratio1) target DPLL = 200*2 = 400MHz */ 247d8a94458SPaul Walmsley #define M5B_DPLL_MULT_12 (50 << 12) 248d8a94458SPaul Walmsley #define M5B_DPLL_DIV_12 (2 << 8) 249d8a94458SPaul Walmsley #define M5B_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 250d8a94458SPaul Walmsley M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \ 251d8a94458SPaul Walmsley MX_APLLS_CLIKIN_12) 252d8a94458SPaul Walmsley #define M5B_DPLL_MULT_13 (200 << 12) 253d8a94458SPaul Walmsley #define M5B_DPLL_DIV_13 (12 << 8) 254d8a94458SPaul Walmsley 255d8a94458SPaul Walmsley #define M5B_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 256d8a94458SPaul Walmsley M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \ 257d8a94458SPaul Walmsley MX_APLLS_CLIKIN_13) 258d8a94458SPaul Walmsley #define M5B_DPLL_MULT_19 (125 << 12) 259d8a94458SPaul Walmsley #define M5B_DPLL_DIV_19 (31 << 8) 260d8a94458SPaul Walmsley #define M5B_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ 261d8a94458SPaul Walmsley M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \ 262d8a94458SPaul Walmsley MX_APLLS_CLIKIN_19_2) 263d8a94458SPaul Walmsley /* 264d8a94458SPaul Walmsley * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz 265d8a94458SPaul Walmsley */ 266d8a94458SPaul Walmsley #define M4_DPLL_MULT_12 (133 << 12) 267d8a94458SPaul Walmsley #define M4_DPLL_DIV_12 (3 << 8) 268d8a94458SPaul Walmsley #define M4_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 269d8a94458SPaul Walmsley M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \ 270d8a94458SPaul Walmsley MX_APLLS_CLIKIN_12) 271d8a94458SPaul Walmsley 272d8a94458SPaul Walmsley #define M4_DPLL_MULT_13 (399 << 12) 273d8a94458SPaul Walmsley #define M4_DPLL_DIV_13 (12 << 8) 274d8a94458SPaul Walmsley #define M4_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 275d8a94458SPaul Walmsley M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \ 276d8a94458SPaul Walmsley MX_APLLS_CLIKIN_13) 277d8a94458SPaul Walmsley 278d8a94458SPaul Walmsley #define M4_DPLL_MULT_19 (145 << 12) 279d8a94458SPaul Walmsley #define M4_DPLL_DIV_19 (6 << 8) 280d8a94458SPaul Walmsley #define M4_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ 281d8a94458SPaul Walmsley M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \ 282d8a94458SPaul Walmsley MX_APLLS_CLIKIN_19_2) 283d8a94458SPaul Walmsley 284d8a94458SPaul Walmsley /* 285d8a94458SPaul Walmsley * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz 286d8a94458SPaul Walmsley */ 287d8a94458SPaul Walmsley #define M3_DPLL_MULT_12 (55 << 12) 288d8a94458SPaul Walmsley #define M3_DPLL_DIV_12 (1 << 8) 289d8a94458SPaul Walmsley #define M3_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 290d8a94458SPaul Walmsley M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \ 291d8a94458SPaul Walmsley MX_APLLS_CLIKIN_12) 292d8a94458SPaul Walmsley #define M3_DPLL_MULT_13 (76 << 12) 293d8a94458SPaul Walmsley #define M3_DPLL_DIV_13 (2 << 8) 294d8a94458SPaul Walmsley #define M3_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 295d8a94458SPaul Walmsley M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \ 296d8a94458SPaul Walmsley MX_APLLS_CLIKIN_13) 297d8a94458SPaul Walmsley #define M3_DPLL_MULT_19 (17 << 12) 298d8a94458SPaul Walmsley #define M3_DPLL_DIV_19 (0 << 8) 299d8a94458SPaul Walmsley #define M3_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ 300d8a94458SPaul Walmsley M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \ 301d8a94458SPaul Walmsley MX_APLLS_CLIKIN_19_2) 302d8a94458SPaul Walmsley 303d8a94458SPaul Walmsley /* 304d8a94458SPaul Walmsley * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz 305d8a94458SPaul Walmsley */ 306d8a94458SPaul Walmsley #define M2_DPLL_MULT_12 (55 << 12) 307d8a94458SPaul Walmsley #define M2_DPLL_DIV_12 (1 << 8) 308d8a94458SPaul Walmsley #define M2_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 309d8a94458SPaul Walmsley M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \ 310d8a94458SPaul Walmsley MX_APLLS_CLIKIN_12) 311d8a94458SPaul Walmsley 312d8a94458SPaul Walmsley /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2, 313d8a94458SPaul Walmsley * relock time issue */ 314d8a94458SPaul Walmsley /* Core frequency changed from 330/165 to 329/164 MHz*/ 315d8a94458SPaul Walmsley #define M2_DPLL_MULT_13 (76 << 12) 316d8a94458SPaul Walmsley #define M2_DPLL_DIV_13 (2 << 8) 317d8a94458SPaul Walmsley #define M2_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 318d8a94458SPaul Walmsley M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \ 319d8a94458SPaul Walmsley MX_APLLS_CLIKIN_13) 320d8a94458SPaul Walmsley 321d8a94458SPaul Walmsley #define M2_DPLL_MULT_19 (17 << 12) 322d8a94458SPaul Walmsley #define M2_DPLL_DIV_19 (0 << 8) 323d8a94458SPaul Walmsley #define M2_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ 324d8a94458SPaul Walmsley M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \ 325d8a94458SPaul Walmsley MX_APLLS_CLIKIN_19_2) 326d8a94458SPaul Walmsley 327d8a94458SPaul Walmsley /* boot (boot) */ 328d8a94458SPaul Walmsley #define MB_DPLL_MULT (1 << 12) 329d8a94458SPaul Walmsley #define MB_DPLL_DIV (0 << 8) 330d8a94458SPaul Walmsley #define MB_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 331d8a94458SPaul Walmsley MB_DPLL_DIV | MB_DPLL_MULT | \ 332d8a94458SPaul Walmsley MX_APLLS_CLIKIN_12) 333d8a94458SPaul Walmsley 334d8a94458SPaul Walmsley #define MB_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 335d8a94458SPaul Walmsley MB_DPLL_DIV | MB_DPLL_MULT | \ 336d8a94458SPaul Walmsley MX_APLLS_CLIKIN_13) 337d8a94458SPaul Walmsley 338d8a94458SPaul Walmsley #define MB_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ 339d8a94458SPaul Walmsley MB_DPLL_DIV | MB_DPLL_MULT | \ 340d8a94458SPaul Walmsley MX_APLLS_CLIKIN_19) 341d8a94458SPaul Walmsley 342d8a94458SPaul Walmsley /* 343d8a94458SPaul Walmsley * 2430 - chassis (sedna) 344d8a94458SPaul Walmsley * 165 (ratio1) same as above #2 345d8a94458SPaul Walmsley * 150 (ratio1) 346d8a94458SPaul Walmsley * 133 (ratio2) same as above #4 347d8a94458SPaul Walmsley * 110 (ratio2) same as above #3 348d8a94458SPaul Walmsley * 104 (ratio2) 349d8a94458SPaul Walmsley * boot (boot) 350d8a94458SPaul Walmsley */ 351d8a94458SPaul Walmsley 352d8a94458SPaul Walmsley /* PRCM I target DPLL = 2*330MHz = 660MHz */ 353d8a94458SPaul Walmsley #define MI_DPLL_MULT_12 (55 << 12) 354d8a94458SPaul Walmsley #define MI_DPLL_DIV_12 (1 << 8) 355d8a94458SPaul Walmsley #define MI_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 356d8a94458SPaul Walmsley MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \ 357d8a94458SPaul Walmsley MX_APLLS_CLIKIN_12) 358d8a94458SPaul Walmsley 359d8a94458SPaul Walmsley /* 360d8a94458SPaul Walmsley * 2420 Equivalent - mode registers 361d8a94458SPaul Walmsley * PRCM II , target DPLL = 2*300MHz = 600MHz 362d8a94458SPaul Walmsley */ 363d8a94458SPaul Walmsley #define MII_DPLL_MULT_12 (50 << 12) 364d8a94458SPaul Walmsley #define MII_DPLL_DIV_12 (1 << 8) 365d8a94458SPaul Walmsley #define MII_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 366d8a94458SPaul Walmsley MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \ 367d8a94458SPaul Walmsley MX_APLLS_CLIKIN_12) 368d8a94458SPaul Walmsley #define MII_DPLL_MULT_13 (300 << 12) 369d8a94458SPaul Walmsley #define MII_DPLL_DIV_13 (12 << 8) 370d8a94458SPaul Walmsley #define MII_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 371d8a94458SPaul Walmsley MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \ 372d8a94458SPaul Walmsley MX_APLLS_CLIKIN_13) 373d8a94458SPaul Walmsley 374d8a94458SPaul Walmsley /* PRCM III target DPLL = 2*266 = 532MHz*/ 375d8a94458SPaul Walmsley #define MIII_DPLL_MULT_12 (133 << 12) 376d8a94458SPaul Walmsley #define MIII_DPLL_DIV_12 (5 << 8) 377d8a94458SPaul Walmsley #define MIII_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 378d8a94458SPaul Walmsley MIII_DPLL_DIV_12 | \ 379d8a94458SPaul Walmsley MIII_DPLL_MULT_12 | MX_APLLS_CLIKIN_12) 380d8a94458SPaul Walmsley #define MIII_DPLL_MULT_13 (266 << 12) 381d8a94458SPaul Walmsley #define MIII_DPLL_DIV_13 (12 << 8) 382d8a94458SPaul Walmsley #define MIII_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 383d8a94458SPaul Walmsley MIII_DPLL_DIV_13 | \ 384d8a94458SPaul Walmsley MIII_DPLL_MULT_13 | MX_APLLS_CLIKIN_13) 385d8a94458SPaul Walmsley 386d8a94458SPaul Walmsley /* PRCM VII (boot bypass) */ 387d8a94458SPaul Walmsley #define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL 388d8a94458SPaul Walmsley #define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL 389d8a94458SPaul Walmsley 390d8a94458SPaul Walmsley /* High and low operation value */ 391d8a94458SPaul Walmsley #define MX_CLKSEL2_PLL_2x_VAL (2 << 0) 392d8a94458SPaul Walmsley #define MX_CLKSEL2_PLL_1x_VAL (1 << 0) 393d8a94458SPaul Walmsley 394d8a94458SPaul Walmsley /* MPU speed defines */ 395d8a94458SPaul Walmsley #define S12M 12000000 396d8a94458SPaul Walmsley #define S13M 13000000 397d8a94458SPaul Walmsley #define S19M 19200000 398d8a94458SPaul Walmsley #define S26M 26000000 399d8a94458SPaul Walmsley #define S100M 100000000 400d8a94458SPaul Walmsley #define S133M 133000000 401d8a94458SPaul Walmsley #define S150M 150000000 402d8a94458SPaul Walmsley #define S164M 164000000 403d8a94458SPaul Walmsley #define S165M 165000000 404d8a94458SPaul Walmsley #define S199M 199000000 405d8a94458SPaul Walmsley #define S200M 200000000 406d8a94458SPaul Walmsley #define S266M 266000000 407d8a94458SPaul Walmsley #define S300M 300000000 408d8a94458SPaul Walmsley #define S329M 329000000 409d8a94458SPaul Walmsley #define S330M 330000000 410d8a94458SPaul Walmsley #define S399M 399000000 411d8a94458SPaul Walmsley #define S400M 400000000 412d8a94458SPaul Walmsley #define S532M 532000000 413d8a94458SPaul Walmsley #define S600M 600000000 414d8a94458SPaul Walmsley #define S658M 658000000 415d8a94458SPaul Walmsley #define S660M 660000000 416d8a94458SPaul Walmsley #define S798M 798000000 417d8a94458SPaul Walmsley 418d8a94458SPaul Walmsley 419d8a94458SPaul Walmsley extern const struct prcm_config omap2420_rate_table[]; 42056213ca4STony Lindgren 42156213ca4STony Lindgren #ifdef CONFIG_ARCH_OMAP2430 422d8a94458SPaul Walmsley extern const struct prcm_config omap2430_rate_table[]; 42356213ca4STony Lindgren #else 42456213ca4STony Lindgren #define omap2430_rate_table NULL 42556213ca4STony Lindgren #endif 426d8a94458SPaul Walmsley extern const struct prcm_config *rate_table; 427d8a94458SPaul Walmsley extern const struct prcm_config *curr_prcm_set; 428d8a94458SPaul Walmsley 429d8a94458SPaul Walmsley #endif 430