1d8a94458SPaul Walmsley /* 2ca6eccb3SPaul Walmsley * opp2430_data.c - old-style "OPP" table for OMAP2430 3d8a94458SPaul Walmsley * 4d8a94458SPaul Walmsley * Copyright (C) 2005-2009 Texas Instruments, Inc. 5d8a94458SPaul Walmsley * Copyright (C) 2004-2009 Nokia Corporation 6d8a94458SPaul Walmsley * 7d8a94458SPaul Walmsley * Richard Woodruff <r-woodruff2@ti.com> 8d8a94458SPaul Walmsley * 9d8a94458SPaul Walmsley * The OMAP2 processor can be run at several discrete 'PRCM configurations'. 10d8a94458SPaul Walmsley * These configurations are characterized by voltage and speed for clocks. 11d8a94458SPaul Walmsley * The device is only validated for certain combinations. One way to express 12ca6eccb3SPaul Walmsley * these combinations is via the 'ratios' which the clocks operate with 13d8a94458SPaul Walmsley * respect to each other. These ratio sets are for a given voltage/DPLL 14ca6eccb3SPaul Walmsley * setting. All configurations can be described by a DPLL setting and a ratio. 15d8a94458SPaul Walmsley * 16d8a94458SPaul Walmsley * 2430 differs from 2420 in that there are no more phase synchronizers used. 17d8a94458SPaul Walmsley * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs 18d8a94458SPaul Walmsley * 2430 (iva2.1, NOdsp, mdm) 19d8a94458SPaul Walmsley * 20d8a94458SPaul Walmsley * XXX Missing voltage data. 21ca6eccb3SPaul Walmsley * XXX Missing 19.2MHz sys_clk rate sets. 22d8a94458SPaul Walmsley * 23d8a94458SPaul Walmsley * THe format described in this file is deprecated. Once a reasonable 24d8a94458SPaul Walmsley * OPP API exists, the data in this file should be converted to use it. 25d8a94458SPaul Walmsley * 26d8a94458SPaul Walmsley * This is technically part of the OMAP2xxx clock code. 27d8a94458SPaul Walmsley */ 28d8a94458SPaul Walmsley 29d8a94458SPaul Walmsley #include "opp2xxx.h" 30d8a94458SPaul Walmsley #include "sdrc.h" 31d8a94458SPaul Walmsley #include "clock.h" 32d8a94458SPaul Walmsley 33ca6eccb3SPaul Walmsley /* 34ca6eccb3SPaul Walmsley * Key dividers which make up a PRCM set. Ratios for a PRCM are mandated. 35d8a94458SPaul Walmsley * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU, 36d8a94458SPaul Walmsley * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL, 37d8a94458SPaul Walmsley * CM_CLKSEL2_PLL, CM_CLKSEL_MDM 38d8a94458SPaul Walmsley * 39ca6eccb3SPaul Walmsley * Filling in table based on 2430-SDPs variants available. There are 40ca6eccb3SPaul Walmsley * quite a few more rate combinations which could be defined. 41d8a94458SPaul Walmsley * 42ca6eccb3SPaul Walmsley * When multiple values are defined the start up will try and choose 43ca6eccb3SPaul Walmsley * the fastest one. If a 'fast' value is defined, then automatically, 44ca6eccb3SPaul Walmsley * the /2 one should be included as it can be used. Generally having 45ca6eccb3SPaul Walmsley * more than one fast set does not make sense, as static timings need 46ca6eccb3SPaul Walmsley * to be changed to change the set. The exception is the bypass 47ca6eccb3SPaul Walmsley * setting which is available for low power bypass. 48d8a94458SPaul Walmsley * 49d8a94458SPaul Walmsley * Note: This table needs to be sorted, fastest to slowest. 50ca6eccb3SPaul Walmsley */ 51d8a94458SPaul Walmsley const struct prcm_config omap2430_rate_table[] = { 52d8a94458SPaul Walmsley /* PRCM #4 - ratio2 (ES2.1) - FAST */ 53d8a94458SPaul Walmsley {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */ 54d8a94458SPaul Walmsley R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, 55d8a94458SPaul Walmsley R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL, 56d8a94458SPaul Walmsley MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL, 57d8a94458SPaul Walmsley SDRC_RFR_CTRL_133MHz, 58d8a94458SPaul Walmsley RATE_IN_243X}, 59d8a94458SPaul Walmsley 60d8a94458SPaul Walmsley /* PRCM #2 - ratio1 (ES2) - FAST */ 61d8a94458SPaul Walmsley {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */ 62d8a94458SPaul Walmsley R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, 63d8a94458SPaul Walmsley R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL, 64d8a94458SPaul Walmsley MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, 65d8a94458SPaul Walmsley SDRC_RFR_CTRL_165MHz, 66d8a94458SPaul Walmsley RATE_IN_243X}, 67d8a94458SPaul Walmsley 68d8a94458SPaul Walmsley /* PRCM #5a - ratio1 - FAST */ 69d8a94458SPaul Walmsley {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ 70d8a94458SPaul Walmsley R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, 71d8a94458SPaul Walmsley R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, 72d8a94458SPaul Walmsley MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, 73d8a94458SPaul Walmsley SDRC_RFR_CTRL_133MHz, 74d8a94458SPaul Walmsley RATE_IN_243X}, 75d8a94458SPaul Walmsley 76d8a94458SPaul Walmsley /* PRCM #5b - ratio1 - FAST */ 77d8a94458SPaul Walmsley {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */ 78d8a94458SPaul Walmsley R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, 79d8a94458SPaul Walmsley R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, 80d8a94458SPaul Walmsley MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, 81d8a94458SPaul Walmsley SDRC_RFR_CTRL_100MHz, 82d8a94458SPaul Walmsley RATE_IN_243X}, 83d8a94458SPaul Walmsley 84d8a94458SPaul Walmsley /* PRCM #4 - ratio1 (ES2.1) - SLOW */ 85d8a94458SPaul Walmsley {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */ 86d8a94458SPaul Walmsley R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, 87d8a94458SPaul Walmsley R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL, 88d8a94458SPaul Walmsley MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL, 89d8a94458SPaul Walmsley SDRC_RFR_CTRL_133MHz, 90d8a94458SPaul Walmsley RATE_IN_243X}, 91d8a94458SPaul Walmsley 92d8a94458SPaul Walmsley /* PRCM #2 - ratio1 (ES2) - SLOW */ 93d8a94458SPaul Walmsley {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */ 94d8a94458SPaul Walmsley R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, 95d8a94458SPaul Walmsley R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL, 96d8a94458SPaul Walmsley MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, 97d8a94458SPaul Walmsley SDRC_RFR_CTRL_165MHz, 98d8a94458SPaul Walmsley RATE_IN_243X}, 99d8a94458SPaul Walmsley 100d8a94458SPaul Walmsley /* PRCM #5a - ratio1 - SLOW */ 101d8a94458SPaul Walmsley {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ 102d8a94458SPaul Walmsley R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, 103d8a94458SPaul Walmsley R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, 104d8a94458SPaul Walmsley MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, 105d8a94458SPaul Walmsley SDRC_RFR_CTRL_133MHz, 106d8a94458SPaul Walmsley RATE_IN_243X}, 107d8a94458SPaul Walmsley 108d8a94458SPaul Walmsley /* PRCM #5b - ratio1 - SLOW*/ 109d8a94458SPaul Walmsley {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */ 110d8a94458SPaul Walmsley R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, 111d8a94458SPaul Walmsley R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, 112d8a94458SPaul Walmsley MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, 113d8a94458SPaul Walmsley SDRC_RFR_CTRL_100MHz, 114d8a94458SPaul Walmsley RATE_IN_243X}, 115d8a94458SPaul Walmsley 116d8a94458SPaul Walmsley /* PRCM-boot/bypass */ 117d8a94458SPaul Walmsley {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */ 118d8a94458SPaul Walmsley RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, 119d8a94458SPaul Walmsley RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL, 120d8a94458SPaul Walmsley MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, 121d8a94458SPaul Walmsley SDRC_RFR_CTRL_BYPASS, 122d8a94458SPaul Walmsley RATE_IN_243X}, 123d8a94458SPaul Walmsley 124d8a94458SPaul Walmsley /* PRCM-boot/bypass */ 125d8a94458SPaul Walmsley {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */ 126d8a94458SPaul Walmsley RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, 127d8a94458SPaul Walmsley RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL, 128d8a94458SPaul Walmsley MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, 129d8a94458SPaul Walmsley SDRC_RFR_CTRL_BYPASS, 130d8a94458SPaul Walmsley RATE_IN_243X}, 131d8a94458SPaul Walmsley 132d8a94458SPaul Walmsley { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 133d8a94458SPaul Walmsley }; 134