1 /* 2 * This file configures the internal USB PHY in OMAP4430. Used 3 * with TWL6030 transceiver and MUSB on OMAP4430. 4 * 5 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * Author: Hema HK <hemahk@ti.com> 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 * 22 */ 23 24 #include <linux/types.h> 25 #include <linux/delay.h> 26 #include <linux/clk.h> 27 #include <linux/io.h> 28 #include <linux/err.h> 29 #include <linux/usb.h> 30 #include <linux/usb/musb.h> 31 32 #include "soc.h" 33 #include "control.h" 34 #include "usb.h" 35 36 #define CONTROL_DEV_CONF 0x300 37 #define PHY_PD 0x1 38 39 /** 40 * omap4430_phy_power_down: disable MUSB PHY during early init 41 * 42 * OMAP4 MUSB PHY module is enabled by default on reset, but this will 43 * prevent core retention if not disabled by SW. USB driver will 44 * later on enable this, once and if the driver needs it. 45 */ 46 static int __init omap4430_phy_power_down(void) 47 { 48 void __iomem *ctrl_base; 49 50 if (!cpu_is_omap44xx()) 51 return 0; 52 53 ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K); 54 if (!ctrl_base) { 55 pr_err("control module ioremap failed\n"); 56 return -ENOMEM; 57 } 58 59 /* Power down the phy */ 60 __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF); 61 62 iounmap(ctrl_base); 63 64 return 0; 65 } 66 omap_early_initcall(omap4430_phy_power_down); 67 68 void am35x_musb_reset(void) 69 { 70 u32 regval; 71 72 /* Reset the musb interface */ 73 regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); 74 75 regval |= AM35XX_USBOTGSS_SW_RST; 76 omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); 77 78 regval &= ~AM35XX_USBOTGSS_SW_RST; 79 omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); 80 81 regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); 82 } 83 84 void am35x_musb_phy_power(u8 on) 85 { 86 unsigned long timeout = jiffies + msecs_to_jiffies(100); 87 u32 devconf2; 88 89 if (on) { 90 /* 91 * Start the on-chip PHY and its PLL. 92 */ 93 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); 94 95 devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN); 96 devconf2 |= CONF2_PHY_PLLON; 97 98 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); 99 100 pr_info(KERN_INFO "Waiting for PHY clock good...\n"); 101 while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2) 102 & CONF2_PHYCLKGD)) { 103 cpu_relax(); 104 105 if (time_after(jiffies, timeout)) { 106 pr_err(KERN_ERR "musb PHY clock good timed out\n"); 107 break; 108 } 109 } 110 } else { 111 /* 112 * Power down the on-chip PHY. 113 */ 114 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); 115 116 devconf2 &= ~CONF2_PHY_PLLON; 117 devconf2 |= CONF2_PHYPWRDN | CONF2_OTGPWRDN; 118 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); 119 } 120 } 121 122 void am35x_musb_clear_irq(void) 123 { 124 u32 regval; 125 126 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); 127 regval |= AM35XX_USBOTGSS_INT_CLR; 128 omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR); 129 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); 130 } 131 132 void am35x_set_mode(u8 musb_mode) 133 { 134 u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); 135 136 devconf2 &= ~CONF2_OTGMODE; 137 switch (musb_mode) { 138 case MUSB_HOST: /* Force VBUS valid, ID = 0 */ 139 devconf2 |= CONF2_FORCE_HOST; 140 break; 141 case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */ 142 devconf2 |= CONF2_FORCE_DEVICE; 143 break; 144 case MUSB_OTG: /* Don't override the VBUS/ID comparators */ 145 devconf2 |= CONF2_NO_OVERRIDE; 146 break; 147 default: 148 pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode); 149 } 150 151 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); 152 } 153 154 void ti81xx_musb_phy_power(u8 on) 155 { 156 void __iomem *scm_base = NULL; 157 u32 usbphycfg; 158 159 scm_base = ioremap(TI81XX_SCM_BASE, SZ_2K); 160 if (!scm_base) { 161 pr_err("system control module ioremap failed\n"); 162 return; 163 } 164 165 usbphycfg = __raw_readl(scm_base + USBCTRL0); 166 167 if (on) { 168 if (cpu_is_ti816x()) { 169 usbphycfg |= TI816X_USBPHY0_NORMAL_MODE; 170 usbphycfg &= ~TI816X_USBPHY_REFCLK_OSC; 171 } else if (cpu_is_ti814x()) { 172 usbphycfg &= ~(USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN 173 | USBPHY_DPINPUT | USBPHY_DMINPUT); 174 usbphycfg |= (USBPHY_OTGVDET_EN | USBPHY_OTGSESSEND_EN 175 | USBPHY_DPOPBUFCTL | USBPHY_DMOPBUFCTL); 176 } 177 } else { 178 if (cpu_is_ti816x()) 179 usbphycfg &= ~TI816X_USBPHY0_NORMAL_MODE; 180 else if (cpu_is_ti814x()) 181 usbphycfg |= USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN; 182 183 } 184 __raw_writel(usbphycfg, scm_base + USBCTRL0); 185 186 iounmap(scm_base); 187 } 188