1 /* 2 * DM81xx hwmod data. 3 * 4 * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/ 5 * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/ 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation version 2. 10 * 11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 12 * kind, whether express or implied; without even the implied warranty 13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 */ 17 18 #include <linux/platform_data/gpio-omap.h> 19 #include <linux/platform_data/hsmmc-omap.h> 20 #include <linux/platform_data/spi-omap2-mcspi.h> 21 #include <plat/dmtimer.h> 22 23 #include "omap_hwmod_common_data.h" 24 #include "cm81xx.h" 25 #include "ti81xx.h" 26 #include "wd_timer.h" 27 28 /* 29 * DM816X hardware modules integration data 30 * 31 * Note: This is incomplete and at present, not generated from h/w database. 32 */ 33 34 /* 35 * Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS" 36 * also dm816x TRM 18.7.17 CM_ALWON device register values minus 0x1400. 37 */ 38 #define DM81XX_CM_ALWON_MCASP0_CLKCTRL 0x140 39 #define DM81XX_CM_ALWON_MCASP1_CLKCTRL 0x144 40 #define DM81XX_CM_ALWON_MCASP2_CLKCTRL 0x148 41 #define DM81XX_CM_ALWON_MCBSP_CLKCTRL 0x14c 42 #define DM81XX_CM_ALWON_UART_0_CLKCTRL 0x150 43 #define DM81XX_CM_ALWON_UART_1_CLKCTRL 0x154 44 #define DM81XX_CM_ALWON_UART_2_CLKCTRL 0x158 45 #define DM81XX_CM_ALWON_GPIO_0_CLKCTRL 0x15c 46 #define DM81XX_CM_ALWON_GPIO_1_CLKCTRL 0x160 47 #define DM81XX_CM_ALWON_I2C_0_CLKCTRL 0x164 48 #define DM81XX_CM_ALWON_I2C_1_CLKCTRL 0x168 49 #define DM81XX_CM_ALWON_WDTIMER_CLKCTRL 0x18c 50 #define DM81XX_CM_ALWON_SPI_CLKCTRL 0x190 51 #define DM81XX_CM_ALWON_MAILBOX_CLKCTRL 0x194 52 #define DM81XX_CM_ALWON_SPINBOX_CLKCTRL 0x198 53 #define DM81XX_CM_ALWON_MMUDATA_CLKCTRL 0x19c 54 #define DM81XX_CM_ALWON_MMUCFG_CLKCTRL 0x1a8 55 #define DM81XX_CM_ALWON_CONTROL_CLKCTRL 0x1c4 56 #define DM81XX_CM_ALWON_GPMC_CLKCTRL 0x1d0 57 #define DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL 0x1d4 58 #define DM81XX_CM_ALWON_L3_CLKCTRL 0x1e4 59 #define DM81XX_CM_ALWON_L4HS_CLKCTRL 0x1e8 60 #define DM81XX_CM_ALWON_L4LS_CLKCTRL 0x1ec 61 #define DM81XX_CM_ALWON_RTC_CLKCTRL 0x1f0 62 #define DM81XX_CM_ALWON_TPCC_CLKCTRL 0x1f4 63 #define DM81XX_CM_ALWON_TPTC0_CLKCTRL 0x1f8 64 #define DM81XX_CM_ALWON_TPTC1_CLKCTRL 0x1fc 65 #define DM81XX_CM_ALWON_TPTC2_CLKCTRL 0x200 66 #define DM81XX_CM_ALWON_TPTC3_CLKCTRL 0x204 67 68 /* Registers specific to dm814x */ 69 #define DM814X_CM_ALWON_MCASP_3_4_5_CLKCTRL 0x16c 70 #define DM814X_CM_ALWON_ATL_CLKCTRL 0x170 71 #define DM814X_CM_ALWON_MLB_CLKCTRL 0x174 72 #define DM814X_CM_ALWON_PATA_CLKCTRL 0x178 73 #define DM814X_CM_ALWON_UART_3_CLKCTRL 0x180 74 #define DM814X_CM_ALWON_UART_4_CLKCTRL 0x184 75 #define DM814X_CM_ALWON_UART_5_CLKCTRL 0x188 76 #define DM814X_CM_ALWON_OCM_0_CLKCTRL 0x1b4 77 #define DM814X_CM_ALWON_VCP_CLKCTRL 0x1b8 78 #define DM814X_CM_ALWON_MPU_CLKCTRL 0x1dc 79 #define DM814X_CM_ALWON_DEBUGSS_CLKCTRL 0x1e0 80 #define DM814X_CM_ALWON_DCAN_0_1_CLKCTRL 0x218 81 #define DM814X_CM_ALWON_MMCHS_0_CLKCTRL 0x21c 82 #define DM814X_CM_ALWON_MMCHS_1_CLKCTRL 0x220 83 #define DM814X_CM_ALWON_MMCHS_2_CLKCTRL 0x224 84 #define DM814X_CM_ALWON_CUST_EFUSE_CLKCTRL 0x228 85 86 /* Registers specific to dm816x */ 87 #define DM816X_DM_ALWON_BASE 0x1400 88 #define DM816X_CM_ALWON_TIMER_1_CLKCTRL (0x1570 - DM816X_DM_ALWON_BASE) 89 #define DM816X_CM_ALWON_TIMER_2_CLKCTRL (0x1574 - DM816X_DM_ALWON_BASE) 90 #define DM816X_CM_ALWON_TIMER_3_CLKCTRL (0x1578 - DM816X_DM_ALWON_BASE) 91 #define DM816X_CM_ALWON_TIMER_4_CLKCTRL (0x157c - DM816X_DM_ALWON_BASE) 92 #define DM816X_CM_ALWON_TIMER_5_CLKCTRL (0x1580 - DM816X_DM_ALWON_BASE) 93 #define DM816X_CM_ALWON_TIMER_6_CLKCTRL (0x1584 - DM816X_DM_ALWON_BASE) 94 #define DM816X_CM_ALWON_TIMER_7_CLKCTRL (0x1588 - DM816X_DM_ALWON_BASE) 95 #define DM816X_CM_ALWON_SDIO_CLKCTRL (0x15b0 - DM816X_DM_ALWON_BASE) 96 #define DM816X_CM_ALWON_OCMC_0_CLKCTRL (0x15b4 - DM816X_DM_ALWON_BASE) 97 #define DM816X_CM_ALWON_OCMC_1_CLKCTRL (0x15b8 - DM816X_DM_ALWON_BASE) 98 #define DM816X_CM_ALWON_ETHERNET_1_CLKCTRL (0x15d8 - DM816X_DM_ALWON_BASE) 99 #define DM816X_CM_ALWON_MPU_CLKCTRL (0x15dc - DM816X_DM_ALWON_BASE) 100 #define DM816X_CM_ALWON_SR_0_CLKCTRL (0x1608 - DM816X_DM_ALWON_BASE) 101 #define DM816X_CM_ALWON_SR_1_CLKCTRL (0x160c - DM816X_DM_ALWON_BASE) 102 103 /* 104 * The default .clkctrl_offs field is offset from CM_DEFAULT, that's 105 * TRM 18.7.6 CM_DEFAULT device register values minus 0x500 106 */ 107 #define DM81XX_CM_DEFAULT_OFFSET 0x500 108 #define DM81XX_CM_DEFAULT_USB_CLKCTRL (0x558 - DM81XX_CM_DEFAULT_OFFSET) 109 110 /* L3 Interconnect entries clocked at 125, 250 and 500MHz */ 111 static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = { 112 .name = "alwon_l3_slow", 113 .clkdm_name = "alwon_l3s_clkdm", 114 .class = &l3_hwmod_class, 115 .flags = HWMOD_NO_IDLEST, 116 }; 117 118 static struct omap_hwmod dm81xx_default_l3_slow_hwmod = { 119 .name = "default_l3_slow", 120 .clkdm_name = "default_l3_slow_clkdm", 121 .class = &l3_hwmod_class, 122 .flags = HWMOD_NO_IDLEST, 123 }; 124 125 static struct omap_hwmod dm81xx_alwon_l3_med_hwmod = { 126 .name = "l3_med", 127 .clkdm_name = "alwon_l3_med_clkdm", 128 .class = &l3_hwmod_class, 129 .flags = HWMOD_NO_IDLEST, 130 }; 131 132 static struct omap_hwmod dm81xx_alwon_l3_fast_hwmod = { 133 .name = "l3_fast", 134 .clkdm_name = "alwon_l3_fast_clkdm", 135 .class = &l3_hwmod_class, 136 .flags = HWMOD_NO_IDLEST, 137 }; 138 139 /* 140 * L4 standard peripherals, see TRM table 1-12 for devices using this. 141 * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock. 142 */ 143 static struct omap_hwmod dm81xx_l4_ls_hwmod = { 144 .name = "l4_ls", 145 .clkdm_name = "alwon_l3s_clkdm", 146 .class = &l4_hwmod_class, 147 }; 148 149 /* 150 * L4 high-speed peripherals. For devices using this, please see the TRM 151 * table 1-13. On dm816x, only EMAC, MDIO and SATA use this. See also TRM 152 * table 1-73 for devices using 250MHz SYSCLK5 clock. 153 */ 154 static struct omap_hwmod dm81xx_l4_hs_hwmod = { 155 .name = "l4_hs", 156 .clkdm_name = "alwon_l3_med_clkdm", 157 .class = &l4_hwmod_class, 158 }; 159 160 /* L3 slow -> L4 ls peripheral interface running at 125MHz */ 161 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_ls = { 162 .master = &dm81xx_alwon_l3_slow_hwmod, 163 .slave = &dm81xx_l4_ls_hwmod, 164 .user = OCP_USER_MPU, 165 }; 166 167 /* L3 med -> L4 fast peripheral interface running at 250MHz */ 168 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_hs = { 169 .master = &dm81xx_alwon_l3_med_hwmod, 170 .slave = &dm81xx_l4_hs_hwmod, 171 .user = OCP_USER_MPU, 172 }; 173 174 /* MPU */ 175 static struct omap_hwmod dm814x_mpu_hwmod = { 176 .name = "mpu", 177 .clkdm_name = "alwon_l3s_clkdm", 178 .class = &mpu_hwmod_class, 179 .flags = HWMOD_INIT_NO_IDLE, 180 .main_clk = "mpu_ck", 181 .prcm = { 182 .omap4 = { 183 .clkctrl_offs = DM814X_CM_ALWON_MPU_CLKCTRL, 184 .modulemode = MODULEMODE_SWCTRL, 185 }, 186 }, 187 }; 188 189 static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_slow = { 190 .master = &dm814x_mpu_hwmod, 191 .slave = &dm81xx_alwon_l3_slow_hwmod, 192 .user = OCP_USER_MPU, 193 }; 194 195 /* L3 med peripheral interface running at 200MHz */ 196 static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_med = { 197 .master = &dm814x_mpu_hwmod, 198 .slave = &dm81xx_alwon_l3_med_hwmod, 199 .user = OCP_USER_MPU, 200 }; 201 202 static struct omap_hwmod dm816x_mpu_hwmod = { 203 .name = "mpu", 204 .clkdm_name = "alwon_mpu_clkdm", 205 .class = &mpu_hwmod_class, 206 .flags = HWMOD_INIT_NO_IDLE, 207 .main_clk = "mpu_ck", 208 .prcm = { 209 .omap4 = { 210 .clkctrl_offs = DM816X_CM_ALWON_MPU_CLKCTRL, 211 .modulemode = MODULEMODE_SWCTRL, 212 }, 213 }, 214 }; 215 216 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_slow = { 217 .master = &dm816x_mpu_hwmod, 218 .slave = &dm81xx_alwon_l3_slow_hwmod, 219 .user = OCP_USER_MPU, 220 }; 221 222 /* L3 med peripheral interface running at 250MHz */ 223 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med = { 224 .master = &dm816x_mpu_hwmod, 225 .slave = &dm81xx_alwon_l3_med_hwmod, 226 .user = OCP_USER_MPU, 227 }; 228 229 /* UART common */ 230 static struct omap_hwmod_class_sysconfig uart_sysc = { 231 .rev_offs = 0x50, 232 .sysc_offs = 0x54, 233 .syss_offs = 0x58, 234 .sysc_flags = SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | 235 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 236 SYSS_HAS_RESET_STATUS, 237 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 238 MSTANDBY_SMART_WKUP, 239 .sysc_fields = &omap_hwmod_sysc_type1, 240 }; 241 242 static struct omap_hwmod_class uart_class = { 243 .name = "uart", 244 .sysc = &uart_sysc, 245 }; 246 247 static struct omap_hwmod dm81xx_uart1_hwmod = { 248 .name = "uart1", 249 .clkdm_name = "alwon_l3s_clkdm", 250 .main_clk = "sysclk10_ck", 251 .prcm = { 252 .omap4 = { 253 .clkctrl_offs = DM81XX_CM_ALWON_UART_0_CLKCTRL, 254 .modulemode = MODULEMODE_SWCTRL, 255 }, 256 }, 257 .class = &uart_class, 258 .flags = DEBUG_TI81XXUART1_FLAGS, 259 }; 260 261 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart1 = { 262 .master = &dm81xx_l4_ls_hwmod, 263 .slave = &dm81xx_uart1_hwmod, 264 .clk = "sysclk6_ck", 265 .user = OCP_USER_MPU, 266 }; 267 268 static struct omap_hwmod dm81xx_uart2_hwmod = { 269 .name = "uart2", 270 .clkdm_name = "alwon_l3s_clkdm", 271 .main_clk = "sysclk10_ck", 272 .prcm = { 273 .omap4 = { 274 .clkctrl_offs = DM81XX_CM_ALWON_UART_1_CLKCTRL, 275 .modulemode = MODULEMODE_SWCTRL, 276 }, 277 }, 278 .class = &uart_class, 279 .flags = DEBUG_TI81XXUART2_FLAGS, 280 }; 281 282 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart2 = { 283 .master = &dm81xx_l4_ls_hwmod, 284 .slave = &dm81xx_uart2_hwmod, 285 .clk = "sysclk6_ck", 286 .user = OCP_USER_MPU, 287 }; 288 289 static struct omap_hwmod dm81xx_uart3_hwmod = { 290 .name = "uart3", 291 .clkdm_name = "alwon_l3s_clkdm", 292 .main_clk = "sysclk10_ck", 293 .prcm = { 294 .omap4 = { 295 .clkctrl_offs = DM81XX_CM_ALWON_UART_2_CLKCTRL, 296 .modulemode = MODULEMODE_SWCTRL, 297 }, 298 }, 299 .class = &uart_class, 300 .flags = DEBUG_TI81XXUART3_FLAGS, 301 }; 302 303 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart3 = { 304 .master = &dm81xx_l4_ls_hwmod, 305 .slave = &dm81xx_uart3_hwmod, 306 .clk = "sysclk6_ck", 307 .user = OCP_USER_MPU, 308 }; 309 310 static struct omap_hwmod_class_sysconfig wd_timer_sysc = { 311 .rev_offs = 0x0, 312 .sysc_offs = 0x10, 313 .syss_offs = 0x14, 314 .sysc_flags = SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | 315 SYSS_HAS_RESET_STATUS, 316 .sysc_fields = &omap_hwmod_sysc_type1, 317 }; 318 319 static struct omap_hwmod_class wd_timer_class = { 320 .name = "wd_timer", 321 .sysc = &wd_timer_sysc, 322 .pre_shutdown = &omap2_wd_timer_disable, 323 .reset = &omap2_wd_timer_reset, 324 }; 325 326 static struct omap_hwmod dm81xx_wd_timer_hwmod = { 327 .name = "wd_timer", 328 .clkdm_name = "alwon_l3s_clkdm", 329 .main_clk = "sysclk18_ck", 330 .flags = HWMOD_NO_IDLEST, 331 .prcm = { 332 .omap4 = { 333 .clkctrl_offs = DM81XX_CM_ALWON_WDTIMER_CLKCTRL, 334 .modulemode = MODULEMODE_SWCTRL, 335 }, 336 }, 337 .class = &wd_timer_class, 338 }; 339 340 static struct omap_hwmod_ocp_if dm81xx_l4_ls__wd_timer1 = { 341 .master = &dm81xx_l4_ls_hwmod, 342 .slave = &dm81xx_wd_timer_hwmod, 343 .clk = "sysclk6_ck", 344 .user = OCP_USER_MPU, 345 }; 346 347 /* I2C common */ 348 static struct omap_hwmod_class_sysconfig i2c_sysc = { 349 .rev_offs = 0x0, 350 .sysc_offs = 0x10, 351 .syss_offs = 0x90, 352 .sysc_flags = SYSC_HAS_SIDLEMODE | 353 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 354 SYSC_HAS_AUTOIDLE, 355 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 356 .sysc_fields = &omap_hwmod_sysc_type1, 357 }; 358 359 static struct omap_hwmod_class i2c_class = { 360 .name = "i2c", 361 .sysc = &i2c_sysc, 362 }; 363 364 static struct omap_hwmod dm81xx_i2c1_hwmod = { 365 .name = "i2c1", 366 .clkdm_name = "alwon_l3s_clkdm", 367 .main_clk = "sysclk10_ck", 368 .prcm = { 369 .omap4 = { 370 .clkctrl_offs = DM81XX_CM_ALWON_I2C_0_CLKCTRL, 371 .modulemode = MODULEMODE_SWCTRL, 372 }, 373 }, 374 .class = &i2c_class, 375 }; 376 377 static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c1 = { 378 .master = &dm81xx_l4_ls_hwmod, 379 .slave = &dm81xx_i2c1_hwmod, 380 .clk = "sysclk6_ck", 381 .user = OCP_USER_MPU, 382 }; 383 384 static struct omap_hwmod dm81xx_i2c2_hwmod = { 385 .name = "i2c2", 386 .clkdm_name = "alwon_l3s_clkdm", 387 .main_clk = "sysclk10_ck", 388 .prcm = { 389 .omap4 = { 390 .clkctrl_offs = DM81XX_CM_ALWON_I2C_1_CLKCTRL, 391 .modulemode = MODULEMODE_SWCTRL, 392 }, 393 }, 394 .class = &i2c_class, 395 }; 396 397 static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = { 398 .rev_offs = 0x0000, 399 .sysc_offs = 0x0010, 400 .syss_offs = 0x0014, 401 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 402 SYSC_HAS_SOFTRESET | 403 SYSS_HAS_RESET_STATUS, 404 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 405 .sysc_fields = &omap_hwmod_sysc_type1, 406 }; 407 408 static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = { 409 .master = &dm81xx_l4_ls_hwmod, 410 .slave = &dm81xx_i2c2_hwmod, 411 .clk = "sysclk6_ck", 412 .user = OCP_USER_MPU, 413 }; 414 415 static struct omap_hwmod_class dm81xx_elm_hwmod_class = { 416 .name = "elm", 417 .sysc = &dm81xx_elm_sysc, 418 }; 419 420 static struct omap_hwmod dm81xx_elm_hwmod = { 421 .name = "elm", 422 .clkdm_name = "alwon_l3s_clkdm", 423 .class = &dm81xx_elm_hwmod_class, 424 .main_clk = "sysclk6_ck", 425 }; 426 427 static struct omap_hwmod_ocp_if dm81xx_l4_ls__elm = { 428 .master = &dm81xx_l4_ls_hwmod, 429 .slave = &dm81xx_elm_hwmod, 430 .user = OCP_USER_MPU, 431 }; 432 433 static struct omap_hwmod_class_sysconfig dm81xx_gpio_sysc = { 434 .rev_offs = 0x0000, 435 .sysc_offs = 0x0010, 436 .syss_offs = 0x0114, 437 .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | 438 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 439 SYSS_HAS_RESET_STATUS, 440 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 441 SIDLE_SMART_WKUP, 442 .sysc_fields = &omap_hwmod_sysc_type1, 443 }; 444 445 static struct omap_hwmod_class dm81xx_gpio_hwmod_class = { 446 .name = "gpio", 447 .sysc = &dm81xx_gpio_sysc, 448 .rev = 2, 449 }; 450 451 static struct omap_gpio_dev_attr gpio_dev_attr = { 452 .bank_width = 32, 453 .dbck_flag = true, 454 }; 455 456 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { 457 { .role = "dbclk", .clk = "sysclk18_ck" }, 458 }; 459 460 static struct omap_hwmod dm81xx_gpio1_hwmod = { 461 .name = "gpio1", 462 .clkdm_name = "alwon_l3s_clkdm", 463 .class = &dm81xx_gpio_hwmod_class, 464 .main_clk = "sysclk6_ck", 465 .prcm = { 466 .omap4 = { 467 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_0_CLKCTRL, 468 .modulemode = MODULEMODE_SWCTRL, 469 }, 470 }, 471 .opt_clks = gpio1_opt_clks, 472 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), 473 .dev_attr = &gpio_dev_attr, 474 }; 475 476 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = { 477 .master = &dm81xx_l4_ls_hwmod, 478 .slave = &dm81xx_gpio1_hwmod, 479 .user = OCP_USER_MPU, 480 }; 481 482 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { 483 { .role = "dbclk", .clk = "sysclk18_ck" }, 484 }; 485 486 static struct omap_hwmod dm81xx_gpio2_hwmod = { 487 .name = "gpio2", 488 .clkdm_name = "alwon_l3s_clkdm", 489 .class = &dm81xx_gpio_hwmod_class, 490 .main_clk = "sysclk6_ck", 491 .prcm = { 492 .omap4 = { 493 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL, 494 .modulemode = MODULEMODE_SWCTRL, 495 }, 496 }, 497 .opt_clks = gpio2_opt_clks, 498 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), 499 .dev_attr = &gpio_dev_attr, 500 }; 501 502 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = { 503 .master = &dm81xx_l4_ls_hwmod, 504 .slave = &dm81xx_gpio2_hwmod, 505 .user = OCP_USER_MPU, 506 }; 507 508 static struct omap_hwmod_class_sysconfig dm81xx_gpmc_sysc = { 509 .rev_offs = 0x0, 510 .sysc_offs = 0x10, 511 .syss_offs = 0x14, 512 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 513 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, 514 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 515 .sysc_fields = &omap_hwmod_sysc_type1, 516 }; 517 518 static struct omap_hwmod_class dm81xx_gpmc_hwmod_class = { 519 .name = "gpmc", 520 .sysc = &dm81xx_gpmc_sysc, 521 }; 522 523 static struct omap_hwmod dm81xx_gpmc_hwmod = { 524 .name = "gpmc", 525 .clkdm_name = "alwon_l3s_clkdm", 526 .class = &dm81xx_gpmc_hwmod_class, 527 .main_clk = "sysclk6_ck", 528 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ 529 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS, 530 .prcm = { 531 .omap4 = { 532 .clkctrl_offs = DM81XX_CM_ALWON_GPMC_CLKCTRL, 533 .modulemode = MODULEMODE_SWCTRL, 534 }, 535 }, 536 }; 537 538 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = { 539 .master = &dm81xx_alwon_l3_slow_hwmod, 540 .slave = &dm81xx_gpmc_hwmod, 541 .user = OCP_USER_MPU, 542 }; 543 544 static struct omap_hwmod_class_sysconfig dm81xx_usbhsotg_sysc = { 545 .rev_offs = 0x0, 546 .sysc_offs = 0x10, 547 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | 548 SYSC_HAS_SOFTRESET, 549 .idlemodes = SIDLE_SMART | MSTANDBY_FORCE | MSTANDBY_SMART, 550 .sysc_fields = &omap_hwmod_sysc_type2, 551 }; 552 553 static struct omap_hwmod_class dm81xx_usbotg_class = { 554 .name = "usbotg", 555 .sysc = &dm81xx_usbhsotg_sysc, 556 }; 557 558 static struct omap_hwmod dm814x_usbss_hwmod = { 559 .name = "usb_otg_hs", 560 .clkdm_name = "default_l3_slow_clkdm", 561 .main_clk = "pll260dcoclkldo", /* 481c5260.adpll.dcoclkldo */ 562 .prcm = { 563 .omap4 = { 564 .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL, 565 .modulemode = MODULEMODE_SWCTRL, 566 }, 567 }, 568 .class = &dm81xx_usbotg_class, 569 }; 570 571 static struct omap_hwmod_ocp_if dm814x_default_l3_slow__usbss = { 572 .master = &dm81xx_default_l3_slow_hwmod, 573 .slave = &dm814x_usbss_hwmod, 574 .clk = "sysclk6_ck", 575 .user = OCP_USER_MPU, 576 }; 577 578 static struct omap_hwmod dm816x_usbss_hwmod = { 579 .name = "usb_otg_hs", 580 .clkdm_name = "default_l3_slow_clkdm", 581 .main_clk = "sysclk6_ck", 582 .prcm = { 583 .omap4 = { 584 .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL, 585 .modulemode = MODULEMODE_SWCTRL, 586 }, 587 }, 588 .class = &dm81xx_usbotg_class, 589 }; 590 591 static struct omap_hwmod_ocp_if dm816x_default_l3_slow__usbss = { 592 .master = &dm81xx_default_l3_slow_hwmod, 593 .slave = &dm816x_usbss_hwmod, 594 .clk = "sysclk6_ck", 595 .user = OCP_USER_MPU, 596 }; 597 598 static struct omap_hwmod_class_sysconfig dm816x_timer_sysc = { 599 .rev_offs = 0x0000, 600 .sysc_offs = 0x0010, 601 .syss_offs = 0x0014, 602 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET, 603 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 604 SIDLE_SMART_WKUP, 605 .sysc_fields = &omap_hwmod_sysc_type2, 606 }; 607 608 static struct omap_hwmod_class dm816x_timer_hwmod_class = { 609 .name = "timer", 610 .sysc = &dm816x_timer_sysc, 611 }; 612 613 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { 614 .timer_capability = OMAP_TIMER_ALWON, 615 }; 616 617 static struct omap_hwmod dm814x_timer1_hwmod = { 618 .name = "timer1", 619 .clkdm_name = "alwon_l3s_clkdm", 620 .main_clk = "timer_sys_ck", 621 .dev_attr = &capability_alwon_dev_attr, 622 .class = &dm816x_timer_hwmod_class, 623 .flags = HWMOD_NO_IDLEST, 624 }; 625 626 static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = { 627 .master = &dm81xx_l4_ls_hwmod, 628 .slave = &dm814x_timer1_hwmod, 629 .clk = "timer_sys_ck", 630 .user = OCP_USER_MPU, 631 }; 632 633 static struct omap_hwmod dm816x_timer1_hwmod = { 634 .name = "timer1", 635 .clkdm_name = "alwon_l3s_clkdm", 636 .main_clk = "timer1_fck", 637 .prcm = { 638 .omap4 = { 639 .clkctrl_offs = DM816X_CM_ALWON_TIMER_1_CLKCTRL, 640 .modulemode = MODULEMODE_SWCTRL, 641 }, 642 }, 643 .dev_attr = &capability_alwon_dev_attr, 644 .class = &dm816x_timer_hwmod_class, 645 }; 646 647 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = { 648 .master = &dm81xx_l4_ls_hwmod, 649 .slave = &dm816x_timer1_hwmod, 650 .clk = "sysclk6_ck", 651 .user = OCP_USER_MPU, 652 }; 653 654 static struct omap_hwmod dm814x_timer2_hwmod = { 655 .name = "timer2", 656 .clkdm_name = "alwon_l3s_clkdm", 657 .main_clk = "timer_sys_ck", 658 .dev_attr = &capability_alwon_dev_attr, 659 .class = &dm816x_timer_hwmod_class, 660 .flags = HWMOD_NO_IDLEST, 661 }; 662 663 static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = { 664 .master = &dm81xx_l4_ls_hwmod, 665 .slave = &dm814x_timer2_hwmod, 666 .clk = "timer_sys_ck", 667 .user = OCP_USER_MPU, 668 }; 669 670 static struct omap_hwmod dm816x_timer2_hwmod = { 671 .name = "timer2", 672 .clkdm_name = "alwon_l3s_clkdm", 673 .main_clk = "timer2_fck", 674 .prcm = { 675 .omap4 = { 676 .clkctrl_offs = DM816X_CM_ALWON_TIMER_2_CLKCTRL, 677 .modulemode = MODULEMODE_SWCTRL, 678 }, 679 }, 680 .dev_attr = &capability_alwon_dev_attr, 681 .class = &dm816x_timer_hwmod_class, 682 }; 683 684 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = { 685 .master = &dm81xx_l4_ls_hwmod, 686 .slave = &dm816x_timer2_hwmod, 687 .clk = "sysclk6_ck", 688 .user = OCP_USER_MPU, 689 }; 690 691 static struct omap_hwmod dm816x_timer3_hwmod = { 692 .name = "timer3", 693 .clkdm_name = "alwon_l3s_clkdm", 694 .main_clk = "timer3_fck", 695 .prcm = { 696 .omap4 = { 697 .clkctrl_offs = DM816X_CM_ALWON_TIMER_3_CLKCTRL, 698 .modulemode = MODULEMODE_SWCTRL, 699 }, 700 }, 701 .dev_attr = &capability_alwon_dev_attr, 702 .class = &dm816x_timer_hwmod_class, 703 }; 704 705 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer3 = { 706 .master = &dm81xx_l4_ls_hwmod, 707 .slave = &dm816x_timer3_hwmod, 708 .clk = "sysclk6_ck", 709 .user = OCP_USER_MPU, 710 }; 711 712 static struct omap_hwmod dm816x_timer4_hwmod = { 713 .name = "timer4", 714 .clkdm_name = "alwon_l3s_clkdm", 715 .main_clk = "timer4_fck", 716 .prcm = { 717 .omap4 = { 718 .clkctrl_offs = DM816X_CM_ALWON_TIMER_4_CLKCTRL, 719 .modulemode = MODULEMODE_SWCTRL, 720 }, 721 }, 722 .dev_attr = &capability_alwon_dev_attr, 723 .class = &dm816x_timer_hwmod_class, 724 }; 725 726 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer4 = { 727 .master = &dm81xx_l4_ls_hwmod, 728 .slave = &dm816x_timer4_hwmod, 729 .clk = "sysclk6_ck", 730 .user = OCP_USER_MPU, 731 }; 732 733 static struct omap_hwmod dm816x_timer5_hwmod = { 734 .name = "timer5", 735 .clkdm_name = "alwon_l3s_clkdm", 736 .main_clk = "timer5_fck", 737 .prcm = { 738 .omap4 = { 739 .clkctrl_offs = DM816X_CM_ALWON_TIMER_5_CLKCTRL, 740 .modulemode = MODULEMODE_SWCTRL, 741 }, 742 }, 743 .dev_attr = &capability_alwon_dev_attr, 744 .class = &dm816x_timer_hwmod_class, 745 }; 746 747 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer5 = { 748 .master = &dm81xx_l4_ls_hwmod, 749 .slave = &dm816x_timer5_hwmod, 750 .clk = "sysclk6_ck", 751 .user = OCP_USER_MPU, 752 }; 753 754 static struct omap_hwmod dm816x_timer6_hwmod = { 755 .name = "timer6", 756 .clkdm_name = "alwon_l3s_clkdm", 757 .main_clk = "timer6_fck", 758 .prcm = { 759 .omap4 = { 760 .clkctrl_offs = DM816X_CM_ALWON_TIMER_6_CLKCTRL, 761 .modulemode = MODULEMODE_SWCTRL, 762 }, 763 }, 764 .dev_attr = &capability_alwon_dev_attr, 765 .class = &dm816x_timer_hwmod_class, 766 }; 767 768 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer6 = { 769 .master = &dm81xx_l4_ls_hwmod, 770 .slave = &dm816x_timer6_hwmod, 771 .clk = "sysclk6_ck", 772 .user = OCP_USER_MPU, 773 }; 774 775 static struct omap_hwmod dm816x_timer7_hwmod = { 776 .name = "timer7", 777 .clkdm_name = "alwon_l3s_clkdm", 778 .main_clk = "timer7_fck", 779 .prcm = { 780 .omap4 = { 781 .clkctrl_offs = DM816X_CM_ALWON_TIMER_7_CLKCTRL, 782 .modulemode = MODULEMODE_SWCTRL, 783 }, 784 }, 785 .dev_attr = &capability_alwon_dev_attr, 786 .class = &dm816x_timer_hwmod_class, 787 }; 788 789 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = { 790 .master = &dm81xx_l4_ls_hwmod, 791 .slave = &dm816x_timer7_hwmod, 792 .clk = "sysclk6_ck", 793 .user = OCP_USER_MPU, 794 }; 795 796 /* CPSW on dm814x */ 797 static struct omap_hwmod_class_sysconfig dm814x_cpgmac_sysc = { 798 .rev_offs = 0x0, 799 .sysc_offs = 0x8, 800 .syss_offs = 0x4, 801 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | 802 SYSS_HAS_RESET_STATUS, 803 .idlemodes = SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE | 804 MSTANDBY_NO, 805 .sysc_fields = &omap_hwmod_sysc_type3, 806 }; 807 808 static struct omap_hwmod_class dm814x_cpgmac0_hwmod_class = { 809 .name = "cpgmac0", 810 .sysc = &dm814x_cpgmac_sysc, 811 }; 812 813 static struct omap_hwmod dm814x_cpgmac0_hwmod = { 814 .name = "cpgmac0", 815 .class = &dm814x_cpgmac0_hwmod_class, 816 .clkdm_name = "alwon_ethernet_clkdm", 817 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, 818 .main_clk = "cpsw_125mhz_gclk", 819 .prcm = { 820 .omap4 = { 821 .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL, 822 .modulemode = MODULEMODE_SWCTRL, 823 }, 824 }, 825 }; 826 827 static struct omap_hwmod_class dm814x_mdio_hwmod_class = { 828 .name = "davinci_mdio", 829 }; 830 831 static struct omap_hwmod dm814x_mdio_hwmod = { 832 .name = "davinci_mdio", 833 .class = &dm814x_mdio_hwmod_class, 834 .clkdm_name = "alwon_ethernet_clkdm", 835 .main_clk = "cpsw_125mhz_gclk", 836 }; 837 838 static struct omap_hwmod_ocp_if dm814x_l4_hs__cpgmac0 = { 839 .master = &dm81xx_l4_hs_hwmod, 840 .slave = &dm814x_cpgmac0_hwmod, 841 .clk = "cpsw_125mhz_gclk", 842 .user = OCP_USER_MPU, 843 }; 844 845 static struct omap_hwmod_ocp_if dm814x_cpgmac0__mdio = { 846 .master = &dm814x_cpgmac0_hwmod, 847 .slave = &dm814x_mdio_hwmod, 848 .user = OCP_USER_MPU, 849 .flags = HWMOD_NO_IDLEST, 850 }; 851 852 /* EMAC Ethernet */ 853 static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = { 854 .rev_offs = 0x0, 855 .sysc_offs = 0x4, 856 .sysc_flags = SYSC_HAS_SOFTRESET, 857 .sysc_fields = &omap_hwmod_sysc_type2, 858 }; 859 860 static struct omap_hwmod_class dm816x_emac_hwmod_class = { 861 .name = "emac", 862 .sysc = &dm816x_emac_sysc, 863 }; 864 865 /* 866 * On dm816x the MDIO is within EMAC0. As the MDIO driver is a separate 867 * driver probed before EMAC0, we let MDIO do the clock idling. 868 */ 869 static struct omap_hwmod dm816x_emac0_hwmod = { 870 .name = "emac0", 871 .clkdm_name = "alwon_ethernet_clkdm", 872 .class = &dm816x_emac_hwmod_class, 873 }; 874 875 static struct omap_hwmod_ocp_if dm81xx_l4_hs__emac0 = { 876 .master = &dm81xx_l4_hs_hwmod, 877 .slave = &dm816x_emac0_hwmod, 878 .clk = "sysclk5_ck", 879 .user = OCP_USER_MPU, 880 }; 881 882 static struct omap_hwmod_class dm81xx_mdio_hwmod_class = { 883 .name = "davinci_mdio", 884 .sysc = &dm816x_emac_sysc, 885 }; 886 887 static struct omap_hwmod dm81xx_emac0_mdio_hwmod = { 888 .name = "davinci_mdio", 889 .class = &dm81xx_mdio_hwmod_class, 890 .clkdm_name = "alwon_ethernet_clkdm", 891 .main_clk = "sysclk24_ck", 892 .flags = HWMOD_NO_IDLEST, 893 /* 894 * REVISIT: This should be moved to the emac0_hwmod 895 * once we have a better way to handle device slaves. 896 */ 897 .prcm = { 898 .omap4 = { 899 .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL, 900 .modulemode = MODULEMODE_SWCTRL, 901 }, 902 }, 903 }; 904 905 static struct omap_hwmod_ocp_if dm81xx_emac0__mdio = { 906 .master = &dm81xx_l4_hs_hwmod, 907 .slave = &dm81xx_emac0_mdio_hwmod, 908 .user = OCP_USER_MPU, 909 }; 910 911 static struct omap_hwmod dm816x_emac1_hwmod = { 912 .name = "emac1", 913 .clkdm_name = "alwon_ethernet_clkdm", 914 .main_clk = "sysclk24_ck", 915 .flags = HWMOD_NO_IDLEST, 916 .prcm = { 917 .omap4 = { 918 .clkctrl_offs = DM816X_CM_ALWON_ETHERNET_1_CLKCTRL, 919 .modulemode = MODULEMODE_SWCTRL, 920 }, 921 }, 922 .class = &dm816x_emac_hwmod_class, 923 }; 924 925 static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = { 926 .master = &dm81xx_l4_hs_hwmod, 927 .slave = &dm816x_emac1_hwmod, 928 .clk = "sysclk5_ck", 929 .user = OCP_USER_MPU, 930 }; 931 932 static struct omap_hwmod_class_sysconfig dm81xx_mmc_sysc = { 933 .rev_offs = 0x0, 934 .sysc_offs = 0x110, 935 .syss_offs = 0x114, 936 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 937 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 938 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, 939 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 940 .sysc_fields = &omap_hwmod_sysc_type1, 941 }; 942 943 static struct omap_hwmod_class dm81xx_mmc_class = { 944 .name = "mmc", 945 .sysc = &dm81xx_mmc_sysc, 946 }; 947 948 static struct omap_hwmod_opt_clk dm81xx_mmc_opt_clks[] = { 949 { .role = "dbck", .clk = "sysclk18_ck", }, 950 }; 951 952 static struct omap_hsmmc_dev_attr mmc_dev_attr = { 953 }; 954 955 static struct omap_hwmod dm814x_mmc1_hwmod = { 956 .name = "mmc1", 957 .clkdm_name = "alwon_l3s_clkdm", 958 .opt_clks = dm81xx_mmc_opt_clks, 959 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), 960 .main_clk = "sysclk8_ck", 961 .prcm = { 962 .omap4 = { 963 .clkctrl_offs = DM814X_CM_ALWON_MMCHS_0_CLKCTRL, 964 .modulemode = MODULEMODE_SWCTRL, 965 }, 966 }, 967 .dev_attr = &mmc_dev_attr, 968 .class = &dm81xx_mmc_class, 969 }; 970 971 static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc1 = { 972 .master = &dm81xx_l4_ls_hwmod, 973 .slave = &dm814x_mmc1_hwmod, 974 .clk = "sysclk6_ck", 975 .user = OCP_USER_MPU, 976 .flags = OMAP_FIREWALL_L4 977 }; 978 979 static struct omap_hwmod dm814x_mmc2_hwmod = { 980 .name = "mmc2", 981 .clkdm_name = "alwon_l3s_clkdm", 982 .opt_clks = dm81xx_mmc_opt_clks, 983 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), 984 .main_clk = "sysclk8_ck", 985 .prcm = { 986 .omap4 = { 987 .clkctrl_offs = DM814X_CM_ALWON_MMCHS_1_CLKCTRL, 988 .modulemode = MODULEMODE_SWCTRL, 989 }, 990 }, 991 .dev_attr = &mmc_dev_attr, 992 .class = &dm81xx_mmc_class, 993 }; 994 995 static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc2 = { 996 .master = &dm81xx_l4_ls_hwmod, 997 .slave = &dm814x_mmc2_hwmod, 998 .clk = "sysclk6_ck", 999 .user = OCP_USER_MPU, 1000 .flags = OMAP_FIREWALL_L4 1001 }; 1002 1003 static struct omap_hwmod dm814x_mmc3_hwmod = { 1004 .name = "mmc3", 1005 .clkdm_name = "alwon_l3_med_clkdm", 1006 .opt_clks = dm81xx_mmc_opt_clks, 1007 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), 1008 .main_clk = "sysclk8_ck", 1009 .prcm = { 1010 .omap4 = { 1011 .clkctrl_offs = DM814X_CM_ALWON_MMCHS_2_CLKCTRL, 1012 .modulemode = MODULEMODE_SWCTRL, 1013 }, 1014 }, 1015 .dev_attr = &mmc_dev_attr, 1016 .class = &dm81xx_mmc_class, 1017 }; 1018 1019 static struct omap_hwmod_ocp_if dm814x_alwon_l3_med__mmc3 = { 1020 .master = &dm81xx_alwon_l3_med_hwmod, 1021 .slave = &dm814x_mmc3_hwmod, 1022 .clk = "sysclk4_ck", 1023 .user = OCP_USER_MPU, 1024 }; 1025 1026 static struct omap_hwmod dm816x_mmc1_hwmod = { 1027 .name = "mmc1", 1028 .clkdm_name = "alwon_l3s_clkdm", 1029 .opt_clks = dm81xx_mmc_opt_clks, 1030 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), 1031 .main_clk = "sysclk10_ck", 1032 .prcm = { 1033 .omap4 = { 1034 .clkctrl_offs = DM816X_CM_ALWON_SDIO_CLKCTRL, 1035 .modulemode = MODULEMODE_SWCTRL, 1036 }, 1037 }, 1038 .dev_attr = &mmc_dev_attr, 1039 .class = &dm81xx_mmc_class, 1040 }; 1041 1042 static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = { 1043 .master = &dm81xx_l4_ls_hwmod, 1044 .slave = &dm816x_mmc1_hwmod, 1045 .clk = "sysclk6_ck", 1046 .user = OCP_USER_MPU, 1047 .flags = OMAP_FIREWALL_L4 1048 }; 1049 1050 static struct omap_hwmod_class_sysconfig dm816x_mcspi_sysc = { 1051 .rev_offs = 0x0, 1052 .sysc_offs = 0x110, 1053 .syss_offs = 0x114, 1054 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1055 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1056 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, 1057 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 1058 .sysc_fields = &omap_hwmod_sysc_type1, 1059 }; 1060 1061 static struct omap_hwmod_class dm816x_mcspi_class = { 1062 .name = "mcspi", 1063 .sysc = &dm816x_mcspi_sysc, 1064 .rev = OMAP3_MCSPI_REV, 1065 }; 1066 1067 static struct omap2_mcspi_dev_attr dm816x_mcspi1_dev_attr = { 1068 .num_chipselect = 4, 1069 }; 1070 1071 static struct omap_hwmod dm81xx_mcspi1_hwmod = { 1072 .name = "mcspi1", 1073 .clkdm_name = "alwon_l3s_clkdm", 1074 .main_clk = "sysclk10_ck", 1075 .prcm = { 1076 .omap4 = { 1077 .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL, 1078 .modulemode = MODULEMODE_SWCTRL, 1079 }, 1080 }, 1081 .class = &dm816x_mcspi_class, 1082 .dev_attr = &dm816x_mcspi1_dev_attr, 1083 }; 1084 1085 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = { 1086 .master = &dm81xx_l4_ls_hwmod, 1087 .slave = &dm81xx_mcspi1_hwmod, 1088 .clk = "sysclk6_ck", 1089 .user = OCP_USER_MPU, 1090 }; 1091 1092 static struct omap_hwmod_class_sysconfig dm81xx_mailbox_sysc = { 1093 .rev_offs = 0x000, 1094 .sysc_offs = 0x010, 1095 .syss_offs = 0x014, 1096 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1097 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE, 1098 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 1099 .sysc_fields = &omap_hwmod_sysc_type1, 1100 }; 1101 1102 static struct omap_hwmod_class dm81xx_mailbox_hwmod_class = { 1103 .name = "mailbox", 1104 .sysc = &dm81xx_mailbox_sysc, 1105 }; 1106 1107 static struct omap_hwmod dm81xx_mailbox_hwmod = { 1108 .name = "mailbox", 1109 .clkdm_name = "alwon_l3s_clkdm", 1110 .class = &dm81xx_mailbox_hwmod_class, 1111 .main_clk = "sysclk6_ck", 1112 .prcm = { 1113 .omap4 = { 1114 .clkctrl_offs = DM81XX_CM_ALWON_MAILBOX_CLKCTRL, 1115 .modulemode = MODULEMODE_SWCTRL, 1116 }, 1117 }, 1118 }; 1119 1120 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mailbox = { 1121 .master = &dm81xx_l4_ls_hwmod, 1122 .slave = &dm81xx_mailbox_hwmod, 1123 .user = OCP_USER_MPU, 1124 }; 1125 1126 static struct omap_hwmod_class_sysconfig dm81xx_spinbox_sysc = { 1127 .rev_offs = 0x000, 1128 .sysc_offs = 0x010, 1129 .syss_offs = 0x014, 1130 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1131 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE, 1132 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 1133 .sysc_fields = &omap_hwmod_sysc_type1, 1134 }; 1135 1136 static struct omap_hwmod_class dm81xx_spinbox_hwmod_class = { 1137 .name = "spinbox", 1138 .sysc = &dm81xx_spinbox_sysc, 1139 }; 1140 1141 static struct omap_hwmod dm81xx_spinbox_hwmod = { 1142 .name = "spinbox", 1143 .clkdm_name = "alwon_l3s_clkdm", 1144 .class = &dm81xx_spinbox_hwmod_class, 1145 .main_clk = "sysclk6_ck", 1146 .prcm = { 1147 .omap4 = { 1148 .clkctrl_offs = DM81XX_CM_ALWON_SPINBOX_CLKCTRL, 1149 .modulemode = MODULEMODE_SWCTRL, 1150 }, 1151 }, 1152 }; 1153 1154 static struct omap_hwmod_ocp_if dm81xx_l4_ls__spinbox = { 1155 .master = &dm81xx_l4_ls_hwmod, 1156 .slave = &dm81xx_spinbox_hwmod, 1157 .user = OCP_USER_MPU, 1158 }; 1159 1160 static struct omap_hwmod_class dm81xx_tpcc_hwmod_class = { 1161 .name = "tpcc", 1162 }; 1163 1164 static struct omap_hwmod dm81xx_tpcc_hwmod = { 1165 .name = "tpcc", 1166 .class = &dm81xx_tpcc_hwmod_class, 1167 .clkdm_name = "alwon_l3s_clkdm", 1168 .main_clk = "sysclk4_ck", 1169 .prcm = { 1170 .omap4 = { 1171 .clkctrl_offs = DM81XX_CM_ALWON_TPCC_CLKCTRL, 1172 .modulemode = MODULEMODE_SWCTRL, 1173 }, 1174 }, 1175 }; 1176 1177 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tpcc = { 1178 .master = &dm81xx_alwon_l3_fast_hwmod, 1179 .slave = &dm81xx_tpcc_hwmod, 1180 .clk = "sysclk4_ck", 1181 .user = OCP_USER_MPU, 1182 }; 1183 1184 static struct omap_hwmod_addr_space dm81xx_tptc0_addr_space[] = { 1185 { 1186 .pa_start = 0x49800000, 1187 .pa_end = 0x49800000 + SZ_8K - 1, 1188 .flags = ADDR_TYPE_RT, 1189 }, 1190 { }, 1191 }; 1192 1193 static struct omap_hwmod_class dm81xx_tptc0_hwmod_class = { 1194 .name = "tptc0", 1195 }; 1196 1197 static struct omap_hwmod dm81xx_tptc0_hwmod = { 1198 .name = "tptc0", 1199 .class = &dm81xx_tptc0_hwmod_class, 1200 .clkdm_name = "alwon_l3s_clkdm", 1201 .main_clk = "sysclk4_ck", 1202 .prcm = { 1203 .omap4 = { 1204 .clkctrl_offs = DM81XX_CM_ALWON_TPTC0_CLKCTRL, 1205 .modulemode = MODULEMODE_SWCTRL, 1206 }, 1207 }, 1208 }; 1209 1210 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc0 = { 1211 .master = &dm81xx_alwon_l3_fast_hwmod, 1212 .slave = &dm81xx_tptc0_hwmod, 1213 .clk = "sysclk4_ck", 1214 .addr = dm81xx_tptc0_addr_space, 1215 .user = OCP_USER_MPU, 1216 }; 1217 1218 static struct omap_hwmod_ocp_if dm81xx_tptc0__alwon_l3_fast = { 1219 .master = &dm81xx_tptc0_hwmod, 1220 .slave = &dm81xx_alwon_l3_fast_hwmod, 1221 .clk = "sysclk4_ck", 1222 .addr = dm81xx_tptc0_addr_space, 1223 .user = OCP_USER_MPU, 1224 }; 1225 1226 static struct omap_hwmod_addr_space dm81xx_tptc1_addr_space[] = { 1227 { 1228 .pa_start = 0x49900000, 1229 .pa_end = 0x49900000 + SZ_8K - 1, 1230 .flags = ADDR_TYPE_RT, 1231 }, 1232 { }, 1233 }; 1234 1235 static struct omap_hwmod_class dm81xx_tptc1_hwmod_class = { 1236 .name = "tptc1", 1237 }; 1238 1239 static struct omap_hwmod dm81xx_tptc1_hwmod = { 1240 .name = "tptc1", 1241 .class = &dm81xx_tptc1_hwmod_class, 1242 .clkdm_name = "alwon_l3s_clkdm", 1243 .main_clk = "sysclk4_ck", 1244 .prcm = { 1245 .omap4 = { 1246 .clkctrl_offs = DM81XX_CM_ALWON_TPTC1_CLKCTRL, 1247 .modulemode = MODULEMODE_SWCTRL, 1248 }, 1249 }, 1250 }; 1251 1252 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc1 = { 1253 .master = &dm81xx_alwon_l3_fast_hwmod, 1254 .slave = &dm81xx_tptc1_hwmod, 1255 .clk = "sysclk4_ck", 1256 .addr = dm81xx_tptc1_addr_space, 1257 .user = OCP_USER_MPU, 1258 }; 1259 1260 static struct omap_hwmod_ocp_if dm81xx_tptc1__alwon_l3_fast = { 1261 .master = &dm81xx_tptc1_hwmod, 1262 .slave = &dm81xx_alwon_l3_fast_hwmod, 1263 .clk = "sysclk4_ck", 1264 .addr = dm81xx_tptc1_addr_space, 1265 .user = OCP_USER_MPU, 1266 }; 1267 1268 static struct omap_hwmod_addr_space dm81xx_tptc2_addr_space[] = { 1269 { 1270 .pa_start = 0x49a00000, 1271 .pa_end = 0x49a00000 + SZ_8K - 1, 1272 .flags = ADDR_TYPE_RT, 1273 }, 1274 { }, 1275 }; 1276 1277 static struct omap_hwmod_class dm81xx_tptc2_hwmod_class = { 1278 .name = "tptc2", 1279 }; 1280 1281 static struct omap_hwmod dm81xx_tptc2_hwmod = { 1282 .name = "tptc2", 1283 .class = &dm81xx_tptc2_hwmod_class, 1284 .clkdm_name = "alwon_l3s_clkdm", 1285 .main_clk = "sysclk4_ck", 1286 .prcm = { 1287 .omap4 = { 1288 .clkctrl_offs = DM81XX_CM_ALWON_TPTC2_CLKCTRL, 1289 .modulemode = MODULEMODE_SWCTRL, 1290 }, 1291 }, 1292 }; 1293 1294 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc2 = { 1295 .master = &dm81xx_alwon_l3_fast_hwmod, 1296 .slave = &dm81xx_tptc2_hwmod, 1297 .clk = "sysclk4_ck", 1298 .addr = dm81xx_tptc2_addr_space, 1299 .user = OCP_USER_MPU, 1300 }; 1301 1302 static struct omap_hwmod_ocp_if dm81xx_tptc2__alwon_l3_fast = { 1303 .master = &dm81xx_tptc2_hwmod, 1304 .slave = &dm81xx_alwon_l3_fast_hwmod, 1305 .clk = "sysclk4_ck", 1306 .addr = dm81xx_tptc2_addr_space, 1307 .user = OCP_USER_MPU, 1308 }; 1309 1310 static struct omap_hwmod_addr_space dm81xx_tptc3_addr_space[] = { 1311 { 1312 .pa_start = 0x49b00000, 1313 .pa_end = 0x49b00000 + SZ_8K - 1, 1314 .flags = ADDR_TYPE_RT, 1315 }, 1316 { }, 1317 }; 1318 1319 static struct omap_hwmod_class dm81xx_tptc3_hwmod_class = { 1320 .name = "tptc3", 1321 }; 1322 1323 static struct omap_hwmod dm81xx_tptc3_hwmod = { 1324 .name = "tptc3", 1325 .class = &dm81xx_tptc3_hwmod_class, 1326 .clkdm_name = "alwon_l3s_clkdm", 1327 .main_clk = "sysclk4_ck", 1328 .prcm = { 1329 .omap4 = { 1330 .clkctrl_offs = DM81XX_CM_ALWON_TPTC3_CLKCTRL, 1331 .modulemode = MODULEMODE_SWCTRL, 1332 }, 1333 }, 1334 }; 1335 1336 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc3 = { 1337 .master = &dm81xx_alwon_l3_fast_hwmod, 1338 .slave = &dm81xx_tptc3_hwmod, 1339 .clk = "sysclk4_ck", 1340 .addr = dm81xx_tptc3_addr_space, 1341 .user = OCP_USER_MPU, 1342 }; 1343 1344 static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = { 1345 .master = &dm81xx_tptc3_hwmod, 1346 .slave = &dm81xx_alwon_l3_fast_hwmod, 1347 .clk = "sysclk4_ck", 1348 .addr = dm81xx_tptc3_addr_space, 1349 .user = OCP_USER_MPU, 1350 }; 1351 1352 /* 1353 * REVISIT: Test and enable the following once clocks work: 1354 * dm81xx_l4_ls__gpio1 1355 * dm81xx_l4_ls__gpio2 1356 * dm81xx_l4_ls__mailbox 1357 * 1358 * Also note that some devices share a single clkctrl_offs.. 1359 * For example, i2c1 and 3 share one, and i2c2 and 4 share one. 1360 */ 1361 static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = { 1362 &dm814x_mpu__alwon_l3_slow, 1363 &dm814x_mpu__alwon_l3_med, 1364 &dm81xx_alwon_l3_slow__l4_ls, 1365 &dm81xx_alwon_l3_slow__l4_hs, 1366 &dm81xx_l4_ls__uart1, 1367 &dm81xx_l4_ls__uart2, 1368 &dm81xx_l4_ls__uart3, 1369 &dm81xx_l4_ls__wd_timer1, 1370 &dm81xx_l4_ls__i2c1, 1371 &dm81xx_l4_ls__i2c2, 1372 &dm81xx_l4_ls__elm, 1373 &dm81xx_l4_ls__mcspi1, 1374 &dm814x_l4_ls__mmc1, 1375 &dm814x_l4_ls__mmc2, 1376 &dm81xx_alwon_l3_fast__tpcc, 1377 &dm81xx_alwon_l3_fast__tptc0, 1378 &dm81xx_alwon_l3_fast__tptc1, 1379 &dm81xx_alwon_l3_fast__tptc2, 1380 &dm81xx_alwon_l3_fast__tptc3, 1381 &dm81xx_tptc0__alwon_l3_fast, 1382 &dm81xx_tptc1__alwon_l3_fast, 1383 &dm81xx_tptc2__alwon_l3_fast, 1384 &dm81xx_tptc3__alwon_l3_fast, 1385 &dm814x_l4_ls__timer1, 1386 &dm814x_l4_ls__timer2, 1387 &dm814x_l4_hs__cpgmac0, 1388 &dm814x_cpgmac0__mdio, 1389 &dm81xx_alwon_l3_slow__gpmc, 1390 &dm814x_default_l3_slow__usbss, 1391 &dm814x_alwon_l3_med__mmc3, 1392 NULL, 1393 }; 1394 1395 int __init dm814x_hwmod_init(void) 1396 { 1397 omap_hwmod_init(); 1398 return omap_hwmod_register_links(dm814x_hwmod_ocp_ifs); 1399 } 1400 1401 static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = { 1402 &dm816x_mpu__alwon_l3_slow, 1403 &dm816x_mpu__alwon_l3_med, 1404 &dm81xx_alwon_l3_slow__l4_ls, 1405 &dm81xx_alwon_l3_slow__l4_hs, 1406 &dm81xx_l4_ls__uart1, 1407 &dm81xx_l4_ls__uart2, 1408 &dm81xx_l4_ls__uart3, 1409 &dm81xx_l4_ls__wd_timer1, 1410 &dm81xx_l4_ls__i2c1, 1411 &dm81xx_l4_ls__i2c2, 1412 &dm81xx_l4_ls__gpio1, 1413 &dm81xx_l4_ls__gpio2, 1414 &dm81xx_l4_ls__elm, 1415 &dm816x_l4_ls__mmc1, 1416 &dm816x_l4_ls__timer1, 1417 &dm816x_l4_ls__timer2, 1418 &dm816x_l4_ls__timer3, 1419 &dm816x_l4_ls__timer4, 1420 &dm816x_l4_ls__timer5, 1421 &dm816x_l4_ls__timer6, 1422 &dm816x_l4_ls__timer7, 1423 &dm81xx_l4_ls__mcspi1, 1424 &dm81xx_l4_ls__mailbox, 1425 &dm81xx_l4_ls__spinbox, 1426 &dm81xx_l4_hs__emac0, 1427 &dm81xx_emac0__mdio, 1428 &dm816x_l4_hs__emac1, 1429 &dm81xx_alwon_l3_fast__tpcc, 1430 &dm81xx_alwon_l3_fast__tptc0, 1431 &dm81xx_alwon_l3_fast__tptc1, 1432 &dm81xx_alwon_l3_fast__tptc2, 1433 &dm81xx_alwon_l3_fast__tptc3, 1434 &dm81xx_tptc0__alwon_l3_fast, 1435 &dm81xx_tptc1__alwon_l3_fast, 1436 &dm81xx_tptc2__alwon_l3_fast, 1437 &dm81xx_tptc3__alwon_l3_fast, 1438 &dm81xx_alwon_l3_slow__gpmc, 1439 &dm816x_default_l3_slow__usbss, 1440 NULL, 1441 }; 1442 1443 int __init dm816x_hwmod_init(void) 1444 { 1445 omap_hwmod_init(); 1446 return omap_hwmod_register_links(dm816x_hwmod_ocp_ifs); 1447 } 1448