1 /*
2  * DM81xx hwmod data.
3  *
4  * Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/
5  * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation version 2.
10  *
11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12  * kind, whether express or implied; without even the implied warranty
13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17 
18 #include <linux/types.h>
19 
20 #include <linux/platform_data/hsmmc-omap.h>
21 
22 #include "omap_hwmod_common_data.h"
23 #include "cm81xx.h"
24 #include "ti81xx.h"
25 #include "wd_timer.h"
26 
27 /*
28  * DM816X hardware modules integration data
29  *
30  * Note: This is incomplete and at present, not generated from h/w database.
31  */
32 
33 /*
34  * Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS"
35  * also dm816x TRM 18.7.17 CM_ALWON device register values minus 0x1400.
36  */
37 #define DM81XX_CM_ALWON_MCASP0_CLKCTRL		0x140
38 #define DM81XX_CM_ALWON_MCASP1_CLKCTRL		0x144
39 #define DM81XX_CM_ALWON_MCASP2_CLKCTRL		0x148
40 #define DM81XX_CM_ALWON_MCBSP_CLKCTRL		0x14c
41 #define DM81XX_CM_ALWON_UART_0_CLKCTRL		0x150
42 #define DM81XX_CM_ALWON_UART_1_CLKCTRL		0x154
43 #define DM81XX_CM_ALWON_UART_2_CLKCTRL		0x158
44 #define DM81XX_CM_ALWON_GPIO_0_CLKCTRL		0x15c
45 #define DM81XX_CM_ALWON_GPIO_1_CLKCTRL		0x160
46 #define DM81XX_CM_ALWON_I2C_0_CLKCTRL		0x164
47 #define DM81XX_CM_ALWON_I2C_1_CLKCTRL		0x168
48 #define DM81XX_CM_ALWON_WDTIMER_CLKCTRL		0x18c
49 #define DM81XX_CM_ALWON_SPI_CLKCTRL		0x190
50 #define DM81XX_CM_ALWON_MAILBOX_CLKCTRL		0x194
51 #define DM81XX_CM_ALWON_SPINBOX_CLKCTRL		0x198
52 #define DM81XX_CM_ALWON_MMUDATA_CLKCTRL		0x19c
53 #define DM81XX_CM_ALWON_MMUCFG_CLKCTRL		0x1a8
54 #define DM81XX_CM_ALWON_CONTROL_CLKCTRL		0x1c4
55 #define DM81XX_CM_ALWON_GPMC_CLKCTRL		0x1d0
56 #define DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL	0x1d4
57 #define DM81XX_CM_ALWON_L3_CLKCTRL		0x1e4
58 #define DM81XX_CM_ALWON_L4HS_CLKCTRL		0x1e8
59 #define DM81XX_CM_ALWON_L4LS_CLKCTRL		0x1ec
60 #define DM81XX_CM_ALWON_RTC_CLKCTRL		0x1f0
61 #define DM81XX_CM_ALWON_TPCC_CLKCTRL		0x1f4
62 #define DM81XX_CM_ALWON_TPTC0_CLKCTRL		0x1f8
63 #define DM81XX_CM_ALWON_TPTC1_CLKCTRL		0x1fc
64 #define DM81XX_CM_ALWON_TPTC2_CLKCTRL		0x200
65 #define DM81XX_CM_ALWON_TPTC3_CLKCTRL		0x204
66 
67 /* Registers specific to dm814x */
68 #define DM814X_CM_ALWON_MCASP_3_4_5_CLKCTRL	0x16c
69 #define DM814X_CM_ALWON_ATL_CLKCTRL		0x170
70 #define DM814X_CM_ALWON_MLB_CLKCTRL		0x174
71 #define DM814X_CM_ALWON_PATA_CLKCTRL		0x178
72 #define DM814X_CM_ALWON_UART_3_CLKCTRL		0x180
73 #define DM814X_CM_ALWON_UART_4_CLKCTRL		0x184
74 #define DM814X_CM_ALWON_UART_5_CLKCTRL		0x188
75 #define DM814X_CM_ALWON_OCM_0_CLKCTRL		0x1b4
76 #define DM814X_CM_ALWON_VCP_CLKCTRL		0x1b8
77 #define DM814X_CM_ALWON_MPU_CLKCTRL		0x1dc
78 #define DM814X_CM_ALWON_DEBUGSS_CLKCTRL		0x1e0
79 #define DM814X_CM_ALWON_DCAN_0_1_CLKCTRL	0x218
80 #define DM814X_CM_ALWON_MMCHS_0_CLKCTRL		0x21c
81 #define DM814X_CM_ALWON_MMCHS_1_CLKCTRL		0x220
82 #define DM814X_CM_ALWON_MMCHS_2_CLKCTRL		0x224
83 #define DM814X_CM_ALWON_CUST_EFUSE_CLKCTRL	0x228
84 
85 /* Registers specific to dm816x */
86 #define DM816X_DM_ALWON_BASE		0x1400
87 #define DM816X_CM_ALWON_TIMER_1_CLKCTRL	(0x1570 - DM816X_DM_ALWON_BASE)
88 #define DM816X_CM_ALWON_TIMER_2_CLKCTRL	(0x1574 - DM816X_DM_ALWON_BASE)
89 #define DM816X_CM_ALWON_TIMER_3_CLKCTRL	(0x1578 - DM816X_DM_ALWON_BASE)
90 #define DM816X_CM_ALWON_TIMER_4_CLKCTRL	(0x157c - DM816X_DM_ALWON_BASE)
91 #define DM816X_CM_ALWON_TIMER_5_CLKCTRL	(0x1580 - DM816X_DM_ALWON_BASE)
92 #define DM816X_CM_ALWON_TIMER_6_CLKCTRL	(0x1584 - DM816X_DM_ALWON_BASE)
93 #define DM816X_CM_ALWON_TIMER_7_CLKCTRL	(0x1588 - DM816X_DM_ALWON_BASE)
94 #define DM816X_CM_ALWON_SDIO_CLKCTRL	(0x15b0 - DM816X_DM_ALWON_BASE)
95 #define DM816X_CM_ALWON_OCMC_0_CLKCTRL	(0x15b4 - DM816X_DM_ALWON_BASE)
96 #define DM816X_CM_ALWON_OCMC_1_CLKCTRL	(0x15b8 - DM816X_DM_ALWON_BASE)
97 #define DM816X_CM_ALWON_ETHERNET_1_CLKCTRL (0x15d8 - DM816X_DM_ALWON_BASE)
98 #define DM816X_CM_ALWON_MPU_CLKCTRL	(0x15dc - DM816X_DM_ALWON_BASE)
99 #define DM816X_CM_ALWON_SR_0_CLKCTRL	(0x1608 - DM816X_DM_ALWON_BASE)
100 #define DM816X_CM_ALWON_SR_1_CLKCTRL	(0x160c - DM816X_DM_ALWON_BASE)
101 
102 /*
103  * The default .clkctrl_offs field is offset from CM_DEFAULT, that's
104  * TRM 18.7.6 CM_DEFAULT device register values minus 0x500
105  */
106 #define DM81XX_CM_DEFAULT_OFFSET	0x500
107 #define DM81XX_CM_DEFAULT_USB_CLKCTRL	(0x558 - DM81XX_CM_DEFAULT_OFFSET)
108 #define DM81XX_CM_DEFAULT_SATA_CLKCTRL	(0x560 - DM81XX_CM_DEFAULT_OFFSET)
109 
110 /* L3 Interconnect entries clocked at 125, 250 and 500MHz */
111 static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = {
112 	.name		= "alwon_l3_slow",
113 	.clkdm_name	= "alwon_l3s_clkdm",
114 	.class		= &l3_hwmod_class,
115 	.flags		= HWMOD_NO_IDLEST,
116 };
117 
118 static struct omap_hwmod dm81xx_default_l3_slow_hwmod = {
119 	.name		= "default_l3_slow",
120 	.clkdm_name	= "default_l3_slow_clkdm",
121 	.class		= &l3_hwmod_class,
122 	.flags		= HWMOD_NO_IDLEST,
123 };
124 
125 static struct omap_hwmod dm81xx_alwon_l3_med_hwmod = {
126 	.name		= "l3_med",
127 	.clkdm_name	= "alwon_l3_med_clkdm",
128 	.class		= &l3_hwmod_class,
129 	.flags		= HWMOD_NO_IDLEST,
130 };
131 
132 /*
133  * L4 standard peripherals, see TRM table 1-12 for devices using this.
134  * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock.
135  */
136 static struct omap_hwmod dm81xx_l4_ls_hwmod = {
137 	.name		= "l4_ls",
138 	.clkdm_name	= "alwon_l3s_clkdm",
139 	.class		= &l4_hwmod_class,
140 	.flags		= HWMOD_NO_IDLEST,
141 };
142 
143 /*
144  * L4 high-speed peripherals. For devices using this, please see the TRM
145  * table 1-13. On dm816x, only EMAC, MDIO and SATA use this. See also TRM
146  * table 1-73 for devices using 250MHz SYSCLK5 clock.
147  */
148 static struct omap_hwmod dm81xx_l4_hs_hwmod = {
149 	.name		= "l4_hs",
150 	.clkdm_name	= "alwon_l3_med_clkdm",
151 	.class		= &l4_hwmod_class,
152 	.flags		= HWMOD_NO_IDLEST,
153 };
154 
155 /* L3 slow -> L4 ls peripheral interface running at 125MHz */
156 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_ls = {
157 	.master	= &dm81xx_alwon_l3_slow_hwmod,
158 	.slave	= &dm81xx_l4_ls_hwmod,
159 	.user	= OCP_USER_MPU,
160 };
161 
162 /* L3 med -> L4 fast peripheral interface running at 250MHz */
163 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_hs = {
164 	.master	= &dm81xx_alwon_l3_med_hwmod,
165 	.slave	= &dm81xx_l4_hs_hwmod,
166 	.user	= OCP_USER_MPU,
167 };
168 
169 /* MPU */
170 static struct omap_hwmod dm814x_mpu_hwmod = {
171 	.name		= "mpu",
172 	.clkdm_name	= "alwon_l3s_clkdm",
173 	.class		= &mpu_hwmod_class,
174 	.flags		= HWMOD_INIT_NO_IDLE,
175 	.main_clk	= "mpu_ck",
176 	.prcm		= {
177 		.omap4 = {
178 			.clkctrl_offs = DM814X_CM_ALWON_MPU_CLKCTRL,
179 			.modulemode = MODULEMODE_SWCTRL,
180 		},
181 	},
182 };
183 
184 static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_slow = {
185 	.master		= &dm814x_mpu_hwmod,
186 	.slave		= &dm81xx_alwon_l3_slow_hwmod,
187 	.user		= OCP_USER_MPU,
188 };
189 
190 /* L3 med peripheral interface running at 200MHz */
191 static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_med = {
192 	.master	= &dm814x_mpu_hwmod,
193 	.slave	= &dm81xx_alwon_l3_med_hwmod,
194 	.user	= OCP_USER_MPU,
195 };
196 
197 static struct omap_hwmod dm816x_mpu_hwmod = {
198 	.name		= "mpu",
199 	.clkdm_name	= "alwon_mpu_clkdm",
200 	.class		= &mpu_hwmod_class,
201 	.flags		= HWMOD_INIT_NO_IDLE,
202 	.main_clk	= "mpu_ck",
203 	.prcm		= {
204 		.omap4 = {
205 			.clkctrl_offs = DM816X_CM_ALWON_MPU_CLKCTRL,
206 			.modulemode = MODULEMODE_SWCTRL,
207 		},
208 	},
209 };
210 
211 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_slow = {
212 	.master		= &dm816x_mpu_hwmod,
213 	.slave		= &dm81xx_alwon_l3_slow_hwmod,
214 	.user		= OCP_USER_MPU,
215 };
216 
217 /* L3 med peripheral interface running at 250MHz */
218 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med = {
219 	.master	= &dm816x_mpu_hwmod,
220 	.slave	= &dm81xx_alwon_l3_med_hwmod,
221 	.user	= OCP_USER_MPU,
222 };
223 
224 /* RTC */
225 static struct omap_hwmod_class_sysconfig ti81xx_rtc_sysc = {
226 	.rev_offs	= 0x74,
227 	.sysc_offs	= 0x78,
228 	.sysc_flags	= SYSC_HAS_SIDLEMODE,
229 	.idlemodes	= SIDLE_FORCE | SIDLE_NO |
230 			  SIDLE_SMART | SIDLE_SMART_WKUP,
231 	.sysc_fields	= &omap_hwmod_sysc_type3,
232 };
233 
234 static struct omap_hwmod_class ti81xx_rtc_hwmod_class = {
235 	.name		= "rtc",
236 	.sysc		= &ti81xx_rtc_sysc,
237 };
238 
239 static struct omap_hwmod ti81xx_rtc_hwmod = {
240 	.name		= "rtc",
241 	.class		= &ti81xx_rtc_hwmod_class,
242 	.clkdm_name	= "alwon_l3s_clkdm",
243 	.flags		= HWMOD_NO_IDLEST,
244 	.main_clk	= "sysclk18_ck",
245 	.prcm		= {
246 		.omap4	= {
247 			.clkctrl_offs = DM81XX_CM_ALWON_RTC_CLKCTRL,
248 			.modulemode = MODULEMODE_SWCTRL,
249 		},
250 	},
251 };
252 
253 static struct omap_hwmod_ocp_if ti81xx_l4_ls__rtc = {
254 	.master		= &dm81xx_l4_ls_hwmod,
255 	.slave		= &ti81xx_rtc_hwmod,
256 	.clk		= "sysclk6_ck",
257 	.user		= OCP_USER_MPU,
258 };
259 
260 /* UART common */
261 static struct omap_hwmod_class_sysconfig uart_sysc = {
262 	.rev_offs	= 0x50,
263 	.sysc_offs	= 0x54,
264 	.syss_offs	= 0x58,
265 	.sysc_flags	= SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
266 				SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
267 				SYSS_HAS_RESET_STATUS,
268 	.idlemodes	= SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
269 				MSTANDBY_SMART_WKUP,
270 	.sysc_fields	= &omap_hwmod_sysc_type1,
271 };
272 
273 static struct omap_hwmod_class uart_class = {
274 	.name = "uart",
275 	.sysc = &uart_sysc,
276 };
277 
278 static struct omap_hwmod dm81xx_uart1_hwmod = {
279 	.name		= "uart1",
280 	.clkdm_name	= "alwon_l3s_clkdm",
281 	.main_clk	= "sysclk10_ck",
282 	.prcm		= {
283 		.omap4 = {
284 			.clkctrl_offs = DM81XX_CM_ALWON_UART_0_CLKCTRL,
285 			.modulemode = MODULEMODE_SWCTRL,
286 		},
287 	},
288 	.class		= &uart_class,
289 	.flags		= DEBUG_TI81XXUART1_FLAGS,
290 };
291 
292 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart1 = {
293 	.master		= &dm81xx_l4_ls_hwmod,
294 	.slave		= &dm81xx_uart1_hwmod,
295 	.clk		= "sysclk6_ck",
296 	.user		= OCP_USER_MPU,
297 };
298 
299 static struct omap_hwmod dm81xx_uart2_hwmod = {
300 	.name		= "uart2",
301 	.clkdm_name	= "alwon_l3s_clkdm",
302 	.main_clk	= "sysclk10_ck",
303 	.prcm		= {
304 		.omap4 = {
305 			.clkctrl_offs = DM81XX_CM_ALWON_UART_1_CLKCTRL,
306 			.modulemode = MODULEMODE_SWCTRL,
307 		},
308 	},
309 	.class		= &uart_class,
310 	.flags		= DEBUG_TI81XXUART2_FLAGS,
311 };
312 
313 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart2 = {
314 	.master		= &dm81xx_l4_ls_hwmod,
315 	.slave		= &dm81xx_uart2_hwmod,
316 	.clk		= "sysclk6_ck",
317 	.user		= OCP_USER_MPU,
318 };
319 
320 static struct omap_hwmod dm81xx_uart3_hwmod = {
321 	.name		= "uart3",
322 	.clkdm_name	= "alwon_l3s_clkdm",
323 	.main_clk	= "sysclk10_ck",
324 	.prcm		= {
325 		.omap4 = {
326 			.clkctrl_offs = DM81XX_CM_ALWON_UART_2_CLKCTRL,
327 			.modulemode = MODULEMODE_SWCTRL,
328 		},
329 	},
330 	.class		= &uart_class,
331 	.flags		= DEBUG_TI81XXUART3_FLAGS,
332 };
333 
334 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart3 = {
335 	.master		= &dm81xx_l4_ls_hwmod,
336 	.slave		= &dm81xx_uart3_hwmod,
337 	.clk		= "sysclk6_ck",
338 	.user		= OCP_USER_MPU,
339 };
340 
341 static struct omap_hwmod_class_sysconfig wd_timer_sysc = {
342 	.rev_offs	= 0x0,
343 	.sysc_offs	= 0x10,
344 	.syss_offs	= 0x14,
345 	.sysc_flags	= SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
346 				SYSS_HAS_RESET_STATUS,
347 	.sysc_fields	= &omap_hwmod_sysc_type1,
348 };
349 
350 static struct omap_hwmod_class wd_timer_class = {
351 	.name		= "wd_timer",
352 	.sysc		= &wd_timer_sysc,
353 	.pre_shutdown	= &omap2_wd_timer_disable,
354 	.reset		= &omap2_wd_timer_reset,
355 };
356 
357 static struct omap_hwmod dm81xx_wd_timer_hwmod = {
358 	.name		= "wd_timer",
359 	.clkdm_name	= "alwon_l3s_clkdm",
360 	.main_clk	= "sysclk18_ck",
361 	.flags		= HWMOD_NO_IDLEST,
362 	.prcm		= {
363 		.omap4 = {
364 			.clkctrl_offs = DM81XX_CM_ALWON_WDTIMER_CLKCTRL,
365 			.modulemode = MODULEMODE_SWCTRL,
366 		},
367 	},
368 	.class		= &wd_timer_class,
369 };
370 
371 static struct omap_hwmod_ocp_if dm81xx_l4_ls__wd_timer1 = {
372 	.master		= &dm81xx_l4_ls_hwmod,
373 	.slave		= &dm81xx_wd_timer_hwmod,
374 	.clk		= "sysclk6_ck",
375 	.user		= OCP_USER_MPU,
376 };
377 
378 /* I2C common */
379 static struct omap_hwmod_class_sysconfig i2c_sysc = {
380 	.rev_offs	= 0x0,
381 	.sysc_offs	= 0x10,
382 	.syss_offs	= 0x90,
383 	.sysc_flags	= SYSC_HAS_SIDLEMODE |
384 				SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
385 				SYSC_HAS_AUTOIDLE,
386 	.idlemodes	= SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
387 	.sysc_fields	= &omap_hwmod_sysc_type1,
388 };
389 
390 static struct omap_hwmod_class i2c_class = {
391 	.name = "i2c",
392 	.sysc = &i2c_sysc,
393 };
394 
395 static struct omap_hwmod dm81xx_i2c1_hwmod = {
396 	.name		= "i2c1",
397 	.clkdm_name	= "alwon_l3s_clkdm",
398 	.main_clk	= "sysclk10_ck",
399 	.prcm		= {
400 		.omap4 = {
401 			.clkctrl_offs = DM81XX_CM_ALWON_I2C_0_CLKCTRL,
402 			.modulemode = MODULEMODE_SWCTRL,
403 		},
404 	},
405 	.class		= &i2c_class,
406 };
407 
408 static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c1 = {
409 	.master		= &dm81xx_l4_ls_hwmod,
410 	.slave		= &dm81xx_i2c1_hwmod,
411 	.clk		= "sysclk6_ck",
412 	.user		= OCP_USER_MPU,
413 };
414 
415 static struct omap_hwmod dm81xx_i2c2_hwmod = {
416 	.name		= "i2c2",
417 	.clkdm_name	= "alwon_l3s_clkdm",
418 	.main_clk	= "sysclk10_ck",
419 	.prcm		= {
420 		.omap4 = {
421 			.clkctrl_offs = DM81XX_CM_ALWON_I2C_1_CLKCTRL,
422 			.modulemode = MODULEMODE_SWCTRL,
423 		},
424 	},
425 	.class		= &i2c_class,
426 };
427 
428 static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = {
429 	.master		= &dm81xx_l4_ls_hwmod,
430 	.slave		= &dm81xx_i2c2_hwmod,
431 	.clk		= "sysclk6_ck",
432 	.user		= OCP_USER_MPU,
433 };
434 
435 static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = {
436 	.rev_offs	= 0x0000,
437 	.sysc_offs	= 0x0010,
438 	.syss_offs	= 0x0014,
439 	.sysc_flags	= SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
440 				SYSC_HAS_SOFTRESET |
441 				SYSS_HAS_RESET_STATUS,
442 	.idlemodes	= SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
443 	.sysc_fields	= &omap_hwmod_sysc_type1,
444 };
445 
446 static struct omap_hwmod_class dm81xx_elm_hwmod_class = {
447 	.name = "elm",
448 	.sysc = &dm81xx_elm_sysc,
449 };
450 
451 static struct omap_hwmod dm81xx_elm_hwmod = {
452 	.name		= "elm",
453 	.clkdm_name	= "alwon_l3s_clkdm",
454 	.class		= &dm81xx_elm_hwmod_class,
455 	.main_clk	= "sysclk6_ck",
456 };
457 
458 static struct omap_hwmod_ocp_if dm81xx_l4_ls__elm = {
459 	.master		= &dm81xx_l4_ls_hwmod,
460 	.slave		= &dm81xx_elm_hwmod,
461 	.clk		= "sysclk6_ck",
462 	.user		= OCP_USER_MPU,
463 };
464 
465 static struct omap_hwmod_class_sysconfig dm81xx_gpio_sysc = {
466 	.rev_offs	= 0x0000,
467 	.sysc_offs	= 0x0010,
468 	.syss_offs	= 0x0114,
469 	.sysc_flags	= SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
470 				SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
471 				SYSS_HAS_RESET_STATUS,
472 	.idlemodes	= SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
473 				SIDLE_SMART_WKUP,
474 	.sysc_fields	= &omap_hwmod_sysc_type1,
475 };
476 
477 static struct omap_hwmod_class dm81xx_gpio_hwmod_class = {
478 	.name	= "gpio",
479 	.sysc	= &dm81xx_gpio_sysc,
480 };
481 
482 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
483 	{ .role = "dbclk", .clk = "sysclk18_ck" },
484 };
485 
486 static struct omap_hwmod dm81xx_gpio1_hwmod = {
487 	.name		= "gpio1",
488 	.clkdm_name	= "alwon_l3s_clkdm",
489 	.class		= &dm81xx_gpio_hwmod_class,
490 	.main_clk	= "sysclk6_ck",
491 	.prcm = {
492 		.omap4 = {
493 			.clkctrl_offs = DM81XX_CM_ALWON_GPIO_0_CLKCTRL,
494 			.modulemode = MODULEMODE_SWCTRL,
495 		},
496 	},
497 	.opt_clks	= gpio1_opt_clks,
498 	.opt_clks_cnt	= ARRAY_SIZE(gpio1_opt_clks),
499 };
500 
501 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = {
502 	.master		= &dm81xx_l4_ls_hwmod,
503 	.slave		= &dm81xx_gpio1_hwmod,
504 	.clk		= "sysclk6_ck",
505 	.user		= OCP_USER_MPU,
506 };
507 
508 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
509 	{ .role = "dbclk", .clk = "sysclk18_ck" },
510 };
511 
512 static struct omap_hwmod dm81xx_gpio2_hwmod = {
513 	.name		= "gpio2",
514 	.clkdm_name	= "alwon_l3s_clkdm",
515 	.class		= &dm81xx_gpio_hwmod_class,
516 	.main_clk	= "sysclk6_ck",
517 	.prcm = {
518 		.omap4 = {
519 			.clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL,
520 			.modulemode = MODULEMODE_SWCTRL,
521 		},
522 	},
523 	.opt_clks	= gpio2_opt_clks,
524 	.opt_clks_cnt	= ARRAY_SIZE(gpio2_opt_clks),
525 };
526 
527 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = {
528 	.master		= &dm81xx_l4_ls_hwmod,
529 	.slave		= &dm81xx_gpio2_hwmod,
530 	.clk		= "sysclk6_ck",
531 	.user		= OCP_USER_MPU,
532 };
533 
534 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
535 	{ .role = "dbclk", .clk = "sysclk18_ck" },
536 };
537 
538 static struct omap_hwmod dm81xx_gpio3_hwmod = {
539 	.name		= "gpio3",
540 	.clkdm_name	= "alwon_l3s_clkdm",
541 	.class		= &dm81xx_gpio_hwmod_class,
542 	.main_clk	= "sysclk6_ck",
543 	.prcm = {
544 		.omap4 = {
545 			.clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL,
546 			.modulemode = MODULEMODE_SWCTRL,
547 		},
548 	},
549 	.opt_clks	= gpio3_opt_clks,
550 	.opt_clks_cnt	= ARRAY_SIZE(gpio3_opt_clks),
551 };
552 
553 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio3 = {
554 	.master		= &dm81xx_l4_ls_hwmod,
555 	.slave		= &dm81xx_gpio3_hwmod,
556 	.clk		= "sysclk6_ck",
557 	.user		= OCP_USER_MPU,
558 };
559 
560 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
561 	{ .role = "dbclk", .clk = "sysclk18_ck" },
562 };
563 
564 static struct omap_hwmod dm81xx_gpio4_hwmod = {
565 	.name		= "gpio4",
566 	.clkdm_name	= "alwon_l3s_clkdm",
567 	.class		= &dm81xx_gpio_hwmod_class,
568 	.main_clk	= "sysclk6_ck",
569 	.prcm = {
570 		.omap4 = {
571 			.clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL,
572 			.modulemode = MODULEMODE_SWCTRL,
573 		},
574 	},
575 	.opt_clks	= gpio4_opt_clks,
576 	.opt_clks_cnt	= ARRAY_SIZE(gpio4_opt_clks),
577 };
578 
579 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio4 = {
580 	.master		= &dm81xx_l4_ls_hwmod,
581 	.slave		= &dm81xx_gpio4_hwmod,
582 	.clk		= "sysclk6_ck",
583 	.user		= OCP_USER_MPU,
584 };
585 
586 static struct omap_hwmod_class_sysconfig dm81xx_gpmc_sysc = {
587 	.rev_offs	= 0x0,
588 	.sysc_offs	= 0x10,
589 	.syss_offs	= 0x14,
590 	.sysc_flags	= SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
591 				SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
592 	.idlemodes	= SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
593 	.sysc_fields	= &omap_hwmod_sysc_type1,
594 };
595 
596 static struct omap_hwmod_class dm81xx_gpmc_hwmod_class = {
597 	.name	= "gpmc",
598 	.sysc	= &dm81xx_gpmc_sysc,
599 };
600 
601 static struct omap_hwmod dm81xx_gpmc_hwmod = {
602 	.name		= "gpmc",
603 	.clkdm_name	= "alwon_l3s_clkdm",
604 	.class		= &dm81xx_gpmc_hwmod_class,
605 	.main_clk	= "sysclk6_ck",
606 	/* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
607 	.flags		= DEBUG_OMAP_GPMC_HWMOD_FLAGS,
608 	.prcm = {
609 		.omap4 = {
610 			.clkctrl_offs = DM81XX_CM_ALWON_GPMC_CLKCTRL,
611 			.modulemode = MODULEMODE_SWCTRL,
612 		},
613 	},
614 };
615 
616 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = {
617 	.master		= &dm81xx_alwon_l3_slow_hwmod,
618 	.slave		= &dm81xx_gpmc_hwmod,
619 	.user		= OCP_USER_MPU,
620 };
621 
622 /* USB needs udelay 1 after reset at least on hp t410, use 2 for margin */
623 static struct omap_hwmod_class_sysconfig dm81xx_usbhsotg_sysc = {
624 	.rev_offs	= 0x0,
625 	.sysc_offs	= 0x10,
626 	.srst_udelay	= 2,
627 	.sysc_flags	= SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
628 				SYSC_HAS_SOFTRESET,
629 	.idlemodes	= SIDLE_SMART | MSTANDBY_FORCE | MSTANDBY_SMART,
630 	.sysc_fields	= &omap_hwmod_sysc_type2,
631 };
632 
633 static struct omap_hwmod_class dm81xx_usbotg_class = {
634 	.name = "usbotg",
635 	.sysc = &dm81xx_usbhsotg_sysc,
636 };
637 
638 static struct omap_hwmod dm814x_usbss_hwmod = {
639 	.name		= "usb_otg_hs",
640 	.clkdm_name	= "default_l3_slow_clkdm",
641 	.main_clk	= "pll260dcoclkldo",	/* 481c5260.adpll.dcoclkldo */
642 	.prcm		= {
643 		.omap4 = {
644 			.clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL,
645 			.modulemode = MODULEMODE_SWCTRL,
646 		},
647 	},
648 	.class		= &dm81xx_usbotg_class,
649 };
650 
651 static struct omap_hwmod_ocp_if dm814x_default_l3_slow__usbss = {
652 	.master		= &dm81xx_default_l3_slow_hwmod,
653 	.slave		= &dm814x_usbss_hwmod,
654 	.clk		= "sysclk6_ck",
655 	.user		= OCP_USER_MPU,
656 };
657 
658 static struct omap_hwmod dm816x_usbss_hwmod = {
659 	.name		= "usb_otg_hs",
660 	.clkdm_name	= "default_l3_slow_clkdm",
661 	.main_clk	= "sysclk6_ck",
662 	.prcm		= {
663 		.omap4 = {
664 			.clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL,
665 			.modulemode = MODULEMODE_SWCTRL,
666 		},
667 	},
668 	.class		= &dm81xx_usbotg_class,
669 };
670 
671 static struct omap_hwmod_ocp_if dm816x_default_l3_slow__usbss = {
672 	.master		= &dm81xx_default_l3_slow_hwmod,
673 	.slave		= &dm816x_usbss_hwmod,
674 	.clk		= "sysclk6_ck",
675 	.user		= OCP_USER_MPU,
676 };
677 
678 static struct omap_hwmod_class_sysconfig dm816x_timer_sysc = {
679 	.rev_offs	= 0x0000,
680 	.sysc_offs	= 0x0010,
681 	.syss_offs	= 0x0014,
682 	.sysc_flags	= SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET,
683 	.idlemodes	= SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
684 				SIDLE_SMART_WKUP,
685 	.sysc_fields	= &omap_hwmod_sysc_type2,
686 };
687 
688 static struct omap_hwmod_class dm816x_timer_hwmod_class = {
689 	.name = "timer",
690 	.sysc = &dm816x_timer_sysc,
691 };
692 
693 static struct omap_hwmod dm816x_timer3_hwmod = {
694 	.name		= "timer3",
695 	.clkdm_name	= "alwon_l3s_clkdm",
696 	.main_clk	= "timer3_fck",
697 	.prcm		= {
698 		.omap4 = {
699 			.clkctrl_offs = DM816X_CM_ALWON_TIMER_3_CLKCTRL,
700 			.modulemode = MODULEMODE_SWCTRL,
701 		},
702 	},
703 	.class		= &dm816x_timer_hwmod_class,
704 };
705 
706 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer3 = {
707 	.master		= &dm81xx_l4_ls_hwmod,
708 	.slave		= &dm816x_timer3_hwmod,
709 	.clk		= "sysclk6_ck",
710 	.user		= OCP_USER_MPU,
711 };
712 
713 static struct omap_hwmod dm816x_timer4_hwmod = {
714 	.name		= "timer4",
715 	.clkdm_name	= "alwon_l3s_clkdm",
716 	.main_clk	= "timer4_fck",
717 	.prcm		= {
718 		.omap4 = {
719 			.clkctrl_offs = DM816X_CM_ALWON_TIMER_4_CLKCTRL,
720 			.modulemode = MODULEMODE_SWCTRL,
721 		},
722 	},
723 	.class		= &dm816x_timer_hwmod_class,
724 };
725 
726 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer4 = {
727 	.master		= &dm81xx_l4_ls_hwmod,
728 	.slave		= &dm816x_timer4_hwmod,
729 	.clk		= "sysclk6_ck",
730 	.user		= OCP_USER_MPU,
731 };
732 
733 static struct omap_hwmod dm816x_timer5_hwmod = {
734 	.name		= "timer5",
735 	.clkdm_name	= "alwon_l3s_clkdm",
736 	.main_clk	= "timer5_fck",
737 	.prcm		= {
738 		.omap4 = {
739 			.clkctrl_offs = DM816X_CM_ALWON_TIMER_5_CLKCTRL,
740 			.modulemode = MODULEMODE_SWCTRL,
741 		},
742 	},
743 	.class		= &dm816x_timer_hwmod_class,
744 };
745 
746 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer5 = {
747 	.master		= &dm81xx_l4_ls_hwmod,
748 	.slave		= &dm816x_timer5_hwmod,
749 	.clk		= "sysclk6_ck",
750 	.user		= OCP_USER_MPU,
751 };
752 
753 static struct omap_hwmod dm816x_timer6_hwmod = {
754 	.name		= "timer6",
755 	.clkdm_name	= "alwon_l3s_clkdm",
756 	.main_clk	= "timer6_fck",
757 	.prcm		= {
758 		.omap4 = {
759 			.clkctrl_offs = DM816X_CM_ALWON_TIMER_6_CLKCTRL,
760 			.modulemode = MODULEMODE_SWCTRL,
761 		},
762 	},
763 	.class		= &dm816x_timer_hwmod_class,
764 };
765 
766 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer6 = {
767 	.master		= &dm81xx_l4_ls_hwmod,
768 	.slave		= &dm816x_timer6_hwmod,
769 	.clk		= "sysclk6_ck",
770 	.user		= OCP_USER_MPU,
771 };
772 
773 static struct omap_hwmod dm816x_timer7_hwmod = {
774 	.name		= "timer7",
775 	.clkdm_name	= "alwon_l3s_clkdm",
776 	.main_clk	= "timer7_fck",
777 	.prcm		= {
778 		.omap4 = {
779 			.clkctrl_offs = DM816X_CM_ALWON_TIMER_7_CLKCTRL,
780 			.modulemode = MODULEMODE_SWCTRL,
781 		},
782 	},
783 	.class		= &dm816x_timer_hwmod_class,
784 };
785 
786 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = {
787 	.master		= &dm81xx_l4_ls_hwmod,
788 	.slave		= &dm816x_timer7_hwmod,
789 	.clk		= "sysclk6_ck",
790 	.user		= OCP_USER_MPU,
791 };
792 
793 /* EMAC Ethernet */
794 static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = {
795 	.rev_offs	= 0x0,
796 	.sysc_offs	= 0x4,
797 	.sysc_flags	= SYSC_HAS_SOFTRESET,
798 	.sysc_fields	= &omap_hwmod_sysc_type2,
799 };
800 
801 static struct omap_hwmod_class dm816x_emac_hwmod_class = {
802 	.name		= "emac",
803 	.sysc		= &dm816x_emac_sysc,
804 };
805 
806 /*
807  * On dm816x the MDIO is within EMAC0. As the MDIO driver is a separate
808  * driver probed before EMAC0, we let MDIO do the clock idling.
809  */
810 static struct omap_hwmod dm816x_emac0_hwmod = {
811 	.name		= "emac0",
812 	.clkdm_name	= "alwon_ethernet_clkdm",
813 	.class		= &dm816x_emac_hwmod_class,
814 	.flags		= HWMOD_NO_IDLEST,
815 };
816 
817 static struct omap_hwmod_ocp_if dm81xx_l4_hs__emac0 = {
818 	.master		= &dm81xx_l4_hs_hwmod,
819 	.slave		= &dm816x_emac0_hwmod,
820 	.clk		= "sysclk5_ck",
821 	.user		= OCP_USER_MPU,
822 };
823 
824 static struct omap_hwmod_class dm81xx_mdio_hwmod_class = {
825 	.name		= "davinci_mdio",
826 	.sysc		= &dm816x_emac_sysc,
827 };
828 
829 static struct omap_hwmod dm81xx_emac0_mdio_hwmod = {
830 	.name		= "davinci_mdio",
831 	.class		= &dm81xx_mdio_hwmod_class,
832 	.clkdm_name	= "alwon_ethernet_clkdm",
833 	.main_clk	= "sysclk24_ck",
834 	.flags		= HWMOD_NO_IDLEST,
835 	/*
836 	 * REVISIT: This should be moved to the emac0_hwmod
837 	 * once we have a better way to handle device slaves.
838 	 */
839 	.prcm		= {
840 		.omap4 = {
841 			.clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
842 			.modulemode = MODULEMODE_SWCTRL,
843 		},
844 	},
845 };
846 
847 static struct omap_hwmod_ocp_if dm81xx_emac0__mdio = {
848 	.master		= &dm81xx_l4_hs_hwmod,
849 	.slave		= &dm81xx_emac0_mdio_hwmod,
850 	.user		= OCP_USER_MPU,
851 };
852 
853 static struct omap_hwmod dm816x_emac1_hwmod = {
854 	.name		= "emac1",
855 	.clkdm_name	= "alwon_ethernet_clkdm",
856 	.main_clk	= "sysclk24_ck",
857 	.flags		= HWMOD_NO_IDLEST,
858 	.prcm		= {
859 		.omap4 = {
860 			.clkctrl_offs = DM816X_CM_ALWON_ETHERNET_1_CLKCTRL,
861 			.modulemode = MODULEMODE_SWCTRL,
862 		},
863 	},
864 	.class		= &dm816x_emac_hwmod_class,
865 };
866 
867 static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = {
868 	.master		= &dm81xx_l4_hs_hwmod,
869 	.slave		= &dm816x_emac1_hwmod,
870 	.clk		= "sysclk5_ck",
871 	.user		= OCP_USER_MPU,
872 };
873 
874 static struct omap_hwmod_class_sysconfig dm81xx_sata_sysc = {
875 	.rev_offs	= 0x00fc,
876 	.sysc_offs	= 0x1100,
877 	.sysc_flags	= SYSC_HAS_SIDLEMODE,
878 	.idlemodes	= SIDLE_FORCE,
879 	.sysc_fields	= &omap_hwmod_sysc_type3,
880 };
881 
882 static struct omap_hwmod_class dm81xx_sata_hwmod_class = {
883 	.name	= "sata",
884 	.sysc	= &dm81xx_sata_sysc,
885 };
886 
887 static struct omap_hwmod dm81xx_sata_hwmod = {
888 	.name		= "sata",
889 	.clkdm_name	= "default_clkdm",
890 	.flags		= HWMOD_NO_IDLEST,
891 	.prcm = {
892 		.omap4 = {
893 			.clkctrl_offs = DM81XX_CM_DEFAULT_SATA_CLKCTRL,
894 			.modulemode   = MODULEMODE_SWCTRL,
895 		},
896 	},
897 	.class		= &dm81xx_sata_hwmod_class,
898 };
899 
900 static struct omap_hwmod_ocp_if dm81xx_l4_hs__sata = {
901 	.master		= &dm81xx_l4_hs_hwmod,
902 	.slave		= &dm81xx_sata_hwmod,
903 	.clk		= "sysclk5_ck",
904 	.user		= OCP_USER_MPU,
905 };
906 
907 static struct omap_hwmod_class_sysconfig dm81xx_mmc_sysc = {
908 	.rev_offs	= 0x0,
909 	.sysc_offs	= 0x110,
910 	.syss_offs	= 0x114,
911 	.sysc_flags	= SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
912 				SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
913 				SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
914 	.idlemodes	= SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
915 	.sysc_fields	= &omap_hwmod_sysc_type1,
916 };
917 
918 static struct omap_hwmod_class dm81xx_mmc_class = {
919 	.name = "mmc",
920 	.sysc = &dm81xx_mmc_sysc,
921 };
922 
923 static struct omap_hwmod_opt_clk dm81xx_mmc_opt_clks[] = {
924 	{ .role = "dbck", .clk = "sysclk18_ck", },
925 };
926 
927 static struct omap_hsmmc_dev_attr mmc_dev_attr = {
928 };
929 
930 static struct omap_hwmod dm814x_mmc1_hwmod = {
931 	.name		= "mmc1",
932 	.clkdm_name	= "alwon_l3s_clkdm",
933 	.opt_clks	= dm81xx_mmc_opt_clks,
934 	.opt_clks_cnt	= ARRAY_SIZE(dm81xx_mmc_opt_clks),
935 	.main_clk	= "sysclk8_ck",
936 	.prcm		= {
937 		.omap4 = {
938 			.clkctrl_offs = DM814X_CM_ALWON_MMCHS_0_CLKCTRL,
939 			.modulemode = MODULEMODE_SWCTRL,
940 		},
941 	},
942 	.dev_attr	= &mmc_dev_attr,
943 	.class		= &dm81xx_mmc_class,
944 };
945 
946 static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc1 = {
947 	.master		= &dm81xx_l4_ls_hwmod,
948 	.slave		= &dm814x_mmc1_hwmod,
949 	.clk		= "sysclk6_ck",
950 	.user		= OCP_USER_MPU,
951 	.flags		= OMAP_FIREWALL_L4
952 };
953 
954 static struct omap_hwmod dm814x_mmc2_hwmod = {
955 	.name		= "mmc2",
956 	.clkdm_name	= "alwon_l3s_clkdm",
957 	.opt_clks	= dm81xx_mmc_opt_clks,
958 	.opt_clks_cnt	= ARRAY_SIZE(dm81xx_mmc_opt_clks),
959 	.main_clk	= "sysclk8_ck",
960 	.prcm		= {
961 		.omap4 = {
962 			.clkctrl_offs = DM814X_CM_ALWON_MMCHS_1_CLKCTRL,
963 			.modulemode = MODULEMODE_SWCTRL,
964 		},
965 	},
966 	.dev_attr	= &mmc_dev_attr,
967 	.class		= &dm81xx_mmc_class,
968 };
969 
970 static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc2 = {
971 	.master		= &dm81xx_l4_ls_hwmod,
972 	.slave		= &dm814x_mmc2_hwmod,
973 	.clk		= "sysclk6_ck",
974 	.user		= OCP_USER_MPU,
975 	.flags		= OMAP_FIREWALL_L4
976 };
977 
978 static struct omap_hwmod dm814x_mmc3_hwmod = {
979 	.name		= "mmc3",
980 	.clkdm_name	= "alwon_l3_med_clkdm",
981 	.opt_clks	= dm81xx_mmc_opt_clks,
982 	.opt_clks_cnt	= ARRAY_SIZE(dm81xx_mmc_opt_clks),
983 	.main_clk	= "sysclk8_ck",
984 	.prcm		= {
985 		.omap4 = {
986 			.clkctrl_offs = DM814X_CM_ALWON_MMCHS_2_CLKCTRL,
987 			.modulemode = MODULEMODE_SWCTRL,
988 		},
989 	},
990 	.dev_attr	= &mmc_dev_attr,
991 	.class		= &dm81xx_mmc_class,
992 };
993 
994 static struct omap_hwmod_ocp_if dm814x_alwon_l3_med__mmc3 = {
995 	.master		= &dm81xx_alwon_l3_med_hwmod,
996 	.slave		= &dm814x_mmc3_hwmod,
997 	.clk		= "sysclk4_ck",
998 	.user		= OCP_USER_MPU,
999 };
1000 
1001 static struct omap_hwmod dm816x_mmc1_hwmod = {
1002 	.name		= "mmc1",
1003 	.clkdm_name	= "alwon_l3s_clkdm",
1004 	.opt_clks	= dm81xx_mmc_opt_clks,
1005 	.opt_clks_cnt	= ARRAY_SIZE(dm81xx_mmc_opt_clks),
1006 	.main_clk	= "sysclk10_ck",
1007 	.prcm		= {
1008 		.omap4 = {
1009 			.clkctrl_offs = DM816X_CM_ALWON_SDIO_CLKCTRL,
1010 			.modulemode = MODULEMODE_SWCTRL,
1011 		},
1012 	},
1013 	.dev_attr	= &mmc_dev_attr,
1014 	.class		= &dm81xx_mmc_class,
1015 };
1016 
1017 static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = {
1018 	.master		= &dm81xx_l4_ls_hwmod,
1019 	.slave		= &dm816x_mmc1_hwmod,
1020 	.clk		= "sysclk6_ck",
1021 	.user		= OCP_USER_MPU,
1022 	.flags		= OMAP_FIREWALL_L4
1023 };
1024 
1025 static struct omap_hwmod_class_sysconfig dm816x_mcspi_sysc = {
1026 	.rev_offs	= 0x0,
1027 	.sysc_offs	= 0x110,
1028 	.syss_offs	= 0x114,
1029 	.sysc_flags	= SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1030 				SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1031 				SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
1032 	.idlemodes	= SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1033 	.sysc_fields	= &omap_hwmod_sysc_type1,
1034 };
1035 
1036 static struct omap_hwmod_class dm816x_mcspi_class = {
1037 	.name = "mcspi",
1038 	.sysc = &dm816x_mcspi_sysc,
1039 };
1040 
1041 static struct omap_hwmod dm81xx_mcspi1_hwmod = {
1042 	.name		= "mcspi1",
1043 	.clkdm_name	= "alwon_l3s_clkdm",
1044 	.main_clk	= "sysclk10_ck",
1045 	.prcm		= {
1046 		.omap4 = {
1047 			.clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
1048 			.modulemode = MODULEMODE_SWCTRL,
1049 		},
1050 	},
1051 	.class		= &dm816x_mcspi_class,
1052 };
1053 
1054 static struct omap_hwmod dm81xx_mcspi2_hwmod = {
1055 	.name		= "mcspi2",
1056 	.clkdm_name	= "alwon_l3s_clkdm",
1057 	.main_clk	= "sysclk10_ck",
1058 	.prcm		= {
1059 		.omap4 = {
1060 			.clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
1061 			.modulemode = MODULEMODE_SWCTRL,
1062 		},
1063 	},
1064 	.class		= &dm816x_mcspi_class,
1065 };
1066 
1067 static struct omap_hwmod dm81xx_mcspi3_hwmod = {
1068 	.name		= "mcspi3",
1069 	.clkdm_name	= "alwon_l3s_clkdm",
1070 	.main_clk	= "sysclk10_ck",
1071 	.prcm		= {
1072 		.omap4 = {
1073 			.clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
1074 			.modulemode = MODULEMODE_SWCTRL,
1075 		},
1076 	},
1077 	.class		= &dm816x_mcspi_class,
1078 };
1079 
1080 static struct omap_hwmod dm81xx_mcspi4_hwmod = {
1081 	.name		= "mcspi4",
1082 	.clkdm_name	= "alwon_l3s_clkdm",
1083 	.main_clk	= "sysclk10_ck",
1084 	.prcm		= {
1085 		.omap4 = {
1086 			.clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
1087 			.modulemode = MODULEMODE_SWCTRL,
1088 		},
1089 	},
1090 	.class		= &dm816x_mcspi_class,
1091 };
1092 
1093 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = {
1094 	.master		= &dm81xx_l4_ls_hwmod,
1095 	.slave		= &dm81xx_mcspi1_hwmod,
1096 	.clk		= "sysclk6_ck",
1097 	.user		= OCP_USER_MPU,
1098 };
1099 
1100 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi2 = {
1101 	.master		= &dm81xx_l4_ls_hwmod,
1102 	.slave		= &dm81xx_mcspi2_hwmod,
1103 	.clk		= "sysclk6_ck",
1104 	.user		= OCP_USER_MPU,
1105 };
1106 
1107 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi3 = {
1108 	.master		= &dm81xx_l4_ls_hwmod,
1109 	.slave		= &dm81xx_mcspi3_hwmod,
1110 	.clk		= "sysclk6_ck",
1111 	.user		= OCP_USER_MPU,
1112 };
1113 
1114 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi4 = {
1115 	.master		= &dm81xx_l4_ls_hwmod,
1116 	.slave		= &dm81xx_mcspi4_hwmod,
1117 	.clk		= "sysclk6_ck",
1118 	.user		= OCP_USER_MPU,
1119 };
1120 
1121 static struct omap_hwmod_class_sysconfig dm81xx_mailbox_sysc = {
1122 	.rev_offs	= 0x000,
1123 	.sysc_offs	= 0x010,
1124 	.syss_offs	= 0x014,
1125 	.sysc_flags	= SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1126 				SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE,
1127 	.idlemodes	= SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1128 	.sysc_fields	= &omap_hwmod_sysc_type1,
1129 };
1130 
1131 static struct omap_hwmod_class dm81xx_mailbox_hwmod_class = {
1132 	.name = "mailbox",
1133 	.sysc = &dm81xx_mailbox_sysc,
1134 };
1135 
1136 static struct omap_hwmod dm81xx_mailbox_hwmod = {
1137 	.name		= "mailbox",
1138 	.clkdm_name	= "alwon_l3s_clkdm",
1139 	.class		= &dm81xx_mailbox_hwmod_class,
1140 	.main_clk	= "sysclk6_ck",
1141 	.prcm		= {
1142 		.omap4 = {
1143 			.clkctrl_offs = DM81XX_CM_ALWON_MAILBOX_CLKCTRL,
1144 			.modulemode = MODULEMODE_SWCTRL,
1145 		},
1146 	},
1147 };
1148 
1149 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mailbox = {
1150 	.master		= &dm81xx_l4_ls_hwmod,
1151 	.slave		= &dm81xx_mailbox_hwmod,
1152 	.clk		= "sysclk6_ck",
1153 	.user		= OCP_USER_MPU,
1154 };
1155 
1156 static struct omap_hwmod_class_sysconfig dm81xx_spinbox_sysc = {
1157 	.rev_offs	= 0x000,
1158 	.sysc_offs	= 0x010,
1159 	.syss_offs	= 0x014,
1160 	.sysc_flags	= SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1161 				SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE,
1162 	.idlemodes	= SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1163 	.sysc_fields	= &omap_hwmod_sysc_type1,
1164 };
1165 
1166 static struct omap_hwmod_class dm81xx_spinbox_hwmod_class = {
1167 	.name = "spinbox",
1168 	.sysc = &dm81xx_spinbox_sysc,
1169 };
1170 
1171 static struct omap_hwmod dm81xx_spinbox_hwmod = {
1172 	.name		= "spinbox",
1173 	.clkdm_name	= "alwon_l3s_clkdm",
1174 	.class		= &dm81xx_spinbox_hwmod_class,
1175 	.main_clk	= "sysclk6_ck",
1176 	.prcm		= {
1177 		.omap4 = {
1178 			.clkctrl_offs = DM81XX_CM_ALWON_SPINBOX_CLKCTRL,
1179 			.modulemode = MODULEMODE_SWCTRL,
1180 		},
1181 	},
1182 };
1183 
1184 static struct omap_hwmod_ocp_if dm81xx_l4_ls__spinbox = {
1185 	.master		= &dm81xx_l4_ls_hwmod,
1186 	.slave		= &dm81xx_spinbox_hwmod,
1187 	.clk		= "sysclk6_ck",
1188 	.user		= OCP_USER_MPU,
1189 };
1190 
1191 /*
1192  * REVISIT: Test and enable the following once clocks work:
1193  * dm81xx_l4_ls__mailbox
1194  *
1195  * Also note that some devices share a single clkctrl_offs..
1196  * For example, i2c1 and 3 share one, and i2c2 and 4 share one.
1197  */
1198 static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
1199 	&dm814x_mpu__alwon_l3_slow,
1200 	&dm814x_mpu__alwon_l3_med,
1201 	&dm81xx_alwon_l3_slow__l4_ls,
1202 	&dm81xx_alwon_l3_slow__l4_hs,
1203 	&dm81xx_l4_ls__uart1,
1204 	&dm81xx_l4_ls__uart2,
1205 	&dm81xx_l4_ls__uart3,
1206 	&dm81xx_l4_ls__wd_timer1,
1207 	&dm81xx_l4_ls__i2c1,
1208 	&dm81xx_l4_ls__i2c2,
1209 	&dm81xx_l4_ls__gpio1,
1210 	&dm81xx_l4_ls__gpio2,
1211 	&dm81xx_l4_ls__gpio3,
1212 	&dm81xx_l4_ls__gpio4,
1213 	&dm81xx_l4_ls__elm,
1214 	&dm81xx_l4_ls__mcspi1,
1215 	&dm81xx_l4_ls__mcspi2,
1216 	&dm81xx_l4_ls__mcspi3,
1217 	&dm81xx_l4_ls__mcspi4,
1218 	&dm814x_l4_ls__mmc1,
1219 	&dm814x_l4_ls__mmc2,
1220 	&ti81xx_l4_ls__rtc,
1221 	&dm81xx_alwon_l3_slow__gpmc,
1222 	&dm814x_default_l3_slow__usbss,
1223 	&dm814x_alwon_l3_med__mmc3,
1224 	NULL,
1225 };
1226 
1227 int __init dm814x_hwmod_init(void)
1228 {
1229 	omap_hwmod_init();
1230 	return omap_hwmod_register_links(dm814x_hwmod_ocp_ifs);
1231 }
1232 
1233 static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
1234 	&dm816x_mpu__alwon_l3_slow,
1235 	&dm816x_mpu__alwon_l3_med,
1236 	&dm81xx_alwon_l3_slow__l4_ls,
1237 	&dm81xx_alwon_l3_slow__l4_hs,
1238 	&dm81xx_l4_ls__uart1,
1239 	&dm81xx_l4_ls__uart2,
1240 	&dm81xx_l4_ls__uart3,
1241 	&dm81xx_l4_ls__wd_timer1,
1242 	&dm81xx_l4_ls__i2c1,
1243 	&dm81xx_l4_ls__i2c2,
1244 	&dm81xx_l4_ls__gpio1,
1245 	&dm81xx_l4_ls__gpio2,
1246 	&dm81xx_l4_ls__elm,
1247 	&ti81xx_l4_ls__rtc,
1248 	&dm816x_l4_ls__mmc1,
1249 	&dm816x_l4_ls__timer3,
1250 	&dm816x_l4_ls__timer4,
1251 	&dm816x_l4_ls__timer5,
1252 	&dm816x_l4_ls__timer6,
1253 	&dm816x_l4_ls__timer7,
1254 	&dm81xx_l4_ls__mcspi1,
1255 	&dm81xx_l4_ls__mailbox,
1256 	&dm81xx_l4_ls__spinbox,
1257 	&dm81xx_l4_hs__emac0,
1258 	&dm81xx_emac0__mdio,
1259 	&dm816x_l4_hs__emac1,
1260 	&dm81xx_l4_hs__sata,
1261 	&dm81xx_alwon_l3_slow__gpmc,
1262 	&dm816x_default_l3_slow__usbss,
1263 	NULL,
1264 };
1265 
1266 int __init dm816x_hwmod_init(void)
1267 {
1268 	omap_hwmod_init();
1269 	return omap_hwmod_register_links(dm816x_hwmod_ocp_ifs);
1270 }
1271