1 /* 2 * DM81xx hwmod data. 3 * 4 * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/ 5 * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/ 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation version 2. 10 * 11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 12 * kind, whether express or implied; without even the implied warranty 13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 */ 17 18 #include <linux/platform_data/gpio-omap.h> 19 #include <linux/platform_data/hsmmc-omap.h> 20 #include <linux/platform_data/spi-omap2-mcspi.h> 21 #include <plat/dmtimer.h> 22 23 #include "omap_hwmod_common_data.h" 24 #include "cm81xx.h" 25 #include "ti81xx.h" 26 #include "wd_timer.h" 27 28 /* 29 * DM816X hardware modules integration data 30 * 31 * Note: This is incomplete and at present, not generated from h/w database. 32 */ 33 34 /* 35 * Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS" 36 * also dm816x TRM 18.7.17 CM_ALWON device register values minus 0x1400. 37 */ 38 #define DM81XX_CM_ALWON_MCASP0_CLKCTRL 0x140 39 #define DM81XX_CM_ALWON_MCASP1_CLKCTRL 0x144 40 #define DM81XX_CM_ALWON_MCASP2_CLKCTRL 0x148 41 #define DM81XX_CM_ALWON_MCBSP_CLKCTRL 0x14c 42 #define DM81XX_CM_ALWON_UART_0_CLKCTRL 0x150 43 #define DM81XX_CM_ALWON_UART_1_CLKCTRL 0x154 44 #define DM81XX_CM_ALWON_UART_2_CLKCTRL 0x158 45 #define DM81XX_CM_ALWON_GPIO_0_CLKCTRL 0x15c 46 #define DM81XX_CM_ALWON_GPIO_1_CLKCTRL 0x160 47 #define DM81XX_CM_ALWON_I2C_0_CLKCTRL 0x164 48 #define DM81XX_CM_ALWON_I2C_1_CLKCTRL 0x168 49 #define DM81XX_CM_ALWON_WDTIMER_CLKCTRL 0x18c 50 #define DM81XX_CM_ALWON_SPI_CLKCTRL 0x190 51 #define DM81XX_CM_ALWON_MAILBOX_CLKCTRL 0x194 52 #define DM81XX_CM_ALWON_SPINBOX_CLKCTRL 0x198 53 #define DM81XX_CM_ALWON_MMUDATA_CLKCTRL 0x19c 54 #define DM81XX_CM_ALWON_MMUCFG_CLKCTRL 0x1a8 55 #define DM81XX_CM_ALWON_CONTROL_CLKCTRL 0x1c4 56 #define DM81XX_CM_ALWON_GPMC_CLKCTRL 0x1d0 57 #define DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL 0x1d4 58 #define DM81XX_CM_ALWON_L3_CLKCTRL 0x1e4 59 #define DM81XX_CM_ALWON_L4HS_CLKCTRL 0x1e8 60 #define DM81XX_CM_ALWON_L4LS_CLKCTRL 0x1ec 61 #define DM81XX_CM_ALWON_RTC_CLKCTRL 0x1f0 62 #define DM81XX_CM_ALWON_TPCC_CLKCTRL 0x1f4 63 #define DM81XX_CM_ALWON_TPTC0_CLKCTRL 0x1f8 64 #define DM81XX_CM_ALWON_TPTC1_CLKCTRL 0x1fc 65 #define DM81XX_CM_ALWON_TPTC2_CLKCTRL 0x200 66 #define DM81XX_CM_ALWON_TPTC3_CLKCTRL 0x204 67 68 /* Registers specific to dm814x */ 69 #define DM814X_CM_ALWON_MCASP_3_4_5_CLKCTRL 0x16c 70 #define DM814X_CM_ALWON_ATL_CLKCTRL 0x170 71 #define DM814X_CM_ALWON_MLB_CLKCTRL 0x174 72 #define DM814X_CM_ALWON_PATA_CLKCTRL 0x178 73 #define DM814X_CM_ALWON_UART_3_CLKCTRL 0x180 74 #define DM814X_CM_ALWON_UART_4_CLKCTRL 0x184 75 #define DM814X_CM_ALWON_UART_5_CLKCTRL 0x188 76 #define DM814X_CM_ALWON_OCM_0_CLKCTRL 0x1b4 77 #define DM814X_CM_ALWON_VCP_CLKCTRL 0x1b8 78 #define DM814X_CM_ALWON_MPU_CLKCTRL 0x1dc 79 #define DM814X_CM_ALWON_DEBUGSS_CLKCTRL 0x1e0 80 #define DM814X_CM_ALWON_DCAN_0_1_CLKCTRL 0x218 81 #define DM814X_CM_ALWON_MMCHS_0_CLKCTRL 0x21c 82 #define DM814X_CM_ALWON_MMCHS_1_CLKCTRL 0x220 83 #define DM814X_CM_ALWON_MMCHS_2_CLKCTRL 0x224 84 #define DM814X_CM_ALWON_CUST_EFUSE_CLKCTRL 0x228 85 86 /* Registers specific to dm816x */ 87 #define DM816X_DM_ALWON_BASE 0x1400 88 #define DM816X_CM_ALWON_TIMER_1_CLKCTRL (0x1570 - DM816X_DM_ALWON_BASE) 89 #define DM816X_CM_ALWON_TIMER_2_CLKCTRL (0x1574 - DM816X_DM_ALWON_BASE) 90 #define DM816X_CM_ALWON_TIMER_3_CLKCTRL (0x1578 - DM816X_DM_ALWON_BASE) 91 #define DM816X_CM_ALWON_TIMER_4_CLKCTRL (0x157c - DM816X_DM_ALWON_BASE) 92 #define DM816X_CM_ALWON_TIMER_5_CLKCTRL (0x1580 - DM816X_DM_ALWON_BASE) 93 #define DM816X_CM_ALWON_TIMER_6_CLKCTRL (0x1584 - DM816X_DM_ALWON_BASE) 94 #define DM816X_CM_ALWON_TIMER_7_CLKCTRL (0x1588 - DM816X_DM_ALWON_BASE) 95 #define DM816X_CM_ALWON_SDIO_CLKCTRL (0x15b0 - DM816X_DM_ALWON_BASE) 96 #define DM816X_CM_ALWON_OCMC_0_CLKCTRL (0x15b4 - DM816X_DM_ALWON_BASE) 97 #define DM816X_CM_ALWON_OCMC_1_CLKCTRL (0x15b8 - DM816X_DM_ALWON_BASE) 98 #define DM816X_CM_ALWON_ETHERNET_1_CLKCTRL (0x15d8 - DM816X_DM_ALWON_BASE) 99 #define DM816X_CM_ALWON_MPU_CLKCTRL (0x15dc - DM816X_DM_ALWON_BASE) 100 #define DM816X_CM_ALWON_SR_0_CLKCTRL (0x1608 - DM816X_DM_ALWON_BASE) 101 #define DM816X_CM_ALWON_SR_1_CLKCTRL (0x160c - DM816X_DM_ALWON_BASE) 102 103 /* 104 * The default .clkctrl_offs field is offset from CM_DEFAULT, that's 105 * TRM 18.7.6 CM_DEFAULT device register values minus 0x500 106 */ 107 #define DM81XX_CM_DEFAULT_OFFSET 0x500 108 #define DM81XX_CM_DEFAULT_USB_CLKCTRL (0x558 - DM81XX_CM_DEFAULT_OFFSET) 109 #define DM81XX_CM_DEFAULT_SATA_CLKCTRL (0x560 - DM81XX_CM_DEFAULT_OFFSET) 110 111 /* L3 Interconnect entries clocked at 125, 250 and 500MHz */ 112 static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = { 113 .name = "alwon_l3_slow", 114 .clkdm_name = "alwon_l3s_clkdm", 115 .class = &l3_hwmod_class, 116 .flags = HWMOD_NO_IDLEST, 117 }; 118 119 static struct omap_hwmod dm81xx_default_l3_slow_hwmod = { 120 .name = "default_l3_slow", 121 .clkdm_name = "default_l3_slow_clkdm", 122 .class = &l3_hwmod_class, 123 .flags = HWMOD_NO_IDLEST, 124 }; 125 126 static struct omap_hwmod dm81xx_alwon_l3_med_hwmod = { 127 .name = "l3_med", 128 .clkdm_name = "alwon_l3_med_clkdm", 129 .class = &l3_hwmod_class, 130 .flags = HWMOD_NO_IDLEST, 131 }; 132 133 static struct omap_hwmod dm81xx_alwon_l3_fast_hwmod = { 134 .name = "l3_fast", 135 .clkdm_name = "alwon_l3_fast_clkdm", 136 .class = &l3_hwmod_class, 137 .flags = HWMOD_NO_IDLEST, 138 }; 139 140 /* 141 * L4 standard peripherals, see TRM table 1-12 for devices using this. 142 * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock. 143 */ 144 static struct omap_hwmod dm81xx_l4_ls_hwmod = { 145 .name = "l4_ls", 146 .clkdm_name = "alwon_l3s_clkdm", 147 .class = &l4_hwmod_class, 148 .flags = HWMOD_NO_IDLEST, 149 }; 150 151 /* 152 * L4 high-speed peripherals. For devices using this, please see the TRM 153 * table 1-13. On dm816x, only EMAC, MDIO and SATA use this. See also TRM 154 * table 1-73 for devices using 250MHz SYSCLK5 clock. 155 */ 156 static struct omap_hwmod dm81xx_l4_hs_hwmod = { 157 .name = "l4_hs", 158 .clkdm_name = "alwon_l3_med_clkdm", 159 .class = &l4_hwmod_class, 160 .flags = HWMOD_NO_IDLEST, 161 }; 162 163 /* L3 slow -> L4 ls peripheral interface running at 125MHz */ 164 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_ls = { 165 .master = &dm81xx_alwon_l3_slow_hwmod, 166 .slave = &dm81xx_l4_ls_hwmod, 167 .user = OCP_USER_MPU, 168 }; 169 170 /* L3 med -> L4 fast peripheral interface running at 250MHz */ 171 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_hs = { 172 .master = &dm81xx_alwon_l3_med_hwmod, 173 .slave = &dm81xx_l4_hs_hwmod, 174 .user = OCP_USER_MPU, 175 }; 176 177 /* MPU */ 178 static struct omap_hwmod dm814x_mpu_hwmod = { 179 .name = "mpu", 180 .clkdm_name = "alwon_l3s_clkdm", 181 .class = &mpu_hwmod_class, 182 .flags = HWMOD_INIT_NO_IDLE, 183 .main_clk = "mpu_ck", 184 .prcm = { 185 .omap4 = { 186 .clkctrl_offs = DM814X_CM_ALWON_MPU_CLKCTRL, 187 .modulemode = MODULEMODE_SWCTRL, 188 }, 189 }, 190 }; 191 192 static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_slow = { 193 .master = &dm814x_mpu_hwmod, 194 .slave = &dm81xx_alwon_l3_slow_hwmod, 195 .user = OCP_USER_MPU, 196 }; 197 198 /* L3 med peripheral interface running at 200MHz */ 199 static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_med = { 200 .master = &dm814x_mpu_hwmod, 201 .slave = &dm81xx_alwon_l3_med_hwmod, 202 .user = OCP_USER_MPU, 203 }; 204 205 static struct omap_hwmod dm816x_mpu_hwmod = { 206 .name = "mpu", 207 .clkdm_name = "alwon_mpu_clkdm", 208 .class = &mpu_hwmod_class, 209 .flags = HWMOD_INIT_NO_IDLE, 210 .main_clk = "mpu_ck", 211 .prcm = { 212 .omap4 = { 213 .clkctrl_offs = DM816X_CM_ALWON_MPU_CLKCTRL, 214 .modulemode = MODULEMODE_SWCTRL, 215 }, 216 }, 217 }; 218 219 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_slow = { 220 .master = &dm816x_mpu_hwmod, 221 .slave = &dm81xx_alwon_l3_slow_hwmod, 222 .user = OCP_USER_MPU, 223 }; 224 225 /* L3 med peripheral interface running at 250MHz */ 226 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med = { 227 .master = &dm816x_mpu_hwmod, 228 .slave = &dm81xx_alwon_l3_med_hwmod, 229 .user = OCP_USER_MPU, 230 }; 231 232 /* RTC */ 233 static struct omap_hwmod_class_sysconfig ti81xx_rtc_sysc = { 234 .rev_offs = 0x74, 235 .sysc_offs = 0x78, 236 .sysc_flags = SYSC_HAS_SIDLEMODE, 237 .idlemodes = SIDLE_FORCE | SIDLE_NO | 238 SIDLE_SMART | SIDLE_SMART_WKUP, 239 .sysc_fields = &omap_hwmod_sysc_type3, 240 }; 241 242 static struct omap_hwmod_class ti81xx_rtc_hwmod_class = { 243 .name = "rtc", 244 .sysc = &ti81xx_rtc_sysc, 245 }; 246 247 static struct omap_hwmod ti81xx_rtc_hwmod = { 248 .name = "rtc", 249 .class = &ti81xx_rtc_hwmod_class, 250 .clkdm_name = "alwon_l3s_clkdm", 251 .flags = HWMOD_NO_IDLEST, 252 .main_clk = "sysclk18_ck", 253 .prcm = { 254 .omap4 = { 255 .clkctrl_offs = DM81XX_CM_ALWON_RTC_CLKCTRL, 256 .modulemode = MODULEMODE_SWCTRL, 257 }, 258 }, 259 }; 260 261 static struct omap_hwmod_ocp_if ti81xx_l4_ls__rtc = { 262 .master = &dm81xx_l4_ls_hwmod, 263 .slave = &ti81xx_rtc_hwmod, 264 .clk = "sysclk6_ck", 265 .user = OCP_USER_MPU, 266 }; 267 268 /* UART common */ 269 static struct omap_hwmod_class_sysconfig uart_sysc = { 270 .rev_offs = 0x50, 271 .sysc_offs = 0x54, 272 .syss_offs = 0x58, 273 .sysc_flags = SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | 274 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 275 SYSS_HAS_RESET_STATUS, 276 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 277 MSTANDBY_SMART_WKUP, 278 .sysc_fields = &omap_hwmod_sysc_type1, 279 }; 280 281 static struct omap_hwmod_class uart_class = { 282 .name = "uart", 283 .sysc = &uart_sysc, 284 }; 285 286 static struct omap_hwmod dm81xx_uart1_hwmod = { 287 .name = "uart1", 288 .clkdm_name = "alwon_l3s_clkdm", 289 .main_clk = "sysclk10_ck", 290 .prcm = { 291 .omap4 = { 292 .clkctrl_offs = DM81XX_CM_ALWON_UART_0_CLKCTRL, 293 .modulemode = MODULEMODE_SWCTRL, 294 }, 295 }, 296 .class = &uart_class, 297 .flags = DEBUG_TI81XXUART1_FLAGS, 298 }; 299 300 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart1 = { 301 .master = &dm81xx_l4_ls_hwmod, 302 .slave = &dm81xx_uart1_hwmod, 303 .clk = "sysclk6_ck", 304 .user = OCP_USER_MPU, 305 }; 306 307 static struct omap_hwmod dm81xx_uart2_hwmod = { 308 .name = "uart2", 309 .clkdm_name = "alwon_l3s_clkdm", 310 .main_clk = "sysclk10_ck", 311 .prcm = { 312 .omap4 = { 313 .clkctrl_offs = DM81XX_CM_ALWON_UART_1_CLKCTRL, 314 .modulemode = MODULEMODE_SWCTRL, 315 }, 316 }, 317 .class = &uart_class, 318 .flags = DEBUG_TI81XXUART2_FLAGS, 319 }; 320 321 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart2 = { 322 .master = &dm81xx_l4_ls_hwmod, 323 .slave = &dm81xx_uart2_hwmod, 324 .clk = "sysclk6_ck", 325 .user = OCP_USER_MPU, 326 }; 327 328 static struct omap_hwmod dm81xx_uart3_hwmod = { 329 .name = "uart3", 330 .clkdm_name = "alwon_l3s_clkdm", 331 .main_clk = "sysclk10_ck", 332 .prcm = { 333 .omap4 = { 334 .clkctrl_offs = DM81XX_CM_ALWON_UART_2_CLKCTRL, 335 .modulemode = MODULEMODE_SWCTRL, 336 }, 337 }, 338 .class = &uart_class, 339 .flags = DEBUG_TI81XXUART3_FLAGS, 340 }; 341 342 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart3 = { 343 .master = &dm81xx_l4_ls_hwmod, 344 .slave = &dm81xx_uart3_hwmod, 345 .clk = "sysclk6_ck", 346 .user = OCP_USER_MPU, 347 }; 348 349 static struct omap_hwmod_class_sysconfig wd_timer_sysc = { 350 .rev_offs = 0x0, 351 .sysc_offs = 0x10, 352 .syss_offs = 0x14, 353 .sysc_flags = SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | 354 SYSS_HAS_RESET_STATUS, 355 .sysc_fields = &omap_hwmod_sysc_type1, 356 }; 357 358 static struct omap_hwmod_class wd_timer_class = { 359 .name = "wd_timer", 360 .sysc = &wd_timer_sysc, 361 .pre_shutdown = &omap2_wd_timer_disable, 362 .reset = &omap2_wd_timer_reset, 363 }; 364 365 static struct omap_hwmod dm81xx_wd_timer_hwmod = { 366 .name = "wd_timer", 367 .clkdm_name = "alwon_l3s_clkdm", 368 .main_clk = "sysclk18_ck", 369 .flags = HWMOD_NO_IDLEST, 370 .prcm = { 371 .omap4 = { 372 .clkctrl_offs = DM81XX_CM_ALWON_WDTIMER_CLKCTRL, 373 .modulemode = MODULEMODE_SWCTRL, 374 }, 375 }, 376 .class = &wd_timer_class, 377 }; 378 379 static struct omap_hwmod_ocp_if dm81xx_l4_ls__wd_timer1 = { 380 .master = &dm81xx_l4_ls_hwmod, 381 .slave = &dm81xx_wd_timer_hwmod, 382 .clk = "sysclk6_ck", 383 .user = OCP_USER_MPU, 384 }; 385 386 /* I2C common */ 387 static struct omap_hwmod_class_sysconfig i2c_sysc = { 388 .rev_offs = 0x0, 389 .sysc_offs = 0x10, 390 .syss_offs = 0x90, 391 .sysc_flags = SYSC_HAS_SIDLEMODE | 392 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 393 SYSC_HAS_AUTOIDLE, 394 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 395 .sysc_fields = &omap_hwmod_sysc_type1, 396 }; 397 398 static struct omap_hwmod_class i2c_class = { 399 .name = "i2c", 400 .sysc = &i2c_sysc, 401 }; 402 403 static struct omap_hwmod dm81xx_i2c1_hwmod = { 404 .name = "i2c1", 405 .clkdm_name = "alwon_l3s_clkdm", 406 .main_clk = "sysclk10_ck", 407 .prcm = { 408 .omap4 = { 409 .clkctrl_offs = DM81XX_CM_ALWON_I2C_0_CLKCTRL, 410 .modulemode = MODULEMODE_SWCTRL, 411 }, 412 }, 413 .class = &i2c_class, 414 }; 415 416 static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c1 = { 417 .master = &dm81xx_l4_ls_hwmod, 418 .slave = &dm81xx_i2c1_hwmod, 419 .clk = "sysclk6_ck", 420 .user = OCP_USER_MPU, 421 }; 422 423 static struct omap_hwmod dm81xx_i2c2_hwmod = { 424 .name = "i2c2", 425 .clkdm_name = "alwon_l3s_clkdm", 426 .main_clk = "sysclk10_ck", 427 .prcm = { 428 .omap4 = { 429 .clkctrl_offs = DM81XX_CM_ALWON_I2C_1_CLKCTRL, 430 .modulemode = MODULEMODE_SWCTRL, 431 }, 432 }, 433 .class = &i2c_class, 434 }; 435 436 static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = { 437 .rev_offs = 0x0000, 438 .sysc_offs = 0x0010, 439 .syss_offs = 0x0014, 440 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 441 SYSC_HAS_SOFTRESET | 442 SYSS_HAS_RESET_STATUS, 443 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 444 .sysc_fields = &omap_hwmod_sysc_type1, 445 }; 446 447 static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = { 448 .master = &dm81xx_l4_ls_hwmod, 449 .slave = &dm81xx_i2c2_hwmod, 450 .clk = "sysclk6_ck", 451 .user = OCP_USER_MPU, 452 }; 453 454 static struct omap_hwmod_class dm81xx_elm_hwmod_class = { 455 .name = "elm", 456 .sysc = &dm81xx_elm_sysc, 457 }; 458 459 static struct omap_hwmod dm81xx_elm_hwmod = { 460 .name = "elm", 461 .clkdm_name = "alwon_l3s_clkdm", 462 .class = &dm81xx_elm_hwmod_class, 463 .main_clk = "sysclk6_ck", 464 }; 465 466 static struct omap_hwmod_ocp_if dm81xx_l4_ls__elm = { 467 .master = &dm81xx_l4_ls_hwmod, 468 .slave = &dm81xx_elm_hwmod, 469 .clk = "sysclk6_ck", 470 .user = OCP_USER_MPU, 471 }; 472 473 static struct omap_hwmod_class_sysconfig dm81xx_gpio_sysc = { 474 .rev_offs = 0x0000, 475 .sysc_offs = 0x0010, 476 .syss_offs = 0x0114, 477 .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | 478 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 479 SYSS_HAS_RESET_STATUS, 480 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 481 SIDLE_SMART_WKUP, 482 .sysc_fields = &omap_hwmod_sysc_type1, 483 }; 484 485 static struct omap_hwmod_class dm81xx_gpio_hwmod_class = { 486 .name = "gpio", 487 .sysc = &dm81xx_gpio_sysc, 488 .rev = 2, 489 }; 490 491 static struct omap_gpio_dev_attr gpio_dev_attr = { 492 .bank_width = 32, 493 .dbck_flag = true, 494 }; 495 496 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { 497 { .role = "dbclk", .clk = "sysclk18_ck" }, 498 }; 499 500 static struct omap_hwmod dm81xx_gpio1_hwmod = { 501 .name = "gpio1", 502 .clkdm_name = "alwon_l3s_clkdm", 503 .class = &dm81xx_gpio_hwmod_class, 504 .main_clk = "sysclk6_ck", 505 .prcm = { 506 .omap4 = { 507 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_0_CLKCTRL, 508 .modulemode = MODULEMODE_SWCTRL, 509 }, 510 }, 511 .opt_clks = gpio1_opt_clks, 512 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), 513 .dev_attr = &gpio_dev_attr, 514 }; 515 516 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = { 517 .master = &dm81xx_l4_ls_hwmod, 518 .slave = &dm81xx_gpio1_hwmod, 519 .clk = "sysclk6_ck", 520 .user = OCP_USER_MPU, 521 }; 522 523 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { 524 { .role = "dbclk", .clk = "sysclk18_ck" }, 525 }; 526 527 static struct omap_hwmod dm81xx_gpio2_hwmod = { 528 .name = "gpio2", 529 .clkdm_name = "alwon_l3s_clkdm", 530 .class = &dm81xx_gpio_hwmod_class, 531 .main_clk = "sysclk6_ck", 532 .prcm = { 533 .omap4 = { 534 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL, 535 .modulemode = MODULEMODE_SWCTRL, 536 }, 537 }, 538 .opt_clks = gpio2_opt_clks, 539 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), 540 .dev_attr = &gpio_dev_attr, 541 }; 542 543 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = { 544 .master = &dm81xx_l4_ls_hwmod, 545 .slave = &dm81xx_gpio2_hwmod, 546 .clk = "sysclk6_ck", 547 .user = OCP_USER_MPU, 548 }; 549 550 static struct omap_hwmod_class_sysconfig dm81xx_gpmc_sysc = { 551 .rev_offs = 0x0, 552 .sysc_offs = 0x10, 553 .syss_offs = 0x14, 554 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 555 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, 556 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 557 .sysc_fields = &omap_hwmod_sysc_type1, 558 }; 559 560 static struct omap_hwmod_class dm81xx_gpmc_hwmod_class = { 561 .name = "gpmc", 562 .sysc = &dm81xx_gpmc_sysc, 563 }; 564 565 static struct omap_hwmod dm81xx_gpmc_hwmod = { 566 .name = "gpmc", 567 .clkdm_name = "alwon_l3s_clkdm", 568 .class = &dm81xx_gpmc_hwmod_class, 569 .main_clk = "sysclk6_ck", 570 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ 571 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS, 572 .prcm = { 573 .omap4 = { 574 .clkctrl_offs = DM81XX_CM_ALWON_GPMC_CLKCTRL, 575 .modulemode = MODULEMODE_SWCTRL, 576 }, 577 }, 578 }; 579 580 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = { 581 .master = &dm81xx_alwon_l3_slow_hwmod, 582 .slave = &dm81xx_gpmc_hwmod, 583 .user = OCP_USER_MPU, 584 }; 585 586 /* USB needs udelay 1 after reset at least on hp t410, use 2 for margin */ 587 static struct omap_hwmod_class_sysconfig dm81xx_usbhsotg_sysc = { 588 .rev_offs = 0x0, 589 .sysc_offs = 0x10, 590 .srst_udelay = 2, 591 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | 592 SYSC_HAS_SOFTRESET, 593 .idlemodes = SIDLE_SMART | MSTANDBY_FORCE | MSTANDBY_SMART, 594 .sysc_fields = &omap_hwmod_sysc_type2, 595 }; 596 597 static struct omap_hwmod_class dm81xx_usbotg_class = { 598 .name = "usbotg", 599 .sysc = &dm81xx_usbhsotg_sysc, 600 }; 601 602 static struct omap_hwmod dm814x_usbss_hwmod = { 603 .name = "usb_otg_hs", 604 .clkdm_name = "default_l3_slow_clkdm", 605 .main_clk = "pll260dcoclkldo", /* 481c5260.adpll.dcoclkldo */ 606 .prcm = { 607 .omap4 = { 608 .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL, 609 .modulemode = MODULEMODE_SWCTRL, 610 }, 611 }, 612 .class = &dm81xx_usbotg_class, 613 }; 614 615 static struct omap_hwmod_ocp_if dm814x_default_l3_slow__usbss = { 616 .master = &dm81xx_default_l3_slow_hwmod, 617 .slave = &dm814x_usbss_hwmod, 618 .clk = "sysclk6_ck", 619 .user = OCP_USER_MPU, 620 }; 621 622 static struct omap_hwmod dm816x_usbss_hwmod = { 623 .name = "usb_otg_hs", 624 .clkdm_name = "default_l3_slow_clkdm", 625 .main_clk = "sysclk6_ck", 626 .prcm = { 627 .omap4 = { 628 .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL, 629 .modulemode = MODULEMODE_SWCTRL, 630 }, 631 }, 632 .class = &dm81xx_usbotg_class, 633 }; 634 635 static struct omap_hwmod_ocp_if dm816x_default_l3_slow__usbss = { 636 .master = &dm81xx_default_l3_slow_hwmod, 637 .slave = &dm816x_usbss_hwmod, 638 .clk = "sysclk6_ck", 639 .user = OCP_USER_MPU, 640 }; 641 642 static struct omap_hwmod_class_sysconfig dm816x_timer_sysc = { 643 .rev_offs = 0x0000, 644 .sysc_offs = 0x0010, 645 .syss_offs = 0x0014, 646 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET, 647 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 648 SIDLE_SMART_WKUP, 649 .sysc_fields = &omap_hwmod_sysc_type2, 650 }; 651 652 static struct omap_hwmod_class dm816x_timer_hwmod_class = { 653 .name = "timer", 654 .sysc = &dm816x_timer_sysc, 655 }; 656 657 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { 658 .timer_capability = OMAP_TIMER_ALWON, 659 }; 660 661 static struct omap_hwmod dm814x_timer1_hwmod = { 662 .name = "timer1", 663 .clkdm_name = "alwon_l3s_clkdm", 664 .main_clk = "timer1_fck", 665 .dev_attr = &capability_alwon_dev_attr, 666 .class = &dm816x_timer_hwmod_class, 667 .flags = HWMOD_NO_IDLEST, 668 }; 669 670 static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = { 671 .master = &dm81xx_l4_ls_hwmod, 672 .slave = &dm814x_timer1_hwmod, 673 .clk = "sysclk6_ck", 674 .user = OCP_USER_MPU, 675 }; 676 677 static struct omap_hwmod dm816x_timer1_hwmod = { 678 .name = "timer1", 679 .clkdm_name = "alwon_l3s_clkdm", 680 .main_clk = "timer1_fck", 681 .prcm = { 682 .omap4 = { 683 .clkctrl_offs = DM816X_CM_ALWON_TIMER_1_CLKCTRL, 684 .modulemode = MODULEMODE_SWCTRL, 685 }, 686 }, 687 .dev_attr = &capability_alwon_dev_attr, 688 .class = &dm816x_timer_hwmod_class, 689 }; 690 691 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = { 692 .master = &dm81xx_l4_ls_hwmod, 693 .slave = &dm816x_timer1_hwmod, 694 .clk = "sysclk6_ck", 695 .user = OCP_USER_MPU, 696 }; 697 698 static struct omap_hwmod dm814x_timer2_hwmod = { 699 .name = "timer2", 700 .clkdm_name = "alwon_l3s_clkdm", 701 .main_clk = "timer2_fck", 702 .dev_attr = &capability_alwon_dev_attr, 703 .class = &dm816x_timer_hwmod_class, 704 .flags = HWMOD_NO_IDLEST, 705 }; 706 707 static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = { 708 .master = &dm81xx_l4_ls_hwmod, 709 .slave = &dm814x_timer2_hwmod, 710 .clk = "sysclk6_ck", 711 .user = OCP_USER_MPU, 712 }; 713 714 static struct omap_hwmod dm816x_timer2_hwmod = { 715 .name = "timer2", 716 .clkdm_name = "alwon_l3s_clkdm", 717 .main_clk = "timer2_fck", 718 .prcm = { 719 .omap4 = { 720 .clkctrl_offs = DM816X_CM_ALWON_TIMER_2_CLKCTRL, 721 .modulemode = MODULEMODE_SWCTRL, 722 }, 723 }, 724 .dev_attr = &capability_alwon_dev_attr, 725 .class = &dm816x_timer_hwmod_class, 726 }; 727 728 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = { 729 .master = &dm81xx_l4_ls_hwmod, 730 .slave = &dm816x_timer2_hwmod, 731 .clk = "sysclk6_ck", 732 .user = OCP_USER_MPU, 733 }; 734 735 static struct omap_hwmod dm816x_timer3_hwmod = { 736 .name = "timer3", 737 .clkdm_name = "alwon_l3s_clkdm", 738 .main_clk = "timer3_fck", 739 .prcm = { 740 .omap4 = { 741 .clkctrl_offs = DM816X_CM_ALWON_TIMER_3_CLKCTRL, 742 .modulemode = MODULEMODE_SWCTRL, 743 }, 744 }, 745 .dev_attr = &capability_alwon_dev_attr, 746 .class = &dm816x_timer_hwmod_class, 747 }; 748 749 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer3 = { 750 .master = &dm81xx_l4_ls_hwmod, 751 .slave = &dm816x_timer3_hwmod, 752 .clk = "sysclk6_ck", 753 .user = OCP_USER_MPU, 754 }; 755 756 static struct omap_hwmod dm816x_timer4_hwmod = { 757 .name = "timer4", 758 .clkdm_name = "alwon_l3s_clkdm", 759 .main_clk = "timer4_fck", 760 .prcm = { 761 .omap4 = { 762 .clkctrl_offs = DM816X_CM_ALWON_TIMER_4_CLKCTRL, 763 .modulemode = MODULEMODE_SWCTRL, 764 }, 765 }, 766 .dev_attr = &capability_alwon_dev_attr, 767 .class = &dm816x_timer_hwmod_class, 768 }; 769 770 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer4 = { 771 .master = &dm81xx_l4_ls_hwmod, 772 .slave = &dm816x_timer4_hwmod, 773 .clk = "sysclk6_ck", 774 .user = OCP_USER_MPU, 775 }; 776 777 static struct omap_hwmod dm816x_timer5_hwmod = { 778 .name = "timer5", 779 .clkdm_name = "alwon_l3s_clkdm", 780 .main_clk = "timer5_fck", 781 .prcm = { 782 .omap4 = { 783 .clkctrl_offs = DM816X_CM_ALWON_TIMER_5_CLKCTRL, 784 .modulemode = MODULEMODE_SWCTRL, 785 }, 786 }, 787 .dev_attr = &capability_alwon_dev_attr, 788 .class = &dm816x_timer_hwmod_class, 789 }; 790 791 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer5 = { 792 .master = &dm81xx_l4_ls_hwmod, 793 .slave = &dm816x_timer5_hwmod, 794 .clk = "sysclk6_ck", 795 .user = OCP_USER_MPU, 796 }; 797 798 static struct omap_hwmod dm816x_timer6_hwmod = { 799 .name = "timer6", 800 .clkdm_name = "alwon_l3s_clkdm", 801 .main_clk = "timer6_fck", 802 .prcm = { 803 .omap4 = { 804 .clkctrl_offs = DM816X_CM_ALWON_TIMER_6_CLKCTRL, 805 .modulemode = MODULEMODE_SWCTRL, 806 }, 807 }, 808 .dev_attr = &capability_alwon_dev_attr, 809 .class = &dm816x_timer_hwmod_class, 810 }; 811 812 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer6 = { 813 .master = &dm81xx_l4_ls_hwmod, 814 .slave = &dm816x_timer6_hwmod, 815 .clk = "sysclk6_ck", 816 .user = OCP_USER_MPU, 817 }; 818 819 static struct omap_hwmod dm816x_timer7_hwmod = { 820 .name = "timer7", 821 .clkdm_name = "alwon_l3s_clkdm", 822 .main_clk = "timer7_fck", 823 .prcm = { 824 .omap4 = { 825 .clkctrl_offs = DM816X_CM_ALWON_TIMER_7_CLKCTRL, 826 .modulemode = MODULEMODE_SWCTRL, 827 }, 828 }, 829 .dev_attr = &capability_alwon_dev_attr, 830 .class = &dm816x_timer_hwmod_class, 831 }; 832 833 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = { 834 .master = &dm81xx_l4_ls_hwmod, 835 .slave = &dm816x_timer7_hwmod, 836 .clk = "sysclk6_ck", 837 .user = OCP_USER_MPU, 838 }; 839 840 /* CPSW on dm814x */ 841 static struct omap_hwmod_class_sysconfig dm814x_cpgmac_sysc = { 842 .rev_offs = 0x0, 843 .sysc_offs = 0x8, 844 .syss_offs = 0x4, 845 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | 846 SYSS_HAS_RESET_STATUS, 847 .idlemodes = SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE | 848 MSTANDBY_NO, 849 .sysc_fields = &omap_hwmod_sysc_type3, 850 }; 851 852 static struct omap_hwmod_class dm814x_cpgmac0_hwmod_class = { 853 .name = "cpgmac0", 854 .sysc = &dm814x_cpgmac_sysc, 855 }; 856 857 static struct omap_hwmod dm814x_cpgmac0_hwmod = { 858 .name = "cpgmac0", 859 .class = &dm814x_cpgmac0_hwmod_class, 860 .clkdm_name = "alwon_ethernet_clkdm", 861 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, 862 .main_clk = "cpsw_125mhz_gclk", 863 .prcm = { 864 .omap4 = { 865 .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL, 866 .modulemode = MODULEMODE_SWCTRL, 867 }, 868 }, 869 }; 870 871 static struct omap_hwmod_class dm814x_mdio_hwmod_class = { 872 .name = "davinci_mdio", 873 }; 874 875 static struct omap_hwmod dm814x_mdio_hwmod = { 876 .name = "davinci_mdio", 877 .class = &dm814x_mdio_hwmod_class, 878 .clkdm_name = "alwon_ethernet_clkdm", 879 .main_clk = "cpsw_125mhz_gclk", 880 }; 881 882 static struct omap_hwmod_ocp_if dm814x_l4_hs__cpgmac0 = { 883 .master = &dm81xx_l4_hs_hwmod, 884 .slave = &dm814x_cpgmac0_hwmod, 885 .clk = "cpsw_125mhz_gclk", 886 .user = OCP_USER_MPU, 887 }; 888 889 static struct omap_hwmod_ocp_if dm814x_cpgmac0__mdio = { 890 .master = &dm814x_cpgmac0_hwmod, 891 .slave = &dm814x_mdio_hwmod, 892 .user = OCP_USER_MPU, 893 .flags = HWMOD_NO_IDLEST, 894 }; 895 896 /* EMAC Ethernet */ 897 static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = { 898 .rev_offs = 0x0, 899 .sysc_offs = 0x4, 900 .sysc_flags = SYSC_HAS_SOFTRESET, 901 .sysc_fields = &omap_hwmod_sysc_type2, 902 }; 903 904 static struct omap_hwmod_class dm816x_emac_hwmod_class = { 905 .name = "emac", 906 .sysc = &dm816x_emac_sysc, 907 }; 908 909 /* 910 * On dm816x the MDIO is within EMAC0. As the MDIO driver is a separate 911 * driver probed before EMAC0, we let MDIO do the clock idling. 912 */ 913 static struct omap_hwmod dm816x_emac0_hwmod = { 914 .name = "emac0", 915 .clkdm_name = "alwon_ethernet_clkdm", 916 .class = &dm816x_emac_hwmod_class, 917 .flags = HWMOD_NO_IDLEST, 918 }; 919 920 static struct omap_hwmod_ocp_if dm81xx_l4_hs__emac0 = { 921 .master = &dm81xx_l4_hs_hwmod, 922 .slave = &dm816x_emac0_hwmod, 923 .clk = "sysclk5_ck", 924 .user = OCP_USER_MPU, 925 }; 926 927 static struct omap_hwmod_class dm81xx_mdio_hwmod_class = { 928 .name = "davinci_mdio", 929 .sysc = &dm816x_emac_sysc, 930 }; 931 932 static struct omap_hwmod dm81xx_emac0_mdio_hwmod = { 933 .name = "davinci_mdio", 934 .class = &dm81xx_mdio_hwmod_class, 935 .clkdm_name = "alwon_ethernet_clkdm", 936 .main_clk = "sysclk24_ck", 937 .flags = HWMOD_NO_IDLEST, 938 /* 939 * REVISIT: This should be moved to the emac0_hwmod 940 * once we have a better way to handle device slaves. 941 */ 942 .prcm = { 943 .omap4 = { 944 .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL, 945 .modulemode = MODULEMODE_SWCTRL, 946 }, 947 }, 948 }; 949 950 static struct omap_hwmod_ocp_if dm81xx_emac0__mdio = { 951 .master = &dm81xx_l4_hs_hwmod, 952 .slave = &dm81xx_emac0_mdio_hwmod, 953 .user = OCP_USER_MPU, 954 }; 955 956 static struct omap_hwmod dm816x_emac1_hwmod = { 957 .name = "emac1", 958 .clkdm_name = "alwon_ethernet_clkdm", 959 .main_clk = "sysclk24_ck", 960 .flags = HWMOD_NO_IDLEST, 961 .prcm = { 962 .omap4 = { 963 .clkctrl_offs = DM816X_CM_ALWON_ETHERNET_1_CLKCTRL, 964 .modulemode = MODULEMODE_SWCTRL, 965 }, 966 }, 967 .class = &dm816x_emac_hwmod_class, 968 }; 969 970 static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = { 971 .master = &dm81xx_l4_hs_hwmod, 972 .slave = &dm816x_emac1_hwmod, 973 .clk = "sysclk5_ck", 974 .user = OCP_USER_MPU, 975 }; 976 977 static struct omap_hwmod_class_sysconfig dm81xx_sata_sysc = { 978 .sysc_offs = 0x1100, 979 .sysc_flags = SYSC_HAS_SIDLEMODE, 980 .idlemodes = SIDLE_FORCE, 981 .sysc_fields = &omap_hwmod_sysc_type3, 982 }; 983 984 static struct omap_hwmod_class dm81xx_sata_hwmod_class = { 985 .name = "sata", 986 .sysc = &dm81xx_sata_sysc, 987 }; 988 989 static struct omap_hwmod dm81xx_sata_hwmod = { 990 .name = "sata", 991 .clkdm_name = "default_sata_clkdm", 992 .flags = HWMOD_NO_IDLEST, 993 .prcm = { 994 .omap4 = { 995 .clkctrl_offs = DM81XX_CM_DEFAULT_SATA_CLKCTRL, 996 .modulemode = MODULEMODE_SWCTRL, 997 }, 998 }, 999 .class = &dm81xx_sata_hwmod_class, 1000 }; 1001 1002 static struct omap_hwmod_ocp_if dm81xx_l4_hs__sata = { 1003 .master = &dm81xx_l4_hs_hwmod, 1004 .slave = &dm81xx_sata_hwmod, 1005 .clk = "sysclk5_ck", 1006 .user = OCP_USER_MPU, 1007 }; 1008 1009 static struct omap_hwmod_class_sysconfig dm81xx_mmc_sysc = { 1010 .rev_offs = 0x0, 1011 .sysc_offs = 0x110, 1012 .syss_offs = 0x114, 1013 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1014 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1015 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, 1016 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 1017 .sysc_fields = &omap_hwmod_sysc_type1, 1018 }; 1019 1020 static struct omap_hwmod_class dm81xx_mmc_class = { 1021 .name = "mmc", 1022 .sysc = &dm81xx_mmc_sysc, 1023 }; 1024 1025 static struct omap_hwmod_opt_clk dm81xx_mmc_opt_clks[] = { 1026 { .role = "dbck", .clk = "sysclk18_ck", }, 1027 }; 1028 1029 static struct omap_hsmmc_dev_attr mmc_dev_attr = { 1030 }; 1031 1032 static struct omap_hwmod dm814x_mmc1_hwmod = { 1033 .name = "mmc1", 1034 .clkdm_name = "alwon_l3s_clkdm", 1035 .opt_clks = dm81xx_mmc_opt_clks, 1036 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), 1037 .main_clk = "sysclk8_ck", 1038 .prcm = { 1039 .omap4 = { 1040 .clkctrl_offs = DM814X_CM_ALWON_MMCHS_0_CLKCTRL, 1041 .modulemode = MODULEMODE_SWCTRL, 1042 }, 1043 }, 1044 .dev_attr = &mmc_dev_attr, 1045 .class = &dm81xx_mmc_class, 1046 }; 1047 1048 static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc1 = { 1049 .master = &dm81xx_l4_ls_hwmod, 1050 .slave = &dm814x_mmc1_hwmod, 1051 .clk = "sysclk6_ck", 1052 .user = OCP_USER_MPU, 1053 .flags = OMAP_FIREWALL_L4 1054 }; 1055 1056 static struct omap_hwmod dm814x_mmc2_hwmod = { 1057 .name = "mmc2", 1058 .clkdm_name = "alwon_l3s_clkdm", 1059 .opt_clks = dm81xx_mmc_opt_clks, 1060 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), 1061 .main_clk = "sysclk8_ck", 1062 .prcm = { 1063 .omap4 = { 1064 .clkctrl_offs = DM814X_CM_ALWON_MMCHS_1_CLKCTRL, 1065 .modulemode = MODULEMODE_SWCTRL, 1066 }, 1067 }, 1068 .dev_attr = &mmc_dev_attr, 1069 .class = &dm81xx_mmc_class, 1070 }; 1071 1072 static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc2 = { 1073 .master = &dm81xx_l4_ls_hwmod, 1074 .slave = &dm814x_mmc2_hwmod, 1075 .clk = "sysclk6_ck", 1076 .user = OCP_USER_MPU, 1077 .flags = OMAP_FIREWALL_L4 1078 }; 1079 1080 static struct omap_hwmod dm814x_mmc3_hwmod = { 1081 .name = "mmc3", 1082 .clkdm_name = "alwon_l3_med_clkdm", 1083 .opt_clks = dm81xx_mmc_opt_clks, 1084 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), 1085 .main_clk = "sysclk8_ck", 1086 .prcm = { 1087 .omap4 = { 1088 .clkctrl_offs = DM814X_CM_ALWON_MMCHS_2_CLKCTRL, 1089 .modulemode = MODULEMODE_SWCTRL, 1090 }, 1091 }, 1092 .dev_attr = &mmc_dev_attr, 1093 .class = &dm81xx_mmc_class, 1094 }; 1095 1096 static struct omap_hwmod_ocp_if dm814x_alwon_l3_med__mmc3 = { 1097 .master = &dm81xx_alwon_l3_med_hwmod, 1098 .slave = &dm814x_mmc3_hwmod, 1099 .clk = "sysclk4_ck", 1100 .user = OCP_USER_MPU, 1101 }; 1102 1103 static struct omap_hwmod dm816x_mmc1_hwmod = { 1104 .name = "mmc1", 1105 .clkdm_name = "alwon_l3s_clkdm", 1106 .opt_clks = dm81xx_mmc_opt_clks, 1107 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), 1108 .main_clk = "sysclk10_ck", 1109 .prcm = { 1110 .omap4 = { 1111 .clkctrl_offs = DM816X_CM_ALWON_SDIO_CLKCTRL, 1112 .modulemode = MODULEMODE_SWCTRL, 1113 }, 1114 }, 1115 .dev_attr = &mmc_dev_attr, 1116 .class = &dm81xx_mmc_class, 1117 }; 1118 1119 static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = { 1120 .master = &dm81xx_l4_ls_hwmod, 1121 .slave = &dm816x_mmc1_hwmod, 1122 .clk = "sysclk6_ck", 1123 .user = OCP_USER_MPU, 1124 .flags = OMAP_FIREWALL_L4 1125 }; 1126 1127 static struct omap_hwmod_class_sysconfig dm816x_mcspi_sysc = { 1128 .rev_offs = 0x0, 1129 .sysc_offs = 0x110, 1130 .syss_offs = 0x114, 1131 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1132 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1133 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, 1134 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 1135 .sysc_fields = &omap_hwmod_sysc_type1, 1136 }; 1137 1138 static struct omap_hwmod_class dm816x_mcspi_class = { 1139 .name = "mcspi", 1140 .sysc = &dm816x_mcspi_sysc, 1141 .rev = OMAP3_MCSPI_REV, 1142 }; 1143 1144 static struct omap2_mcspi_dev_attr dm816x_mcspi1_dev_attr = { 1145 .num_chipselect = 4, 1146 }; 1147 1148 static struct omap_hwmod dm81xx_mcspi1_hwmod = { 1149 .name = "mcspi1", 1150 .clkdm_name = "alwon_l3s_clkdm", 1151 .main_clk = "sysclk10_ck", 1152 .prcm = { 1153 .omap4 = { 1154 .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL, 1155 .modulemode = MODULEMODE_SWCTRL, 1156 }, 1157 }, 1158 .class = &dm816x_mcspi_class, 1159 .dev_attr = &dm816x_mcspi1_dev_attr, 1160 }; 1161 1162 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = { 1163 .master = &dm81xx_l4_ls_hwmod, 1164 .slave = &dm81xx_mcspi1_hwmod, 1165 .clk = "sysclk6_ck", 1166 .user = OCP_USER_MPU, 1167 }; 1168 1169 static struct omap_hwmod_class_sysconfig dm81xx_mailbox_sysc = { 1170 .rev_offs = 0x000, 1171 .sysc_offs = 0x010, 1172 .syss_offs = 0x014, 1173 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1174 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE, 1175 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 1176 .sysc_fields = &omap_hwmod_sysc_type1, 1177 }; 1178 1179 static struct omap_hwmod_class dm81xx_mailbox_hwmod_class = { 1180 .name = "mailbox", 1181 .sysc = &dm81xx_mailbox_sysc, 1182 }; 1183 1184 static struct omap_hwmod dm81xx_mailbox_hwmod = { 1185 .name = "mailbox", 1186 .clkdm_name = "alwon_l3s_clkdm", 1187 .class = &dm81xx_mailbox_hwmod_class, 1188 .main_clk = "sysclk6_ck", 1189 .prcm = { 1190 .omap4 = { 1191 .clkctrl_offs = DM81XX_CM_ALWON_MAILBOX_CLKCTRL, 1192 .modulemode = MODULEMODE_SWCTRL, 1193 }, 1194 }, 1195 }; 1196 1197 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mailbox = { 1198 .master = &dm81xx_l4_ls_hwmod, 1199 .slave = &dm81xx_mailbox_hwmod, 1200 .clk = "sysclk6_ck", 1201 .user = OCP_USER_MPU, 1202 }; 1203 1204 static struct omap_hwmod_class_sysconfig dm81xx_spinbox_sysc = { 1205 .rev_offs = 0x000, 1206 .sysc_offs = 0x010, 1207 .syss_offs = 0x014, 1208 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1209 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE, 1210 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 1211 .sysc_fields = &omap_hwmod_sysc_type1, 1212 }; 1213 1214 static struct omap_hwmod_class dm81xx_spinbox_hwmod_class = { 1215 .name = "spinbox", 1216 .sysc = &dm81xx_spinbox_sysc, 1217 }; 1218 1219 static struct omap_hwmod dm81xx_spinbox_hwmod = { 1220 .name = "spinbox", 1221 .clkdm_name = "alwon_l3s_clkdm", 1222 .class = &dm81xx_spinbox_hwmod_class, 1223 .main_clk = "sysclk6_ck", 1224 .prcm = { 1225 .omap4 = { 1226 .clkctrl_offs = DM81XX_CM_ALWON_SPINBOX_CLKCTRL, 1227 .modulemode = MODULEMODE_SWCTRL, 1228 }, 1229 }, 1230 }; 1231 1232 static struct omap_hwmod_ocp_if dm81xx_l4_ls__spinbox = { 1233 .master = &dm81xx_l4_ls_hwmod, 1234 .slave = &dm81xx_spinbox_hwmod, 1235 .clk = "sysclk6_ck", 1236 .user = OCP_USER_MPU, 1237 }; 1238 1239 static struct omap_hwmod_class dm81xx_tpcc_hwmod_class = { 1240 .name = "tpcc", 1241 }; 1242 1243 static struct omap_hwmod dm81xx_tpcc_hwmod = { 1244 .name = "tpcc", 1245 .class = &dm81xx_tpcc_hwmod_class, 1246 .clkdm_name = "alwon_l3s_clkdm", 1247 .main_clk = "sysclk4_ck", 1248 .prcm = { 1249 .omap4 = { 1250 .clkctrl_offs = DM81XX_CM_ALWON_TPCC_CLKCTRL, 1251 .modulemode = MODULEMODE_SWCTRL, 1252 }, 1253 }, 1254 }; 1255 1256 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tpcc = { 1257 .master = &dm81xx_alwon_l3_fast_hwmod, 1258 .slave = &dm81xx_tpcc_hwmod, 1259 .clk = "sysclk4_ck", 1260 .user = OCP_USER_MPU, 1261 }; 1262 1263 static struct omap_hwmod_class dm81xx_tptc0_hwmod_class = { 1264 .name = "tptc0", 1265 }; 1266 1267 static struct omap_hwmod dm81xx_tptc0_hwmod = { 1268 .name = "tptc0", 1269 .class = &dm81xx_tptc0_hwmod_class, 1270 .clkdm_name = "alwon_l3s_clkdm", 1271 .main_clk = "sysclk4_ck", 1272 .prcm = { 1273 .omap4 = { 1274 .clkctrl_offs = DM81XX_CM_ALWON_TPTC0_CLKCTRL, 1275 .modulemode = MODULEMODE_SWCTRL, 1276 }, 1277 }, 1278 }; 1279 1280 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc0 = { 1281 .master = &dm81xx_alwon_l3_fast_hwmod, 1282 .slave = &dm81xx_tptc0_hwmod, 1283 .clk = "sysclk4_ck", 1284 .user = OCP_USER_MPU, 1285 }; 1286 1287 static struct omap_hwmod_ocp_if dm81xx_tptc0__alwon_l3_fast = { 1288 .master = &dm81xx_tptc0_hwmod, 1289 .slave = &dm81xx_alwon_l3_fast_hwmod, 1290 .clk = "sysclk4_ck", 1291 .user = OCP_USER_MPU, 1292 }; 1293 1294 static struct omap_hwmod_class dm81xx_tptc1_hwmod_class = { 1295 .name = "tptc1", 1296 }; 1297 1298 static struct omap_hwmod dm81xx_tptc1_hwmod = { 1299 .name = "tptc1", 1300 .class = &dm81xx_tptc1_hwmod_class, 1301 .clkdm_name = "alwon_l3s_clkdm", 1302 .main_clk = "sysclk4_ck", 1303 .prcm = { 1304 .omap4 = { 1305 .clkctrl_offs = DM81XX_CM_ALWON_TPTC1_CLKCTRL, 1306 .modulemode = MODULEMODE_SWCTRL, 1307 }, 1308 }, 1309 }; 1310 1311 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc1 = { 1312 .master = &dm81xx_alwon_l3_fast_hwmod, 1313 .slave = &dm81xx_tptc1_hwmod, 1314 .clk = "sysclk4_ck", 1315 .user = OCP_USER_MPU, 1316 }; 1317 1318 static struct omap_hwmod_ocp_if dm81xx_tptc1__alwon_l3_fast = { 1319 .master = &dm81xx_tptc1_hwmod, 1320 .slave = &dm81xx_alwon_l3_fast_hwmod, 1321 .clk = "sysclk4_ck", 1322 .user = OCP_USER_MPU, 1323 }; 1324 1325 static struct omap_hwmod_class dm81xx_tptc2_hwmod_class = { 1326 .name = "tptc2", 1327 }; 1328 1329 static struct omap_hwmod dm81xx_tptc2_hwmod = { 1330 .name = "tptc2", 1331 .class = &dm81xx_tptc2_hwmod_class, 1332 .clkdm_name = "alwon_l3s_clkdm", 1333 .main_clk = "sysclk4_ck", 1334 .prcm = { 1335 .omap4 = { 1336 .clkctrl_offs = DM81XX_CM_ALWON_TPTC2_CLKCTRL, 1337 .modulemode = MODULEMODE_SWCTRL, 1338 }, 1339 }, 1340 }; 1341 1342 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc2 = { 1343 .master = &dm81xx_alwon_l3_fast_hwmod, 1344 .slave = &dm81xx_tptc2_hwmod, 1345 .clk = "sysclk4_ck", 1346 .user = OCP_USER_MPU, 1347 }; 1348 1349 static struct omap_hwmod_ocp_if dm81xx_tptc2__alwon_l3_fast = { 1350 .master = &dm81xx_tptc2_hwmod, 1351 .slave = &dm81xx_alwon_l3_fast_hwmod, 1352 .clk = "sysclk4_ck", 1353 .user = OCP_USER_MPU, 1354 }; 1355 1356 static struct omap_hwmod_class dm81xx_tptc3_hwmod_class = { 1357 .name = "tptc3", 1358 }; 1359 1360 static struct omap_hwmod dm81xx_tptc3_hwmod = { 1361 .name = "tptc3", 1362 .class = &dm81xx_tptc3_hwmod_class, 1363 .clkdm_name = "alwon_l3s_clkdm", 1364 .main_clk = "sysclk4_ck", 1365 .prcm = { 1366 .omap4 = { 1367 .clkctrl_offs = DM81XX_CM_ALWON_TPTC3_CLKCTRL, 1368 .modulemode = MODULEMODE_SWCTRL, 1369 }, 1370 }, 1371 }; 1372 1373 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc3 = { 1374 .master = &dm81xx_alwon_l3_fast_hwmod, 1375 .slave = &dm81xx_tptc3_hwmod, 1376 .clk = "sysclk4_ck", 1377 .user = OCP_USER_MPU, 1378 }; 1379 1380 static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = { 1381 .master = &dm81xx_tptc3_hwmod, 1382 .slave = &dm81xx_alwon_l3_fast_hwmod, 1383 .clk = "sysclk4_ck", 1384 .user = OCP_USER_MPU, 1385 }; 1386 1387 /* 1388 * REVISIT: Test and enable the following once clocks work: 1389 * dm81xx_l4_ls__mailbox 1390 * 1391 * Also note that some devices share a single clkctrl_offs.. 1392 * For example, i2c1 and 3 share one, and i2c2 and 4 share one. 1393 */ 1394 static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = { 1395 &dm814x_mpu__alwon_l3_slow, 1396 &dm814x_mpu__alwon_l3_med, 1397 &dm81xx_alwon_l3_slow__l4_ls, 1398 &dm81xx_alwon_l3_slow__l4_hs, 1399 &dm81xx_l4_ls__uart1, 1400 &dm81xx_l4_ls__uart2, 1401 &dm81xx_l4_ls__uart3, 1402 &dm81xx_l4_ls__wd_timer1, 1403 &dm81xx_l4_ls__i2c1, 1404 &dm81xx_l4_ls__i2c2, 1405 &dm81xx_l4_ls__gpio1, 1406 &dm81xx_l4_ls__gpio2, 1407 &dm81xx_l4_ls__elm, 1408 &dm81xx_l4_ls__mcspi1, 1409 &dm814x_l4_ls__mmc1, 1410 &dm814x_l4_ls__mmc2, 1411 &ti81xx_l4_ls__rtc, 1412 &dm81xx_alwon_l3_fast__tpcc, 1413 &dm81xx_alwon_l3_fast__tptc0, 1414 &dm81xx_alwon_l3_fast__tptc1, 1415 &dm81xx_alwon_l3_fast__tptc2, 1416 &dm81xx_alwon_l3_fast__tptc3, 1417 &dm81xx_tptc0__alwon_l3_fast, 1418 &dm81xx_tptc1__alwon_l3_fast, 1419 &dm81xx_tptc2__alwon_l3_fast, 1420 &dm81xx_tptc3__alwon_l3_fast, 1421 &dm814x_l4_ls__timer1, 1422 &dm814x_l4_ls__timer2, 1423 &dm814x_l4_hs__cpgmac0, 1424 &dm814x_cpgmac0__mdio, 1425 &dm81xx_alwon_l3_slow__gpmc, 1426 &dm814x_default_l3_slow__usbss, 1427 &dm814x_alwon_l3_med__mmc3, 1428 NULL, 1429 }; 1430 1431 int __init dm814x_hwmod_init(void) 1432 { 1433 omap_hwmod_init(); 1434 return omap_hwmod_register_links(dm814x_hwmod_ocp_ifs); 1435 } 1436 1437 static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = { 1438 &dm816x_mpu__alwon_l3_slow, 1439 &dm816x_mpu__alwon_l3_med, 1440 &dm81xx_alwon_l3_slow__l4_ls, 1441 &dm81xx_alwon_l3_slow__l4_hs, 1442 &dm81xx_l4_ls__uart1, 1443 &dm81xx_l4_ls__uart2, 1444 &dm81xx_l4_ls__uart3, 1445 &dm81xx_l4_ls__wd_timer1, 1446 &dm81xx_l4_ls__i2c1, 1447 &dm81xx_l4_ls__i2c2, 1448 &dm81xx_l4_ls__gpio1, 1449 &dm81xx_l4_ls__gpio2, 1450 &dm81xx_l4_ls__elm, 1451 &ti81xx_l4_ls__rtc, 1452 &dm816x_l4_ls__mmc1, 1453 &dm816x_l4_ls__timer1, 1454 &dm816x_l4_ls__timer2, 1455 &dm816x_l4_ls__timer3, 1456 &dm816x_l4_ls__timer4, 1457 &dm816x_l4_ls__timer5, 1458 &dm816x_l4_ls__timer6, 1459 &dm816x_l4_ls__timer7, 1460 &dm81xx_l4_ls__mcspi1, 1461 &dm81xx_l4_ls__mailbox, 1462 &dm81xx_l4_ls__spinbox, 1463 &dm81xx_l4_hs__emac0, 1464 &dm81xx_emac0__mdio, 1465 &dm816x_l4_hs__emac1, 1466 &dm81xx_l4_hs__sata, 1467 &dm81xx_alwon_l3_fast__tpcc, 1468 &dm81xx_alwon_l3_fast__tptc0, 1469 &dm81xx_alwon_l3_fast__tptc1, 1470 &dm81xx_alwon_l3_fast__tptc2, 1471 &dm81xx_alwon_l3_fast__tptc3, 1472 &dm81xx_tptc0__alwon_l3_fast, 1473 &dm81xx_tptc1__alwon_l3_fast, 1474 &dm81xx_tptc2__alwon_l3_fast, 1475 &dm81xx_tptc3__alwon_l3_fast, 1476 &dm81xx_alwon_l3_slow__gpmc, 1477 &dm816x_default_l3_slow__usbss, 1478 NULL, 1479 }; 1480 1481 int __init dm816x_hwmod_init(void) 1482 { 1483 omap_hwmod_init(); 1484 return omap_hwmod_register_links(dm816x_hwmod_ocp_ifs); 1485 } 1486