1 /* 2 * DM81xx hwmod data. 3 * 4 * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/ 5 * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/ 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation version 2. 10 * 11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 12 * kind, whether express or implied; without even the implied warranty 13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 */ 17 18 #include <linux/platform_data/gpio-omap.h> 19 #include <linux/platform_data/hsmmc-omap.h> 20 #include <linux/platform_data/spi-omap2-mcspi.h> 21 #include <plat/dmtimer.h> 22 23 #include "omap_hwmod_common_data.h" 24 #include "cm81xx.h" 25 #include "ti81xx.h" 26 #include "wd_timer.h" 27 28 /* 29 * DM816X hardware modules integration data 30 * 31 * Note: This is incomplete and at present, not generated from h/w database. 32 */ 33 34 /* 35 * Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS" 36 * also dm816x TRM 18.7.17 CM_ALWON device register values minus 0x1400. 37 */ 38 #define DM81XX_CM_ALWON_MCASP0_CLKCTRL 0x140 39 #define DM81XX_CM_ALWON_MCASP1_CLKCTRL 0x144 40 #define DM81XX_CM_ALWON_MCASP2_CLKCTRL 0x148 41 #define DM81XX_CM_ALWON_MCBSP_CLKCTRL 0x14c 42 #define DM81XX_CM_ALWON_UART_0_CLKCTRL 0x150 43 #define DM81XX_CM_ALWON_UART_1_CLKCTRL 0x154 44 #define DM81XX_CM_ALWON_UART_2_CLKCTRL 0x158 45 #define DM81XX_CM_ALWON_GPIO_0_CLKCTRL 0x15c 46 #define DM81XX_CM_ALWON_GPIO_1_CLKCTRL 0x160 47 #define DM81XX_CM_ALWON_I2C_0_CLKCTRL 0x164 48 #define DM81XX_CM_ALWON_I2C_1_CLKCTRL 0x168 49 #define DM81XX_CM_ALWON_WDTIMER_CLKCTRL 0x18c 50 #define DM81XX_CM_ALWON_SPI_CLKCTRL 0x190 51 #define DM81XX_CM_ALWON_MAILBOX_CLKCTRL 0x194 52 #define DM81XX_CM_ALWON_SPINBOX_CLKCTRL 0x198 53 #define DM81XX_CM_ALWON_MMUDATA_CLKCTRL 0x19c 54 #define DM81XX_CM_ALWON_MMUCFG_CLKCTRL 0x1a8 55 #define DM81XX_CM_ALWON_CONTROL_CLKCTRL 0x1c4 56 #define DM81XX_CM_ALWON_GPMC_CLKCTRL 0x1d0 57 #define DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL 0x1d4 58 #define DM81XX_CM_ALWON_L3_CLKCTRL 0x1e4 59 #define DM81XX_CM_ALWON_L4HS_CLKCTRL 0x1e8 60 #define DM81XX_CM_ALWON_L4LS_CLKCTRL 0x1ec 61 #define DM81XX_CM_ALWON_RTC_CLKCTRL 0x1f0 62 #define DM81XX_CM_ALWON_TPCC_CLKCTRL 0x1f4 63 #define DM81XX_CM_ALWON_TPTC0_CLKCTRL 0x1f8 64 #define DM81XX_CM_ALWON_TPTC1_CLKCTRL 0x1fc 65 #define DM81XX_CM_ALWON_TPTC2_CLKCTRL 0x200 66 #define DM81XX_CM_ALWON_TPTC3_CLKCTRL 0x204 67 68 /* Registers specific to dm814x */ 69 #define DM814X_CM_ALWON_MCASP_3_4_5_CLKCTRL 0x16c 70 #define DM814X_CM_ALWON_ATL_CLKCTRL 0x170 71 #define DM814X_CM_ALWON_MLB_CLKCTRL 0x174 72 #define DM814X_CM_ALWON_PATA_CLKCTRL 0x178 73 #define DM814X_CM_ALWON_UART_3_CLKCTRL 0x180 74 #define DM814X_CM_ALWON_UART_4_CLKCTRL 0x184 75 #define DM814X_CM_ALWON_UART_5_CLKCTRL 0x188 76 #define DM814X_CM_ALWON_OCM_0_CLKCTRL 0x1b4 77 #define DM814X_CM_ALWON_VCP_CLKCTRL 0x1b8 78 #define DM814X_CM_ALWON_MPU_CLKCTRL 0x1dc 79 #define DM814X_CM_ALWON_DEBUGSS_CLKCTRL 0x1e0 80 #define DM814X_CM_ALWON_DCAN_0_1_CLKCTRL 0x218 81 #define DM814X_CM_ALWON_MMCHS_0_CLKCTRL 0x21c 82 #define DM814X_CM_ALWON_MMCHS_1_CLKCTRL 0x220 83 #define DM814X_CM_ALWON_MMCHS_2_CLKCTRL 0x224 84 #define DM814X_CM_ALWON_CUST_EFUSE_CLKCTRL 0x228 85 86 /* Registers specific to dm816x */ 87 #define DM816X_DM_ALWON_BASE 0x1400 88 #define DM816X_CM_ALWON_TIMER_1_CLKCTRL (0x1570 - DM816X_DM_ALWON_BASE) 89 #define DM816X_CM_ALWON_TIMER_2_CLKCTRL (0x1574 - DM816X_DM_ALWON_BASE) 90 #define DM816X_CM_ALWON_TIMER_3_CLKCTRL (0x1578 - DM816X_DM_ALWON_BASE) 91 #define DM816X_CM_ALWON_TIMER_4_CLKCTRL (0x157c - DM816X_DM_ALWON_BASE) 92 #define DM816X_CM_ALWON_TIMER_5_CLKCTRL (0x1580 - DM816X_DM_ALWON_BASE) 93 #define DM816X_CM_ALWON_TIMER_6_CLKCTRL (0x1584 - DM816X_DM_ALWON_BASE) 94 #define DM816X_CM_ALWON_TIMER_7_CLKCTRL (0x1588 - DM816X_DM_ALWON_BASE) 95 #define DM816X_CM_ALWON_SDIO_CLKCTRL (0x15b0 - DM816X_DM_ALWON_BASE) 96 #define DM816X_CM_ALWON_OCMC_0_CLKCTRL (0x15b4 - DM816X_DM_ALWON_BASE) 97 #define DM816X_CM_ALWON_OCMC_1_CLKCTRL (0x15b8 - DM816X_DM_ALWON_BASE) 98 #define DM816X_CM_ALWON_ETHERNET_1_CLKCTRL (0x15d8 - DM816X_DM_ALWON_BASE) 99 #define DM816X_CM_ALWON_MPU_CLKCTRL (0x15dc - DM816X_DM_ALWON_BASE) 100 #define DM816X_CM_ALWON_SR_0_CLKCTRL (0x1608 - DM816X_DM_ALWON_BASE) 101 #define DM816X_CM_ALWON_SR_1_CLKCTRL (0x160c - DM816X_DM_ALWON_BASE) 102 103 /* 104 * The default .clkctrl_offs field is offset from CM_DEFAULT, that's 105 * TRM 18.7.6 CM_DEFAULT device register values minus 0x500 106 */ 107 #define DM816X_CM_DEFAULT_OFFSET 0x500 108 #define DM816X_CM_DEFAULT_USB_CLKCTRL (0x558 - DM816X_CM_DEFAULT_OFFSET) 109 110 /* L3 Interconnect entries clocked at 125, 250 and 500MHz */ 111 static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = { 112 .name = "alwon_l3_slow", 113 .clkdm_name = "alwon_l3s_clkdm", 114 .class = &l3_hwmod_class, 115 .flags = HWMOD_NO_IDLEST, 116 }; 117 118 static struct omap_hwmod dm81xx_default_l3_slow_hwmod = { 119 .name = "default_l3_slow", 120 .clkdm_name = "default_l3_slow_clkdm", 121 .class = &l3_hwmod_class, 122 .flags = HWMOD_NO_IDLEST, 123 }; 124 125 static struct omap_hwmod dm81xx_alwon_l3_med_hwmod = { 126 .name = "l3_med", 127 .clkdm_name = "alwon_l3_med_clkdm", 128 .class = &l3_hwmod_class, 129 .flags = HWMOD_NO_IDLEST, 130 }; 131 132 static struct omap_hwmod dm81xx_alwon_l3_fast_hwmod = { 133 .name = "l3_fast", 134 .clkdm_name = "alwon_l3_fast_clkdm", 135 .class = &l3_hwmod_class, 136 .flags = HWMOD_NO_IDLEST, 137 }; 138 139 /* 140 * L4 standard peripherals, see TRM table 1-12 for devices using this. 141 * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock. 142 */ 143 static struct omap_hwmod dm81xx_l4_ls_hwmod = { 144 .name = "l4_ls", 145 .clkdm_name = "alwon_l3s_clkdm", 146 .class = &l4_hwmod_class, 147 }; 148 149 /* 150 * L4 high-speed peripherals. For devices using this, please see the TRM 151 * table 1-13. On dm816x, only EMAC, MDIO and SATA use this. See also TRM 152 * table 1-73 for devices using 250MHz SYSCLK5 clock. 153 */ 154 static struct omap_hwmod dm81xx_l4_hs_hwmod = { 155 .name = "l4_hs", 156 .clkdm_name = "alwon_l3_med_clkdm", 157 .class = &l4_hwmod_class, 158 }; 159 160 /* L3 slow -> L4 ls peripheral interface running at 125MHz */ 161 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_ls = { 162 .master = &dm81xx_alwon_l3_slow_hwmod, 163 .slave = &dm81xx_l4_ls_hwmod, 164 .user = OCP_USER_MPU, 165 }; 166 167 /* L3 med -> L4 fast peripheral interface running at 250MHz */ 168 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_hs = { 169 .master = &dm81xx_alwon_l3_med_hwmod, 170 .slave = &dm81xx_l4_hs_hwmod, 171 .user = OCP_USER_MPU, 172 }; 173 174 /* MPU */ 175 static struct omap_hwmod dm814x_mpu_hwmod = { 176 .name = "mpu", 177 .clkdm_name = "alwon_l3s_clkdm", 178 .class = &mpu_hwmod_class, 179 .flags = HWMOD_INIT_NO_IDLE, 180 .main_clk = "mpu_ck", 181 .prcm = { 182 .omap4 = { 183 .clkctrl_offs = DM814X_CM_ALWON_MPU_CLKCTRL, 184 .modulemode = MODULEMODE_SWCTRL, 185 }, 186 }, 187 }; 188 189 static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_slow = { 190 .master = &dm814x_mpu_hwmod, 191 .slave = &dm81xx_alwon_l3_slow_hwmod, 192 .user = OCP_USER_MPU, 193 }; 194 195 /* L3 med peripheral interface running at 200MHz */ 196 static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_med = { 197 .master = &dm814x_mpu_hwmod, 198 .slave = &dm81xx_alwon_l3_med_hwmod, 199 .user = OCP_USER_MPU, 200 }; 201 202 static struct omap_hwmod dm816x_mpu_hwmod = { 203 .name = "mpu", 204 .clkdm_name = "alwon_mpu_clkdm", 205 .class = &mpu_hwmod_class, 206 .flags = HWMOD_INIT_NO_IDLE, 207 .main_clk = "mpu_ck", 208 .prcm = { 209 .omap4 = { 210 .clkctrl_offs = DM816X_CM_ALWON_MPU_CLKCTRL, 211 .modulemode = MODULEMODE_SWCTRL, 212 }, 213 }, 214 }; 215 216 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_slow = { 217 .master = &dm816x_mpu_hwmod, 218 .slave = &dm81xx_alwon_l3_slow_hwmod, 219 .user = OCP_USER_MPU, 220 }; 221 222 /* L3 med peripheral interface running at 250MHz */ 223 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med = { 224 .master = &dm816x_mpu_hwmod, 225 .slave = &dm81xx_alwon_l3_med_hwmod, 226 .user = OCP_USER_MPU, 227 }; 228 229 /* UART common */ 230 static struct omap_hwmod_class_sysconfig uart_sysc = { 231 .rev_offs = 0x50, 232 .sysc_offs = 0x54, 233 .syss_offs = 0x58, 234 .sysc_flags = SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | 235 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 236 SYSS_HAS_RESET_STATUS, 237 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 238 MSTANDBY_SMART_WKUP, 239 .sysc_fields = &omap_hwmod_sysc_type1, 240 }; 241 242 static struct omap_hwmod_class uart_class = { 243 .name = "uart", 244 .sysc = &uart_sysc, 245 }; 246 247 static struct omap_hwmod dm81xx_uart1_hwmod = { 248 .name = "uart1", 249 .clkdm_name = "alwon_l3s_clkdm", 250 .main_clk = "sysclk10_ck", 251 .prcm = { 252 .omap4 = { 253 .clkctrl_offs = DM81XX_CM_ALWON_UART_0_CLKCTRL, 254 .modulemode = MODULEMODE_SWCTRL, 255 }, 256 }, 257 .class = &uart_class, 258 .flags = DEBUG_TI81XXUART1_FLAGS, 259 }; 260 261 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart1 = { 262 .master = &dm81xx_l4_ls_hwmod, 263 .slave = &dm81xx_uart1_hwmod, 264 .clk = "sysclk6_ck", 265 .user = OCP_USER_MPU, 266 }; 267 268 static struct omap_hwmod dm81xx_uart2_hwmod = { 269 .name = "uart2", 270 .clkdm_name = "alwon_l3s_clkdm", 271 .main_clk = "sysclk10_ck", 272 .prcm = { 273 .omap4 = { 274 .clkctrl_offs = DM81XX_CM_ALWON_UART_1_CLKCTRL, 275 .modulemode = MODULEMODE_SWCTRL, 276 }, 277 }, 278 .class = &uart_class, 279 .flags = DEBUG_TI81XXUART2_FLAGS, 280 }; 281 282 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart2 = { 283 .master = &dm81xx_l4_ls_hwmod, 284 .slave = &dm81xx_uart2_hwmod, 285 .clk = "sysclk6_ck", 286 .user = OCP_USER_MPU, 287 }; 288 289 static struct omap_hwmod dm81xx_uart3_hwmod = { 290 .name = "uart3", 291 .clkdm_name = "alwon_l3s_clkdm", 292 .main_clk = "sysclk10_ck", 293 .prcm = { 294 .omap4 = { 295 .clkctrl_offs = DM81XX_CM_ALWON_UART_2_CLKCTRL, 296 .modulemode = MODULEMODE_SWCTRL, 297 }, 298 }, 299 .class = &uart_class, 300 .flags = DEBUG_TI81XXUART3_FLAGS, 301 }; 302 303 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart3 = { 304 .master = &dm81xx_l4_ls_hwmod, 305 .slave = &dm81xx_uart3_hwmod, 306 .clk = "sysclk6_ck", 307 .user = OCP_USER_MPU, 308 }; 309 310 static struct omap_hwmod_class_sysconfig wd_timer_sysc = { 311 .rev_offs = 0x0, 312 .sysc_offs = 0x10, 313 .syss_offs = 0x14, 314 .sysc_flags = SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | 315 SYSS_HAS_RESET_STATUS, 316 .sysc_fields = &omap_hwmod_sysc_type1, 317 }; 318 319 static struct omap_hwmod_class wd_timer_class = { 320 .name = "wd_timer", 321 .sysc = &wd_timer_sysc, 322 .pre_shutdown = &omap2_wd_timer_disable, 323 .reset = &omap2_wd_timer_reset, 324 }; 325 326 static struct omap_hwmod dm81xx_wd_timer_hwmod = { 327 .name = "wd_timer", 328 .clkdm_name = "alwon_l3s_clkdm", 329 .main_clk = "sysclk18_ck", 330 .flags = HWMOD_NO_IDLEST, 331 .prcm = { 332 .omap4 = { 333 .clkctrl_offs = DM81XX_CM_ALWON_WDTIMER_CLKCTRL, 334 .modulemode = MODULEMODE_SWCTRL, 335 }, 336 }, 337 .class = &wd_timer_class, 338 }; 339 340 static struct omap_hwmod_ocp_if dm81xx_l4_ls__wd_timer1 = { 341 .master = &dm81xx_l4_ls_hwmod, 342 .slave = &dm81xx_wd_timer_hwmod, 343 .clk = "sysclk6_ck", 344 .user = OCP_USER_MPU, 345 }; 346 347 /* I2C common */ 348 static struct omap_hwmod_class_sysconfig i2c_sysc = { 349 .rev_offs = 0x0, 350 .sysc_offs = 0x10, 351 .syss_offs = 0x90, 352 .sysc_flags = SYSC_HAS_SIDLEMODE | 353 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 354 SYSC_HAS_AUTOIDLE, 355 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 356 .sysc_fields = &omap_hwmod_sysc_type1, 357 }; 358 359 static struct omap_hwmod_class i2c_class = { 360 .name = "i2c", 361 .sysc = &i2c_sysc, 362 }; 363 364 static struct omap_hwmod dm81xx_i2c1_hwmod = { 365 .name = "i2c1", 366 .clkdm_name = "alwon_l3s_clkdm", 367 .main_clk = "sysclk10_ck", 368 .prcm = { 369 .omap4 = { 370 .clkctrl_offs = DM81XX_CM_ALWON_I2C_0_CLKCTRL, 371 .modulemode = MODULEMODE_SWCTRL, 372 }, 373 }, 374 .class = &i2c_class, 375 }; 376 377 static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c1 = { 378 .master = &dm81xx_l4_ls_hwmod, 379 .slave = &dm81xx_i2c1_hwmod, 380 .clk = "sysclk6_ck", 381 .user = OCP_USER_MPU, 382 }; 383 384 static struct omap_hwmod dm81xx_i2c2_hwmod = { 385 .name = "i2c2", 386 .clkdm_name = "alwon_l3s_clkdm", 387 .main_clk = "sysclk10_ck", 388 .prcm = { 389 .omap4 = { 390 .clkctrl_offs = DM81XX_CM_ALWON_I2C_1_CLKCTRL, 391 .modulemode = MODULEMODE_SWCTRL, 392 }, 393 }, 394 .class = &i2c_class, 395 }; 396 397 static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = { 398 .rev_offs = 0x0000, 399 .sysc_offs = 0x0010, 400 .syss_offs = 0x0014, 401 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 402 SYSC_HAS_SOFTRESET | 403 SYSS_HAS_RESET_STATUS, 404 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 405 .sysc_fields = &omap_hwmod_sysc_type1, 406 }; 407 408 static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = { 409 .master = &dm81xx_l4_ls_hwmod, 410 .slave = &dm81xx_i2c2_hwmod, 411 .clk = "sysclk6_ck", 412 .user = OCP_USER_MPU, 413 }; 414 415 static struct omap_hwmod_class dm81xx_elm_hwmod_class = { 416 .name = "elm", 417 .sysc = &dm81xx_elm_sysc, 418 }; 419 420 static struct omap_hwmod dm81xx_elm_hwmod = { 421 .name = "elm", 422 .clkdm_name = "alwon_l3s_clkdm", 423 .class = &dm81xx_elm_hwmod_class, 424 .main_clk = "sysclk6_ck", 425 }; 426 427 static struct omap_hwmod_ocp_if dm81xx_l4_ls__elm = { 428 .master = &dm81xx_l4_ls_hwmod, 429 .slave = &dm81xx_elm_hwmod, 430 .user = OCP_USER_MPU, 431 }; 432 433 static struct omap_hwmod_class_sysconfig dm81xx_gpio_sysc = { 434 .rev_offs = 0x0000, 435 .sysc_offs = 0x0010, 436 .syss_offs = 0x0114, 437 .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | 438 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 439 SYSS_HAS_RESET_STATUS, 440 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 441 SIDLE_SMART_WKUP, 442 .sysc_fields = &omap_hwmod_sysc_type1, 443 }; 444 445 static struct omap_hwmod_class dm81xx_gpio_hwmod_class = { 446 .name = "gpio", 447 .sysc = &dm81xx_gpio_sysc, 448 .rev = 2, 449 }; 450 451 static struct omap_gpio_dev_attr gpio_dev_attr = { 452 .bank_width = 32, 453 .dbck_flag = true, 454 }; 455 456 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { 457 { .role = "dbclk", .clk = "sysclk18_ck" }, 458 }; 459 460 static struct omap_hwmod dm81xx_gpio1_hwmod = { 461 .name = "gpio1", 462 .clkdm_name = "alwon_l3s_clkdm", 463 .class = &dm81xx_gpio_hwmod_class, 464 .main_clk = "sysclk6_ck", 465 .prcm = { 466 .omap4 = { 467 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_0_CLKCTRL, 468 .modulemode = MODULEMODE_SWCTRL, 469 }, 470 }, 471 .opt_clks = gpio1_opt_clks, 472 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), 473 .dev_attr = &gpio_dev_attr, 474 }; 475 476 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = { 477 .master = &dm81xx_l4_ls_hwmod, 478 .slave = &dm81xx_gpio1_hwmod, 479 .user = OCP_USER_MPU, 480 }; 481 482 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { 483 { .role = "dbclk", .clk = "sysclk18_ck" }, 484 }; 485 486 static struct omap_hwmod dm81xx_gpio2_hwmod = { 487 .name = "gpio2", 488 .clkdm_name = "alwon_l3s_clkdm", 489 .class = &dm81xx_gpio_hwmod_class, 490 .main_clk = "sysclk6_ck", 491 .prcm = { 492 .omap4 = { 493 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL, 494 .modulemode = MODULEMODE_SWCTRL, 495 }, 496 }, 497 .opt_clks = gpio2_opt_clks, 498 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), 499 .dev_attr = &gpio_dev_attr, 500 }; 501 502 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = { 503 .master = &dm81xx_l4_ls_hwmod, 504 .slave = &dm81xx_gpio2_hwmod, 505 .user = OCP_USER_MPU, 506 }; 507 508 static struct omap_hwmod_class_sysconfig dm81xx_gpmc_sysc = { 509 .rev_offs = 0x0, 510 .sysc_offs = 0x10, 511 .syss_offs = 0x14, 512 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 513 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, 514 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 515 .sysc_fields = &omap_hwmod_sysc_type1, 516 }; 517 518 static struct omap_hwmod_class dm81xx_gpmc_hwmod_class = { 519 .name = "gpmc", 520 .sysc = &dm81xx_gpmc_sysc, 521 }; 522 523 static struct omap_hwmod dm81xx_gpmc_hwmod = { 524 .name = "gpmc", 525 .clkdm_name = "alwon_l3s_clkdm", 526 .class = &dm81xx_gpmc_hwmod_class, 527 .main_clk = "sysclk6_ck", 528 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ 529 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS, 530 .prcm = { 531 .omap4 = { 532 .clkctrl_offs = DM81XX_CM_ALWON_GPMC_CLKCTRL, 533 .modulemode = MODULEMODE_SWCTRL, 534 }, 535 }, 536 }; 537 538 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = { 539 .master = &dm81xx_alwon_l3_slow_hwmod, 540 .slave = &dm81xx_gpmc_hwmod, 541 .user = OCP_USER_MPU, 542 }; 543 544 static struct omap_hwmod_class_sysconfig dm81xx_usbhsotg_sysc = { 545 .rev_offs = 0x0, 546 .sysc_offs = 0x10, 547 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | 548 SYSC_HAS_SOFTRESET, 549 .idlemodes = SIDLE_SMART | MSTANDBY_FORCE | MSTANDBY_SMART, 550 .sysc_fields = &omap_hwmod_sysc_type2, 551 }; 552 553 static struct omap_hwmod_class dm81xx_usbotg_class = { 554 .name = "usbotg", 555 .sysc = &dm81xx_usbhsotg_sysc, 556 }; 557 558 static struct omap_hwmod dm81xx_usbss_hwmod = { 559 .name = "usb_otg_hs", 560 .clkdm_name = "default_l3_slow_clkdm", 561 .main_clk = "sysclk6_ck", 562 .prcm = { 563 .omap4 = { 564 .clkctrl_offs = DM816X_CM_DEFAULT_USB_CLKCTRL, 565 .modulemode = MODULEMODE_SWCTRL, 566 }, 567 }, 568 .class = &dm81xx_usbotg_class, 569 }; 570 571 static struct omap_hwmod_ocp_if dm81xx_default_l3_slow__usbss = { 572 .master = &dm81xx_default_l3_slow_hwmod, 573 .slave = &dm81xx_usbss_hwmod, 574 .clk = "sysclk6_ck", 575 .user = OCP_USER_MPU, 576 }; 577 578 static struct omap_hwmod_class_sysconfig dm816x_timer_sysc = { 579 .rev_offs = 0x0000, 580 .sysc_offs = 0x0010, 581 .syss_offs = 0x0014, 582 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET, 583 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 584 SIDLE_SMART_WKUP, 585 .sysc_fields = &omap_hwmod_sysc_type2, 586 }; 587 588 static struct omap_hwmod_class dm816x_timer_hwmod_class = { 589 .name = "timer", 590 .sysc = &dm816x_timer_sysc, 591 }; 592 593 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { 594 .timer_capability = OMAP_TIMER_ALWON, 595 }; 596 597 static struct omap_hwmod dm814x_timer1_hwmod = { 598 .name = "timer1", 599 .clkdm_name = "alwon_l3s_clkdm", 600 .main_clk = "timer_sys_ck", 601 .dev_attr = &capability_alwon_dev_attr, 602 .class = &dm816x_timer_hwmod_class, 603 .flags = HWMOD_NO_IDLEST, 604 }; 605 606 static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = { 607 .master = &dm81xx_l4_ls_hwmod, 608 .slave = &dm814x_timer1_hwmod, 609 .clk = "timer_sys_ck", 610 .user = OCP_USER_MPU, 611 }; 612 613 static struct omap_hwmod dm816x_timer1_hwmod = { 614 .name = "timer1", 615 .clkdm_name = "alwon_l3s_clkdm", 616 .main_clk = "timer1_fck", 617 .prcm = { 618 .omap4 = { 619 .clkctrl_offs = DM816X_CM_ALWON_TIMER_1_CLKCTRL, 620 .modulemode = MODULEMODE_SWCTRL, 621 }, 622 }, 623 .dev_attr = &capability_alwon_dev_attr, 624 .class = &dm816x_timer_hwmod_class, 625 }; 626 627 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = { 628 .master = &dm81xx_l4_ls_hwmod, 629 .slave = &dm816x_timer1_hwmod, 630 .clk = "sysclk6_ck", 631 .user = OCP_USER_MPU, 632 }; 633 634 static struct omap_hwmod dm814x_timer2_hwmod = { 635 .name = "timer2", 636 .clkdm_name = "alwon_l3s_clkdm", 637 .main_clk = "timer_sys_ck", 638 .dev_attr = &capability_alwon_dev_attr, 639 .class = &dm816x_timer_hwmod_class, 640 .flags = HWMOD_NO_IDLEST, 641 }; 642 643 static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = { 644 .master = &dm81xx_l4_ls_hwmod, 645 .slave = &dm814x_timer2_hwmod, 646 .clk = "timer_sys_ck", 647 .user = OCP_USER_MPU, 648 }; 649 650 static struct omap_hwmod dm816x_timer2_hwmod = { 651 .name = "timer2", 652 .clkdm_name = "alwon_l3s_clkdm", 653 .main_clk = "timer2_fck", 654 .prcm = { 655 .omap4 = { 656 .clkctrl_offs = DM816X_CM_ALWON_TIMER_2_CLKCTRL, 657 .modulemode = MODULEMODE_SWCTRL, 658 }, 659 }, 660 .dev_attr = &capability_alwon_dev_attr, 661 .class = &dm816x_timer_hwmod_class, 662 }; 663 664 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = { 665 .master = &dm81xx_l4_ls_hwmod, 666 .slave = &dm816x_timer2_hwmod, 667 .clk = "sysclk6_ck", 668 .user = OCP_USER_MPU, 669 }; 670 671 static struct omap_hwmod dm816x_timer3_hwmod = { 672 .name = "timer3", 673 .clkdm_name = "alwon_l3s_clkdm", 674 .main_clk = "timer3_fck", 675 .prcm = { 676 .omap4 = { 677 .clkctrl_offs = DM816X_CM_ALWON_TIMER_3_CLKCTRL, 678 .modulemode = MODULEMODE_SWCTRL, 679 }, 680 }, 681 .dev_attr = &capability_alwon_dev_attr, 682 .class = &dm816x_timer_hwmod_class, 683 }; 684 685 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer3 = { 686 .master = &dm81xx_l4_ls_hwmod, 687 .slave = &dm816x_timer3_hwmod, 688 .clk = "sysclk6_ck", 689 .user = OCP_USER_MPU, 690 }; 691 692 static struct omap_hwmod dm816x_timer4_hwmod = { 693 .name = "timer4", 694 .clkdm_name = "alwon_l3s_clkdm", 695 .main_clk = "timer4_fck", 696 .prcm = { 697 .omap4 = { 698 .clkctrl_offs = DM816X_CM_ALWON_TIMER_4_CLKCTRL, 699 .modulemode = MODULEMODE_SWCTRL, 700 }, 701 }, 702 .dev_attr = &capability_alwon_dev_attr, 703 .class = &dm816x_timer_hwmod_class, 704 }; 705 706 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer4 = { 707 .master = &dm81xx_l4_ls_hwmod, 708 .slave = &dm816x_timer4_hwmod, 709 .clk = "sysclk6_ck", 710 .user = OCP_USER_MPU, 711 }; 712 713 static struct omap_hwmod dm816x_timer5_hwmod = { 714 .name = "timer5", 715 .clkdm_name = "alwon_l3s_clkdm", 716 .main_clk = "timer5_fck", 717 .prcm = { 718 .omap4 = { 719 .clkctrl_offs = DM816X_CM_ALWON_TIMER_5_CLKCTRL, 720 .modulemode = MODULEMODE_SWCTRL, 721 }, 722 }, 723 .dev_attr = &capability_alwon_dev_attr, 724 .class = &dm816x_timer_hwmod_class, 725 }; 726 727 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer5 = { 728 .master = &dm81xx_l4_ls_hwmod, 729 .slave = &dm816x_timer5_hwmod, 730 .clk = "sysclk6_ck", 731 .user = OCP_USER_MPU, 732 }; 733 734 static struct omap_hwmod dm816x_timer6_hwmod = { 735 .name = "timer6", 736 .clkdm_name = "alwon_l3s_clkdm", 737 .main_clk = "timer6_fck", 738 .prcm = { 739 .omap4 = { 740 .clkctrl_offs = DM816X_CM_ALWON_TIMER_6_CLKCTRL, 741 .modulemode = MODULEMODE_SWCTRL, 742 }, 743 }, 744 .dev_attr = &capability_alwon_dev_attr, 745 .class = &dm816x_timer_hwmod_class, 746 }; 747 748 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer6 = { 749 .master = &dm81xx_l4_ls_hwmod, 750 .slave = &dm816x_timer6_hwmod, 751 .clk = "sysclk6_ck", 752 .user = OCP_USER_MPU, 753 }; 754 755 static struct omap_hwmod dm816x_timer7_hwmod = { 756 .name = "timer7", 757 .clkdm_name = "alwon_l3s_clkdm", 758 .main_clk = "timer7_fck", 759 .prcm = { 760 .omap4 = { 761 .clkctrl_offs = DM816X_CM_ALWON_TIMER_7_CLKCTRL, 762 .modulemode = MODULEMODE_SWCTRL, 763 }, 764 }, 765 .dev_attr = &capability_alwon_dev_attr, 766 .class = &dm816x_timer_hwmod_class, 767 }; 768 769 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = { 770 .master = &dm81xx_l4_ls_hwmod, 771 .slave = &dm816x_timer7_hwmod, 772 .clk = "sysclk6_ck", 773 .user = OCP_USER_MPU, 774 }; 775 776 /* CPSW on dm814x */ 777 static struct omap_hwmod_class_sysconfig dm814x_cpgmac_sysc = { 778 .rev_offs = 0x0, 779 .sysc_offs = 0x8, 780 .syss_offs = 0x4, 781 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | 782 SYSS_HAS_RESET_STATUS, 783 .idlemodes = SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE | 784 MSTANDBY_NO, 785 .sysc_fields = &omap_hwmod_sysc_type3, 786 }; 787 788 static struct omap_hwmod_class dm814x_cpgmac0_hwmod_class = { 789 .name = "cpgmac0", 790 .sysc = &dm814x_cpgmac_sysc, 791 }; 792 793 static struct omap_hwmod dm814x_cpgmac0_hwmod = { 794 .name = "cpgmac0", 795 .class = &dm814x_cpgmac0_hwmod_class, 796 .clkdm_name = "alwon_ethernet_clkdm", 797 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, 798 .main_clk = "cpsw_125mhz_gclk", 799 .prcm = { 800 .omap4 = { 801 .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL, 802 .modulemode = MODULEMODE_SWCTRL, 803 }, 804 }, 805 }; 806 807 static struct omap_hwmod_class dm814x_mdio_hwmod_class = { 808 .name = "davinci_mdio", 809 }; 810 811 static struct omap_hwmod dm814x_mdio_hwmod = { 812 .name = "davinci_mdio", 813 .class = &dm814x_mdio_hwmod_class, 814 .clkdm_name = "alwon_ethernet_clkdm", 815 .main_clk = "cpsw_125mhz_gclk", 816 }; 817 818 static struct omap_hwmod_ocp_if dm814x_l4_hs__cpgmac0 = { 819 .master = &dm81xx_l4_hs_hwmod, 820 .slave = &dm814x_cpgmac0_hwmod, 821 .clk = "cpsw_125mhz_gclk", 822 .user = OCP_USER_MPU, 823 }; 824 825 static struct omap_hwmod_ocp_if dm814x_cpgmac0__mdio = { 826 .master = &dm814x_cpgmac0_hwmod, 827 .slave = &dm814x_mdio_hwmod, 828 .user = OCP_USER_MPU, 829 .flags = HWMOD_NO_IDLEST, 830 }; 831 832 /* EMAC Ethernet */ 833 static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = { 834 .rev_offs = 0x0, 835 .sysc_offs = 0x4, 836 .sysc_flags = SYSC_HAS_SOFTRESET, 837 .sysc_fields = &omap_hwmod_sysc_type2, 838 }; 839 840 static struct omap_hwmod_class dm816x_emac_hwmod_class = { 841 .name = "emac", 842 .sysc = &dm816x_emac_sysc, 843 }; 844 845 /* 846 * On dm816x the MDIO is within EMAC0. As the MDIO driver is a separate 847 * driver probed before EMAC0, we let MDIO do the clock idling. 848 */ 849 static struct omap_hwmod dm816x_emac0_hwmod = { 850 .name = "emac0", 851 .clkdm_name = "alwon_ethernet_clkdm", 852 .class = &dm816x_emac_hwmod_class, 853 }; 854 855 static struct omap_hwmod_ocp_if dm81xx_l4_hs__emac0 = { 856 .master = &dm81xx_l4_hs_hwmod, 857 .slave = &dm816x_emac0_hwmod, 858 .clk = "sysclk5_ck", 859 .user = OCP_USER_MPU, 860 }; 861 862 static struct omap_hwmod_class dm81xx_mdio_hwmod_class = { 863 .name = "davinci_mdio", 864 .sysc = &dm816x_emac_sysc, 865 }; 866 867 static struct omap_hwmod dm81xx_emac0_mdio_hwmod = { 868 .name = "davinci_mdio", 869 .class = &dm81xx_mdio_hwmod_class, 870 .clkdm_name = "alwon_ethernet_clkdm", 871 .main_clk = "sysclk24_ck", 872 .flags = HWMOD_NO_IDLEST, 873 /* 874 * REVISIT: This should be moved to the emac0_hwmod 875 * once we have a better way to handle device slaves. 876 */ 877 .prcm = { 878 .omap4 = { 879 .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL, 880 .modulemode = MODULEMODE_SWCTRL, 881 }, 882 }, 883 }; 884 885 static struct omap_hwmod_ocp_if dm81xx_emac0__mdio = { 886 .master = &dm81xx_l4_hs_hwmod, 887 .slave = &dm81xx_emac0_mdio_hwmod, 888 .user = OCP_USER_MPU, 889 }; 890 891 static struct omap_hwmod dm816x_emac1_hwmod = { 892 .name = "emac1", 893 .clkdm_name = "alwon_ethernet_clkdm", 894 .main_clk = "sysclk24_ck", 895 .flags = HWMOD_NO_IDLEST, 896 .prcm = { 897 .omap4 = { 898 .clkctrl_offs = DM816X_CM_ALWON_ETHERNET_1_CLKCTRL, 899 .modulemode = MODULEMODE_SWCTRL, 900 }, 901 }, 902 .class = &dm816x_emac_hwmod_class, 903 }; 904 905 static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = { 906 .master = &dm81xx_l4_hs_hwmod, 907 .slave = &dm816x_emac1_hwmod, 908 .clk = "sysclk5_ck", 909 .user = OCP_USER_MPU, 910 }; 911 912 static struct omap_hwmod_class_sysconfig dm816x_mmc_sysc = { 913 .rev_offs = 0x0, 914 .sysc_offs = 0x110, 915 .syss_offs = 0x114, 916 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 917 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 918 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, 919 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 920 .sysc_fields = &omap_hwmod_sysc_type1, 921 }; 922 923 static struct omap_hwmod_class dm816x_mmc_class = { 924 .name = "mmc", 925 .sysc = &dm816x_mmc_sysc, 926 }; 927 928 static struct omap_hwmod_opt_clk dm816x_mmc1_opt_clks[] = { 929 { .role = "dbck", .clk = "sysclk18_ck", }, 930 }; 931 932 static struct omap_hsmmc_dev_attr mmc1_dev_attr = { 933 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 934 }; 935 936 static struct omap_hwmod dm816x_mmc1_hwmod = { 937 .name = "mmc1", 938 .clkdm_name = "alwon_l3s_clkdm", 939 .opt_clks = dm816x_mmc1_opt_clks, 940 .opt_clks_cnt = ARRAY_SIZE(dm816x_mmc1_opt_clks), 941 .main_clk = "sysclk10_ck", 942 .prcm = { 943 .omap4 = { 944 .clkctrl_offs = DM816X_CM_ALWON_SDIO_CLKCTRL, 945 .modulemode = MODULEMODE_SWCTRL, 946 }, 947 }, 948 .dev_attr = &mmc1_dev_attr, 949 .class = &dm816x_mmc_class, 950 }; 951 952 static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = { 953 .master = &dm81xx_l4_ls_hwmod, 954 .slave = &dm816x_mmc1_hwmod, 955 .clk = "sysclk6_ck", 956 .user = OCP_USER_MPU, 957 .flags = OMAP_FIREWALL_L4 958 }; 959 960 static struct omap_hwmod_class_sysconfig dm816x_mcspi_sysc = { 961 .rev_offs = 0x0, 962 .sysc_offs = 0x110, 963 .syss_offs = 0x114, 964 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 965 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 966 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, 967 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 968 .sysc_fields = &omap_hwmod_sysc_type1, 969 }; 970 971 static struct omap_hwmod_class dm816x_mcspi_class = { 972 .name = "mcspi", 973 .sysc = &dm816x_mcspi_sysc, 974 .rev = OMAP3_MCSPI_REV, 975 }; 976 977 static struct omap2_mcspi_dev_attr dm816x_mcspi1_dev_attr = { 978 .num_chipselect = 4, 979 }; 980 981 static struct omap_hwmod dm81xx_mcspi1_hwmod = { 982 .name = "mcspi1", 983 .clkdm_name = "alwon_l3s_clkdm", 984 .main_clk = "sysclk10_ck", 985 .prcm = { 986 .omap4 = { 987 .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL, 988 .modulemode = MODULEMODE_SWCTRL, 989 }, 990 }, 991 .class = &dm816x_mcspi_class, 992 .dev_attr = &dm816x_mcspi1_dev_attr, 993 }; 994 995 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = { 996 .master = &dm81xx_l4_ls_hwmod, 997 .slave = &dm81xx_mcspi1_hwmod, 998 .clk = "sysclk6_ck", 999 .user = OCP_USER_MPU, 1000 }; 1001 1002 static struct omap_hwmod_class_sysconfig dm81xx_mailbox_sysc = { 1003 .rev_offs = 0x000, 1004 .sysc_offs = 0x010, 1005 .syss_offs = 0x014, 1006 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1007 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE, 1008 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 1009 .sysc_fields = &omap_hwmod_sysc_type1, 1010 }; 1011 1012 static struct omap_hwmod_class dm81xx_mailbox_hwmod_class = { 1013 .name = "mailbox", 1014 .sysc = &dm81xx_mailbox_sysc, 1015 }; 1016 1017 static struct omap_hwmod dm81xx_mailbox_hwmod = { 1018 .name = "mailbox", 1019 .clkdm_name = "alwon_l3s_clkdm", 1020 .class = &dm81xx_mailbox_hwmod_class, 1021 .main_clk = "sysclk6_ck", 1022 .prcm = { 1023 .omap4 = { 1024 .clkctrl_offs = DM81XX_CM_ALWON_MAILBOX_CLKCTRL, 1025 .modulemode = MODULEMODE_SWCTRL, 1026 }, 1027 }, 1028 }; 1029 1030 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mailbox = { 1031 .master = &dm81xx_l4_ls_hwmod, 1032 .slave = &dm81xx_mailbox_hwmod, 1033 .user = OCP_USER_MPU, 1034 }; 1035 1036 static struct omap_hwmod_class dm81xx_tpcc_hwmod_class = { 1037 .name = "tpcc", 1038 }; 1039 1040 static struct omap_hwmod dm81xx_tpcc_hwmod = { 1041 .name = "tpcc", 1042 .class = &dm81xx_tpcc_hwmod_class, 1043 .clkdm_name = "alwon_l3s_clkdm", 1044 .main_clk = "sysclk4_ck", 1045 .prcm = { 1046 .omap4 = { 1047 .clkctrl_offs = DM81XX_CM_ALWON_TPCC_CLKCTRL, 1048 .modulemode = MODULEMODE_SWCTRL, 1049 }, 1050 }, 1051 }; 1052 1053 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tpcc = { 1054 .master = &dm81xx_alwon_l3_fast_hwmod, 1055 .slave = &dm81xx_tpcc_hwmod, 1056 .clk = "sysclk4_ck", 1057 .user = OCP_USER_MPU, 1058 }; 1059 1060 static struct omap_hwmod_addr_space dm81xx_tptc0_addr_space[] = { 1061 { 1062 .pa_start = 0x49800000, 1063 .pa_end = 0x49800000 + SZ_8K - 1, 1064 .flags = ADDR_TYPE_RT, 1065 }, 1066 { }, 1067 }; 1068 1069 static struct omap_hwmod_class dm81xx_tptc0_hwmod_class = { 1070 .name = "tptc0", 1071 }; 1072 1073 static struct omap_hwmod dm81xx_tptc0_hwmod = { 1074 .name = "tptc0", 1075 .class = &dm81xx_tptc0_hwmod_class, 1076 .clkdm_name = "alwon_l3s_clkdm", 1077 .main_clk = "sysclk4_ck", 1078 .prcm = { 1079 .omap4 = { 1080 .clkctrl_offs = DM81XX_CM_ALWON_TPTC0_CLKCTRL, 1081 .modulemode = MODULEMODE_SWCTRL, 1082 }, 1083 }, 1084 }; 1085 1086 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc0 = { 1087 .master = &dm81xx_alwon_l3_fast_hwmod, 1088 .slave = &dm81xx_tptc0_hwmod, 1089 .clk = "sysclk4_ck", 1090 .addr = dm81xx_tptc0_addr_space, 1091 .user = OCP_USER_MPU, 1092 }; 1093 1094 static struct omap_hwmod_ocp_if dm81xx_tptc0__alwon_l3_fast = { 1095 .master = &dm81xx_tptc0_hwmod, 1096 .slave = &dm81xx_alwon_l3_fast_hwmod, 1097 .clk = "sysclk4_ck", 1098 .addr = dm81xx_tptc0_addr_space, 1099 .user = OCP_USER_MPU, 1100 }; 1101 1102 static struct omap_hwmod_addr_space dm81xx_tptc1_addr_space[] = { 1103 { 1104 .pa_start = 0x49900000, 1105 .pa_end = 0x49900000 + SZ_8K - 1, 1106 .flags = ADDR_TYPE_RT, 1107 }, 1108 { }, 1109 }; 1110 1111 static struct omap_hwmod_class dm81xx_tptc1_hwmod_class = { 1112 .name = "tptc1", 1113 }; 1114 1115 static struct omap_hwmod dm81xx_tptc1_hwmod = { 1116 .name = "tptc1", 1117 .class = &dm81xx_tptc1_hwmod_class, 1118 .clkdm_name = "alwon_l3s_clkdm", 1119 .main_clk = "sysclk4_ck", 1120 .prcm = { 1121 .omap4 = { 1122 .clkctrl_offs = DM81XX_CM_ALWON_TPTC1_CLKCTRL, 1123 .modulemode = MODULEMODE_SWCTRL, 1124 }, 1125 }, 1126 }; 1127 1128 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc1 = { 1129 .master = &dm81xx_alwon_l3_fast_hwmod, 1130 .slave = &dm81xx_tptc1_hwmod, 1131 .clk = "sysclk4_ck", 1132 .addr = dm81xx_tptc1_addr_space, 1133 .user = OCP_USER_MPU, 1134 }; 1135 1136 static struct omap_hwmod_ocp_if dm81xx_tptc1__alwon_l3_fast = { 1137 .master = &dm81xx_tptc1_hwmod, 1138 .slave = &dm81xx_alwon_l3_fast_hwmod, 1139 .clk = "sysclk4_ck", 1140 .addr = dm81xx_tptc1_addr_space, 1141 .user = OCP_USER_MPU, 1142 }; 1143 1144 static struct omap_hwmod_addr_space dm81xx_tptc2_addr_space[] = { 1145 { 1146 .pa_start = 0x49a00000, 1147 .pa_end = 0x49a00000 + SZ_8K - 1, 1148 .flags = ADDR_TYPE_RT, 1149 }, 1150 { }, 1151 }; 1152 1153 static struct omap_hwmod_class dm81xx_tptc2_hwmod_class = { 1154 .name = "tptc2", 1155 }; 1156 1157 static struct omap_hwmod dm81xx_tptc2_hwmod = { 1158 .name = "tptc2", 1159 .class = &dm81xx_tptc2_hwmod_class, 1160 .clkdm_name = "alwon_l3s_clkdm", 1161 .main_clk = "sysclk4_ck", 1162 .prcm = { 1163 .omap4 = { 1164 .clkctrl_offs = DM81XX_CM_ALWON_TPTC2_CLKCTRL, 1165 .modulemode = MODULEMODE_SWCTRL, 1166 }, 1167 }, 1168 }; 1169 1170 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc2 = { 1171 .master = &dm81xx_alwon_l3_fast_hwmod, 1172 .slave = &dm81xx_tptc2_hwmod, 1173 .clk = "sysclk4_ck", 1174 .addr = dm81xx_tptc2_addr_space, 1175 .user = OCP_USER_MPU, 1176 }; 1177 1178 static struct omap_hwmod_ocp_if dm81xx_tptc2__alwon_l3_fast = { 1179 .master = &dm81xx_tptc2_hwmod, 1180 .slave = &dm81xx_alwon_l3_fast_hwmod, 1181 .clk = "sysclk4_ck", 1182 .addr = dm81xx_tptc2_addr_space, 1183 .user = OCP_USER_MPU, 1184 }; 1185 1186 static struct omap_hwmod_addr_space dm81xx_tptc3_addr_space[] = { 1187 { 1188 .pa_start = 0x49b00000, 1189 .pa_end = 0x49b00000 + SZ_8K - 1, 1190 .flags = ADDR_TYPE_RT, 1191 }, 1192 { }, 1193 }; 1194 1195 static struct omap_hwmod_class dm81xx_tptc3_hwmod_class = { 1196 .name = "tptc3", 1197 }; 1198 1199 static struct omap_hwmod dm81xx_tptc3_hwmod = { 1200 .name = "tptc3", 1201 .class = &dm81xx_tptc3_hwmod_class, 1202 .clkdm_name = "alwon_l3s_clkdm", 1203 .main_clk = "sysclk4_ck", 1204 .prcm = { 1205 .omap4 = { 1206 .clkctrl_offs = DM81XX_CM_ALWON_TPTC3_CLKCTRL, 1207 .modulemode = MODULEMODE_SWCTRL, 1208 }, 1209 }, 1210 }; 1211 1212 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc3 = { 1213 .master = &dm81xx_alwon_l3_fast_hwmod, 1214 .slave = &dm81xx_tptc3_hwmod, 1215 .clk = "sysclk4_ck", 1216 .addr = dm81xx_tptc3_addr_space, 1217 .user = OCP_USER_MPU, 1218 }; 1219 1220 static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = { 1221 .master = &dm81xx_tptc3_hwmod, 1222 .slave = &dm81xx_alwon_l3_fast_hwmod, 1223 .clk = "sysclk4_ck", 1224 .addr = dm81xx_tptc3_addr_space, 1225 .user = OCP_USER_MPU, 1226 }; 1227 1228 /* 1229 * REVISIT: Test and enable the following once clocks work: 1230 * dm81xx_l4_ls__gpio1 1231 * dm81xx_l4_ls__gpio2 1232 * dm81xx_l4_ls__mailbox 1233 * dm81xx_alwon_l3_slow__gpmc 1234 * dm81xx_default_l3_slow__usbss 1235 * 1236 * Also note that some devices share a single clkctrl_offs.. 1237 * For example, i2c1 and 3 share one, and i2c2 and 4 share one. 1238 */ 1239 static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = { 1240 &dm814x_mpu__alwon_l3_slow, 1241 &dm814x_mpu__alwon_l3_med, 1242 &dm81xx_alwon_l3_slow__l4_ls, 1243 &dm81xx_alwon_l3_slow__l4_hs, 1244 &dm81xx_l4_ls__uart1, 1245 &dm81xx_l4_ls__uart2, 1246 &dm81xx_l4_ls__uart3, 1247 &dm81xx_l4_ls__wd_timer1, 1248 &dm81xx_l4_ls__i2c1, 1249 &dm81xx_l4_ls__i2c2, 1250 &dm81xx_l4_ls__elm, 1251 &dm81xx_l4_ls__mcspi1, 1252 &dm81xx_alwon_l3_fast__tpcc, 1253 &dm81xx_alwon_l3_fast__tptc0, 1254 &dm81xx_alwon_l3_fast__tptc1, 1255 &dm81xx_alwon_l3_fast__tptc2, 1256 &dm81xx_alwon_l3_fast__tptc3, 1257 &dm81xx_tptc0__alwon_l3_fast, 1258 &dm81xx_tptc1__alwon_l3_fast, 1259 &dm81xx_tptc2__alwon_l3_fast, 1260 &dm81xx_tptc3__alwon_l3_fast, 1261 &dm814x_l4_ls__timer1, 1262 &dm814x_l4_ls__timer2, 1263 &dm814x_l4_hs__cpgmac0, 1264 &dm814x_cpgmac0__mdio, 1265 NULL, 1266 }; 1267 1268 int __init dm814x_hwmod_init(void) 1269 { 1270 omap_hwmod_init(); 1271 return omap_hwmod_register_links(dm814x_hwmod_ocp_ifs); 1272 } 1273 1274 static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = { 1275 &dm816x_mpu__alwon_l3_slow, 1276 &dm816x_mpu__alwon_l3_med, 1277 &dm81xx_alwon_l3_slow__l4_ls, 1278 &dm81xx_alwon_l3_slow__l4_hs, 1279 &dm81xx_l4_ls__uart1, 1280 &dm81xx_l4_ls__uart2, 1281 &dm81xx_l4_ls__uart3, 1282 &dm81xx_l4_ls__wd_timer1, 1283 &dm81xx_l4_ls__i2c1, 1284 &dm81xx_l4_ls__i2c2, 1285 &dm81xx_l4_ls__gpio1, 1286 &dm81xx_l4_ls__gpio2, 1287 &dm81xx_l4_ls__elm, 1288 &dm816x_l4_ls__mmc1, 1289 &dm816x_l4_ls__timer1, 1290 &dm816x_l4_ls__timer2, 1291 &dm816x_l4_ls__timer3, 1292 &dm816x_l4_ls__timer4, 1293 &dm816x_l4_ls__timer5, 1294 &dm816x_l4_ls__timer6, 1295 &dm816x_l4_ls__timer7, 1296 &dm81xx_l4_ls__mcspi1, 1297 &dm81xx_l4_ls__mailbox, 1298 &dm81xx_l4_hs__emac0, 1299 &dm81xx_emac0__mdio, 1300 &dm816x_l4_hs__emac1, 1301 &dm81xx_alwon_l3_fast__tpcc, 1302 &dm81xx_alwon_l3_fast__tptc0, 1303 &dm81xx_alwon_l3_fast__tptc1, 1304 &dm81xx_alwon_l3_fast__tptc2, 1305 &dm81xx_alwon_l3_fast__tptc3, 1306 &dm81xx_tptc0__alwon_l3_fast, 1307 &dm81xx_tptc1__alwon_l3_fast, 1308 &dm81xx_tptc2__alwon_l3_fast, 1309 &dm81xx_tptc3__alwon_l3_fast, 1310 &dm81xx_alwon_l3_slow__gpmc, 1311 &dm81xx_default_l3_slow__usbss, 1312 NULL, 1313 }; 1314 1315 int __init dm816x_hwmod_init(void) 1316 { 1317 omap_hwmod_init(); 1318 return omap_hwmod_register_links(dm816x_hwmod_ocp_ifs); 1319 } 1320